1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright 2013 Sascha Hauer, Pengutronix 3 * Copyright 2013 Sascha Hauer, Pengutronix
4 * 4 *
5 * Copyright 2013-2021 TQ-Systems GmbH 5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-grou 6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 */ 7 */
8 8
9 #include <dt-bindings/clock/imx6qdl-clock.h> 9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h> 12 #include <dt-bindings/sound/fsl-imx-audmux.h>
13 13
14 / { 14 / {
15 aliases { 15 aliases {
16 mmc0 = &usdhc3; 16 mmc0 = &usdhc3;
17 mmc1 = &usdhc2; 17 mmc1 = &usdhc2;
18 /delete-property/ mmc2; 18 /delete-property/ mmc2;
19 /delete-property/ mmc3; 19 /delete-property/ mmc3;
20 rtc0 = &rtc0; 20 rtc0 = &rtc0;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &uart2; 24 stdout-path = &uart2;
25 }; 25 };
26 26
27 beeper: gpio-beeper { 27 beeper: gpio-beeper {
28 compatible = "gpio-beeper"; 28 compatible = "gpio-beeper";
29 pinctrl-names = "default"; 29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpiobeep 30 pinctrl-0 = <&pinctrl_gpiobeeper>;
31 gpios = <&gpio1 21 GPIO_ACTIVE 31 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
32 }; 32 };
33 33
34 gpio_buttons: gpio-buttons { 34 gpio_buttons: gpio-buttons {
35 compatible = "gpio-keys"; 35 compatible = "gpio-keys";
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpiobutt 37 pinctrl-0 = <&pinctrl_gpiobuttons>;
38 38
39 button-1 { 39 button-1 {
40 label = "s6"; 40 label = "s6";
41 linux,code = <KEY_F6>; 41 linux,code = <KEY_F6>;
42 gpios = <&gpio7 13 GPI 42 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
43 wakeup-source; 43 wakeup-source;
44 }; 44 };
45 45
46 button-2 { 46 button-2 {
47 label = "s7"; 47 label = "s7";
48 linux,code = <KEY_F7>; 48 linux,code = <KEY_F7>;
49 gpios = <&gpio7 12 GPI 49 gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
50 wakeup-source; 50 wakeup-source;
51 }; 51 };
52 52
53 button-3 { 53 button-3 {
54 label = "s8"; 54 label = "s8";
55 linux,code = <KEY_F8>; 55 linux,code = <KEY_F8>;
56 gpios = <&gpio1 8 GPIO 56 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
57 wakeup-source; 57 wakeup-source;
58 }; 58 };
59 }; 59 };
60 60
61 gpio-leds { 61 gpio-leds {
62 compatible = "gpio-leds"; 62 compatible = "gpio-leds";
63 pinctrl-names = "default"; 63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_gpioled> 64 pinctrl-0 = <&pinctrl_gpioled>;
65 65
66 led1 { 66 led1 {
67 label = "led1"; 67 label = "led1";
68 gpios = <&gpio6 16 GPI 68 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger 69 linux,default-trigger = "default-on";
70 }; 70 };
71 71
72 led2 { 72 led2 {
73 label = "led2"; 73 label = "led2";
74 gpios = <&gpio6 31 GPI 74 gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
75 linux,default-trigger 75 linux,default-trigger = "heartbeat";
76 }; 76 };
77 }; 77 };
78 78
79 reg_mba6_3p3v: regulator-mba6-3p3v { 79 reg_mba6_3p3v: regulator-mba6-3p3v {
80 compatible = "regulator-fixed" 80 compatible = "regulator-fixed";
81 regulator-name = "supply-mba6- 81 regulator-name = "supply-mba6-3p3v";
82 regulator-min-microvolt = <330 82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <330 83 regulator-max-microvolt = <3300000>;
84 regulator-always-on; 84 regulator-always-on;
85 }; 85 };
86 86
87 reg_pcie: regulator-pcie { 87 reg_pcie: regulator-pcie {
88 compatible = "regulator-fixed" 88 compatible = "regulator-fixed";
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_regpcie> 90 pinctrl-0 = <&pinctrl_regpcie>;
91 regulator-name = "supply-pcie" 91 regulator-name = "supply-pcie";
92 regulator-min-microvolt = <330 92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <330 93 regulator-max-microvolt = <3300000>;
94 /* PCIE.PWR_EN */ 94 /* PCIE.PWR_EN */
95 gpio = <&gpio2 0 GPIO_ACTIVE_H 95 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
96 enable-active-high; 96 enable-active-high;
97 regulator-always-on; 97 regulator-always-on;
98 vin-supply = <®_mba6_3p3v>; 98 vin-supply = <®_mba6_3p3v>;
99 }; 99 };
100 100
101 reg_vcc3v3_audio: regulator-vcc3v3-aud 101 reg_vcc3v3_audio: regulator-vcc3v3-audio {
102 compatible = "regulator-fixed" 102 compatible = "regulator-fixed";
103 regulator-name = "vcc3v3-audio 103 regulator-name = "vcc3v3-audio";
104 regulator-min-microvolt = <330 104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <330 105 regulator-max-microvolt = <3300000>;
106 vin-supply = <®_mba6_3p3v>; 106 vin-supply = <®_mba6_3p3v>;
107 }; 107 };
108 108
109 sound { 109 sound {
110 compatible = "fsl,imx-audio-tl 110 compatible = "fsl,imx-audio-tlv320aic32x4";
111 pinctrl-names = "default"; 111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_audmux>; 112 pinctrl-0 = <&pinctrl_audmux>;
113 model = "imx-audio-tlv320aic32 113 model = "imx-audio-tlv320aic32x4";
114 ssi-controller = <&ssi1>; 114 ssi-controller = <&ssi1>;
115 audio-codec = <&tlv320aic32x4> 115 audio-codec = <&tlv320aic32x4>;
116 audio-asrc = <&asrc>; 116 audio-asrc = <&asrc>;
117 audio-routing = 117 audio-routing =
118 "IN3_L", "Mic Jack", 118 "IN3_L", "Mic Jack",
119 "Mic Jack", "Mic Bias" 119 "Mic Jack", "Mic Bias",
120 "IN1_L", "Line In Jack 120 "IN1_L", "Line In Jack",
121 "IN1_R", "Line In Jack 121 "IN1_R", "Line In Jack",
122 "Line Out Jack", "LOL" 122 "Line Out Jack", "LOL",
123 "Line Out Jack", "LOR" 123 "Line Out Jack", "LOR";
124 mux-int-port = <1>; 124 mux-int-port = <1>;
125 mux-ext-port = <3>; 125 mux-ext-port = <3>;
126 }; 126 };
127 }; 127 };
128 128
129 &audmux { 129 &audmux {
130 status = "okay"; 130 status = "okay";
131 131
132 mux-ssi0 { 132 mux-ssi0 {
133 fsl,audmux-port = <MX31_AUDMUX 133 fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
134 fsl,port-config = < 134 fsl,port-config = <
135 (IMX_AUDMUX_V2_PTCR_SY 135 (IMX_AUDMUX_V2_PTCR_SYN |
136 IMX_AUDMUX_V2_ 136 IMX_AUDMUX_V2_PTCR_TFSDIR |
137 IMX_AUDMUX_V2_ 137 IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
138 IMX_AUDMUX_V2_ 138 IMX_AUDMUX_V2_PTCR_TCLKDIR |
139 IMX_AUDMUX_V2_ 139 IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
140 IMX_AUDMUX_V2_PDCR_RXD 140 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
141 >; 141 >;
142 }; 142 };
143 143
144 mux-aud3 { 144 mux-aud3 {
145 fsl,audmux-port = <MX31_AUDMUX 145 fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
146 fsl,port-config = < 146 fsl,port-config = <
147 IMX_AUDMUX_V2_PTCR_SYN 147 IMX_AUDMUX_V2_PTCR_SYN
148 IMX_AUDMUX_V2_PDCR_RXD 148 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
149 >; 149 >;
150 }; 150 };
151 }; 151 };
152 152
153 &can1 { 153 &can1 {
154 pinctrl-names = "default"; 154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_can1>; 155 pinctrl-0 = <&pinctrl_can1>;
156 status = "okay"; 156 status = "okay";
157 }; 157 };
158 158
159 &can2 { 159 &can2 {
160 pinctrl-names = "default"; 160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_can2>; 161 pinctrl-0 = <&pinctrl_can2>;
162 status = "okay"; 162 status = "okay";
163 }; 163 };
164 164
165 &ecspi1 { 165 &ecspi1 {
166 pinctrl-names = "default"; 166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_ecspi1>, <&pinct 167 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
168 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0 168 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
169 }; 169 };
170 170
171 &fec { 171 &fec {
172 phy-mode = "rgmii-id"; 172 phy-mode = "rgmii-id";
173 phy-handle = <ðphy>; 173 phy-handle = <ðphy>;
174 mac-address = [00 00 00 00 00 00]; 174 mac-address = [00 00 00 00 00 00];
175 status = "okay"; 175 status = "okay";
176 176
177 mdio { 177 mdio {
178 #address-cells = <1>; 178 #address-cells = <1>;
179 #size-cells = <0>; 179 #size-cells = <0>;
180 180
181 ethphy: ethernet-phy@3 { 181 ethphy: ethernet-phy@3 {
182 compatible = "ethernet 182 compatible = "ethernet-phy-ieee802.3-c22";
183 reg = <3>; 183 reg = <3>;
184 interrupt-parent = <&g 184 interrupt-parent = <&gpio1>;
185 interrupts = <28 IRQ_T 185 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
186 reset-gpios = <&gpio1 186 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
187 reset-assert-us = <100 187 reset-assert-us = <1000>;
188 reset-deassert-us = <1 188 reset-deassert-us = <100000>;
189 micrel,force-master; 189 micrel,force-master;
190 max-speed = <1000>; 190 max-speed = <1000>;
191 }; 191 };
192 }; 192 };
193 }; 193 };
194 194
195 &hdmi { 195 &hdmi {
196 pinctrl-names = "default"; 196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_hdmi>; 197 pinctrl-0 = <&pinctrl_hdmi>;
198 ddc-i2c-bus = <&i2c2>; 198 ddc-i2c-bus = <&i2c2>;
199 status = "okay"; 199 status = "okay";
200 }; 200 };
201 201
202 &i2c1 { 202 &i2c1 {
203 tlv320aic32x4: audio-codec@18 { 203 tlv320aic32x4: audio-codec@18 {
204 compatible = "ti,tlv320aic32x4 204 compatible = "ti,tlv320aic32x4";
205 reg = <0x18>; 205 reg = <0x18>;
206 clocks = <&clks IMX6QDL_CLK_CK 206 clocks = <&clks IMX6QDL_CLK_CKO>;
207 clock-names = "mclk"; 207 clock-names = "mclk";
208 pinctrl-names = "default"; 208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_codec>; 209 pinctrl-0 = <&pinctrl_codec>;
210 ldoin-supply = <®_vcc3v3_au 210 ldoin-supply = <®_vcc3v3_audio>;
211 iov-supply = <®_mba6_3p3v>; 211 iov-supply = <®_mba6_3p3v>;
212 }; 212 };
213 }; 213 };
214 214
215 /* DDC */ 215 /* DDC */
216 &i2c2 { 216 &i2c2 {
217 clock-frequency = <100000>; 217 clock-frequency = <100000>;
218 pinctrl-names = "default", "gpio"; 218 pinctrl-names = "default", "gpio";
219 pinctrl-0 = <&pinctrl_i2c2>; 219 pinctrl-0 = <&pinctrl_i2c2>;
220 pinctrl-1 = <&pinctrl_i2c2_recovery>; 220 pinctrl-1 = <&pinctrl_i2c2_recovery>;
221 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HI 221 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
222 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HI 222 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
223 status = "okay"; 223 status = "okay";
224 }; 224 };
225 225
226 &pcie { 226 &pcie {
227 pinctrl-names = "default"; 227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_pcie>; 228 pinctrl-0 = <&pinctrl_pcie>;
229 reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW 229 reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
230 vpcie-supply = <®_pcie>; 230 vpcie-supply = <®_pcie>;
231 status = "okay"; 231 status = "okay";
232 }; 232 };
233 233
234 &pwm1 { 234 &pwm1 {
235 pinctrl-names = "default"; 235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_pwm1>; 236 pinctrl-0 = <&pinctrl_pwm1>;
237 status = "okay"; 237 status = "okay";
238 }; 238 };
239 239
240 &pwm3 { 240 &pwm3 {
241 pinctrl-names = "default"; 241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pwm3>; 242 pinctrl-0 = <&pinctrl_pwm3>;
243 status = "okay"; 243 status = "okay";
244 }; 244 };
245 245
246 &pwm4 { 246 &pwm4 {
247 pinctrl-names = "default"; 247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_pwm4>; 248 pinctrl-0 = <&pinctrl_pwm4>;
249 status = "okay"; 249 status = "okay";
250 }; 250 };
251 251
252 &snvs_poweroff { 252 &snvs_poweroff {
253 status = "okay"; 253 status = "okay";
254 }; 254 };
255 255
256 &ssi1 { 256 &ssi1 {
257 status = "okay"; 257 status = "okay";
258 }; 258 };
259 259
260 &uart2 { 260 &uart2 {
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_uart2>; 262 pinctrl-0 = <&pinctrl_uart2>;
263 status = "okay"; 263 status = "okay";
264 }; 264 };
265 265
266 &uart3 { 266 &uart3 {
267 pinctrl-names = "default"; 267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart3>; 268 pinctrl-0 = <&pinctrl_uart3>;
269 uart-has-rtscts; 269 uart-has-rtscts;
270 status = "okay"; 270 status = "okay";
271 }; 271 };
272 272
273 &uart4 { 273 &uart4 {
274 pinctrl-names = "default"; 274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_uart4>; 275 pinctrl-0 = <&pinctrl_uart4>;
276 uart-has-rtscts; 276 uart-has-rtscts;
277 linux,rs485-enabled-at-boot-time; 277 linux,rs485-enabled-at-boot-time;
278 rs485-rts-active-low; 278 rs485-rts-active-low;
279 rs485-rx-during-tx; 279 rs485-rx-during-tx;
280 status = "okay"; 280 status = "okay";
281 }; 281 };
282 282
283 &uart5 { 283 &uart5 {
284 pinctrl-names = "default"; 284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart5>; 285 pinctrl-0 = <&pinctrl_uart5>;
286 uart-has-rtscts; 286 uart-has-rtscts;
287 status = "okay"; 287 status = "okay";
288 }; 288 };
289 289
290 &usbh1 { 290 &usbh1 {
291 disable-over-current; 291 disable-over-current;
292 status = "okay"; 292 status = "okay";
293 #address-cells = <1>; 293 #address-cells = <1>;
294 #size-cells = <0>; 294 #size-cells = <0>;
295 295
296 hub@1 { 296 hub@1 {
297 compatible = "usb424,2517"; 297 compatible = "usb424,2517";
298 reg = <1>; 298 reg = <1>;
299 #address-cells = <1>; 299 #address-cells = <1>;
300 #size-cells = <0>; 300 #size-cells = <0>;
301 vdd-supply = <®_mba6_3p3v>; 301 vdd-supply = <®_mba6_3p3v>;
302 302
303 ethernet@1 { 303 ethernet@1 {
304 compatible = "usb424,9 304 compatible = "usb424,9e00";
305 reg = <1>; 305 reg = <1>;
306 nvmem-cells = <&mba_ma 306 nvmem-cells = <&mba_mac_address>;
307 nvmem-cell-names = "ma 307 nvmem-cell-names = "mac-address";
308 }; 308 };
309 }; 309 };
310 }; 310 };
311 311
312 &usbotg { 312 &usbotg {
313 pinctrl-names = "default"; 313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_usbotg>; 314 pinctrl-0 = <&pinctrl_usbotg>;
315 power-active-high; 315 power-active-high;
316 over-current-active-low; 316 over-current-active-low;
317 srp-disable; 317 srp-disable;
318 hnp-disable; 318 hnp-disable;
319 adp-disable; 319 adp-disable;
320 dr_mode = "otg"; 320 dr_mode = "otg";
321 status = "okay"; 321 status = "okay";
322 }; 322 };
323 323
324 /* SD card slot */ 324 /* SD card slot */
325 &usdhc2 { 325 &usdhc2 {
326 pinctrl-names = "default"; 326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usdhc2>; 327 pinctrl-0 = <&pinctrl_usdhc2>;
328 vmmc-supply = <®_mba6_3p3v>; 328 vmmc-supply = <®_mba6_3p3v>;
329 bus-width = <4>; 329 bus-width = <4>;
330 no-1-8-v; 330 no-1-8-v;
331 no-mmc; 331 no-mmc;
332 no-sdio; 332 no-sdio;
333 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 333 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
334 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH> 334 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
335 status = "okay"; 335 status = "okay";
336 }; 336 };
337 337
338 &wdog1 { 338 &wdog1 {
339 pinctrl-names = "default"; 339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_wdog1>; 340 pinctrl-0 = <&pinctrl_wdog1>;
341 /* does not work on unmodified starter 341 /* does not work on unmodified starter kit */
342 /* fsl,ext-reset-output; */ 342 /* fsl,ext-reset-output; */
343 status = "okay"; 343 status = "okay";
344 }; 344 };
345 345
346 &iomuxc { 346 &iomuxc {
347 pinctrl-names = "default"; 347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_hog>; 348 pinctrl-0 = <&pinctrl_hog>;
349 349
350 pinctrl_audmux: audmuxgrp { 350 pinctrl_audmux: audmuxgrp {
351 fsl,pins = < 351 fsl,pins = <
352 MX6QDL_PAD_CSI0_DAT7__ 352 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
353 MX6QDL_PAD_CSI0_DAT4__ 353 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
354 MX6QDL_PAD_CSI0_DAT5__ 354 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
355 MX6QDL_PAD_CSI0_DAT6__ 355 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
356 >; 356 >;
357 }; 357 };
358 358
359 pinctrl_can1: can1grp { 359 pinctrl_can1: can1grp {
360 fsl,pins = < 360 fsl,pins = <
361 MX6QDL_PAD_KEY_COL2__F 361 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
362 MX6QDL_PAD_KEY_ROW2__F 362 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
363 >; 363 >;
364 }; 364 };
365 365
366 pinctrl_can2: can2grp { 366 pinctrl_can2: can2grp {
367 fsl,pins = < 367 fsl,pins = <
368 MX6QDL_PAD_KEY_COL4__F 368 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
369 MX6QDL_PAD_KEY_ROW4__F 369 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
370 >; 370 >;
371 }; 371 };
372 372
373 pinctrl_codec: codecgrp { 373 pinctrl_codec: codecgrp {
374 fsl,pins = < 374 fsl,pins = <
375 MX6QDL_PAD_CSI0_MCLK__ 375 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
376 >; 376 >;
377 }; 377 };
378 378
379 pinctrl_ecspi1_mba6: ecspimba6grp { 379 pinctrl_ecspi1_mba6: ecspimba6grp {
380 fsl,pins = < 380 fsl,pins = <
381 MX6QDL_PAD_EIM_D24__GP 381 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
382 >; 382 >;
383 }; 383 };
384 384
385 pinctrl_enet: enetgrp { 385 pinctrl_enet: enetgrp {
386 fsl,pins = < 386 fsl,pins = <
387 /* FEC phy IRQ */ 387 /* FEC phy IRQ */
388 MX6QDL_PAD_ENET_TX_EN_ 388 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
389 /* FEC phy reset */ 389 /* FEC phy reset */
390 MX6QDL_PAD_ENET_CRS_DV 390 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
391 /* DSE = 100, 100k up, 391 /* DSE = 100, 100k up, SPEED = MED */
392 MX6QDL_PAD_ENET_MDIO__ 392 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
393 MX6QDL_PAD_ENET_MDC__E 393 MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
394 /* DSE = 111, pull 100 394 /* DSE = 111, pull 100k up */
395 MX6QDL_PAD_RGMII_TXC__ 395 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
396 MX6QDL_PAD_RGMII_TD0__ 396 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
397 MX6QDL_PAD_RGMII_TD1__ 397 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
398 MX6QDL_PAD_RGMII_TD2__ 398 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
399 MX6QDL_PAD_RGMII_TD3__ 399 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
400 MX6QDL_PAD_RGMII_TX_CT 400 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
401 /* DSE = 111, pull ext 401 /* DSE = 111, pull external */
402 MX6QDL_PAD_RGMII_RXC__ 402 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
403 MX6QDL_PAD_RGMII_RD0__ 403 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
404 MX6QDL_PAD_RGMII_RD1__ 404 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
405 MX6QDL_PAD_RGMII_RD2__ 405 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
406 MX6QDL_PAD_RGMII_RD3__ 406 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
407 MX6QDL_PAD_RGMII_RX_CT 407 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
408 /* HYS = 1, DSE = 111, 408 /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
409 MX6QDL_PAD_ENET_REF_CL 409 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
410 >; 410 >;
411 }; 411 };
412 412
413 pinctrl_gpiobeeper: gpiobeepergrp { 413 pinctrl_gpiobeeper: gpiobeepergrp {
414 fsl,pins = < 414 fsl,pins = <
415 MX6QDL_PAD_SD1_DAT3__G 415 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
416 >; 416 >;
417 }; 417 };
418 418
419 pinctrl_gpiobuttons: gpiobuttongrp { 419 pinctrl_gpiobuttons: gpiobuttongrp {
420 fsl,pins = < 420 fsl,pins = <
421 MX6QDL_PAD_GPIO_17__GP 421 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
422 MX6QDL_PAD_GPIO_18__GP 422 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
423 MX6QDL_PAD_GPIO_8__GPI 423 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
424 >; 424 >;
425 }; 425 };
426 426
427 pinctrl_gpioled: gpioledgrp { 427 pinctrl_gpioled: gpioledgrp {
428 fsl,pins = < 428 fsl,pins = <
429 MX6QDL_PAD_NANDF_CS3__ 429 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
430 MX6QDL_PAD_EIM_BCLK__G 430 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
431 >; 431 >;
432 }; 432 };
433 433
434 pinctrl_hdmi: hdmigrp { 434 pinctrl_hdmi: hdmigrp {
435 /* NOTE: DDC is done via I2C2, 435 /* NOTE: DDC is done via I2C2, so DON'T
436 * configure DDC pins for HDMI 436 * configure DDC pins for HDMI!
437 */ 437 */
438 fsl,pins = < 438 fsl,pins = <
439 MX6QDL_PAD_EIM_A25__HD 439 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
440 >; 440 >;
441 }; 441 };
442 442
443 pinctrl_hog: hoggrp { 443 pinctrl_hog: hoggrp {
444 fsl,pins = < 444 fsl,pins = <
445 MX6QDL_PAD_ENET_RXD1__ 445 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
446 MX6QDL_PAD_ENET_TXD1__ 446 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
447 MX6QDL_PAD_ENET_TXD0__ 447 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
448 448
449 MX6QDL_PAD_NANDF_D1__G 449 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
450 MX6QDL_PAD_NANDF_D2__G 450 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
451 MX6QDL_PAD_NANDF_D3__G 451 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
452 MX6QDL_PAD_SD4_DAT0__G 452 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
453 MX6QDL_PAD_EIM_CS0__GP 453 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
454 MX6QDL_PAD_EIM_CS1__GP 454 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
455 MX6QDL_PAD_EIM_OE__GPI 455 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
456 456
457 MX6QDL_PAD_EIM_D20__GP 457 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
458 MX6QDL_PAD_EIM_D26__GP 458 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
459 MX6QDL_PAD_EIM_D27__GP 459 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
460 MX6QDL_PAD_EIM_D28__GP 460 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
461 MX6QDL_PAD_EIM_D29__GP 461 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
462 462
463 MX6QDL_PAD_KEY_COL0__G 463 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
464 MX6QDL_PAD_KEY_ROW0__G 464 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
465 MX6QDL_PAD_KEY_COL1__G 465 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
466 MX6QDL_PAD_KEY_ROW1__G 466 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
467 467
468 MX6QDL_PAD_CSI0_PIXCLK 468 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
469 MX6QDL_PAD_CSI0_DATA_E 469 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
470 MX6QDL_PAD_CSI0_VSYNC_ 470 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
471 471
472 MX6QDL_PAD_NANDF_ALE__ 472 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
473 MX6QDL_PAD_NANDF_CS1__ 473 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
474 >; 474 >;
475 }; 475 };
476 476
477 pinctrl_i2c2: i2c2grp { 477 pinctrl_i2c2: i2c2grp {
478 fsl,pins = < 478 fsl,pins = <
479 MX6QDL_PAD_KEY_COL3__I 479 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
480 MX6QDL_PAD_KEY_ROW3__I 480 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
481 >; 481 >;
482 }; 482 };
483 483
484 pinctrl_i2c2_recovery: i2c2recoverygrp 484 pinctrl_i2c2_recovery: i2c2recoverygrp {
485 fsl,pins = < 485 fsl,pins = <
486 MX6QDL_PAD_KEY_COL3__G 486 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899
487 MX6QDL_PAD_KEY_ROW3__G 487 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899
488 >; 488 >;
489 }; 489 };
490 490
491 pinctrl_pcie: pciegrp { 491 pinctrl_pcie: pciegrp {
492 fsl,pins = < 492 fsl,pins = <
493 /* HYS = 1, DSE = 110, 493 /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
494 MX6QDL_PAD_SD4_DAT3__G 494 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
495 MX6QDL_PAD_NANDF_CLE__ 495 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
496 MX6QDL_PAD_NANDF_CS0__ 496 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
497 >; 497 >;
498 }; 498 };
499 499
500 pinctrl_pwm1: pwm1grp { 500 pinctrl_pwm1: pwm1grp {
501 fsl,pins = < 501 fsl,pins = <
502 /* 100 k PD, DSE 120 O 502 /* 100 k PD, DSE 120 OHM, SPEED LO */
503 MX6QDL_PAD_GPIO_9__PWM 503 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
504 >; 504 >;
505 }; 505 };
506 506
507 pinctrl_pwm3: pwm3grp { 507 pinctrl_pwm3: pwm3grp {
508 fsl,pins = < 508 fsl,pins = <
509 /* 100 k PD, DSE 120 O 509 /* 100 k PD, DSE 120 OHM, SPEED LO */
510 MX6QDL_PAD_SD4_DAT1__P 510 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
511 >; 511 >;
512 }; 512 };
513 513
514 pinctrl_pwm4: pwm4grp { 514 pinctrl_pwm4: pwm4grp {
515 fsl,pins = < 515 fsl,pins = <
516 /* 100 k PD, DSE 120 O 516 /* 100 k PD, DSE 120 OHM, SPEED LO */
517 MX6QDL_PAD_SD4_DAT2__P 517 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
518 >; 518 >;
519 }; 519 };
520 520
521 pinctrl_regpcie: regpciegrp { 521 pinctrl_regpcie: regpciegrp {
522 fsl,pins = < 522 fsl,pins = <
523 /* HYS = 1, DSE = 110, 523 /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
524 MX6QDL_PAD_NANDF_D0__G 524 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
525 >; 525 >;
526 }; 526 };
527 527
528 pinctrl_uart2: uart2grp { 528 pinctrl_uart2: uart2grp {
529 fsl,pins = < 529 fsl,pins = <
530 MX6QDL_PAD_SD4_DAT4__U 530 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
531 MX6QDL_PAD_SD4_DAT7__U 531 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
532 >; 532 >;
533 }; 533 };
534 534
535 pinctrl_uart3: uart3grp { 535 pinctrl_uart3: uart3grp {
536 fsl,pins = < 536 fsl,pins = <
537 MX6QDL_PAD_SD4_CLK__UA 537 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
538 MX6QDL_PAD_SD4_CMD__UA 538 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
539 MX6QDL_PAD_EIM_D30__UA 539 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
540 MX6QDL_PAD_EIM_D31__UA 540 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
541 >; 541 >;
542 }; 542 };
543 543
544 pinctrl_uart4: uart4grp { 544 pinctrl_uart4: uart4grp {
545 fsl,pins = < 545 fsl,pins = <
546 MX6QDL_PAD_CSI0_DAT12_ 546 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
547 MX6QDL_PAD_CSI0_DAT13_ 547 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
548 MX6QDL_PAD_CSI0_DAT16_ 548 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
549 MX6QDL_PAD_CSI0_DAT17_ 549 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
550 >; 550 >;
551 }; 551 };
552 552
553 pinctrl_uart5: uart5grp { 553 pinctrl_uart5: uart5grp {
554 fsl,pins = < 554 fsl,pins = <
555 MX6QDL_PAD_CSI0_DAT14_ 555 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
556 MX6QDL_PAD_CSI0_DAT15_ 556 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
557 MX6QDL_PAD_CSI0_DAT18_ 557 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
558 MX6QDL_PAD_CSI0_DAT19_ 558 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
559 >; 559 >;
560 }; 560 };
561 561
562 pinctrl_usdhc2: usdhc2grp { 562 pinctrl_usdhc2: usdhc2grp {
563 fsl,pins = < 563 fsl,pins = <
564 /* CLK: 47k Pup SPD_LO 564 /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
565 MX6QDL_PAD_SD2_CLK__SD 565 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
566 /* SD2: 47k Pup SPD_LO 566 /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
567 MX6QDL_PAD_SD2_CMD__SD 567 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
568 MX6QDL_PAD_SD2_DAT0__S 568 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
569 MX6QDL_PAD_SD2_DAT1__S 569 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
570 MX6QDL_PAD_SD2_DAT2__S 570 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
571 MX6QDL_PAD_SD2_DAT3__S 571 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
572 572
573 MX6QDL_PAD_GPIO_4__GPI 573 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
574 MX6QDL_PAD_GPIO_2__GPI 574 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
575 >; 575 >;
576 }; 576 };
577 577
578 pinctrl_usbotg: usbotggrp { 578 pinctrl_usbotg: usbotggrp {
579 fsl,pins = < 579 fsl,pins = <
580 MX6QDL_PAD_EIM_D21__US 580 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
581 MX6QDL_PAD_GPIO_1__USB 581 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
582 MX6QDL_PAD_EIM_D22__US 582 MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
583 >; 583 >;
584 }; 584 };
585 585
586 pinctrl_wdog1: wdog1grp { 586 pinctrl_wdog1: wdog1grp {
587 fsl,pins = < 587 fsl,pins = <
588 /* Watchdog out */ 588 /* Watchdog out */
589 MX6QDL_PAD_SD1_DAT2__W 589 MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
590 >; 590 >;
591 }; 591 };
592 }; 592 };
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