1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2016-2017 Zodiac Inflight Inn 3 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/sound/fsl-imx-audmux.h> 7 #include <dt-bindings/sound/fsl-imx-audmux.h>
8 8
9 / { 9 / {
10 chosen { 10 chosen {
11 stdout-path = &uart1; 11 stdout-path = &uart1;
12 }; 12 };
13 13
14 aliases { 14 aliases {
15 mdio-gpio0 = &mdio1; 15 mdio-gpio0 = &mdio1;
16 rtc0 = &ds1341; 16 rtc0 = &ds1341;
17 }; 17 };
18 18
19 mdio1: mdio { 19 mdio1: mdio {
20 compatible = "virtual,mdio-gpi 20 compatible = "virtual,mdio-gpio";
21 #address-cells = <1>; 21 #address-cells = <1>;
22 #size-cells = <0>; 22 #size-cells = <0>;
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_mdio1>; 24 pinctrl-0 = <&pinctrl_mdio1>;
25 gpios = <&gpio6 5 GPIO_ACTIVE_ 25 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
26 &gpio6 4 GPIO_ACTIVE_ 26 &gpio6 4 GPIO_ACTIVE_HIGH>;
27 27
28 phy: ethernet-phy@0 { 28 phy: ethernet-phy@0 {
29 pinctrl-0 = <&pinctrl_ 29 pinctrl-0 = <&pinctrl_rmii_phy_irq>;
30 pinctrl-names = "defau 30 pinctrl-names = "default";
31 reg = <0>; 31 reg = <0>;
32 interrupt-parent = <&g 32 interrupt-parent = <&gpio3>;
33 interrupts = <30 IRQ_T 33 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
34 }; 34 };
35 }; 35 };
36 36
37 reg_28p0v: regulator-28p0v { 37 reg_28p0v: regulator-28p0v {
38 compatible = "regulator-fixed" 38 compatible = "regulator-fixed";
39 regulator-name = "28V_IN"; 39 regulator-name = "28V_IN";
40 regulator-min-microvolt = <280 40 regulator-min-microvolt = <28000000>;
41 regulator-max-microvolt = <280 41 regulator-max-microvolt = <28000000>;
42 regulator-always-on; 42 regulator-always-on;
43 }; 43 };
44 44
45 reg_12p0v: regulator-12p0v { 45 reg_12p0v: regulator-12p0v {
46 compatible = "regulator-fixed" 46 compatible = "regulator-fixed";
47 vin-supply = <®_28p0v>; 47 vin-supply = <®_28p0v>;
48 regulator-name = "12V_MAIN"; 48 regulator-name = "12V_MAIN";
49 regulator-min-microvolt = <120 49 regulator-min-microvolt = <12000000>;
50 regulator-max-microvolt = <120 50 regulator-max-microvolt = <12000000>;
51 regulator-always-on; 51 regulator-always-on;
52 }; 52 };
53 53
54 reg_5p0v_main: regulator-5p0v-main { 54 reg_5p0v_main: regulator-5p0v-main {
55 compatible = "regulator-fixed" 55 compatible = "regulator-fixed";
56 vin-supply = <®_12p0v>; 56 vin-supply = <®_12p0v>;
57 regulator-name = "5V_MAIN"; 57 regulator-name = "5V_MAIN";
58 regulator-min-microvolt = <500 58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <500 59 regulator-max-microvolt = <5000000>;
60 regulator-always-on; 60 regulator-always-on;
61 }; 61 };
62 62
63 reg_3p3v_pmic: regulator-3p3v-pmic { 63 reg_3p3v_pmic: regulator-3p3v-pmic {
64 compatible = "regulator-fixed" 64 compatible = "regulator-fixed";
65 vin-supply = <®_12p0v>; 65 vin-supply = <®_12p0v>;
66 regulator-name = "PMIC_3V3"; 66 regulator-name = "PMIC_3V3";
67 regulator-min-microvolt = <330 67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <330 68 regulator-max-microvolt = <3300000>;
69 regulator-always-on; 69 regulator-always-on;
70 }; 70 };
71 71
72 reg_3p3v: regulator-3p3v { 72 reg_3p3v: regulator-3p3v {
73 compatible = "regulator-fixed" 73 compatible = "regulator-fixed";
74 vin-supply = <®_3p3v_pmic>; 74 vin-supply = <®_3p3v_pmic>;
75 regulator-name = "GEN_3V3"; 75 regulator-name = "GEN_3V3";
76 regulator-min-microvolt = <330 76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <330 77 regulator-max-microvolt = <3300000>;
78 regulator-always-on; 78 regulator-always-on;
79 }; 79 };
80 80
81 reg_3p3v_sd: regulator-3p3v-sd { 81 reg_3p3v_sd: regulator-3p3v-sd {
82 compatible = "regulator-fixed" 82 compatible = "regulator-fixed";
83 pinctrl-names = "default"; 83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_reg_3p3v 84 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
85 vin-supply = <®_3p3v>; 85 vin-supply = <®_3p3v>;
86 regulator-name = "3V3_SD"; 86 regulator-name = "3V3_SD";
87 regulator-min-microvolt = <330 87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <330 88 regulator-max-microvolt = <3300000>;
89 gpio = <&gpio7 8 GPIO_ACTIVE_H 89 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
90 startup-delay-us = <1000>; 90 startup-delay-us = <1000>;
91 enable-active-high; 91 enable-active-high;
92 regulator-always-on; 92 regulator-always-on;
93 }; 93 };
94 94
95 reg_3p3v_display: regulator-3p3v-displ 95 reg_3p3v_display: regulator-3p3v-display {
96 compatible = "regulator-fixed" 96 compatible = "regulator-fixed";
97 vin-supply = <®_12p0v>; 97 vin-supply = <®_12p0v>;
98 regulator-name = "3V3_DISPLAY" 98 regulator-name = "3V3_DISPLAY";
99 regulator-min-microvolt = <330 99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <330 100 regulator-max-microvolt = <3300000>;
101 regulator-always-on; 101 regulator-always-on;
102 }; 102 };
103 103
104 reg_3p3v_ssd: regulator-3p3v-ssd { 104 reg_3p3v_ssd: regulator-3p3v-ssd {
105 compatible = "regulator-fixed" 105 compatible = "regulator-fixed";
106 vin-supply = <®_12p0v>; 106 vin-supply = <®_12p0v>;
107 regulator-name = "3V3_SSD"; 107 regulator-name = "3V3_SSD";
108 regulator-min-microvolt = <330 108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <330 109 regulator-max-microvolt = <3300000>;
110 regulator-always-on; 110 regulator-always-on;
111 }; 111 };
112 112
113 sound1 { 113 sound1 {
114 compatible = "simple-audio-car 114 compatible = "simple-audio-card";
115 simple-audio-card,name = "fron 115 simple-audio-card,name = "front";
116 simple-audio-card,format = "i2 116 simple-audio-card,format = "i2s";
117 simple-audio-card,bitclock-mas 117 simple-audio-card,bitclock-master = <&sound1_codec>;
118 simple-audio-card,frame-master 118 simple-audio-card,frame-master = <&sound1_codec>;
119 simple-audio-card,widgets = 119 simple-audio-card,widgets =
120 "Headphone", "Headphon 120 "Headphone", "Headphone Jack";
121 simple-audio-card,routing = 121 simple-audio-card,routing =
122 "Headphone Jack", "HPA 122 "Headphone Jack", "HPA1 HPLEFT",
123 "Headphone Jack", "HPA 123 "Headphone Jack", "HPA1 HPRIGHT",
124 "HPA1 LEFTIN", "HPL", 124 "HPA1 LEFTIN", "HPL",
125 "HPA1 RIGHTIN", "HPR"; 125 "HPA1 RIGHTIN", "HPR";
126 simple-audio-card,aux-devs = < 126 simple-audio-card,aux-devs = <&hpa1>;
127 127
128 sound1_cpu: simple-audio-card, 128 sound1_cpu: simple-audio-card,cpu {
129 sound-dai = <&ssi2>; 129 sound-dai = <&ssi2>;
130 }; 130 };
131 131
132 sound1_codec: simple-audio-car 132 sound1_codec: simple-audio-card,codec {
133 sound-dai = <&codec1>; 133 sound-dai = <&codec1>;
134 clocks = <&cs2000>; 134 clocks = <&cs2000>;
135 }; 135 };
136 }; 136 };
137 137
138 sound2 { 138 sound2 {
139 compatible = "simple-audio-car 139 compatible = "simple-audio-card";
140 simple-audio-card,name = "peri 140 simple-audio-card,name = "periph";
141 simple-audio-card,format = "i2 141 simple-audio-card,format = "i2s";
142 simple-audio-card,bitclock-mas 142 simple-audio-card,bitclock-master = <&sound2_codec>;
143 simple-audio-card,frame-master 143 simple-audio-card,frame-master = <&sound2_codec>;
144 simple-audio-card,widgets = 144 simple-audio-card,widgets =
145 "Headphone", "Headphon 145 "Headphone", "Headphone Jack";
146 simple-audio-card,routing = 146 simple-audio-card,routing =
147 "Headphone Jack", "HPA 147 "Headphone Jack", "HPA1 HPLEFT",
148 "Headphone Jack", "HPA 148 "Headphone Jack", "HPA1 HPRIGHT",
149 "HPA1 LEFTIN", "HPL", 149 "HPA1 LEFTIN", "HPL",
150 "HPA1 RIGHTIN", "HPR"; 150 "HPA1 RIGHTIN", "HPR";
151 simple-audio-card,aux-devs = < 151 simple-audio-card,aux-devs = <&hpa2>;
152 152
153 sound2_cpu: simple-audio-card, 153 sound2_cpu: simple-audio-card,cpu {
154 sound-dai = <&ssi1>; 154 sound-dai = <&ssi1>;
155 }; 155 };
156 156
157 sound2_codec: simple-audio-car 157 sound2_codec: simple-audio-card,codec {
158 sound-dai = <&codec2>; 158 sound-dai = <&codec2>;
159 clocks = <&cs2000>; 159 clocks = <&cs2000>;
160 }; 160 };
161 }; 161 };
162 162
163 panel { 163 panel {
164 power-supply = <®_3p3v_disp 164 power-supply = <®_3p3v_display>;
165 backlight = <&sp_backlight>; 165 backlight = <&sp_backlight>;
166 status = "disabled"; 166 status = "disabled";
167 167
168 port { 168 port {
169 panel_in: endpoint { 169 panel_in: endpoint {
170 remote-endpoin 170 remote-endpoint = <&lvds0_out>;
171 }; 171 };
172 }; 172 };
173 }; 173 };
174 174
175 disp0: disp0 { 175 disp0: disp0 {
176 #address-cells = <1>; 176 #address-cells = <1>;
177 #size-cells = <0>; 177 #size-cells = <0>;
178 compatible = "fsl,imx-parallel 178 compatible = "fsl,imx-parallel-display";
179 pinctrl-names = "default"; 179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_disp0>; 180 pinctrl-0 = <&pinctrl_disp0>;
181 status = "disabled"; 181 status = "disabled";
182 182
183 port@0 { 183 port@0 {
184 reg = <0>; 184 reg = <0>;
185 185
186 disp0_in_0: endpoint { 186 disp0_in_0: endpoint {
187 remote-endpoin 187 remote-endpoint = <&ipu1_di0_disp0>;
188 }; 188 };
189 }; 189 };
190 190
191 port@1 { 191 port@1 {
192 reg = <1>; 192 reg = <1>;
193 193
194 disp0_out: endpoint { 194 disp0_out: endpoint {
195 remote-endpoin 195 remote-endpoint = <&tc358767_in>;
196 }; 196 };
197 }; 197 };
198 }; 198 };
199 199
200 cs2000_ref: cs2000-ref { 200 cs2000_ref: cs2000-ref {
201 compatible = "fixed-clock"; 201 compatible = "fixed-clock";
202 #clock-cells = <0>; 202 #clock-cells = <0>;
203 clock-frequency = <24576000>; 203 clock-frequency = <24576000>;
204 }; 204 };
205 205
206 cs2000_in_dummy: cs2000-in-dummy { 206 cs2000_in_dummy: cs2000-in-dummy {
207 compatible = "fixed-clock"; 207 compatible = "fixed-clock";
208 #clock-cells = <0>; 208 #clock-cells = <0>;
209 clock-frequency = <0>; 209 clock-frequency = <0>;
210 }; 210 };
211 211
212 edp_refclk: edp-refclk { 212 edp_refclk: edp-refclk {
213 compatible = "fixed-clock"; 213 compatible = "fixed-clock";
214 #clock-cells = <0>; 214 #clock-cells = <0>;
215 clock-frequency = <19200000>; 215 clock-frequency = <19200000>;
216 }; 216 };
217 }; 217 };
218 218
219 &clks { 219 &clks {
220 assigned-clocks = <&clks IMX6QDL_CLK_L 220 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
221 <&clks IMX6QDL_CLK_L 221 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
222 assigned-clock-parents = <&clks IMX6QD 222 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
223 <&clks IMX6QD 223 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
224 }; 224 };
225 225
226 &cpu0 { 226 &cpu0 {
227 fsl,soc-operating-points = < 227 fsl,soc-operating-points = <
228 /* ARM kHz SOC-PU uV */ 228 /* ARM kHz SOC-PU uV */
229 1200000 1300000 229 1200000 1300000
230 996000 1275000 230 996000 1275000
231 852000 1275000 231 852000 1275000
232 792000 1200000 232 792000 1200000
233 396000 1200000 233 396000 1200000
234 >; 234 >;
235 }; 235 };
236 236
237 ®_arm { 237 ®_arm {
238 vin-supply = <&sw1a_reg>; 238 vin-supply = <&sw1a_reg>;
239 }; 239 };
240 240
241 ®_pu { 241 ®_pu {
242 vin-supply = <&sw1c_reg>; 242 vin-supply = <&sw1c_reg>;
243 }; 243 };
244 244
245 ®_soc { 245 ®_soc {
246 vin-supply = <&sw1c_reg>; 246 vin-supply = <&sw1c_reg>;
247 }; 247 };
248 248
249 &ldb { 249 &ldb {
250 lvds-channel@0 { 250 lvds-channel@0 {
251 port@4 { 251 port@4 {
252 reg = <4>; 252 reg = <4>;
253 253
254 lvds0_out: endpoint { 254 lvds0_out: endpoint {
255 remote-endpoin 255 remote-endpoint = <&panel_in>;
256 }; 256 };
257 }; 257 };
258 }; 258 };
259 }; 259 };
260 260
261 &uart1 { 261 &uart1 {
262 pinctrl-names = "default"; 262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_uart1>; 263 pinctrl-0 = <&pinctrl_uart1>;
264 status = "okay"; 264 status = "okay";
265 }; 265 };
266 266
267 &uart3 { 267 &uart3 {
268 pinctrl-names = "default"; 268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_uart3>; 269 pinctrl-0 = <&pinctrl_uart3>;
270 uart-has-rtscts; 270 uart-has-rtscts;
271 linux,rs485-enabled-at-boot-time; 271 linux,rs485-enabled-at-boot-time;
272 status = "okay"; 272 status = "okay";
273 }; 273 };
274 274
275 &uart4 { 275 &uart4 {
276 pinctrl-names = "default"; 276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart4>; 277 pinctrl-0 = <&pinctrl_uart4>;
278 status = "okay"; 278 status = "okay";
279 279
280 mcu { 280 mcu {
281 compatible = "zii,rave-sp-rdu2 281 compatible = "zii,rave-sp-rdu2";
282 current-speed = <1000000>; 282 current-speed = <1000000>;
283 #address-cells = <1>; 283 #address-cells = <1>;
284 #size-cells = <1>; 284 #size-cells = <1>;
285 285
286 watchdog { 286 watchdog {
287 compatible = "zii,rave 287 compatible = "zii,rave-sp-watchdog";
288 }; 288 };
289 289
290 sp_backlight: backlight { 290 sp_backlight: backlight {
291 compatible = "zii,rave 291 compatible = "zii,rave-sp-backlight";
292 }; 292 };
293 293
294 pwrbutton { 294 pwrbutton {
295 compatible = "zii,rave 295 compatible = "zii,rave-sp-pwrbutton";
296 }; 296 };
297 297
298 eeprom@a3 { 298 eeprom@a3 {
299 compatible = "zii,rave 299 compatible = "zii,rave-sp-eeprom";
300 reg = <0xa3 0x4000>; 300 reg = <0xa3 0x4000>;
301 #address-cells = <1>; 301 #address-cells = <1>;
302 #size-cells = <1>; 302 #size-cells = <1>;
303 zii,eeprom-name = "dds 303 zii,eeprom-name = "dds-eeprom";
304 }; 304 };
305 305
306 eeprom@a4 { 306 eeprom@a4 {
307 compatible = "zii,rave 307 compatible = "zii,rave-sp-eeprom";
308 reg = <0xa4 0x4000>; 308 reg = <0xa4 0x4000>;
309 #address-cells = <1>; 309 #address-cells = <1>;
310 #size-cells = <1>; 310 #size-cells = <1>;
311 zii,eeprom-name = "mai 311 zii,eeprom-name = "main-eeprom";
312 }; 312 };
313 }; 313 };
314 }; 314 };
315 315
316 &ecspi1 { 316 &ecspi1 {
317 pinctrl-names = "default"; 317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_ecspi1>; 318 pinctrl-0 = <&pinctrl_ecspi1>;
319 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW> 319 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
320 status = "okay"; 320 status = "okay";
321 321
322 flash@0 { 322 flash@0 {
323 compatible = "st,m25p128", "je 323 compatible = "st,m25p128", "jedec,spi-nor";
324 spi-max-frequency = <20000000> 324 spi-max-frequency = <20000000>;
325 reg = <0>; 325 reg = <0>;
326 }; 326 };
327 }; 327 };
328 328
329 &gpio3 { 329 &gpio3 {
330 pinctrl-names = "default"; 330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_gpio3_hog>; 331 pinctrl-0 = <&pinctrl_gpio3_hog>;
332 332
333 usb-emulation-hog { 333 usb-emulation-hog {
334 gpio-hog; 334 gpio-hog;
335 gpios = <19 GPIO_ACTIVE_HIGH>; 335 gpios = <19 GPIO_ACTIVE_HIGH>;
336 output-low; 336 output-low;
337 line-name = "usb-emulation"; 337 line-name = "usb-emulation";
338 }; 338 };
339 339
340 usb-mode1-hog { 340 usb-mode1-hog {
341 gpio-hog; 341 gpio-hog;
342 gpios = <20 GPIO_ACTIVE_HIGH>; 342 gpios = <20 GPIO_ACTIVE_HIGH>;
343 output-high; 343 output-high;
344 line-name = "usb-mode1"; 344 line-name = "usb-mode1";
345 }; 345 };
346 346
347 usb-pwr-hog { 347 usb-pwr-hog {
348 gpio-hog; 348 gpio-hog;
349 gpios = <22 GPIO_ACTIVE_LOW>; 349 gpios = <22 GPIO_ACTIVE_LOW>;
350 output-high; 350 output-high;
351 line-name = "usb-pwr-ctrl-en-n 351 line-name = "usb-pwr-ctrl-en-n";
352 }; 352 };
353 353
354 usb-mode2-hog { 354 usb-mode2-hog {
355 gpio-hog; 355 gpio-hog;
356 gpios = <23 GPIO_ACTIVE_HIGH>; 356 gpios = <23 GPIO_ACTIVE_HIGH>;
357 output-high; 357 output-high;
358 line-name = "usb-mode2"; 358 line-name = "usb-mode2";
359 }; 359 };
360 }; 360 };
361 361
362 &i2c1 { 362 &i2c1 {
363 pinctrl-names = "default"; 363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_i2c1>; 364 pinctrl-0 = <&pinctrl_i2c1>;
365 clock-frequency = <100000>; 365 clock-frequency = <100000>;
366 status = "okay"; 366 status = "okay";
367 367
368 codec2: codec@18 { 368 codec2: codec@18 {
369 compatible = "ti,tlv320dac3100 369 compatible = "ti,tlv320dac3100";
370 pinctrl-names = "default"; 370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_codec2>; 371 pinctrl-0 = <&pinctrl_codec2>;
372 reg = <0x18>; 372 reg = <0x18>;
373 #sound-dai-cells = <0>; 373 #sound-dai-cells = <0>;
374 HPVDD-supply = <®_3p3v>; 374 HPVDD-supply = <®_3p3v>;
375 SPRVDD-supply = <®_3p3v>; 375 SPRVDD-supply = <®_3p3v>;
376 SPLVDD-supply = <®_3p3v>; 376 SPLVDD-supply = <®_3p3v>;
377 AVDD-supply = <®_3p3v>; 377 AVDD-supply = <®_3p3v>;
378 IOVDD-supply = <®_3p3v>; 378 IOVDD-supply = <®_3p3v>;
379 DVDD-supply = <&vgen4_reg>; 379 DVDD-supply = <&vgen4_reg>;
380 reset-gpios = <&gpio1 2 GPIO_A 380 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
381 }; 381 };
382 382
383 accel@1c { 383 accel@1c {
384 pinctrl-names = "default"; 384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_accel>; 385 pinctrl-0 = <&pinctrl_accel>;
386 compatible = "fsl,mma8451"; 386 compatible = "fsl,mma8451";
387 reg = <0x1c>; 387 reg = <0x1c>;
388 interrupt-parent = <&gpio1>; 388 interrupt-parent = <&gpio1>;
389 interrupt-names = "INT2"; 389 interrupt-names = "INT2";
390 interrupts = <20 IRQ_TYPE_LEVE 390 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
391 vdd-supply = <®_3p3v>; 391 vdd-supply = <®_3p3v>;
392 vddio-supply = <®_3p3v>; 392 vddio-supply = <®_3p3v>;
393 }; 393 };
394 394
395 hpa2: amp@60 { 395 hpa2: amp@60 {
396 compatible = "ti,tpa6130a2"; 396 compatible = "ti,tpa6130a2";
397 pinctrl-names = "default"; 397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_tpa2>; 398 pinctrl-0 = <&pinctrl_tpa2>;
399 reg = <0x60>; 399 reg = <0x60>;
400 power-gpio = <&gpio1 5 GPIO_AC 400 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
401 Vdd-supply = <®_5p0v_main>; 401 Vdd-supply = <®_5p0v_main>;
402 sound-name-prefix = "HPA1"; 402 sound-name-prefix = "HPA1";
403 }; 403 };
404 404
405 edp-bridge@68 { 405 edp-bridge@68 {
406 compatible = "toshiba,tc358767 406 compatible = "toshiba,tc358767";
407 pinctrl-names = "default"; 407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_tc358767 408 pinctrl-0 = <&pinctrl_tc358767>;
409 reg = <0x68>; 409 reg = <0x68>;
410 shutdown-gpios = <&gpio1 9 GPI 410 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
411 clock-names = "ref"; 411 clock-names = "ref";
412 clocks = <&edp_refclk>; 412 clocks = <&edp_refclk>;
413 status = "disabled"; 413 status = "disabled";
414 414
415 ports { 415 ports {
416 #address-cells = <1>; 416 #address-cells = <1>;
417 #size-cells = <0>; 417 #size-cells = <0>;
418 418
419 port@1 { 419 port@1 {
420 reg = <1>; 420 reg = <1>;
421 421
422 tc358767_in: e 422 tc358767_in: endpoint {
423 remote 423 remote-endpoint = <&disp0_out>;
424 }; 424 };
425 }; 425 };
426 }; 426 };
427 }; 427 };
428 }; 428 };
429 429
430 &i2c2 { 430 &i2c2 {
431 pinctrl-names = "default"; 431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_i2c2>; 432 pinctrl-0 = <&pinctrl_i2c2>;
433 clock-frequency = <100000>; 433 clock-frequency = <100000>;
434 status = "okay"; 434 status = "okay";
435 435
436 pmic@8 { 436 pmic@8 {
437 compatible = "fsl,pfuze100"; 437 compatible = "fsl,pfuze100";
438 pinctrl-names = "default"; 438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_pfuze100 439 pinctrl-0 = <&pinctrl_pfuze100_irq>;
440 reg = <0x08>; 440 reg = <0x08>;
441 interrupt-parent = <&gpio7>; 441 interrupt-parent = <&gpio7>;
442 interrupts = <13 IRQ_TYPE_LEVE 442 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
443 443
444 regulators { 444 regulators {
445 sw1a_reg: sw1ab { 445 sw1a_reg: sw1ab {
446 regulator-min- 446 regulator-min-microvolt = <300000>;
447 regulator-max- 447 regulator-max-microvolt = <1875000>;
448 regulator-boot 448 regulator-boot-on;
449 regulator-alwa 449 regulator-always-on;
450 regulator-ramp 450 regulator-ramp-delay = <6250>;
451 }; 451 };
452 452
453 sw1c_reg: sw1c { 453 sw1c_reg: sw1c {
454 regulator-min- 454 regulator-min-microvolt = <300000>;
455 regulator-max- 455 regulator-max-microvolt = <1875000>;
456 regulator-boot 456 regulator-boot-on;
457 regulator-alwa 457 regulator-always-on;
458 regulator-ramp 458 regulator-ramp-delay = <6250>;
459 }; 459 };
460 460
461 sw2_reg: sw2 { 461 sw2_reg: sw2 {
462 regulator-min- 462 regulator-min-microvolt = <800000>;
463 regulator-max- 463 regulator-max-microvolt = <3000000>;
464 regulator-boot 464 regulator-boot-on;
465 regulator-alwa 465 regulator-always-on;
466 }; 466 };
467 467
468 sw3a_reg: sw3a { 468 sw3a_reg: sw3a {
469 regulator-min- 469 regulator-min-microvolt = <400000>;
470 regulator-max- 470 regulator-max-microvolt = <1500000>;
471 regulator-boot 471 regulator-boot-on;
472 regulator-alwa 472 regulator-always-on;
473 }; 473 };
474 474
475 sw3b_reg: sw3b { 475 sw3b_reg: sw3b {
476 regulator-min- 476 regulator-min-microvolt = <400000>;
477 regulator-max- 477 regulator-max-microvolt = <1500000>;
478 regulator-boot 478 regulator-boot-on;
479 regulator-alwa 479 regulator-always-on;
480 }; 480 };
481 481
482 sw4_reg: sw4 { 482 sw4_reg: sw4 {
483 regulator-min- 483 regulator-min-microvolt = <800000>;
484 regulator-max- 484 regulator-max-microvolt = <1800000>;
485 regulator-boot 485 regulator-boot-on;
486 regulator-alwa 486 regulator-always-on;
487 }; 487 };
488 488
489 snvs_reg: vsnvs { 489 snvs_reg: vsnvs {
490 regulator-min- 490 regulator-min-microvolt = <1000000>;
491 regulator-max- 491 regulator-max-microvolt = <3000000>;
492 regulator-boot 492 regulator-boot-on;
493 regulator-alwa 493 regulator-always-on;
494 }; 494 };
495 495
496 vref_reg: vrefddr { 496 vref_reg: vrefddr {
497 regulator-boot 497 regulator-boot-on;
498 regulator-alwa 498 regulator-always-on;
499 }; 499 };
500 500
501 vgen2_reg: vgen2 { 501 vgen2_reg: vgen2 {
502 regulator-min- 502 regulator-min-microvolt = <1000000>;
503 regulator-max- 503 regulator-max-microvolt = <1500000>;
504 regulator-alwa 504 regulator-always-on;
505 }; 505 };
506 506
507 vgen4_reg: vgen4 { 507 vgen4_reg: vgen4 {
508 regulator-min- 508 regulator-min-microvolt = <1200000>;
509 regulator-max- 509 regulator-max-microvolt = <1800000>;
510 regulator-alwa 510 regulator-always-on;
511 }; 511 };
512 512
513 vgen5_reg: vgen5 { 513 vgen5_reg: vgen5 {
514 regulator-min- 514 regulator-min-microvolt = <1800000>;
515 regulator-max- 515 regulator-max-microvolt = <2500000>;
516 regulator-alwa 516 regulator-always-on;
517 }; 517 };
518 518
519 vgen6_reg: vgen6 { 519 vgen6_reg: vgen6 {
520 regulator-min- 520 regulator-min-microvolt = <1800000>;
521 regulator-max- 521 regulator-max-microvolt = <2800000>;
522 regulator-alwa 522 regulator-always-on;
523 }; 523 };
524 }; 524 };
525 }; 525 };
526 526
527 watchdog@38 { 527 watchdog@38 {
528 compatible = "zii,rave-wdt"; 528 compatible = "zii,rave-wdt";
529 reg = <0x38>; 529 reg = <0x38>;
530 }; 530 };
531 531
532 temp-sense@48 { 532 temp-sense@48 {
533 compatible = "national,lm75"; 533 compatible = "national,lm75";
534 reg = <0x48>; 534 reg = <0x48>;
535 }; 535 };
536 536
537 cs2000: clkgen@4e { 537 cs2000: clkgen@4e {
538 compatible = "cirrus,cs2000-cp 538 compatible = "cirrus,cs2000-cp";
539 reg = <0x4e>; 539 reg = <0x4e>;
540 #clock-cells = <0>; 540 #clock-cells = <0>;
541 clock-names = "clk_in", "ref_c 541 clock-names = "clk_in", "ref_clk";
542 clocks = <&cs2000_in_dummy>, < 542 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
543 assigned-clocks = <&cs2000>; 543 assigned-clocks = <&cs2000>;
544 assigned-clock-rates = <240000 544 assigned-clock-rates = <24000000>;
545 }; 545 };
546 546
547 eeprom@54 { 547 eeprom@54 {
548 compatible = "atmel,24c128"; 548 compatible = "atmel,24c128";
549 reg = <0x54>; 549 reg = <0x54>;
550 }; 550 };
551 551
552 ds1341: rtc@68 { 552 ds1341: rtc@68 {
553 compatible = "dallas,ds1341"; 553 compatible = "dallas,ds1341";
554 reg = <0x68>; 554 reg = <0x68>;
555 }; 555 };
556 }; 556 };
557 557
558 &i2c3 { 558 &i2c3 {
559 pinctrl-names = "default"; 559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_i2c3>; 560 pinctrl-0 = <&pinctrl_i2c3>;
561 clock-frequency = <400000>; 561 clock-frequency = <400000>;
562 status = "okay"; 562 status = "okay";
563 563
564 codec1: codec@18 { 564 codec1: codec@18 {
565 compatible = "ti,tlv320dac3100 565 compatible = "ti,tlv320dac3100";
566 pinctrl-names = "default"; 566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_codec1>; 567 pinctrl-0 = <&pinctrl_codec1>;
568 reg = <0x18>; 568 reg = <0x18>;
569 #sound-dai-cells = <0>; 569 #sound-dai-cells = <0>;
570 HPVDD-supply = <®_3p3v>; 570 HPVDD-supply = <®_3p3v>;
571 SPRVDD-supply = <®_3p3v>; 571 SPRVDD-supply = <®_3p3v>;
572 SPLVDD-supply = <®_3p3v>; 572 SPLVDD-supply = <®_3p3v>;
573 AVDD-supply = <®_3p3v>; 573 AVDD-supply = <®_3p3v>;
574 IOVDD-supply = <®_3p3v>; 574 IOVDD-supply = <®_3p3v>;
575 DVDD-supply = <&vgen4_reg>; 575 DVDD-supply = <&vgen4_reg>;
576 reset-gpios = <&gpio1 0 GPIO_A 576 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
577 }; 577 };
578 578
579 touchscreen@20 { 579 touchscreen@20 {
580 compatible = "syna,rmi4-i2c"; 580 compatible = "syna,rmi4-i2c";
581 pinctrl-names = "default"; 581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_ts>; 582 pinctrl-0 = <&pinctrl_ts>;
583 reg = <0x20>; 583 reg = <0x20>;
584 interrupt-parent = <&gpio1>; 584 interrupt-parent = <&gpio1>;
585 interrupts = <8 IRQ_TYPE_LEVEL 585 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
586 vdd-supply = <®_5p0v_main>; 586 vdd-supply = <®_5p0v_main>;
587 vio-supply = <®_3p3v>; 587 vio-supply = <®_3p3v>;
588 588
589 #address-cells = <1>; 589 #address-cells = <1>;
590 #size-cells = <0>; 590 #size-cells = <0>;
591 591
592 rmi4-f01@1 { 592 rmi4-f01@1 {
593 reg = <0x1>; 593 reg = <0x1>;
594 syna,nosleep-mode = <2 594 syna,nosleep-mode = <2>;
595 }; 595 };
596 596
597 rmi4-f11@11 { 597 rmi4-f11@11 {
598 reg = <0x11>; 598 reg = <0x11>;
599 touchscreen-inverted-x 599 touchscreen-inverted-x;
600 touchscreen-swapped-x- 600 touchscreen-swapped-x-y;
601 syna,sensor-type = <1> 601 syna,sensor-type = <1>;
602 syna,delta-x-threshold 602 syna,delta-x-threshold = <5>;
603 syna,delta-y-threshold 603 syna,delta-y-threshold = <10>;
604 }; 604 };
605 605
606 rmi4-f12@12 { 606 rmi4-f12@12 {
607 reg = <0x12>; 607 reg = <0x12>;
608 touchscreen-inverted-x 608 touchscreen-inverted-x;
609 touchscreen-swapped-x- 609 touchscreen-swapped-x-y;
610 syna,sensor-type = <1> 610 syna,sensor-type = <1>;
611 }; 611 };
612 }; 612 };
613 613
614 touchscreen@2a { 614 touchscreen@2a {
615 compatible = "eeti,exc3000"; 615 compatible = "eeti,exc3000";
616 pinctrl-names = "default"; 616 pinctrl-names = "default";
617 pinctrl-0 = <&pinctrl_ts>; 617 pinctrl-0 = <&pinctrl_ts>;
618 reg = <0x2a>; 618 reg = <0x2a>;
619 interrupt-parent = <&gpio1>; 619 interrupt-parent = <&gpio1>;
620 interrupts = <8 IRQ_TYPE_LEVEL 620 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
621 touchscreen-inverted-x; 621 touchscreen-inverted-x;
622 touchscreen-swapped-x-y; 622 touchscreen-swapped-x-y;
623 status = "disabled"; 623 status = "disabled";
624 }; 624 };
625 625
626 reg_5p0v_user_usb: charger@32 { 626 reg_5p0v_user_usb: charger@32 {
627 compatible = "microchip,ucs100 627 compatible = "microchip,ucs1002";
628 pinctrl-names = "default"; 628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_ucs1002_ 629 pinctrl-0 = <&pinctrl_ucs1002_pins>;
630 reg = <0x32>; 630 reg = <0x32>;
631 interrupts-extended = <&gpio5 631 interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
632 <&gpio3 632 <&gpio3 21 IRQ_TYPE_EDGE_FALLING>;
633 interrupt-names = "a_det", "al 633 interrupt-names = "a_det", "alert";
634 }; 634 };
635 635
636 hpa1: amp@60 { 636 hpa1: amp@60 {
637 compatible = "ti,tpa6130a2"; 637 compatible = "ti,tpa6130a2";
638 pinctrl-names = "default"; 638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_tpa1>; 639 pinctrl-0 = <&pinctrl_tpa1>;
640 reg = <0x60>; 640 reg = <0x60>;
641 power-gpio = <&gpio1 4 GPIO_AC 641 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
642 Vdd-supply = <®_5p0v_main>; 642 Vdd-supply = <®_5p0v_main>;
643 sound-name-prefix = "HPA1"; 643 sound-name-prefix = "HPA1";
644 }; 644 };
645 }; 645 };
646 646
647 &ipu1_di0_disp0 { 647 &ipu1_di0_disp0 {
648 remote-endpoint = <&disp0_in_0>; 648 remote-endpoint = <&disp0_in_0>;
649 }; 649 };
650 650
651 &pcie { 651 &pcie {
652 pinctrl-names = "default"; 652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_pcie>; 653 pinctrl-0 = <&pinctrl_pcie>;
654 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LO 654 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
655 status = "okay"; 655 status = "okay";
656 656
657 host@0 { 657 host@0 {
658 reg = <0 0 0 0 0>; 658 reg = <0 0 0 0 0>;
659 659
660 #address-cells = <3>; 660 #address-cells = <3>;
661 #size-cells = <2>; 661 #size-cells = <2>;
662 662
663 i210: i210@0 { 663 i210: i210@0 {
664 reg = <0 0 0 0 0>; 664 reg = <0 0 0 0 0>;
665 }; 665 };
666 }; 666 };
667 }; 667 };
668 668
669 &usdhc2 { 669 &usdhc2 {
670 pinctrl-names = "default"; 670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_usdhc2>; 671 pinctrl-0 = <&pinctrl_usdhc2>;
672 bus-width = <4>; 672 bus-width = <4>;
673 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 673 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
674 disable-wp; 674 disable-wp;
675 vmmc-supply = <®_3p3v_sd>; 675 vmmc-supply = <®_3p3v_sd>;
676 vqmmc-supply = <®_3p3v>; 676 vqmmc-supply = <®_3p3v>;
677 no-1-8-v; 677 no-1-8-v;
678 no-sdio; 678 no-sdio;
679 status = "okay"; 679 status = "okay";
680 }; 680 };
681 681
682 &usdhc3 { 682 &usdhc3 {
683 pinctrl-names = "default"; 683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_usdhc3>; 684 pinctrl-0 = <&pinctrl_usdhc3>;
685 bus-width = <4>; 685 bus-width = <4>;
686 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 686 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
687 disable-wp; 687 disable-wp;
688 vmmc-supply = <®_3p3v_sd>; 688 vmmc-supply = <®_3p3v_sd>;
689 vqmmc-supply = <®_3p3v>; 689 vqmmc-supply = <®_3p3v>;
690 no-1-8-v; 690 no-1-8-v;
691 no-sdio; 691 no-sdio;
692 status = "okay"; 692 status = "okay";
693 }; 693 };
694 694
695 &usdhc4 { 695 &usdhc4 {
696 pinctrl-names = "default"; 696 pinctrl-names = "default";
697 pinctrl-0 = <&pinctrl_usdhc4>; 697 pinctrl-0 = <&pinctrl_usdhc4>;
698 bus-width = <8>; 698 bus-width = <8>;
699 vmmc-supply = <®_3p3v>; 699 vmmc-supply = <®_3p3v>;
700 vqmmc-supply = <®_3p3v>; 700 vqmmc-supply = <®_3p3v>;
701 no-1-8-v; 701 no-1-8-v;
702 non-removable; 702 non-removable;
703 no-sdio; 703 no-sdio;
704 no-sd; 704 no-sd;
705 status = "okay"; 705 status = "okay";
706 }; 706 };
707 707
708 &sata { 708 &sata {
709 target-supply = <®_3p3v_ssd>; 709 target-supply = <®_3p3v_ssd>;
710 status = "okay"; 710 status = "okay";
711 }; 711 };
712 712
713 &fec { 713 &fec {
714 pinctrl-names = "default"; 714 pinctrl-names = "default";
715 pinctrl-0 = <&pinctrl_enet>; 715 pinctrl-0 = <&pinctrl_enet>;
716 phy-mode = "rmii"; 716 phy-mode = "rmii";
717 phy-handle = <&phy>; 717 phy-handle = <&phy>;
718 phy-reset-gpios = <&gpio1 23 GPIO_ACTI 718 phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
719 phy-reset-duration = <100>; 719 phy-reset-duration = <100>;
720 phy-supply = <®_3p3v>; 720 phy-supply = <®_3p3v>;
721 status = "okay"; 721 status = "okay";
722 722
723 mdio { 723 mdio {
724 #address-cells = <1>; 724 #address-cells = <1>;
725 #size-cells = <0>; 725 #size-cells = <0>;
726 clock-frequency = <12500000>; 726 clock-frequency = <12500000>;
727 suppress-preamble; 727 suppress-preamble;
728 status = "okay"; 728 status = "okay";
729 729
730 switch: switch@0 { 730 switch: switch@0 {
731 compatible = "marvell, 731 compatible = "marvell,mv88e6085";
732 pinctrl-0 = <&pinctrl_ 732 pinctrl-0 = <&pinctrl_switch_irq>;
733 pinctrl-names = "defau 733 pinctrl-names = "default";
734 reg = <0>; 734 reg = <0>;
735 dsa,member = <0 0>; 735 dsa,member = <0 0>;
736 eeprom-length = <512>; 736 eeprom-length = <512>;
737 interrupt-parent = <&g 737 interrupt-parent = <&gpio6>;
738 interrupts = <3 IRQ_TY 738 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
739 interrupt-controller; 739 interrupt-controller;
740 #interrupt-cells = <2> 740 #interrupt-cells = <2>;
741 741
742 ports { 742 ports {
743 #address-cells 743 #address-cells = <1>;
744 #size-cells = 744 #size-cells = <0>;
745 745
746 port@0 { 746 port@0 {
747 reg = 747 reg = <0>;
748 label 748 label = "gigabit_proc";
749 phy-ha 749 phy-handle = <&switchphy0>;
750 }; 750 };
751 751
752 port@1 { 752 port@1 {
753 reg = 753 reg = <1>;
754 label 754 label = "netaux";
755 phy-ha 755 phy-handle = <&switchphy1>;
756 }; 756 };
757 757
758 port@2 { 758 port@2 {
759 reg = 759 reg = <2>;
760 phy-mo 760 phy-mode = "rev-rmii";
761 ethern 761 ethernet = <&fec>;
762 762
763 fixed- 763 fixed-link {
764 764 speed = <100>;
765 765 full-duplex;
766 }; 766 };
767 }; 767 };
768 768
769 port@3 { 769 port@3 {
770 reg = 770 reg = <3>;
771 label 771 label = "netright";
772 phy-ha 772 phy-handle = <&switchphy3>;
773 }; 773 };
774 774
775 port@4 { 775 port@4 {
776 reg = 776 reg = <4>;
777 label 777 label = "netleft";
778 phy-ha 778 phy-handle = <&switchphy4>;
779 }; 779 };
780 }; 780 };
781 781
782 mdio { 782 mdio {
783 #address-cells 783 #address-cells = <1>;
784 #size-cells = 784 #size-cells = <0>;
785 785
786 switchphy0: sw 786 switchphy0: switchphy@0 {
787 reg = 787 reg = <0>;
788 interr 788 interrupt-parent = <&switch>;
789 interr 789 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
790 }; 790 };
791 791
792 switchphy1: sw 792 switchphy1: switchphy@1 {
793 reg = 793 reg = <1>;
794 interr 794 interrupt-parent = <&switch>;
795 interr 795 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
796 }; 796 };
797 797
798 switchphy2: sw 798 switchphy2: switchphy@2 {
799 reg = 799 reg = <2>;
800 interr 800 interrupt-parent = <&switch>;
801 interr 801 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
802 }; 802 };
803 803
804 switchphy3: sw 804 switchphy3: switchphy@3 {
805 reg = 805 reg = <3>;
806 interr 806 interrupt-parent = <&switch>;
807 interr 807 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
808 }; 808 };
809 809
810 switchphy4: sw 810 switchphy4: switchphy@4 {
811 reg = 811 reg = <4>;
812 interr 812 interrupt-parent = <&switch>;
813 interr 813 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
814 }; 814 };
815 }; 815 };
816 }; 816 };
817 }; 817 };
818 }; 818 };
819 819
820 &usbh1 { 820 &usbh1 {
821 vbus-supply = <®_5p0v_main>; 821 vbus-supply = <®_5p0v_main>;
822 disable-over-current; 822 disable-over-current;
823 maximum-speed = "full-speed"; 823 maximum-speed = "full-speed";
824 status = "okay"; 824 status = "okay";
825 }; 825 };
826 826
827 &usbotg { 827 &usbotg {
828 vbus-supply = <®_5p0v_user_usb>; 828 vbus-supply = <®_5p0v_user_usb>;
829 disable-over-current; 829 disable-over-current;
830 dr_mode = "host"; 830 dr_mode = "host";
831 status = "okay"; 831 status = "okay";
832 }; 832 };
833 833
834 &snvs_rtc { 834 &snvs_rtc {
835 status = "disabled"; 835 status = "disabled";
836 }; 836 };
837 837
838 &ssi1 { 838 &ssi1 {
839 status = "okay"; 839 status = "okay";
840 }; 840 };
841 841
842 &ssi2 { 842 &ssi2 {
843 status = "okay"; 843 status = "okay";
844 }; 844 };
845 845
846 &audmux { 846 &audmux {
847 pinctrl-names = "default"; 847 pinctrl-names = "default";
848 pinctrl-0 = <&pinctrl_audmux>; 848 pinctrl-0 = <&pinctrl_audmux>;
849 status = "okay"; 849 status = "okay";
850 850
851 mux-ssi1 { 851 mux-ssi1 {
852 fsl,audmux-port = <0>; 852 fsl,audmux-port = <0>;
853 fsl,port-config = < 853 fsl,port-config = <
854 (IMX_AUDMUX_V2_PTCR_SY 854 (IMX_AUDMUX_V2_PTCR_SYN |
855 IMX_AUDMUX_V2_PTCR_TF 855 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
856 IMX_AUDMUX_V2_PTCR_TC 856 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
857 IMX_AUDMUX_V2_PTCR_TF 857 IMX_AUDMUX_V2_PTCR_TFSDIR |
858 IMX_AUDMUX_V2_PTCR_TC 858 IMX_AUDMUX_V2_PTCR_TCLKDIR)
859 IMX_AUDMUX_V2_PDCR_RXD 859 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
860 >; 860 >;
861 }; 861 };
862 862
863 mux-aud3 { 863 mux-aud3 {
864 fsl,audmux-port = <2>; 864 fsl,audmux-port = <2>;
865 fsl,port-config = < 865 fsl,port-config = <
866 IMX_AUDMUX_V2_PTCR_SYN 866 IMX_AUDMUX_V2_PTCR_SYN
867 IMX_AUDMUX_V2_PDCR_RXD 867 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
868 >; 868 >;
869 }; 869 };
870 870
871 mux-ssi2 { 871 mux-ssi2 {
872 fsl,audmux-port = <1>; 872 fsl,audmux-port = <1>;
873 fsl,port-config = < 873 fsl,port-config = <
874 (IMX_AUDMUX_V2_PTCR_SY 874 (IMX_AUDMUX_V2_PTCR_SYN |
875 IMX_AUDMUX_V2_PTCR_TF 875 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
876 IMX_AUDMUX_V2_PTCR_TC 876 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
877 IMX_AUDMUX_V2_PTCR_TF 877 IMX_AUDMUX_V2_PTCR_TFSDIR |
878 IMX_AUDMUX_V2_PTCR_TC 878 IMX_AUDMUX_V2_PTCR_TCLKDIR)
879 IMX_AUDMUX_V2_PDCR_RXD 879 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
880 >; 880 >;
881 }; 881 };
882 882
883 mux-aud5 { 883 mux-aud5 {
884 fsl,audmux-port = <4>; 884 fsl,audmux-port = <4>;
885 fsl,port-config = < 885 fsl,port-config = <
886 IMX_AUDMUX_V2_PTCR_SYN 886 IMX_AUDMUX_V2_PTCR_SYN
887 IMX_AUDMUX_V2_PDCR_RXD 887 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
888 >; 888 >;
889 }; 889 };
890 }; 890 };
891 891
892 &iomuxc { 892 &iomuxc {
893 pinctrl_accel: accelgrp { 893 pinctrl_accel: accelgrp {
894 fsl,pins = < 894 fsl,pins = <
895 MX6QDL_PAD_SD1_CLK__GP 895 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
896 >; 896 >;
897 }; 897 };
898 898
899 pinctrl_audmux: audmuxgrp { 899 pinctrl_audmux: audmuxgrp {
900 fsl,pins = < 900 fsl,pins = <
901 MX6QDL_PAD_KEY_COL0__A 901 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
902 MX6QDL_PAD_KEY_ROW0__A 902 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
903 MX6QDL_PAD_KEY_COL1__A 903 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
904 MX6QDL_PAD_CSI0_DAT4__ 904 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
905 MX6QDL_PAD_CSI0_DAT5__ 905 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
906 MX6QDL_PAD_CSI0_DAT6__ 906 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
907 >; 907 >;
908 }; 908 };
909 909
910 pinctrl_codec1: dac1grp { 910 pinctrl_codec1: dac1grp {
911 fsl,pins = < 911 fsl,pins = <
912 MX6QDL_PAD_GPIO_0__GPI 912 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038
913 >; 913 >;
914 }; 914 };
915 915
916 pinctrl_codec2: dac2grp { 916 pinctrl_codec2: dac2grp {
917 fsl,pins = < 917 fsl,pins = <
918 MX6QDL_PAD_GPIO_2__GPI 918 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038
919 >; 919 >;
920 }; 920 };
921 921
922 pinctrl_disp0: disp0grp { 922 pinctrl_disp0: disp0grp {
923 fsl,pins = < 923 fsl,pins = <
924 MX6QDL_PAD_DI0_DISP_CL 924 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
925 MX6QDL_PAD_DI0_PIN15__ 925 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9
926 MX6QDL_PAD_DI0_PIN2__I 926 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9
927 MX6QDL_PAD_DI0_PIN3__I 927 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9
928 MX6QDL_PAD_DISP0_DAT0_ 928 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9
929 MX6QDL_PAD_DISP0_DAT1_ 929 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9
930 MX6QDL_PAD_DISP0_DAT2_ 930 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9
931 MX6QDL_PAD_DISP0_DAT3_ 931 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9
932 MX6QDL_PAD_DISP0_DAT4_ 932 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9
933 MX6QDL_PAD_DISP0_DAT5_ 933 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9
934 MX6QDL_PAD_DISP0_DAT6_ 934 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9
935 MX6QDL_PAD_DISP0_DAT7_ 935 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9
936 MX6QDL_PAD_DISP0_DAT8_ 936 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9
937 MX6QDL_PAD_DISP0_DAT9_ 937 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9
938 MX6QDL_PAD_DISP0_DAT10 938 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9
939 MX6QDL_PAD_DISP0_DAT11 939 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9
940 MX6QDL_PAD_DISP0_DAT12 940 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9
941 MX6QDL_PAD_DISP0_DAT13 941 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9
942 MX6QDL_PAD_DISP0_DAT14 942 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9
943 MX6QDL_PAD_DISP0_DAT15 943 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9
944 MX6QDL_PAD_DISP0_DAT16 944 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9
945 MX6QDL_PAD_DISP0_DAT17 945 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9
946 MX6QDL_PAD_DISP0_DAT18 946 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9
947 MX6QDL_PAD_DISP0_DAT19 947 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9
948 MX6QDL_PAD_DISP0_DAT20 948 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9
949 MX6QDL_PAD_DISP0_DAT21 949 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9
950 MX6QDL_PAD_DISP0_DAT22 950 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9
951 MX6QDL_PAD_DISP0_DAT23 951 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9
952 >; 952 >;
953 }; 953 };
954 954
955 pinctrl_ecspi1: ecspi1grp { 955 pinctrl_ecspi1: ecspi1grp {
956 fsl,pins = < 956 fsl,pins = <
957 MX6QDL_PAD_EIM_D17__EC 957 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
958 MX6QDL_PAD_EIM_D18__EC 958 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
959 MX6QDL_PAD_EIM_D16__EC 959 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
960 MX6QDL_PAD_EIM_EB2__GP 960 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1
961 >; 961 >;
962 }; 962 };
963 963
964 pinctrl_enet: enetgrp { 964 pinctrl_enet: enetgrp {
965 fsl,pins = < 965 fsl,pins = <
966 MX6QDL_PAD_ENET_MDC__E 966 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1
967 MX6QDL_PAD_ENET_MDIO__ 967 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1
968 MX6QDL_PAD_ENET_CRS_DV 968 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
969 MX6QDL_PAD_ENET_TX_EN_ 969 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
970 MX6QDL_PAD_ENET_RXD0__ 970 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
971 MX6QDL_PAD_ENET_RXD1__ 971 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
972 MX6QDL_PAD_ENET_TXD0__ 972 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
973 MX6QDL_PAD_ENET_TXD1__ 973 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
974 MX6QDL_PAD_GPIO_16__EN 974 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040
975 MX6QDL_PAD_ENET_RX_ER_ 975 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0
976 MX6QDL_PAD_ENET_REF_CL 976 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
977 >; 977 >;
978 }; 978 };
979 979
980 pinctrl_gpio3_hog: gpio3hoggrp { 980 pinctrl_gpio3_hog: gpio3hoggrp {
981 fsl,pins = < 981 fsl,pins = <
982 MX6QDL_PAD_EIM_D19__GP 982 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
983 MX6QDL_PAD_EIM_D20__GP 983 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
984 MX6QDL_PAD_EIM_D22__GP 984 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
985 MX6QDL_PAD_EIM_D23__GP 985 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
986 >; 986 >;
987 }; 987 };
988 988
989 pinctrl_i2c1: i2c1grp { 989 pinctrl_i2c1: i2c1grp {
990 fsl,pins = < 990 fsl,pins = <
991 MX6QDL_PAD_CSI0_DAT8__ 991 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b811
992 MX6QDL_PAD_CSI0_DAT9__ 992 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b811
993 >; 993 >;
994 }; 994 };
995 995
996 pinctrl_i2c2: i2c2grp { 996 pinctrl_i2c2: i2c2grp {
997 fsl,pins = < 997 fsl,pins = <
998 MX6QDL_PAD_KEY_COL3__I 998 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b811
999 MX6QDL_PAD_KEY_ROW3__I 999 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b811
1000 >; 1000 >;
1001 }; 1001 };
1002 1002
1003 pinctrl_i2c3: i2c3grp { 1003 pinctrl_i2c3: i2c3grp {
1004 fsl,pins = < 1004 fsl,pins = <
1005 MX6QDL_PAD_GPIO_3__I2 1005 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b811
1006 MX6QDL_PAD_GPIO_6__I2 1006 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b811
1007 >; 1007 >;
1008 }; 1008 };
1009 1009
1010 pinctrl_mdio1: bitbangmdiogrp { 1010 pinctrl_mdio1: bitbangmdiogrp {
1011 fsl,pins = < 1011 fsl,pins = <
1012 /* Bitbang MDIO for D 1012 /* Bitbang MDIO for DEB Switch */
1013 MX6QDL_PAD_CSI0_DAT19 1013 MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030
1014 MX6QDL_PAD_CSI0_DAT18 1014 MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830
1015 >; 1015 >;
1016 }; 1016 };
1017 1017
1018 pinctrl_pcie: pciegrp { 1018 pinctrl_pcie: pciegrp {
1019 fsl,pins = < 1019 fsl,pins = <
1020 MX6QDL_PAD_GPIO_17__G 1020 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038
1021 >; 1021 >;
1022 }; 1022 };
1023 1023
1024 pinctrl_pfuze100_irq: pfuze100grp { 1024 pinctrl_pfuze100_irq: pfuze100grp {
1025 fsl,pins = < 1025 fsl,pins = <
1026 MX6QDL_PAD_GPIO_18__G 1026 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000
1027 >; 1027 >;
1028 }; 1028 };
1029 1029
1030 pinctrl_reg_3p3v_sd: mmcsupply1grp { 1030 pinctrl_reg_3p3v_sd: mmcsupply1grp {
1031 fsl,pins = < 1031 fsl,pins = <
1032 MX6QDL_PAD_SD3_RST__G 1032 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858
1033 >; 1033 >;
1034 }; 1034 };
1035 1035
1036 pinctrl_rmii_phy_irq: phygrp { 1036 pinctrl_rmii_phy_irq: phygrp {
1037 fsl,pins = < 1037 fsl,pins = <
1038 MX6QDL_PAD_EIM_D30__G 1038 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
1039 >; 1039 >;
1040 }; 1040 };
1041 1041
1042 pinctrl_switch_irq: switchgrp { 1042 pinctrl_switch_irq: switchgrp {
1043 fsl,pins = < 1043 fsl,pins = <
1044 MX6QDL_PAD_CSI0_DAT17 1044 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000
1045 >; 1045 >;
1046 }; 1046 };
1047 1047
1048 pinctrl_tc358767: tc358767grp { 1048 pinctrl_tc358767: tc358767grp {
1049 fsl,pins = < 1049 fsl,pins = <
1050 MX6QDL_PAD_GPIO_9__GP 1050 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
1051 >; 1051 >;
1052 }; 1052 };
1053 1053
1054 pinctrl_tpa1: tpa6130-1grp { 1054 pinctrl_tpa1: tpa6130-1grp {
1055 fsl,pins = < 1055 fsl,pins = <
1056 MX6QDL_PAD_GPIO_4__GP 1056 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038
1057 >; 1057 >;
1058 }; 1058 };
1059 1059
1060 pinctrl_tpa2: tpa6130-2grp { 1060 pinctrl_tpa2: tpa6130-2grp {
1061 fsl,pins = < 1061 fsl,pins = <
1062 MX6QDL_PAD_GPIO_5__GP 1062 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038
1063 >; 1063 >;
1064 }; 1064 };
1065 1065
1066 pinctrl_ts: tsgrp { 1066 pinctrl_ts: tsgrp {
1067 fsl,pins = < 1067 fsl,pins = <
1068 MX6QDL_PAD_GPIO_8__GP 1068 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
1069 MX6QDL_PAD_GPIO_7__GP 1069 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
1070 >; 1070 >;
1071 }; 1071 };
1072 1072
1073 pinctrl_uart1: uart1grp { 1073 pinctrl_uart1: uart1grp {
1074 fsl,pins = < 1074 fsl,pins = <
1075 MX6QDL_PAD_CSI0_DAT10 1075 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1076 MX6QDL_PAD_CSI0_DAT11 1076 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1077 >; 1077 >;
1078 }; 1078 };
1079 1079
1080 pinctrl_uart3: uart3grp { 1080 pinctrl_uart3: uart3grp {
1081 fsl,pins = < 1081 fsl,pins = <
1082 MX6QDL_PAD_EIM_D24__U 1082 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1083 MX6QDL_PAD_EIM_D25__U 1083 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1084 MX6QDL_PAD_EIM_D31__U 1084 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
1085 >; 1085 >;
1086 }; 1086 };
1087 1087
1088 pinctrl_uart4: uart4grp { 1088 pinctrl_uart4: uart4grp {
1089 fsl,pins = < 1089 fsl,pins = <
1090 MX6QDL_PAD_CSI0_DAT12 1090 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
1091 MX6QDL_PAD_CSI0_DAT13 1091 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
1092 >; 1092 >;
1093 }; 1093 };
1094 1094
1095 pinctrl_ucs1002_pins: ucs1002grp { 1095 pinctrl_ucs1002_pins: ucs1002grp {
1096 fsl,pins = < 1096 fsl,pins = <
1097 MX6QDL_PAD_EIM_A25__G 1097 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
1098 MX6QDL_PAD_EIM_D21__G 1098 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
1099 >; 1099 >;
1100 }; 1100 };
1101 1101
1102 pinctrl_usdhc2: usdhc2grp { 1102 pinctrl_usdhc2: usdhc2grp {
1103 fsl,pins = < 1103 fsl,pins = <
1104 MX6QDL_PAD_SD2_CMD__S 1104 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
1105 MX6QDL_PAD_SD2_CLK__S 1105 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
1106 MX6QDL_PAD_SD2_DAT0__ 1106 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1107 MX6QDL_PAD_SD2_DAT1__ 1107 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1108 MX6QDL_PAD_SD2_DAT2__ 1108 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1109 MX6QDL_PAD_SD2_DAT3__ 1109 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1110 MX6QDL_PAD_NANDF_D2__ 1110 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
1111 >; 1111 >;
1112 }; 1112 };
1113 1113
1114 pinctrl_usdhc3: usdhc3grp { 1114 pinctrl_usdhc3: usdhc3grp {
1115 fsl,pins = < 1115 fsl,pins = <
1116 MX6QDL_PAD_SD3_CMD__S 1116 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059
1117 MX6QDL_PAD_SD3_CLK__S 1117 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
1118 MX6QDL_PAD_SD3_DAT0__ 1118 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1119 MX6QDL_PAD_SD3_DAT1__ 1119 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1120 MX6QDL_PAD_SD3_DAT2__ 1120 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1121 MX6QDL_PAD_SD3_DAT3__ 1121 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1122 MX6QDL_PAD_NANDF_D0__ 1122 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040
1123 1123
1124 >; 1124 >;
1125 }; 1125 };
1126 1126
1127 pinctrl_usdhc4: usdhc4grp { 1127 pinctrl_usdhc4: usdhc4grp {
1128 fsl,pins = < 1128 fsl,pins = <
1129 MX6QDL_PAD_SD4_CMD__S 1129 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1130 MX6QDL_PAD_SD4_CLK__S 1130 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1131 MX6QDL_PAD_SD4_DAT0__ 1131 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1132 MX6QDL_PAD_SD4_DAT1__ 1132 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1133 MX6QDL_PAD_SD4_DAT2__ 1133 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1134 MX6QDL_PAD_SD4_DAT3__ 1134 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1135 MX6QDL_PAD_SD4_DAT4__ 1135 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1136 MX6QDL_PAD_SD4_DAT5__ 1136 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1137 MX6QDL_PAD_SD4_DAT6__ 1137 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1138 MX6QDL_PAD_SD4_DAT7__ 1138 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1139 MX6QDL_PAD_NANDF_ALE_ 1139 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1
1140 >; 1140 >;
1141 }; 1141 };
1142 }; 1142 };
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