1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 // 2 //
3 // Copyright 2016 Freescale Semiconductor, Inc 3 // Copyright 2016 Freescale Semiconductor, Inc.
4 4
5 #include "imx6q.dtsi" 5 #include "imx6q.dtsi"
6 6
7 / { 7 / {
8 soc { 8 soc {
9 ocram2: sram@940000 { 9 ocram2: sram@940000 {
10 compatible = "mmio-sra 10 compatible = "mmio-sram";
11 reg = <0x00940000 0x20 11 reg = <0x00940000 0x20000>;
12 ranges = <0 0x00940000 12 ranges = <0 0x00940000 0x20000>;
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 clocks = <&clks IMX6QD 15 clocks = <&clks IMX6QDL_CLK_OCRAM>;
16 }; 16 };
17 17
18 ocram3: sram@960000 { 18 ocram3: sram@960000 {
19 compatible = "mmio-sra 19 compatible = "mmio-sram";
20 reg = <0x00960000 0x20 20 reg = <0x00960000 0x20000>;
21 ranges = <0 0x00960000 21 ranges = <0 0x00960000 0x20000>;
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <1>; 23 #size-cells = <1>;
24 clocks = <&clks IMX6QD 24 clocks = <&clks IMX6QDL_CLK_OCRAM>;
25 }; 25 };
26 26
27 bus@2100000 { 27 bus@2100000 {
28 pre1: pre@21c8000 { 28 pre1: pre@21c8000 {
29 compatible = " 29 compatible = "fsl,imx6qp-pre";
30 reg = <0x021c8 30 reg = <0x021c8000 0x1000>;
31 interrupts = < 31 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
32 clocks = <&clk 32 clocks = <&clks IMX6QDL_CLK_PRE0>;
33 clock-names = 33 clock-names = "axi";
34 fsl,iram = <&o 34 fsl,iram = <&ocram2>;
35 }; 35 };
36 36
37 pre2: pre@21c9000 { 37 pre2: pre@21c9000 {
38 compatible = " 38 compatible = "fsl,imx6qp-pre";
39 reg = <0x021c9 39 reg = <0x021c9000 0x1000>;
40 interrupts = < 40 interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
41 clocks = <&clk 41 clocks = <&clks IMX6QDL_CLK_PRE1>;
42 clock-names = 42 clock-names = "axi";
43 fsl,iram = <&o 43 fsl,iram = <&ocram2>;
44 }; 44 };
45 45
46 pre3: pre@21ca000 { 46 pre3: pre@21ca000 {
47 compatible = " 47 compatible = "fsl,imx6qp-pre";
48 reg = <0x021ca 48 reg = <0x021ca000 0x1000>;
49 interrupts = < 49 interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
50 clocks = <&clk 50 clocks = <&clks IMX6QDL_CLK_PRE2>;
51 clock-names = 51 clock-names = "axi";
52 fsl,iram = <&o 52 fsl,iram = <&ocram3>;
53 }; 53 };
54 54
55 pre4: pre@21cb000 { 55 pre4: pre@21cb000 {
56 compatible = " 56 compatible = "fsl,imx6qp-pre";
57 reg = <0x021cb 57 reg = <0x021cb000 0x1000>;
58 interrupts = < 58 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
59 clocks = <&clk 59 clocks = <&clks IMX6QDL_CLK_PRE3>;
60 clock-names = 60 clock-names = "axi";
61 fsl,iram = <&o 61 fsl,iram = <&ocram3>;
62 }; 62 };
63 63
64 prg1: prg@21cc000 { 64 prg1: prg@21cc000 {
65 compatible = " 65 compatible = "fsl,imx6qp-prg";
66 reg = <0x021cc 66 reg = <0x021cc000 0x1000>;
67 clocks = <&clk 67 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
68 <&clk 68 <&clks IMX6QDL_CLK_PRG0_AXI>;
69 clock-names = 69 clock-names = "ipg", "axi";
70 fsl,pres = <&p 70 fsl,pres = <&pre1>, <&pre2>, <&pre3>;
71 }; 71 };
72 72
73 prg2: prg@21cd000 { 73 prg2: prg@21cd000 {
74 compatible = " 74 compatible = "fsl,imx6qp-prg";
75 reg = <0x021cd 75 reg = <0x021cd000 0x1000>;
76 clocks = <&clk 76 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
77 <&clk 77 <&clks IMX6QDL_CLK_PRG1_AXI>;
78 clock-names = 78 clock-names = "ipg", "axi";
79 fsl,pres = <&p 79 fsl,pres = <&pre4>, <&pre2>, <&pre3>;
80 }; 80 };
81 }; 81 };
82 }; 82 };
83 }; 83 };
84 84
85 &fec { 85 &fec {
86 interrupts = <0 118 IRQ_TYPE_LEVEL_HIG 86 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
87 <0 119 IRQ_TYPE_LEVEL_HIG 87 <0 119 IRQ_TYPE_LEVEL_HIGH>;
88 }; 88 };
89 89
90 &gpc { 90 &gpc {
91 compatible = "fsl,imx6qp-gpc", "fsl,im 91 compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
92 }; 92 };
93 93
94 &ipu1 { 94 &ipu1 {
95 compatible = "fsl,imx6qp-ipu", "fsl,im 95 compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
96 fsl,prg = <&prg1>; 96 fsl,prg = <&prg1>;
97 }; 97 };
98 98
99 &ipu2 { 99 &ipu2 {
100 compatible = "fsl,imx6qp-ipu", "fsl,im 100 compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
101 fsl,prg = <&prg2>; 101 fsl,prg = <&prg2>;
102 }; 102 };
103 103
104 &ldb { 104 &ldb {
105 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SE 105 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
106 <&clks IMX6QDL_CLK_IPU1_DI0_S 106 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
107 <&clks IMX6QDL_CLK_IPU2_DI0_S 107 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
108 <&clks IMX6QDL_CLK_LDB_DI0_PO 108 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
109 clock-names = "di0_pll", "di1_pll", 109 clock-names = "di0_pll", "di1_pll",
110 "di0_sel", "di1_sel", "d 110 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
111 "di0", "di1"; 111 "di0", "di1";
112 }; 112 };
113 113
114 &mmdc0 { 114 &mmdc0 {
115 compatible = "fsl,imx6qp-mmdc", "fsl,i 115 compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
116 }; 116 };
117 117
118 &pcie { 118 &pcie {
119 compatible = "fsl,imx6qp-pcie"; 119 compatible = "fsl,imx6qp-pcie";
120 }; 120 };
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