1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 // 2 //
3 // Copyright 2014 Freescale Semiconductor, Inc 3 // Copyright 2014 Freescale Semiconductor, Inc.
4 4
5 #include <dt-bindings/clock/imx6sx-clock.h> 5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h" 9 #include "imx6sx-pinfunc.h"
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 /* 14 /*
15 * The decompressor and also some boot 15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be ava 16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS 17 * command line and merge other ATAGS info.
18 */ 18 */
19 chosen {}; 19 chosen {};
20 20
21 aliases { 21 aliases {
22 can0 = &flexcan1; 22 can0 = &flexcan1;
23 can1 = &flexcan2; 23 can1 = &flexcan2;
24 ethernet0 = &fec1; 24 ethernet0 = &fec1;
25 ethernet1 = &fec2; 25 ethernet1 = &fec2;
26 gpio0 = &gpio1; 26 gpio0 = &gpio1;
27 gpio1 = &gpio2; 27 gpio1 = &gpio2;
28 gpio2 = &gpio3; 28 gpio2 = &gpio3;
29 gpio3 = &gpio4; 29 gpio3 = &gpio4;
30 gpio4 = &gpio5; 30 gpio4 = &gpio5;
31 gpio5 = &gpio6; 31 gpio5 = &gpio6;
32 gpio6 = &gpio7; 32 gpio6 = &gpio7;
33 i2c0 = &i2c1; 33 i2c0 = &i2c1;
34 i2c1 = &i2c2; 34 i2c1 = &i2c2;
35 i2c2 = &i2c3; 35 i2c2 = &i2c3;
36 i2c3 = &i2c4; 36 i2c3 = &i2c4;
37 mmc0 = &usdhc1; 37 mmc0 = &usdhc1;
38 mmc1 = &usdhc2; 38 mmc1 = &usdhc2;
39 mmc2 = &usdhc3; 39 mmc2 = &usdhc3;
40 mmc3 = &usdhc4; 40 mmc3 = &usdhc4;
41 serial0 = &uart1; 41 serial0 = &uart1;
42 serial1 = &uart2; 42 serial1 = &uart2;
43 serial2 = &uart3; 43 serial2 = &uart3;
44 serial3 = &uart4; 44 serial3 = &uart4;
45 serial4 = &uart5; 45 serial4 = &uart5;
46 serial5 = &uart6; 46 serial5 = &uart6;
47 spi0 = &ecspi1; 47 spi0 = &ecspi1;
48 spi1 = &ecspi2; 48 spi1 = &ecspi2;
49 spi2 = &ecspi3; 49 spi2 = &ecspi3;
50 spi3 = &ecspi4; 50 spi3 = &ecspi4;
51 spi4 = &ecspi5; 51 spi4 = &ecspi5;
52 usb0 = &usbotg1; 52 usb0 = &usbotg1;
53 usb1 = &usbotg2; 53 usb1 = &usbotg2;
54 usb2 = &usbh; 54 usb2 = &usbh;
55 usbphy0 = &usbphy1; 55 usbphy0 = &usbphy1;
56 usbphy1 = &usbphy2; 56 usbphy1 = &usbphy2;
57 }; 57 };
58 58
59 cpus { 59 cpus {
60 #address-cells = <1>; 60 #address-cells = <1>;
61 #size-cells = <0>; 61 #size-cells = <0>;
62 62
63 cpu0: cpu@0 { 63 cpu0: cpu@0 {
64 compatible = "arm,cort 64 compatible = "arm,cortex-a9";
65 device_type = "cpu"; 65 device_type = "cpu";
66 reg = <0>; 66 reg = <0>;
67 next-level-cache = <&L 67 next-level-cache = <&L2>;
68 operating-points = < 68 operating-points = <
69 /* kHz uV * 69 /* kHz uV */
70 996000 125000 70 996000 1250000
71 792000 117500 71 792000 1175000
72 396000 107500 72 396000 1075000
73 198000 975000 73 198000 975000
74 >; 74 >;
75 fsl,soc-operating-poin 75 fsl,soc-operating-points = <
76 /* ARM kHz SO 76 /* ARM kHz SOC uV */
77 996000 11 77 996000 1175000
78 792000 11 78 792000 1175000
79 396000 11 79 396000 1175000
80 198000 11 80 198000 1175000
81 >; 81 >;
82 clock-latency = <61036 82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>; 83 #cooling-cells = <2>;
84 clocks = <&clks IMX6SX 84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX 85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX 86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX 87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX 88 <&clks IMX6SX_CLK_PLL1_SYS>;
89 clock-names = "arm", " 89 clock-names = "arm", "pll2_pfd2_396m", "step",
90 "pll1_sw 90 "pll1_sw", "pll1_sys";
91 arm-supply = <®_arm 91 arm-supply = <®_arm>;
92 soc-supply = <®_soc 92 soc-supply = <®_soc>;
93 nvmem-cells = <&cpu_sp 93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "sp 94 nvmem-cell-names = "speed_grade";
95 }; 95 };
96 }; 96 };
97 97
98 ckil: clock-ckil { 98 ckil: clock-ckil {
99 compatible = "fixed-clock"; 99 compatible = "fixed-clock";
100 #clock-cells = <0>; 100 #clock-cells = <0>;
101 clock-frequency = <32768>; 101 clock-frequency = <32768>;
102 clock-output-names = "ckil"; 102 clock-output-names = "ckil";
103 }; 103 };
104 104
105 osc: clock-osc { 105 osc: clock-osc {
106 compatible = "fixed-clock"; 106 compatible = "fixed-clock";
107 #clock-cells = <0>; 107 #clock-cells = <0>;
108 clock-frequency = <24000000>; 108 clock-frequency = <24000000>;
109 clock-output-names = "osc"; 109 clock-output-names = "osc";
110 }; 110 };
111 111
112 ipp_di0: clock-ipp-di0 { 112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock"; 113 compatible = "fixed-clock";
114 #clock-cells = <0>; 114 #clock-cells = <0>;
115 clock-frequency = <0>; 115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0" 116 clock-output-names = "ipp_di0";
117 }; 117 };
118 118
119 ipp_di1: clock-ipp-di1 { 119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock"; 120 compatible = "fixed-clock";
121 #clock-cells = <0>; 121 #clock-cells = <0>;
122 clock-frequency = <0>; 122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1" 123 clock-output-names = "ipp_di1";
124 }; 124 };
125 125
126 anaclk1: clock-anaclk1 { 126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock"; 127 compatible = "fixed-clock";
128 #clock-cells = <0>; 128 #clock-cells = <0>;
129 clock-frequency = <0>; 129 clock-frequency = <0>;
130 clock-output-names = "anaclk1" 130 clock-output-names = "anaclk1";
131 }; 131 };
132 132
133 anaclk2: clock-anaclk2 { 133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock"; 134 compatible = "fixed-clock";
135 #clock-cells = <0>; 135 #clock-cells = <0>;
136 clock-frequency = <0>; 136 clock-frequency = <0>;
137 clock-output-names = "anaclk2" 137 clock-output-names = "anaclk2";
138 }; 138 };
139 139
140 mqs: mqs { 140 mqs: mqs {
141 compatible = "fsl,imx6sx-mqs"; 141 compatible = "fsl,imx6sx-mqs";
142 gpr = <&gpr>; 142 gpr = <&gpr>;
143 status = "disabled"; 143 status = "disabled";
144 }; 144 };
145 145
146 pmu { 146 pmu {
147 compatible = "arm,cortex-a9-pm 147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>; 148 interrupt-parent = <&gpc>;
149 interrupts = <GIC_SPI 94 IRQ_T 149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
150 }; 150 };
151 151
152 usbphynop1: usbphynop1 { 152 usbphynop1: usbphynop1 {
153 compatible = "usb-nop-xceiv"; 153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>; 154 #phy-cells = <0>;
155 }; 155 };
156 156
157 soc: soc { 157 soc: soc {
158 #address-cells = <1>; 158 #address-cells = <1>;
159 #size-cells = <1>; 159 #size-cells = <1>;
160 compatible = "simple-bus"; 160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>; 161 interrupt-parent = <&gpc>;
162 ranges; 162 ranges;
163 163
164 ocram_s: sram@8f8000 { 164 ocram_s: sram@8f8000 {
165 compatible = "mmio-sra 165 compatible = "mmio-sram";
166 reg = <0x008f8000 0x40 166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 167 ranges = <0 0x008f8000 0x4000>;
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <1>; 169 #size-cells = <1>;
170 clocks = <&clks IMX6SX 170 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
171 }; 171 };
172 172
173 ocram: sram@900000 { 173 ocram: sram@900000 {
174 compatible = "mmio-sra 174 compatible = "mmio-sram";
175 reg = <0x00900000 0x20 175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 176 ranges = <0 0x00900000 0x20000>;
177 #address-cells = <1>; 177 #address-cells = <1>;
178 #size-cells = <1>; 178 #size-cells = <1>;
179 clocks = <&clks IMX6SX 179 clocks = <&clks IMX6SX_CLK_OCRAM>;
180 }; 180 };
181 181
182 intc: interrupt-controller@a01 182 intc: interrupt-controller@a01000 {
183 compatible = "arm,cort 183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3> 184 #interrupt-cells = <3>;
185 interrupt-controller; 185 interrupt-controller;
186 reg = <0x00a01000 0x10 186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x10 187 <0x00a00100 0x100>;
188 interrupt-parent = <&i 188 interrupt-parent = <&intc>;
189 }; 189 };
190 190
191 L2: cache-controller@a02000 { 191 L2: cache-controller@a02000 {
192 compatible = "arm,pl31 192 compatible = "arm,pl310-cache";
193 reg = <0x00a02000 0x10 193 reg = <0x00a02000 0x1000>;
194 interrupts = <GIC_SPI 194 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
195 cache-unified; 195 cache-unified;
196 cache-level = <2>; 196 cache-level = <2>;
197 arm,tag-latency = <4 2 197 arm,tag-latency = <4 2 3>;
198 arm,data-latency = <4 198 arm,data-latency = <4 2 3>;
199 }; 199 };
200 200
201 gpu: gpu@1800000 { 201 gpu: gpu@1800000 {
202 compatible = "vivante, 202 compatible = "vivante,gc";
203 reg = <0x01800000 0x40 203 reg = <0x01800000 0x4000>;
204 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6SX 205 clocks = <&clks IMX6SX_CLK_GPU>,
206 <&clks IMX6SX 206 <&clks IMX6SX_CLK_GPU>,
207 <&clks IMX6SX 207 <&clks IMX6SX_CLK_GPU>;
208 clock-names = "bus", " 208 clock-names = "bus", "core", "shader";
209 power-domains = <&pd_p 209 power-domains = <&pd_pu>;
210 }; 210 };
211 211
212 dma_apbh: dma-controller@18040 212 dma_apbh: dma-controller@1804000 {
213 compatible = "fsl,imx6 213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
214 reg = <0x01804000 0x20 214 reg = <0x01804000 0x2000>;
215 interrupts = <GIC_SPI 215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
219 #dma-cells = <1>; 219 #dma-cells = <1>;
220 dma-channels = <4>; 220 dma-channels = <4>;
221 clocks = <&clks IMX6SX 221 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
222 }; 222 };
223 223
224 gpmi: nand-controller@1806000 224 gpmi: nand-controller@1806000 {
225 compatible = "fsl,imx6 225 compatible = "fsl,imx6sx-gpmi-nand";
226 #address-cells = <1>; 226 #address-cells = <1>;
227 #size-cells = <1>; 227 #size-cells = <1>;
228 reg = <0x01806000 0x20 228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
229 reg-names = "gpmi-nand 229 reg-names = "gpmi-nand", "bch";
230 interrupts = <GIC_SPI 230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "bch 231 interrupt-names = "bch";
232 clocks = <&clks IMX6SX 232 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
233 <&clks IMX6SX 233 <&clks IMX6SX_CLK_GPMI_APB>,
234 <&clks IMX6SX 234 <&clks IMX6SX_CLK_GPMI_BCH>,
235 <&clks IMX6SX 235 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
236 <&clks IMX6SX 236 <&clks IMX6SX_CLK_PER1_BCH>;
237 clock-names = "gpmi_io 237 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
238 "gpmi_bc 238 "gpmi_bch_apb", "per1_bch";
239 dmas = <&dma_apbh 0>; 239 dmas = <&dma_apbh 0>;
240 dma-names = "rx-tx"; 240 dma-names = "rx-tx";
241 status = "disabled"; 241 status = "disabled";
242 }; 242 };
243 243
244 aips1: bus@2000000 { 244 aips1: bus@2000000 {
245 compatible = "fsl,aips 245 compatible = "fsl,aips-bus", "simple-bus";
246 #address-cells = <1>; 246 #address-cells = <1>;
247 #size-cells = <1>; 247 #size-cells = <1>;
248 reg = <0x02000000 0x10 248 reg = <0x02000000 0x100000>;
249 ranges; 249 ranges;
250 250
251 spba-bus@2000000 { 251 spba-bus@2000000 {
252 compatible = " 252 compatible = "fsl,spba-bus", "simple-bus";
253 #address-cells 253 #address-cells = <1>;
254 #size-cells = 254 #size-cells = <1>;
255 reg = <0x02000 255 reg = <0x02000000 0x40000>;
256 ranges; 256 ranges;
257 257
258 spdif: spdif@2 258 spdif: spdif@2004000 {
259 compat 259 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
260 reg = 260 reg = <0x02004000 0x4000>;
261 interr 261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
262 dmas = 262 dmas = <&sdma 14 18 0>,
263 263 <&sdma 15 18 0>;
264 dma-na 264 dma-names = "rx", "tx";
265 clocks 265 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
266 266 <&clks IMX6SX_CLK_OSC>,
267 267 <&clks IMX6SX_CLK_SPDIF>,
268 268 <&clks 0>, <&clks 0>, <&clks 0>,
269 269 <&clks IMX6SX_CLK_IPG>,
270 270 <&clks 0>, <&clks 0>,
271 271 <&clks IMX6SX_CLK_SPBA>;
272 clock- 272 clock-names = "core", "rxtx0",
273 273 "rxtx1", "rxtx2",
274 274 "rxtx3", "rxtx4",
275 275 "rxtx5", "rxtx6",
276 276 "rxtx7", "spba";
277 status 277 status = "disabled";
278 }; 278 };
279 279
280 ecspi1: spi@20 280 ecspi1: spi@2008000 {
281 #addre 281 #address-cells = <1>;
282 #size- 282 #size-cells = <0>;
283 compat 283 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
284 reg = 284 reg = <0x02008000 0x4000>;
285 interr 285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
286 clocks 286 clocks = <&clks IMX6SX_CLK_ECSPI1>,
287 287 <&clks IMX6SX_CLK_ECSPI1>;
288 clock- 288 clock-names = "ipg", "per";
289 status 289 status = "disabled";
290 }; 290 };
291 291
292 ecspi2: spi@20 292 ecspi2: spi@200c000 {
293 #addre 293 #address-cells = <1>;
294 #size- 294 #size-cells = <0>;
295 compat 295 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
296 reg = 296 reg = <0x0200c000 0x4000>;
297 interr 297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
298 clocks 298 clocks = <&clks IMX6SX_CLK_ECSPI2>,
299 299 <&clks IMX6SX_CLK_ECSPI2>;
300 clock- 300 clock-names = "ipg", "per";
301 status 301 status = "disabled";
302 }; 302 };
303 303
304 ecspi3: spi@20 304 ecspi3: spi@2010000 {
305 #addre 305 #address-cells = <1>;
306 #size- 306 #size-cells = <0>;
307 compat 307 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
308 reg = 308 reg = <0x02010000 0x4000>;
309 interr 309 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
310 clocks 310 clocks = <&clks IMX6SX_CLK_ECSPI3>,
311 311 <&clks IMX6SX_CLK_ECSPI3>;
312 clock- 312 clock-names = "ipg", "per";
313 status 313 status = "disabled";
314 }; 314 };
315 315
316 ecspi4: spi@20 316 ecspi4: spi@2014000 {
317 #addre 317 #address-cells = <1>;
318 #size- 318 #size-cells = <0>;
319 compat 319 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
320 reg = 320 reg = <0x02014000 0x4000>;
321 interr 321 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
322 clocks 322 clocks = <&clks IMX6SX_CLK_ECSPI4>,
323 323 <&clks IMX6SX_CLK_ECSPI4>;
324 clock- 324 clock-names = "ipg", "per";
325 status 325 status = "disabled";
326 }; 326 };
327 327
328 uart1: serial@ 328 uart1: serial@2020000 {
329 compat 329 compatible = "fsl,imx6sx-uart",
330 330 "fsl,imx6q-uart", "fsl,imx21-uart";
331 reg = 331 reg = <0x02020000 0x4000>;
332 interr 332 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
333 clocks 333 clocks = <&clks IMX6SX_CLK_UART_IPG>,
334 334 <&clks IMX6SX_CLK_UART_SERIAL>;
335 clock- 335 clock-names = "ipg", "per";
336 dmas = 336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
337 dma-na 337 dma-names = "rx", "tx";
338 status 338 status = "disabled";
339 }; 339 };
340 340
341 esai: esai@202 341 esai: esai@2024000 {
342 compat 342 compatible = "fsl,imx35-esai";
343 reg = 343 reg = <0x02024000 0x4000>;
344 interr 344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
345 clocks 345 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
346 346 <&clks IMX6SX_CLK_ESAI_EXTAL>,
347 347 <&clks IMX6SX_CLK_ESAI_IPG>,
348 348 <&clks IMX6SX_CLK_SPBA>;
349 clock- 349 clock-names = "core", "extal",
350 350 "fsys", "spba";
351 dmas = 351 dmas = <&sdma 23 21 0>,
352 352 <&sdma 24 21 0>;
353 dma-na 353 dma-names = "rx", "tx";
354 status 354 status = "disabled";
355 }; 355 };
356 356
357 ssi1: ssi@2028 357 ssi1: ssi@2028000 {
358 #sound 358 #sound-dai-cells = <0>;
359 compat 359 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
360 reg = 360 reg = <0x02028000 0x4000>;
361 interr 361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
362 clocks 362 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
363 363 <&clks IMX6SX_CLK_SSI1>;
364 clock- 364 clock-names = "ipg", "baud";
365 dmas = 365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
366 dma-na 366 dma-names = "rx", "tx";
367 fsl,fi 367 fsl,fifo-depth = <15>;
368 status 368 status = "disabled";
369 }; 369 };
370 370
371 ssi2: ssi@202c 371 ssi2: ssi@202c000 {
372 #sound 372 #sound-dai-cells = <0>;
373 compat 373 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
374 reg = 374 reg = <0x0202c000 0x4000>;
375 interr 375 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
376 clocks 376 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
377 377 <&clks IMX6SX_CLK_SSI2>;
378 clock- 378 clock-names = "ipg", "baud";
379 dmas = 379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
380 dma-na 380 dma-names = "rx", "tx";
381 fsl,fi 381 fsl,fifo-depth = <15>;
382 status 382 status = "disabled";
383 }; 383 };
384 384
385 ssi3: ssi@2030 385 ssi3: ssi@2030000 {
386 #sound 386 #sound-dai-cells = <0>;
387 compat 387 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
388 reg = 388 reg = <0x02030000 0x4000>;
389 interr 389 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
390 clocks 390 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
391 391 <&clks IMX6SX_CLK_SSI3>;
392 clock- 392 clock-names = "ipg", "baud";
393 dmas = 393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
394 dma-na 394 dma-names = "rx", "tx";
395 fsl,fi 395 fsl,fifo-depth = <15>;
396 status 396 status = "disabled";
397 }; 397 };
398 398
399 asrc: asrc@203 399 asrc: asrc@2034000 {
400 compat 400 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
401 reg = 401 reg = <0x02034000 0x4000>;
402 interr 402 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
403 clocks 403 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
404 404 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
405 405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 408 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
409 409 <&clks IMX6SX_CLK_SPBA>;
410 clock- 410 clock-names = "mem", "ipg", "asrck_0",
411 411 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
412 412 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
413 413 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
414 414 "asrck_d", "asrck_e", "asrck_f", "spba";
415 dmas = 415 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
416 416 <&sdma 19 23 1>, <&sdma 20 23 1>,
417 417 <&sdma 21 23 1>, <&sdma 22 23 1>;
418 dma-na 418 dma-names = "rxa", "rxb", "rxc",
419 419 "txa", "txb", "txc";
420 fsl,as 420 fsl,asrc-rate = <48000>;
421 fsl,as 421 fsl,asrc-width = <16>;
422 status 422 status = "okay";
423 }; 423 };
424 }; 424 };
425 425
426 pwm1: pwm@2080000 { 426 pwm1: pwm@2080000 {
427 compatible = " 427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
428 reg = <0x02080 428 reg = <0x02080000 0x4000>;
429 interrupts = < 429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clk 430 clocks = <&clks IMX6SX_CLK_PWM1>,
431 <&clk 431 <&clks IMX6SX_CLK_PWM1>;
432 clock-names = 432 clock-names = "ipg", "per";
433 #pwm-cells = < 433 #pwm-cells = <3>;
434 }; 434 };
435 435
436 pwm2: pwm@2084000 { 436 pwm2: pwm@2084000 {
437 compatible = " 437 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
438 reg = <0x02084 438 reg = <0x02084000 0x4000>;
439 interrupts = < 439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clk 440 clocks = <&clks IMX6SX_CLK_PWM2>,
441 <&clk 441 <&clks IMX6SX_CLK_PWM2>;
442 clock-names = 442 clock-names = "ipg", "per";
443 #pwm-cells = < 443 #pwm-cells = <3>;
444 }; 444 };
445 445
446 pwm3: pwm@2088000 { 446 pwm3: pwm@2088000 {
447 compatible = " 447 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
448 reg = <0x02088 448 reg = <0x02088000 0x4000>;
449 interrupts = < 449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clk 450 clocks = <&clks IMX6SX_CLK_PWM3>,
451 <&clk 451 <&clks IMX6SX_CLK_PWM3>;
452 clock-names = 452 clock-names = "ipg", "per";
453 #pwm-cells = < 453 #pwm-cells = <3>;
454 }; 454 };
455 455
456 pwm4: pwm@208c000 { 456 pwm4: pwm@208c000 {
457 compatible = " 457 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
458 reg = <0x0208c 458 reg = <0x0208c000 0x4000>;
459 interrupts = < 459 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk 460 clocks = <&clks IMX6SX_CLK_PWM4>,
461 <&clk 461 <&clks IMX6SX_CLK_PWM4>;
462 clock-names = 462 clock-names = "ipg", "per";
463 #pwm-cells = < 463 #pwm-cells = <3>;
464 }; 464 };
465 465
466 flexcan1: can@2090000 466 flexcan1: can@2090000 {
467 compatible = " 467 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
468 reg = <0x02090 468 reg = <0x02090000 0x4000>;
469 interrupts = < 469 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clk 470 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
471 <&clk 471 <&clks IMX6SX_CLK_CAN1_SERIAL>;
472 clock-names = 472 clock-names = "ipg", "per";
473 fsl,stop-mode 473 fsl,stop-mode = <&gpr 0x10 1>;
474 status = "disa 474 status = "disabled";
475 }; 475 };
476 476
477 flexcan2: can@2094000 477 flexcan2: can@2094000 {
478 compatible = " 478 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
479 reg = <0x02094 479 reg = <0x02094000 0x4000>;
480 interrupts = < 480 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clk 481 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
482 <&clk 482 <&clks IMX6SX_CLK_CAN2_SERIAL>;
483 clock-names = 483 clock-names = "ipg", "per";
484 fsl,stop-mode 484 fsl,stop-mode = <&gpr 0x10 2>;
485 status = "disa 485 status = "disabled";
486 }; 486 };
487 487
488 gpt: timer@2098000 { 488 gpt: timer@2098000 {
489 compatible = " 489 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
490 reg = <0x02098 490 reg = <0x02098000 0x4000>;
491 interrupts = < 491 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clk 492 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
493 <&clk 493 <&clks IMX6SX_CLK_GPT_3M>;
494 clock-names = 494 clock-names = "ipg", "per";
495 }; 495 };
496 496
497 gpio1: gpio@209c000 { 497 gpio1: gpio@209c000 {
498 compatible = " 498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
499 reg = <0x0209c 499 reg = <0x0209c000 0x4000>;
500 interrupts = < 500 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
501 < 501 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
502 gpio-controlle 502 gpio-controller;
503 #gpio-cells = 503 #gpio-cells = <2>;
504 interrupt-cont 504 interrupt-controller;
505 #interrupt-cel 505 #interrupt-cells = <2>;
506 gpio-ranges = 506 gpio-ranges = <&iomuxc 0 5 26>;
507 }; 507 };
508 508
509 gpio2: gpio@20a0000 { 509 gpio2: gpio@20a0000 {
510 compatible = " 510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
511 reg = <0x020a0 511 reg = <0x020a0000 0x4000>;
512 interrupts = < 512 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
513 < 513 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
514 gpio-controlle 514 gpio-controller;
515 #gpio-cells = 515 #gpio-cells = <2>;
516 interrupt-cont 516 interrupt-controller;
517 #interrupt-cel 517 #interrupt-cells = <2>;
518 gpio-ranges = 518 gpio-ranges = <&iomuxc 0 31 20>;
519 }; 519 };
520 520
521 gpio3: gpio@20a4000 { 521 gpio3: gpio@20a4000 {
522 compatible = " 522 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
523 reg = <0x020a4 523 reg = <0x020a4000 0x4000>;
524 interrupts = < 524 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
525 < 525 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
526 gpio-controlle 526 gpio-controller;
527 #gpio-cells = 527 #gpio-cells = <2>;
528 interrupt-cont 528 interrupt-controller;
529 #interrupt-cel 529 #interrupt-cells = <2>;
530 gpio-ranges = 530 gpio-ranges = <&iomuxc 0 51 29>;
531 }; 531 };
532 532
533 gpio4: gpio@20a8000 { 533 gpio4: gpio@20a8000 {
534 compatible = " 534 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
535 reg = <0x020a8 535 reg = <0x020a8000 0x4000>;
536 interrupts = < 536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
537 < 537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
538 gpio-controlle 538 gpio-controller;
539 #gpio-cells = 539 #gpio-cells = <2>;
540 interrupt-cont 540 interrupt-controller;
541 #interrupt-cel 541 #interrupt-cells = <2>;
542 gpio-ranges = 542 gpio-ranges = <&iomuxc 0 80 32>;
543 }; 543 };
544 544
545 gpio5: gpio@20ac000 { 545 gpio5: gpio@20ac000 {
546 compatible = " 546 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
547 reg = <0x020ac 547 reg = <0x020ac000 0x4000>;
548 interrupts = < 548 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
549 < 549 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
550 gpio-controlle 550 gpio-controller;
551 #gpio-cells = 551 #gpio-cells = <2>;
552 interrupt-cont 552 interrupt-controller;
553 #interrupt-cel 553 #interrupt-cells = <2>;
554 gpio-ranges = 554 gpio-ranges = <&iomuxc 0 112 24>;
555 }; 555 };
556 556
557 gpio6: gpio@20b0000 { 557 gpio6: gpio@20b0000 {
558 compatible = " 558 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
559 reg = <0x020b0 559 reg = <0x020b0000 0x4000>;
560 interrupts = < 560 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
561 < 561 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
562 gpio-controlle 562 gpio-controller;
563 #gpio-cells = 563 #gpio-cells = <2>;
564 interrupt-cont 564 interrupt-controller;
565 #interrupt-cel 565 #interrupt-cells = <2>;
566 gpio-ranges = 566 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
567 }; 567 };
568 568
569 gpio7: gpio@20b4000 { 569 gpio7: gpio@20b4000 {
570 compatible = " 570 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
571 reg = <0x020b4 571 reg = <0x020b4000 0x4000>;
572 interrupts = < 572 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
573 < 573 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
574 gpio-controlle 574 gpio-controller;
575 #gpio-cells = 575 #gpio-cells = <2>;
576 interrupt-cont 576 interrupt-controller;
577 #interrupt-cel 577 #interrupt-cells = <2>;
578 gpio-ranges = 578 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
579 }; 579 };
580 580
581 kpp: keypad@20b8000 { 581 kpp: keypad@20b8000 {
582 compatible = " 582 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
583 reg = <0x020b8 583 reg = <0x020b8000 0x4000>;
584 interrupts = < 584 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&clk 585 clocks = <&clks IMX6SX_CLK_IPG>;
586 status = "disa 586 status = "disabled";
587 }; 587 };
588 588
589 wdog1: watchdog@20bc00 589 wdog1: watchdog@20bc000 {
590 compatible = " 590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
591 reg = <0x020bc 591 reg = <0x020bc000 0x4000>;
592 interrupts = < 592 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clk 593 clocks = <&clks IMX6SX_CLK_IPG>;
594 }; 594 };
595 595
596 wdog2: watchdog@20c000 596 wdog2: watchdog@20c0000 {
597 compatible = " 597 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
598 reg = <0x020c0 598 reg = <0x020c0000 0x4000>;
599 interrupts = < 599 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clk 600 clocks = <&clks IMX6SX_CLK_IPG>;
601 status = "disa 601 status = "disabled";
602 }; 602 };
603 603
604 clks: clock-controller 604 clks: clock-controller@20c4000 {
605 compatible = " 605 compatible = "fsl,imx6sx-ccm";
606 reg = <0x020c4 606 reg = <0x020c4000 0x4000>;
607 interrupts = < 607 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
608 < 608 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
609 #clock-cells = 609 #clock-cells = <1>;
610 clocks = <&cki 610 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
611 clock-names = 611 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
612 }; 612 };
613 613
614 anatop: anatop@20c8000 614 anatop: anatop@20c8000 {
615 compatible = " 615 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
616 " 616 "syscon", "simple-mfd";
617 reg = <0x020c8 617 reg = <0x020c8000 0x1000>;
618 interrupts = < 618 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
619 < 619 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
620 < 620 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
621 621
622 reg_vdd1p1: re 622 reg_vdd1p1: regulator-1p1 {
623 compat 623 compatible = "fsl,anatop-regulator";
624 regula 624 regulator-name = "vdd1p1";
625 regula 625 regulator-min-microvolt = <1000000>;
626 regula 626 regulator-max-microvolt = <1200000>;
627 regula 627 regulator-always-on;
628 anatop 628 anatop-reg-offset = <0x110>;
629 anatop 629 anatop-vol-bit-shift = <8>;
630 anatop 630 anatop-vol-bit-width = <5>;
631 anatop 631 anatop-min-bit-val = <4>;
632 anatop 632 anatop-min-voltage = <800000>;
633 anatop 633 anatop-max-voltage = <1375000>;
634 anatop 634 anatop-enable-bit = <0>;
635 }; 635 };
636 636
637 reg_vdd3p0: re 637 reg_vdd3p0: regulator-3p0 {
638 compat 638 compatible = "fsl,anatop-regulator";
639 regula 639 regulator-name = "vdd3p0";
640 regula 640 regulator-min-microvolt = <2800000>;
641 regula 641 regulator-max-microvolt = <3150000>;
642 regula 642 regulator-always-on;
643 anatop 643 anatop-reg-offset = <0x120>;
644 anatop 644 anatop-vol-bit-shift = <8>;
645 anatop 645 anatop-vol-bit-width = <5>;
646 anatop 646 anatop-min-bit-val = <0>;
647 anatop 647 anatop-min-voltage = <2625000>;
648 anatop 648 anatop-max-voltage = <3400000>;
649 anatop 649 anatop-enable-bit = <0>;
650 }; 650 };
651 651
652 reg_vdd2p5: re 652 reg_vdd2p5: regulator-2p5 {
653 compat 653 compatible = "fsl,anatop-regulator";
654 regula 654 regulator-name = "vdd2p5";
655 regula 655 regulator-min-microvolt = <2250000>;
656 regula 656 regulator-max-microvolt = <2750000>;
657 regula 657 regulator-always-on;
658 anatop 658 anatop-reg-offset = <0x130>;
659 anatop 659 anatop-vol-bit-shift = <8>;
660 anatop 660 anatop-vol-bit-width = <5>;
661 anatop 661 anatop-min-bit-val = <0>;
662 anatop 662 anatop-min-voltage = <2100000>;
663 anatop 663 anatop-max-voltage = <2875000>;
664 anatop 664 anatop-enable-bit = <0>;
665 }; 665 };
666 666
667 reg_arm: regul 667 reg_arm: regulator-vddcore {
668 compat 668 compatible = "fsl,anatop-regulator";
669 regula 669 regulator-name = "vddarm";
670 regula 670 regulator-min-microvolt = <725000>;
671 regula 671 regulator-max-microvolt = <1450000>;
672 regula 672 regulator-always-on;
673 anatop 673 anatop-reg-offset = <0x140>;
674 anatop 674 anatop-vol-bit-shift = <0>;
675 anatop 675 anatop-vol-bit-width = <5>;
676 anatop 676 anatop-delay-reg-offset = <0x170>;
677 anatop 677 anatop-delay-bit-shift = <24>;
678 anatop 678 anatop-delay-bit-width = <2>;
679 anatop 679 anatop-min-bit-val = <1>;
680 anatop 680 anatop-min-voltage = <725000>;
681 anatop 681 anatop-max-voltage = <1450000>;
682 }; 682 };
683 683
684 reg_pcie: regu 684 reg_pcie: regulator-vddpcie {
685 compat 685 compatible = "fsl,anatop-regulator";
686 regula 686 regulator-name = "vddpcie";
687 regula 687 regulator-min-microvolt = <725000>;
688 regula 688 regulator-max-microvolt = <1450000>;
689 anatop 689 anatop-reg-offset = <0x140>;
690 anatop 690 anatop-vol-bit-shift = <9>;
691 anatop 691 anatop-vol-bit-width = <5>;
692 anatop 692 anatop-delay-reg-offset = <0x170>;
693 anatop 693 anatop-delay-bit-shift = <26>;
694 anatop 694 anatop-delay-bit-width = <2>;
695 anatop 695 anatop-min-bit-val = <1>;
696 anatop 696 anatop-min-voltage = <725000>;
697 anatop 697 anatop-max-voltage = <1450000>;
698 }; 698 };
699 699
700 reg_soc: regul 700 reg_soc: regulator-vddsoc {
701 compat 701 compatible = "fsl,anatop-regulator";
702 regula 702 regulator-name = "vddsoc";
703 regula 703 regulator-min-microvolt = <725000>;
704 regula 704 regulator-max-microvolt = <1450000>;
705 regula 705 regulator-always-on;
706 anatop 706 anatop-reg-offset = <0x140>;
707 anatop 707 anatop-vol-bit-shift = <18>;
708 anatop 708 anatop-vol-bit-width = <5>;
709 anatop 709 anatop-delay-reg-offset = <0x170>;
710 anatop 710 anatop-delay-bit-shift = <28>;
711 anatop 711 anatop-delay-bit-width = <2>;
712 anatop 712 anatop-min-bit-val = <1>;
713 anatop 713 anatop-min-voltage = <725000>;
714 anatop 714 anatop-max-voltage = <1450000>;
715 }; 715 };
716 716
717 tempmon: tempm 717 tempmon: tempmon {
718 compat 718 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
719 interr 719 interrupt-parent = <&gpc>;
720 interr 720 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
721 fsl,te 721 fsl,tempmon = <&anatop>;
722 nvmem- 722 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
723 nvmem- 723 nvmem-cell-names = "calib", "temp_grade";
724 clocks 724 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
725 }; 725 };
726 }; 726 };
727 727
728 usbphy1: usbphy@20c900 728 usbphy1: usbphy@20c9000 {
729 compatible = " 729 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
730 reg = <0x020c9 730 reg = <0x020c9000 0x1000>;
731 interrupts = < 731 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clk 732 clocks = <&clks IMX6SX_CLK_USBPHY1>;
733 fsl,anatop = < 733 fsl,anatop = <&anatop>;
734 }; 734 };
735 735
736 usbphy2: usbphy@20ca00 736 usbphy2: usbphy@20ca000 {
737 compatible = " 737 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
738 reg = <0x020ca 738 reg = <0x020ca000 0x1000>;
739 interrupts = < 739 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clk 740 clocks = <&clks IMX6SX_CLK_USBPHY2>;
741 fsl,anatop = < 741 fsl,anatop = <&anatop>;
742 }; 742 };
743 743
744 snvs: snvs@20cc000 { 744 snvs: snvs@20cc000 {
745 compatible = " 745 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
746 reg = <0x020cc 746 reg = <0x020cc000 0x4000>;
747 747
748 snvs_rtc: snvs 748 snvs_rtc: snvs-rtc-lp {
749 compat 749 compatible = "fsl,sec-v4.0-mon-rtc-lp";
750 regmap 750 regmap = <&snvs>;
751 offset 751 offset = <0x34>;
752 interr 752 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
753 }; 753 };
754 754
755 snvs_poweroff: 755 snvs_poweroff: snvs-poweroff {
756 compat 756 compatible = "syscon-poweroff";
757 regmap 757 regmap = <&snvs>;
758 offset 758 offset = <0x38>;
759 value 759 value = <0x60>;
760 mask = 760 mask = <0x60>;
761 status 761 status = "disabled";
762 }; 762 };
763 763
764 snvs_pwrkey: s 764 snvs_pwrkey: snvs-powerkey {
765 compat 765 compatible = "fsl,sec-v4.0-pwrkey";
766 regmap 766 regmap = <&snvs>;
767 interr 767 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
768 linux, 768 linux,keycode = <KEY_POWER>;
769 wakeup 769 wakeup-source;
770 status 770 status = "disabled";
771 }; 771 };
772 }; 772 };
773 773
774 epit1: epit@20d0000 { 774 epit1: epit@20d0000 {
775 reg = <0x020d0 775 reg = <0x020d0000 0x4000>;
776 interrupts = < 776 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
777 }; 777 };
778 778
779 epit2: epit@20d4000 { 779 epit2: epit@20d4000 {
780 reg = <0x020d4 780 reg = <0x020d4000 0x4000>;
781 interrupts = < 781 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
782 }; 782 };
783 783
784 src: reset-controller@ 784 src: reset-controller@20d8000 {
785 compatible = " 785 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
786 reg = <0x020d8 786 reg = <0x020d8000 0x4000>;
787 interrupts = < 787 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
788 < 788 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
789 #reset-cells = 789 #reset-cells = <1>;
790 }; 790 };
791 791
792 gpc: gpc@20dc000 { 792 gpc: gpc@20dc000 {
793 compatible = " 793 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
794 reg = <0x020dc 794 reg = <0x020dc000 0x4000>;
795 interrupt-cont 795 interrupt-controller;
796 #interrupt-cel 796 #interrupt-cells = <3>;
797 interrupts = < 797 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
798 interrupt-pare 798 interrupt-parent = <&intc>;
799 clocks = <&clk 799 clocks = <&clks IMX6SX_CLK_IPG>;
800 clock-names = 800 clock-names = "ipg";
801 801
802 pgc { 802 pgc {
803 #addre 803 #address-cells = <1>;
804 #size- 804 #size-cells = <0>;
805 805
806 power- 806 power-domain@0 {
807 807 reg = <0>;
808 808 #power-domain-cells = <0>;
809 }; 809 };
810 810
811 pd_pu: 811 pd_pu: power-domain@1 {
812 812 reg = <1>;
813 813 #power-domain-cells = <0>;
814 814 power-supply = <®_soc>;
815 815 clocks = <&clks IMX6SX_CLK_GPU>;
816 }; 816 };
817 817
818 pd_dis 818 pd_disp: power-domain@2 {
819 819 reg = <2>;
820 820 #power-domain-cells = <0>;
821 821 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
822 822 <&clks IMX6SX_CLK_DISPLAY_AXI>,
823 823 <&clks IMX6SX_CLK_LCDIF1_PIX>,
824 824 <&clks IMX6SX_CLK_LCDIF_APB>,
825 825 <&clks IMX6SX_CLK_LCDIF2_PIX>,
826 826 <&clks IMX6SX_CLK_CSI>,
827 827 <&clks IMX6SX_CLK_VADC>;
828 }; 828 };
829 829
830 pd_pci 830 pd_pci: power-domain@3 {
831 831 reg = <3>;
832 832 #power-domain-cells = <0>;
833 833 power-supply = <®_pcie>;
834 }; 834 };
835 }; 835 };
836 }; 836 };
837 837
838 iomuxc: pinctrl@20e000 838 iomuxc: pinctrl@20e0000 {
839 compatible = " 839 compatible = "fsl,imx6sx-iomuxc";
840 reg = <0x020e0 840 reg = <0x020e0000 0x4000>;
841 }; 841 };
842 842
843 gpr: syscon@20e4000 { 843 gpr: syscon@20e4000 {
844 compatible = " 844 compatible = "fsl,imx6sx-iomuxc-gpr",
845 " 845 "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
846 #address-cells 846 #address-cells = <1>;
847 #size-cells = 847 #size-cells = <1>;
848 reg = <0x020e4 848 reg = <0x020e4000 0x4000>;
849 849
850 lvds_bridge: b 850 lvds_bridge: bridge@18 {
851 compat 851 compatible = "fsl,imx6sx-ldb";
852 reg = 852 reg = <0x18 0x4>;
853 clocks 853 clocks = <&clks IMX6SX_CLK_LDB_DI0>;
854 clock- 854 clock-names = "ldb";
855 status 855 status = "disabled";
856 856
857 ports 857 ports {
858 858 #address-cells = <1>;
859 859 #size-cells = <0>;
860 860
861 861 port@0 {
862 862 reg = <0>;
863 863
864 864 ldb_from_lcdif1: endpoint {
865 865 };
866 866 };
867 867
868 868 port@1 {
869 869 reg = <1>;
870 870
871 871 ldb_lvds_ch0: endpoint {
872 872 };
873 873 };
874 }; 874 };
875 }; 875 };
876 }; 876 };
877 877
878 sdma: dma-controller@2 878 sdma: dma-controller@20ec000 {
879 compatible = " 879 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
880 reg = <0x020ec 880 reg = <0x020ec000 0x4000>;
881 interrupts = < 881 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clk 882 clocks = <&clks IMX6SX_CLK_IPG>,
883 <&clk 883 <&clks IMX6SX_CLK_SDMA>;
884 clock-names = 884 clock-names = "ipg", "ahb";
885 #dma-cells = < 885 #dma-cells = <3>;
886 /* imx6sx reus 886 /* imx6sx reuses imx6q sdma firmware */
887 fsl,sdma-ram-s 887 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
888 }; 888 };
889 }; 889 };
890 890
891 aips2: bus@2100000 { 891 aips2: bus@2100000 {
892 compatible = "fsl,aips 892 compatible = "fsl,aips-bus", "simple-bus";
893 #address-cells = <1>; 893 #address-cells = <1>;
894 #size-cells = <1>; 894 #size-cells = <1>;
895 reg = <0x02100000 0x10 895 reg = <0x02100000 0x100000>;
896 ranges; 896 ranges;
897 897
898 crypto: crypto@2100000 898 crypto: crypto@2100000 {
899 compatible = " 899 compatible = "fsl,sec-v4.0";
900 #address-cells 900 #address-cells = <1>;
901 #size-cells = 901 #size-cells = <1>;
902 reg = <0x21000 902 reg = <0x2100000 0x10000>;
903 ranges = <0 0x 903 ranges = <0 0x2100000 0x10000>;
904 interrupt-pare 904 interrupt-parent = <&intc>;
905 clocks = <&clk 905 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
906 <&clk 906 <&clks IMX6SX_CLK_CAAM_ACLK>,
907 <&clk 907 <&clks IMX6SX_CLK_CAAM_IPG>,
908 <&clk 908 <&clks IMX6SX_CLK_EIM_SLOW>;
909 clock-names = 909 clock-names = "mem", "aclk", "ipg", "emi_slow";
910 910
911 sec_jr0: jr@10 911 sec_jr0: jr@1000 {
912 compat 912 compatible = "fsl,sec-v4.0-job-ring";
913 reg = 913 reg = <0x1000 0x1000>;
914 interr 914 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
915 }; 915 };
916 916
917 sec_jr1: jr@20 917 sec_jr1: jr@2000 {
918 compat 918 compatible = "fsl,sec-v4.0-job-ring";
919 reg = 919 reg = <0x2000 0x1000>;
920 interr 920 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
921 }; 921 };
922 }; 922 };
923 923
924 usbotg1: usb@2184000 { 924 usbotg1: usb@2184000 {
925 compatible = " 925 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
926 reg = <0x02184 926 reg = <0x02184000 0x200>;
927 interrupts = < 927 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clk 928 clocks = <&clks IMX6SX_CLK_USBOH3>;
929 fsl,usbphy = < 929 fsl,usbphy = <&usbphy1>;
930 fsl,usbmisc = 930 fsl,usbmisc = <&usbmisc 0>;
931 ahb-burst-conf 931 ahb-burst-config = <0x0>;
932 tx-burst-size- 932 tx-burst-size-dword = <0x10>;
933 rx-burst-size- 933 rx-burst-size-dword = <0x10>;
934 status = "disa 934 status = "disabled";
935 }; 935 };
936 936
937 usbotg2: usb@2184200 { 937 usbotg2: usb@2184200 {
938 compatible = " 938 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
939 reg = <0x02184 939 reg = <0x02184200 0x200>;
940 interrupts = < 940 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&clk 941 clocks = <&clks IMX6SX_CLK_USBOH3>;
942 fsl,usbphy = < 942 fsl,usbphy = <&usbphy2>;
943 fsl,usbmisc = 943 fsl,usbmisc = <&usbmisc 1>;
944 ahb-burst-conf 944 ahb-burst-config = <0x0>;
945 tx-burst-size- 945 tx-burst-size-dword = <0x10>;
946 rx-burst-size- 946 rx-burst-size-dword = <0x10>;
947 status = "disa 947 status = "disabled";
948 }; 948 };
949 949
950 usbh: usb@2184400 { 950 usbh: usb@2184400 {
951 compatible = " 951 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
952 reg = <0x02184 952 reg = <0x02184400 0x200>;
953 interrupts = < 953 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&clk 954 clocks = <&clks IMX6SX_CLK_USBOH3>;
955 fsl,usbphy = < 955 fsl,usbphy = <&usbphynop1>;
956 fsl,usbmisc = 956 fsl,usbmisc = <&usbmisc 2>;
957 phy_type = "hs 957 phy_type = "hsic";
958 dr_mode = "hos 958 dr_mode = "host";
959 ahb-burst-conf 959 ahb-burst-config = <0x0>;
960 tx-burst-size- 960 tx-burst-size-dword = <0x10>;
961 rx-burst-size- 961 rx-burst-size-dword = <0x10>;
962 status = "disa 962 status = "disabled";
963 }; 963 };
964 964
965 usbmisc: usbmisc@21848 965 usbmisc: usbmisc@2184800 {
966 #index-cells = 966 #index-cells = <1>;
967 compatible = " 967 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
968 reg = <0x02184 968 reg = <0x02184800 0x200>;
969 clocks = <&clk 969 clocks = <&clks IMX6SX_CLK_USBOH3>;
970 }; 970 };
971 971
972 fec1: ethernet@2188000 972 fec1: ethernet@2188000 {
973 compatible = " 973 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
974 reg = <0x02188 974 reg = <0x02188000 0x4000>;
975 interrupt-name 975 interrupt-names = "int0", "pps";
976 interrupts = < 976 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
977 < 977 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clk 978 clocks = <&clks IMX6SX_CLK_ENET>,
979 <&clk 979 <&clks IMX6SX_CLK_ENET_AHB>,
980 <&clk 980 <&clks IMX6SX_CLK_ENET_PTP>,
981 <&clk 981 <&clks IMX6SX_CLK_ENET_REF>,
982 <&clk 982 <&clks IMX6SX_CLK_ENET_PTP>;
983 clock-names = 983 clock-names = "ipg", "ahb", "ptp",
984 984 "enet_clk_ref", "enet_out";
985 fsl,num-tx-que 985 fsl,num-tx-queues = <3>;
986 fsl,num-rx-que 986 fsl,num-rx-queues = <3>;
987 fsl,stop-mode 987 fsl,stop-mode = <&gpr 0x10 3>;
988 status = "disa 988 status = "disabled";
989 }; 989 };
990 990
991 mlb: mlb@218c000 { 991 mlb: mlb@218c000 {
992 reg = <0x0218c 992 reg = <0x0218c000 0x4000>;
993 interrupts = < 993 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
994 < 994 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
995 < 995 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clk 996 clocks = <&clks IMX6SX_CLK_MLB>;
997 status = "disa 997 status = "disabled";
998 }; 998 };
999 999
1000 usdhc1: mmc@2190000 { 1000 usdhc1: mmc@2190000 {
1001 compatible = 1001 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1002 reg = <0x0219 1002 reg = <0x02190000 0x4000>;
1003 interrupts = 1003 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&cl 1004 clocks = <&clks IMX6SX_CLK_USDHC1>,
1005 <&cl 1005 <&clks IMX6SX_CLK_USDHC1>,
1006 <&cl 1006 <&clks IMX6SX_CLK_USDHC1>;
1007 clock-names = 1007 clock-names = "ipg", "ahb", "per";
1008 bus-width = < 1008 bus-width = <4>;
1009 fsl,tuning-st 1009 fsl,tuning-start-tap = <20>;
1010 fsl,tuning-st 1010 fsl,tuning-step = <2>;
1011 status = "dis 1011 status = "disabled";
1012 }; 1012 };
1013 1013
1014 usdhc2: mmc@2194000 { 1014 usdhc2: mmc@2194000 {
1015 compatible = 1015 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1016 reg = <0x0219 1016 reg = <0x02194000 0x4000>;
1017 interrupts = 1017 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&cl 1018 clocks = <&clks IMX6SX_CLK_USDHC2>,
1019 <&cl 1019 <&clks IMX6SX_CLK_USDHC2>,
1020 <&cl 1020 <&clks IMX6SX_CLK_USDHC2>;
1021 clock-names = 1021 clock-names = "ipg", "ahb", "per";
1022 bus-width = < 1022 bus-width = <4>;
1023 fsl,tuning-st 1023 fsl,tuning-start-tap = <20>;
1024 fsl,tuning-st 1024 fsl,tuning-step = <2>;
1025 status = "dis 1025 status = "disabled";
1026 }; 1026 };
1027 1027
1028 usdhc3: mmc@2198000 { 1028 usdhc3: mmc@2198000 {
1029 compatible = 1029 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1030 reg = <0x0219 1030 reg = <0x02198000 0x4000>;
1031 interrupts = 1031 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cl 1032 clocks = <&clks IMX6SX_CLK_USDHC3>,
1033 <&cl 1033 <&clks IMX6SX_CLK_USDHC3>,
1034 <&cl 1034 <&clks IMX6SX_CLK_USDHC3>;
1035 clock-names = 1035 clock-names = "ipg", "ahb", "per";
1036 bus-width = < 1036 bus-width = <4>;
1037 fsl,tuning-st 1037 fsl,tuning-start-tap = <20>;
1038 fsl,tuning-st 1038 fsl,tuning-step = <2>;
1039 status = "dis 1039 status = "disabled";
1040 }; 1040 };
1041 1041
1042 usdhc4: mmc@219c000 { 1042 usdhc4: mmc@219c000 {
1043 compatible = 1043 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1044 reg = <0x0219 1044 reg = <0x0219c000 0x4000>;
1045 interrupts = 1045 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&cl 1046 clocks = <&clks IMX6SX_CLK_USDHC4>,
1047 <&cl 1047 <&clks IMX6SX_CLK_USDHC4>,
1048 <&cl 1048 <&clks IMX6SX_CLK_USDHC4>;
1049 clock-names = 1049 clock-names = "ipg", "ahb", "per";
1050 bus-width = < 1050 bus-width = <4>;
1051 status = "dis 1051 status = "disabled";
1052 }; 1052 };
1053 1053
1054 i2c1: i2c@21a0000 { 1054 i2c1: i2c@21a0000 {
1055 #address-cell 1055 #address-cells = <1>;
1056 #size-cells = 1056 #size-cells = <0>;
1057 compatible = 1057 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1058 reg = <0x021a 1058 reg = <0x021a0000 0x4000>;
1059 interrupts = 1059 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&cl 1060 clocks = <&clks IMX6SX_CLK_I2C1>;
1061 status = "dis 1061 status = "disabled";
1062 }; 1062 };
1063 1063
1064 i2c2: i2c@21a4000 { 1064 i2c2: i2c@21a4000 {
1065 #address-cell 1065 #address-cells = <1>;
1066 #size-cells = 1066 #size-cells = <0>;
1067 compatible = 1067 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1068 reg = <0x021a 1068 reg = <0x021a4000 0x4000>;
1069 interrupts = 1069 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&cl 1070 clocks = <&clks IMX6SX_CLK_I2C2>;
1071 status = "dis 1071 status = "disabled";
1072 }; 1072 };
1073 1073
1074 i2c3: i2c@21a8000 { 1074 i2c3: i2c@21a8000 {
1075 #address-cell 1075 #address-cells = <1>;
1076 #size-cells = 1076 #size-cells = <0>;
1077 compatible = 1077 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1078 reg = <0x021a 1078 reg = <0x021a8000 0x4000>;
1079 interrupts = 1079 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&cl 1080 clocks = <&clks IMX6SX_CLK_I2C3>;
1081 status = "dis 1081 status = "disabled";
1082 }; 1082 };
1083 1083
1084 memory-controller@21b 1084 memory-controller@21b0000 {
1085 compatible = 1085 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1086 reg = <0x021b 1086 reg = <0x021b0000 0x4000>;
1087 clocks = <&cl 1087 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1088 }; 1088 };
1089 1089
1090 fec2: ethernet@21b400 1090 fec2: ethernet@21b4000 {
1091 compatible = 1091 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1092 reg = <0x021b 1092 reg = <0x021b4000 0x4000>;
1093 interrupt-nam 1093 interrupt-names = "int0", "pps";
1094 interrupts = 1094 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1095 1095 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&cl 1096 clocks = <&clks IMX6SX_CLK_ENET>,
1097 <&cl 1097 <&clks IMX6SX_CLK_ENET_AHB>,
1098 <&cl 1098 <&clks IMX6SX_CLK_ENET_PTP>,
1099 <&cl 1099 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1100 <&cl 1100 <&clks IMX6SX_CLK_ENET_PTP>;
1101 clock-names = 1101 clock-names = "ipg", "ahb", "ptp",
1102 1102 "enet_clk_ref", "enet_out";
1103 fsl,stop-mode 1103 fsl,stop-mode = <&gpr 0x10 4>;
1104 status = "dis 1104 status = "disabled";
1105 }; 1105 };
1106 1106
1107 weim: memory-controll 1107 weim: memory-controller@21b8000 {
1108 #address-cell 1108 #address-cells = <2>;
1109 #size-cells = 1109 #size-cells = <1>;
1110 compatible = 1110 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1111 reg = <0x021b 1111 reg = <0x021b8000 0x4000>;
1112 interrupts = 1112 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&cl 1113 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1114 fsl,weim-cs-g 1114 fsl,weim-cs-gpr = <&gpr>;
1115 status = "dis 1115 status = "disabled";
1116 }; 1116 };
1117 1117
1118 ocotp: efuse@21bc000 1118 ocotp: efuse@21bc000 {
1119 #address-cell 1119 #address-cells = <1>;
1120 #size-cells = 1120 #size-cells = <1>;
1121 compatible = 1121 compatible = "fsl,imx6sx-ocotp", "syscon";
1122 reg = <0x021b 1122 reg = <0x021bc000 0x4000>;
1123 clocks = <&cl 1123 clocks = <&clks IMX6SX_CLK_OCOTP>;
1124 1124
1125 cpu_speed_gra 1125 cpu_speed_grade: speed-grade@10 {
1126 reg = 1126 reg = <0x10 4>;
1127 }; 1127 };
1128 1128
1129 tempmon_calib 1129 tempmon_calib: calib@38 {
1130 reg = 1130 reg = <0x38 4>;
1131 }; 1131 };
1132 1132
1133 tempmon_temp_ 1133 tempmon_temp_grade: temp-grade@20 {
1134 reg = 1134 reg = <0x20 4>;
1135 }; 1135 };
1136 }; 1136 };
1137 1137
1138 sai1: sai@21d4000 { 1138 sai1: sai@21d4000 {
1139 compatible = 1139 compatible = "fsl,imx6sx-sai";
1140 reg = <0x021d 1140 reg = <0x021d4000 0x4000>;
1141 interrupts = 1141 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cl 1142 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1143 <&cl 1143 <&clks IMX6SX_CLK_SAI1>,
1144 <&cl 1144 <&clks 0>, <&clks 0>;
1145 clock-names = 1145 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1146 dma-names = " 1146 dma-names = "rx", "tx";
1147 dmas = <&sdma 1147 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1148 status = "dis 1148 status = "disabled";
1149 }; 1149 };
1150 1150
1151 audmux: audmux@21d800 1151 audmux: audmux@21d8000 {
1152 compatible = 1152 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1153 reg = <0x021d 1153 reg = <0x021d8000 0x4000>;
1154 status = "dis 1154 status = "disabled";
1155 }; 1155 };
1156 1156
1157 sai2: sai@21dc000 { 1157 sai2: sai@21dc000 {
1158 compatible = 1158 compatible = "fsl,imx6sx-sai";
1159 reg = <0x021d 1159 reg = <0x021dc000 0x4000>;
1160 interrupts = 1160 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&cl 1161 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1162 <&cl 1162 <&clks IMX6SX_CLK_SAI2>,
1163 <&cl 1163 <&clks 0>, <&clks 0>;
1164 clock-names = 1164 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1165 dma-names = " 1165 dma-names = "rx", "tx";
1166 dmas = <&sdma 1166 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1167 status = "dis 1167 status = "disabled";
1168 }; 1168 };
1169 1169
1170 qspi1: spi@21e0000 { 1170 qspi1: spi@21e0000 {
1171 #address-cell 1171 #address-cells = <1>;
1172 #size-cells = 1172 #size-cells = <0>;
1173 compatible = 1173 compatible = "fsl,imx6sx-qspi";
1174 reg = <0x021e 1174 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1175 reg-names = " 1175 reg-names = "QuadSPI", "QuadSPI-memory";
1176 interrupts = 1176 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cl 1177 clocks = <&clks IMX6SX_CLK_QSPI1>,
1178 <&cl 1178 <&clks IMX6SX_CLK_QSPI1>;
1179 clock-names = 1179 clock-names = "qspi_en", "qspi";
1180 status = "dis 1180 status = "disabled";
1181 }; 1181 };
1182 1182
1183 qspi2: spi@21e4000 { 1183 qspi2: spi@21e4000 {
1184 #address-cell 1184 #address-cells = <1>;
1185 #size-cells = 1185 #size-cells = <0>;
1186 compatible = 1186 compatible = "fsl,imx6sx-qspi";
1187 reg = <0x021e 1187 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1188 reg-names = " 1188 reg-names = "QuadSPI", "QuadSPI-memory";
1189 interrupts = 1189 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&cl 1190 clocks = <&clks IMX6SX_CLK_QSPI2>,
1191 <&cl 1191 <&clks IMX6SX_CLK_QSPI2>;
1192 clock-names = 1192 clock-names = "qspi_en", "qspi";
1193 status = "dis 1193 status = "disabled";
1194 }; 1194 };
1195 1195
1196 uart2: serial@21e8000 1196 uart2: serial@21e8000 {
1197 compatible = 1197 compatible = "fsl,imx6sx-uart",
1198 1198 "fsl,imx6q-uart", "fsl,imx21-uart";
1199 reg = <0x021e 1199 reg = <0x021e8000 0x4000>;
1200 interrupts = 1200 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cl 1201 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1202 <&cl 1202 <&clks IMX6SX_CLK_UART_SERIAL>;
1203 clock-names = 1203 clock-names = "ipg", "per";
1204 dmas = <&sdma 1204 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1205 dma-names = " 1205 dma-names = "rx", "tx";
1206 status = "dis 1206 status = "disabled";
1207 }; 1207 };
1208 1208
1209 uart3: serial@21ec000 1209 uart3: serial@21ec000 {
1210 compatible = 1210 compatible = "fsl,imx6sx-uart",
1211 1211 "fsl,imx6q-uart", "fsl,imx21-uart";
1212 reg = <0x021e 1212 reg = <0x021ec000 0x4000>;
1213 interrupts = 1213 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cl 1214 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1215 <&cl 1215 <&clks IMX6SX_CLK_UART_SERIAL>;
1216 clock-names = 1216 clock-names = "ipg", "per";
1217 dmas = <&sdma 1217 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1218 dma-names = " 1218 dma-names = "rx", "tx";
1219 status = "dis 1219 status = "disabled";
1220 }; 1220 };
1221 1221
1222 uart4: serial@21f0000 1222 uart4: serial@21f0000 {
1223 compatible = 1223 compatible = "fsl,imx6sx-uart",
1224 1224 "fsl,imx6q-uart", "fsl,imx21-uart";
1225 reg = <0x021f 1225 reg = <0x021f0000 0x4000>;
1226 interrupts = 1226 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1227 clocks = <&cl 1227 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1228 <&cl 1228 <&clks IMX6SX_CLK_UART_SERIAL>;
1229 clock-names = 1229 clock-names = "ipg", "per";
1230 dmas = <&sdma 1230 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1231 dma-names = " 1231 dma-names = "rx", "tx";
1232 status = "dis 1232 status = "disabled";
1233 }; 1233 };
1234 1234
1235 uart5: serial@21f4000 1235 uart5: serial@21f4000 {
1236 compatible = 1236 compatible = "fsl,imx6sx-uart",
1237 1237 "fsl,imx6q-uart", "fsl,imx21-uart";
1238 reg = <0x021f 1238 reg = <0x021f4000 0x4000>;
1239 interrupts = 1239 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&cl 1240 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1241 <&cl 1241 <&clks IMX6SX_CLK_UART_SERIAL>;
1242 clock-names = 1242 clock-names = "ipg", "per";
1243 dmas = <&sdma 1243 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1244 dma-names = " 1244 dma-names = "rx", "tx";
1245 status = "dis 1245 status = "disabled";
1246 }; 1246 };
1247 1247
1248 i2c4: i2c@21f8000 { 1248 i2c4: i2c@21f8000 {
1249 #address-cell 1249 #address-cells = <1>;
1250 #size-cells = 1250 #size-cells = <0>;
1251 compatible = 1251 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1252 reg = <0x021f 1252 reg = <0x021f8000 0x4000>;
1253 interrupts = 1253 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1254 clocks = <&cl 1254 clocks = <&clks IMX6SX_CLK_I2C4>;
1255 status = "dis 1255 status = "disabled";
1256 }; 1256 };
1257 }; 1257 };
1258 1258
1259 aips3: bus@2200000 { 1259 aips3: bus@2200000 {
1260 compatible = "fsl,aip 1260 compatible = "fsl,aips-bus", "simple-bus";
1261 #address-cells = <1>; 1261 #address-cells = <1>;
1262 #size-cells = <1>; 1262 #size-cells = <1>;
1263 reg = <0x02200000 0x1 1263 reg = <0x02200000 0x100000>;
1264 ranges; 1264 ranges;
1265 1265
1266 spba-bus@2240000 { 1266 spba-bus@2240000 {
1267 compatible = 1267 compatible = "fsl,spba-bus", "simple-bus";
1268 #address-cell 1268 #address-cells = <1>;
1269 #size-cells = 1269 #size-cells = <1>;
1270 reg = <0x0224 1270 reg = <0x02240000 0x40000>;
1271 ranges; 1271 ranges;
1272 1272
1273 csi1: csi@221 1273 csi1: csi@2214000 {
1274 reg = 1274 reg = <0x02214000 0x4000>;
1275 inter 1275 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1276 clock 1276 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1277 1277 <&clks IMX6SX_CLK_CSI>,
1278 1278 <&clks IMX6SX_CLK_DCIC1>;
1279 clock 1279 clock-names = "disp-axi", "csi_mclk", "dcic";
1280 statu 1280 status = "disabled";
1281 }; 1281 };
1282 1282
1283 pxp: pxp@2218 1283 pxp: pxp@2218000 {
1284 compa 1284 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1285 reg = 1285 reg = <0x02218000 0x4000>;
1286 inter 1286 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1287 clock 1287 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1288 clock 1288 clock-names = "axi";
1289 power 1289 power-domains = <&pd_disp>;
1290 statu 1290 status = "disabled";
1291 }; 1291 };
1292 1292
1293 csi2: csi@221 1293 csi2: csi@221c000 {
1294 reg = 1294 reg = <0x0221c000 0x4000>;
1295 inter 1295 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1296 clock 1296 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1297 1297 <&clks IMX6SX_CLK_CSI>,
1298 1298 <&clks IMX6SX_CLK_DCIC2>;
1299 clock 1299 clock-names = "disp-axi", "csi_mclk", "dcic";
1300 statu 1300 status = "disabled";
1301 }; 1301 };
1302 1302
1303 lcdif1: lcdif 1303 lcdif1: lcdif@2220000 {
1304 compa 1304 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1305 reg = 1305 reg = <0x02220000 0x4000>;
1306 inter 1306 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1307 clock 1307 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1308 1308 <&clks IMX6SX_CLK_LCDIF_APB>,
1309 1309 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1310 clock 1310 clock-names = "pix", "axi", "disp_axi";
1311 assig 1311 assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>,
1312 1312 <&clks IMX6SX_CLK_LCDIF1_SEL>;
1313 assig 1313 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>,
1314 1314 <&clks IMX6SX_CLK_LCDIF1_PODF>;
1315 power 1315 power-domains = <&pd_disp>;
1316 statu 1316 status = "disabled";
1317 1317
1318 port 1318 port {
1319 1319 lcdif1_to_ldb: endpoint {
1320 1320 };
1321 }; 1321 };
1322 }; 1322 };
1323 1323
1324 lcdif2: lcdif 1324 lcdif2: lcdif@2224000 {
1325 compa 1325 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1326 reg = 1326 reg = <0x02224000 0x4000>;
1327 inter 1327 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1328 clock 1328 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1329 1329 <&clks IMX6SX_CLK_LCDIF_APB>,
1330 1330 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1331 clock 1331 clock-names = "pix", "axi", "disp_axi";
1332 power 1332 power-domains = <&pd_disp>;
1333 statu 1333 status = "disabled";
1334 }; 1334 };
1335 1335
1336 vadc: vadc@22 1336 vadc: vadc@2228000 {
1337 reg = 1337 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1338 reg-n 1338 reg-names = "vadc-vafe", "vadc-vdec";
1339 clock 1339 clocks = <&clks IMX6SX_CLK_VADC>,
1340 1340 <&clks IMX6SX_CLK_CSI>;
1341 clock 1341 clock-names = "vadc", "csi";
1342 power 1342 power-domains = <&pd_disp>;
1343 statu 1343 status = "disabled";
1344 }; 1344 };
1345 }; 1345 };
1346 1346
1347 adc1: adc@2280000 { 1347 adc1: adc@2280000 {
1348 compatible = 1348 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1349 reg = <0x0228 1349 reg = <0x02280000 0x4000>;
1350 interrupts = 1350 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1351 clocks = <&cl 1351 clocks = <&clks IMX6SX_CLK_IPG>;
1352 clock-names = 1352 clock-names = "adc";
1353 fsl,adck-max- 1353 fsl,adck-max-frequency = <30000000>, <40000000>,
1354 1354 <20000000>;
1355 status = "dis 1355 status = "disabled";
1356 }; 1356 };
1357 1357
1358 adc2: adc@2284000 { 1358 adc2: adc@2284000 {
1359 compatible = 1359 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1360 reg = <0x0228 1360 reg = <0x02284000 0x4000>;
1361 interrupts = 1361 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&cl 1362 clocks = <&clks IMX6SX_CLK_IPG>;
1363 clock-names = 1363 clock-names = "adc";
1364 fsl,adck-max- 1364 fsl,adck-max-frequency = <30000000>, <40000000>,
1365 1365 <20000000>;
1366 status = "dis 1366 status = "disabled";
1367 }; 1367 };
1368 1368
1369 wdog3: watchdog@22880 1369 wdog3: watchdog@2288000 {
1370 compatible = 1370 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1371 reg = <0x0228 1371 reg = <0x02288000 0x4000>;
1372 interrupts = 1372 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1373 clocks = <&cl 1373 clocks = <&clks IMX6SX_CLK_IPG>;
1374 status = "dis 1374 status = "disabled";
1375 }; 1375 };
1376 1376
1377 ecspi5: spi@228c000 { 1377 ecspi5: spi@228c000 {
1378 #address-cell 1378 #address-cells = <1>;
1379 #size-cells = 1379 #size-cells = <0>;
1380 compatible = 1380 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1381 reg = <0x0228 1381 reg = <0x0228c000 0x4000>;
1382 interrupts = 1382 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&cl 1383 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1384 <&cl 1384 <&clks IMX6SX_CLK_ECSPI5>;
1385 clock-names = 1385 clock-names = "ipg", "per";
1386 status = "dis 1386 status = "disabled";
1387 }; 1387 };
1388 1388
1389 uart6: serial@22a0000 1389 uart6: serial@22a0000 {
1390 compatible = 1390 compatible = "fsl,imx6sx-uart",
1391 1391 "fsl,imx6q-uart", "fsl,imx21-uart";
1392 reg = <0x022a 1392 reg = <0x022a0000 0x4000>;
1393 interrupts = 1393 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&cl 1394 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1395 <&cl 1395 <&clks IMX6SX_CLK_UART_SERIAL>;
1396 clock-names = 1396 clock-names = "ipg", "per";
1397 dmas = <&sdma 1397 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1398 dma-names = " 1398 dma-names = "rx", "tx";
1399 status = "dis 1399 status = "disabled";
1400 }; 1400 };
1401 1401
1402 pwm5: pwm@22a4000 { 1402 pwm5: pwm@22a4000 {
1403 compatible = 1403 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1404 reg = <0x022a 1404 reg = <0x022a4000 0x4000>;
1405 interrupts = 1405 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1406 clocks = <&cl 1406 clocks = <&clks IMX6SX_CLK_PWM5>,
1407 <&cl 1407 <&clks IMX6SX_CLK_PWM5>;
1408 clock-names = 1408 clock-names = "ipg", "per";
1409 #pwm-cells = 1409 #pwm-cells = <3>;
1410 }; 1410 };
1411 1411
1412 pwm6: pwm@22a8000 { 1412 pwm6: pwm@22a8000 {
1413 compatible = 1413 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1414 reg = <0x022a 1414 reg = <0x022a8000 0x4000>;
1415 interrupts = 1415 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1416 clocks = <&cl 1416 clocks = <&clks IMX6SX_CLK_PWM6>,
1417 <&cl 1417 <&clks IMX6SX_CLK_PWM6>;
1418 clock-names = 1418 clock-names = "ipg", "per";
1419 #pwm-cells = 1419 #pwm-cells = <3>;
1420 }; 1420 };
1421 1421
1422 pwm7: pwm@22ac000 { 1422 pwm7: pwm@22ac000 {
1423 compatible = 1423 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1424 reg = <0x022a 1424 reg = <0x022ac000 0x4000>;
1425 interrupts = 1425 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1426 clocks = <&cl 1426 clocks = <&clks IMX6SX_CLK_PWM7>,
1427 <&cl 1427 <&clks IMX6SX_CLK_PWM7>;
1428 clock-names = 1428 clock-names = "ipg", "per";
1429 #pwm-cells = 1429 #pwm-cells = <3>;
1430 }; 1430 };
1431 1431
1432 pwm8: pwm@22b0000 { 1432 pwm8: pwm@22b0000 {
1433 compatible = 1433 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1434 reg = <0x022b 1434 reg = <0x022b0000 0x4000>;
1435 interrupts = 1435 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1436 clocks = <&cl 1436 clocks = <&clks IMX6SX_CLK_PWM8>,
1437 <&cl 1437 <&clks IMX6SX_CLK_PWM8>;
1438 clock-names = 1438 clock-names = "ipg", "per";
1439 #pwm-cells = 1439 #pwm-cells = <3>;
1440 }; 1440 };
1441 }; 1441 };
1442 1442
1443 pcie: pcie@8ffc000 { 1443 pcie: pcie@8ffc000 {
1444 compatible = "fsl,imx 1444 compatible = "fsl,imx6sx-pcie";
1445 reg = <0x08ffc000 0x0 1445 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1446 reg-names = "dbi", "c 1446 reg-names = "dbi", "config";
1447 #address-cells = <3>; 1447 #address-cells = <3>;
1448 #size-cells = <2>; 1448 #size-cells = <2>;
1449 device_type = "pci"; 1449 device_type = "pci";
1450 bus-range = <0x00 0xf 1450 bus-range = <0x00 0xff>;
1451 ranges = <0x81000000 1451 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1452 <0x82000000 1452 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1453 num-lanes = <1>; 1453 num-lanes = <1>;
1454 interrupts = <GIC_SPI 1454 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1455 interrupt-names = "ms 1455 interrupt-names = "msi";
1456 #interrupt-cells = <1 1456 #interrupt-cells = <1>;
1457 interrupt-map-mask = 1457 interrupt-map-mask = <0 0 0 0x7>;
1458 interrupt-map = <0 0 1458 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1459 <0 0 1459 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1460 <0 0 1460 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1461 <0 0 1461 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1462 clocks = <&clks IMX6S 1462 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1463 <&clks IMX6S 1463 <&clks IMX6SX_CLK_LVDS1_OUT>,
1464 <&clks IMX6S 1464 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1465 <&clks IMX6S 1465 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1466 clock-names = "pcie", 1466 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1467 power-domains = <&pd_ 1467 power-domains = <&pd_disp>, <&pd_pci>;
1468 power-domain-names = 1468 power-domain-names = "pcie", "pcie_phy";
1469 status = "disabled"; 1469 status = "disabled";
1470 }; 1470 };
1471 }; 1471 };
1472 }; 1472 };
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