1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Digi International's ConnectCore6UL SBC Exp 3 * Digi International's ConnectCore6UL SBC Express board device tree source
4 * 4 *
5 * Copyright 2018 Digi International, Inc. 5 * Copyright 2018 Digi International, Inc.
6 * 6 *
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6ul.dtsi" 12 #include "imx6ul.dtsi"
13 #include "imx6ul-ccimx6ulsom.dtsi" 13 #include "imx6ul-ccimx6ulsom.dtsi"
14 14
15 / { 15 / {
16 model = "Digi International ConnectCor 16 model = "Digi International ConnectCore 6UL SBC Express.";
17 compatible = "digi,ccimx6ulsbcexpress" 17 compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
18 "fsl,imx6ul"; 18 "fsl,imx6ul";
19 }; 19 };
20 20
21 &adc1 { 21 &adc1 {
22 pinctrl-names = "default"; 22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_adc1>; 23 pinctrl-0 = <&pinctrl_adc1>;
24 status = "okay"; 24 status = "okay";
25 }; 25 };
26 26
27 &can1 { 27 &can1 {
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_flexcan1>; 29 pinctrl-0 = <&pinctrl_flexcan1>;
30 xceiver-supply = <&ext_3v3>; 30 xceiver-supply = <&ext_3v3>;
31 status = "okay"; 31 status = "okay";
32 }; 32 };
33 33
34 &ecspi3 { 34 &ecspi3 {
35 cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW> 35 cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_ecspi3_master>; 37 pinctrl-0 = <&pinctrl_ecspi3_master>;
38 status = "okay"; 38 status = "okay";
39 }; 39 };
40 40
41 &fec1 { 41 &fec1 {
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_enet1>; 43 pinctrl-0 = <&pinctrl_enet1>;
44 phy-mode = "rmii"; 44 phy-mode = "rmii";
45 phy-handle = <ðphy0>; 45 phy-handle = <ðphy0>;
46 status = "okay"; 46 status = "okay";
47 47
48 mdio { 48 mdio {
49 #address-cells = <1>; 49 #address-cells = <1>;
50 #size-cells = <0>; 50 #size-cells = <0>;
51 51
52 ethphy0: ethernet-phy@0 { 52 ethphy0: ethernet-phy@0 {
53 compatible = "ethernet 53 compatible = "ethernet-phy-ieee802.3-c22";
54 smsc,disable-energy-de 54 smsc,disable-energy-detect;
55 reg = <0>; 55 reg = <0>;
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 &i2c2 { 60 &i2c2 {
61 pinctrl-names = "default"; 61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_i2c2>; 62 pinctrl-0 = <&pinctrl_i2c2>;
63 status = "okay"; 63 status = "okay";
64 }; 64 };
65 65
66 &pwm1 { 66 &pwm1 {
67 pinctrl-names = "default"; 67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_pwm1>; 68 pinctrl-0 = <&pinctrl_pwm1>;
69 status = "okay"; 69 status = "okay";
70 }; 70 };
71 71
72 &uart4 { 72 &uart4 {
73 pinctrl-names = "default"; 73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_uart4>; 74 pinctrl-0 = <&pinctrl_uart4>;
75 status = "okay"; 75 status = "okay";
76 }; 76 };
77 77
78 &uart5 { 78 &uart5 {
79 pinctrl-names = "default"; 79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_uart5>; 80 pinctrl-0 = <&pinctrl_uart5>;
81 status = "okay"; 81 status = "okay";
82 }; 82 };
83 83
84 &usbotg1 { 84 &usbotg1 {
85 dr_mode = "host"; 85 dr_mode = "host";
86 disable-over-current; 86 disable-over-current;
87 status = "okay"; 87 status = "okay";
88 }; 88 };
89 89
90 &usbotg2 { 90 &usbotg2 {
91 dr_mode = "host"; 91 dr_mode = "host";
92 disable-over-current; 92 disable-over-current;
93 status = "okay"; 93 status = "okay";
94 }; 94 };
95 95
96 &usdhc2 { 96 &usdhc2 {
97 pinctrl-names = "default"; 97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_usdhc2>; 98 pinctrl-0 = <&pinctrl_usdhc2>;
99 broken-cd; /* no carrier detect l 99 broken-cd; /* no carrier detect line (use polling) */
100 no-1-8-v; 100 no-1-8-v;
101 status = "okay"; 101 status = "okay";
102 }; 102 };
103 103
104 &iomuxc { 104 &iomuxc {
105 pinctrl-names = "default"; 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_hog>; 106 pinctrl-0 = <&pinctrl_hog>;
107 107
108 pinctrl_adc1: adc1grp { 108 pinctrl_adc1: adc1grp {
109 fsl,pins = < 109 fsl,pins = <
110 /* GPIO1_4/ADC1_IN4 (p 110 /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
111 MX6UL_PAD_GPIO1_IO04__ 111 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
112 >; 112 >;
113 }; 113 };
114 114
115 pinctrl_ecspi3_master: ecspi3-1-grp { 115 pinctrl_ecspi3_master: ecspi3-1-grp {
116 fsl,pins = < 116 fsl,pins = <
117 MX6UL_PAD_UART2_RX_DAT 117 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
118 MX6UL_PAD_UART2_CTS_B_ 118 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
119 MX6UL_PAD_UART2_RTS_B_ 119 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
120 MX6UL_PAD_UART2_TX_DAT 120 MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */
121 >; 121 >;
122 }; 122 };
123 123
124 pinctrl_ecspi3_slave: ecspi3-2-grp { 124 pinctrl_ecspi3_slave: ecspi3-2-grp {
125 fsl,pins = < 125 fsl,pins = <
126 MX6UL_PAD_UART2_RX_DAT 126 MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
127 MX6UL_PAD_UART2_CTS_B_ 127 MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
128 MX6UL_PAD_UART2_RTS_B_ 128 MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
129 MX6UL_PAD_UART2_TX_DAT 129 MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */
130 >; 130 >;
131 }; 131 };
132 132
133 pinctrl_enet1: enet1grp { 133 pinctrl_enet1: enet1grp {
134 fsl,pins = < 134 fsl,pins = <
135 MX6UL_PAD_GPIO1_IO07__ 135 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
136 MX6UL_PAD_GPIO1_IO06__ 136 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
137 MX6UL_PAD_ENET1_RX_EN_ 137 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
138 MX6UL_PAD_ENET1_RX_ER_ 138 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
139 MX6UL_PAD_ENET1_RX_DAT 139 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
140 MX6UL_PAD_ENET1_RX_DAT 140 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
141 MX6UL_PAD_ENET1_TX_EN_ 141 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
142 MX6UL_PAD_ENET1_TX_DAT 142 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
143 MX6UL_PAD_ENET1_TX_DAT 143 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
144 MX6UL_PAD_ENET1_TX_CLK 144 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
145 >; 145 >;
146 }; 146 };
147 147
148 pinctrl_flexcan1: flexcan1grp { 148 pinctrl_flexcan1: flexcan1grp {
149 fsl,pins = < 149 fsl,pins = <
150 MX6UL_PAD_LCD_DATA08__ 150 MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
151 MX6UL_PAD_LCD_DATA09__ 151 MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
152 >; 152 >;
153 }; 153 };
154 154
155 pinctrl_i2c2: i2c2grp { 155 pinctrl_i2c2: i2c2grp {
156 fsl,pins = < 156 fsl,pins = <
157 MX6UL_PAD_GPIO1_IO00__ 157 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
158 MX6UL_PAD_GPIO1_IO01__ 158 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
159 >; 159 >;
160 }; 160 };
161 161
162 pinctrl_pwm1: pwm1grp { 162 pinctrl_pwm1: pwm1grp {
163 fsl,pins = < 163 fsl,pins = <
164 MX6UL_PAD_LCD_DATA00__ 164 MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0
165 >; 165 >;
166 }; 166 };
167 167
168 pinctrl_uart4: uart4grp { 168 pinctrl_uart4: uart4grp {
169 fsl,pins = < 169 fsl,pins = <
170 MX6UL_PAD_LCD_CLK__UAR 170 MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
171 MX6UL_PAD_LCD_ENABLE__ 171 MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
172 >; 172 >;
173 }; 173 };
174 174
175 pinctrl_uart5: uart5grp { 175 pinctrl_uart5: uart5grp {
176 fsl,pins = < 176 fsl,pins = <
177 MX6UL_PAD_UART5_TX_DAT 177 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
178 MX6UL_PAD_UART5_RX_DAT 178 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
179 >; 179 >;
180 }; 180 };
181 181
182 pinctrl_usdhc2: usdhc2grp { 182 pinctrl_usdhc2: usdhc2grp {
183 fsl,pins = < 183 fsl,pins = <
184 MX6UL_PAD_CSI_HSYNC__U 184 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
185 MX6UL_PAD_CSI_VSYNC__U 185 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071
186 MX6UL_PAD_CSI_DATA00__ 186 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
187 MX6UL_PAD_CSI_DATA01__ 187 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
188 MX6UL_PAD_CSI_DATA02__ 188 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
189 MX6UL_PAD_CSI_DATA03__ 189 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
190 >; 190 >;
191 }; 191 };
192 192
193 /* General purpose pinctrl */ 193 /* General purpose pinctrl */
194 pinctrl_hog: hoggrp { 194 pinctrl_hog: hoggrp {
195 fsl,pins = < 195 fsl,pins = <
196 /* GPIOs BANK 3 */ 196 /* GPIOs BANK 3 */
197 MX6UL_PAD_LCD_RESET__G 197 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030
198 >; 198 >;
199 }; 199 };
200 }; 200 };
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