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Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ul-opos6uldev.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm/nxp/imx/imx6ul-opos6uldev.dts (Architecture i386) and /scripts/dtc/include-prefixes/arm/nxp/imx/imx6ul-opos6uldev.dts (Architecture alpha)


  1 // SPDX-License-Identifier: GPL-2.0 OR MIT          1 // SPDX-License-Identifier: GPL-2.0 OR MIT
  2 //                                                  2 //
  3 // Copyright 2017 Armadeus Systems <support@arm      3 // Copyright 2017 Armadeus Systems <support@armadeus.com>
  4                                                     4 
  5 /dts-v1/;                                           5 /dts-v1/;
  6 #include "imx6ul-opos6ul.dtsi"                      6 #include "imx6ul-opos6ul.dtsi"
  7 #include "imx6ul-imx6ull-opos6uldev.dtsi"           7 #include "imx6ul-imx6ull-opos6uldev.dtsi"
  8                                                     8 
  9 / {                                                 9 / {
 10         model = "Armadeus Systems OPOS6UL SoM      10         model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
 11         compatible = "armadeus,imx6ul-opos6uld     11         compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
 12 };                                                 12 };
 13                                                    13 
 14 &iomuxc {                                          14 &iomuxc {
 15         pinctrl-0 = <&pinctrl_gpios>, <&pinctr     15         pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
 16                                                    16 
 17         pinctrl_tamper_gpios: tampergpiosgrp {     17         pinctrl_tamper_gpios: tampergpiosgrp {
 18                 fsl,pins = <                       18                 fsl,pins = <
 19                         MX6UL_PAD_SNVS_TAMPER0     19                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x0b0b0
 20                         MX6UL_PAD_SNVS_TAMPER2     20                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x0b0b0
 21                         MX6UL_PAD_SNVS_TAMPER3     21                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x0b0b0
 22                         MX6UL_PAD_SNVS_TAMPER4     22                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x0b0b0
 23                         MX6UL_PAD_SNVS_TAMPER5     23                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x0b0b0
 24                         MX6UL_PAD_SNVS_TAMPER6     24                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x0b0b0
 25                         MX6UL_PAD_SNVS_TAMPER7     25                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x0b0b0
 26                         MX6UL_PAD_SNVS_TAMPER8     26                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x0b0b0
 27                 >;                                 27                 >;
 28         };                                         28         };
 29                                                    29 
 30         pinctrl_usbotg2_vbus: usbotg2vbusgrp {     30         pinctrl_usbotg2_vbus: usbotg2vbusgrp {
 31                 fsl,pins = <                       31                 fsl,pins = <
 32                         MX6UL_PAD_SNVS_TAMPER9     32                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x1b0b0
 33                 >;                                 33                 >;
 34         };                                         34         };
 35                                                    35 
 36         pinctrl_w1: w1grp {                        36         pinctrl_w1: w1grp {
 37                 fsl,pins = <                       37                 fsl,pins = <
 38                         MX6UL_PAD_SNVS_TAMPER1     38                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x0b0b0
 39                 >;                                 39                 >;
 40         };                                         40         };
 41 };                                                 41 };
                                                      

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