1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Copyright 2015 Technexion Ltd. 3 // Copyright 2015 Technexion Ltd.
4 // 4 //
5 // Author: Wig Cheng <wig.cheng@technexion.com 5 // Author: Wig Cheng <wig.cheng@technexion.com>
6 // Richard Hu <richard.hu@technexion.co 6 // Richard Hu <richard.hu@technexion.com>
7 // Tapani Utriainen <tapani@technexion. 7 // Tapani Utriainen <tapani@technexion.com>
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "imx6ul.dtsi" 10 #include "imx6ul.dtsi"
11 11
12 / { 12 / {
13 /* Will be filled by the bootloader */ 13 /* Will be filled by the bootloader */
14 memory@80000000 { 14 memory@80000000 {
15 device_type = "memory"; 15 device_type = "memory";
16 reg = <0x80000000 0>; 16 reg = <0x80000000 0>;
17 }; 17 };
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart6; 20 stdout-path = &uart6;
21 }; 21 };
22 22
23 backlight: backlight { 23 backlight: backlight {
24 compatible = "pwm-backlight"; 24 compatible = "pwm-backlight";
25 pwms = <&pwm3 0 5000000 0>; 25 pwms = <&pwm3 0 5000000 0>;
26 brightness-levels = <0 4 8 16 26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6> 27 default-brightness-level = <6>;
28 status = "okay"; 28 status = "okay";
29 }; 29 };
30 30
31 reg_2p5v: regulator-2p5v { 31 reg_2p5v: regulator-2p5v {
32 compatible = "regulator-fixed" 32 compatible = "regulator-fixed";
33 regulator-name = "2P5V"; 33 regulator-name = "2P5V";
34 regulator-min-microvolt = <250 34 regulator-min-microvolt = <2500000>;
35 regulator-max-microvolt = <250 35 regulator-max-microvolt = <2500000>;
36 }; 36 };
37 37
38 reg_3p3v: regulator-3p3v { 38 reg_3p3v: regulator-3p3v {
39 compatible = "regulator-fixed" 39 compatible = "regulator-fixed";
40 regulator-name = "3P3V"; 40 regulator-name = "3P3V";
41 regulator-min-microvolt = <330 41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <330 42 regulator-max-microvolt = <3300000>;
43 }; 43 };
44 44
45 reg_sd1_vmmc: regulator-sd1-vmmc { 45 reg_sd1_vmmc: regulator-sd1-vmmc {
46 compatible = "regulator-fixed" 46 compatible = "regulator-fixed";
47 regulator-name = "VSD_3V3"; 47 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <330 48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <330 49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio1 9 GPIO_ACTIVE_H 50 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
51 enable-active-high; 51 enable-active-high;
52 }; 52 };
53 53
54 reg_usb_otg_vbus: regulator-usb-otg-vb 54 reg_usb_otg_vbus: regulator-usb-otg-vbus {
55 compatible = "regulator-fixed" 55 compatible = "regulator-fixed";
56 pinctrl-names = "default"; 56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usb_otg1 57 pinctrl-0 = <&pinctrl_usb_otg1>;
58 regulator-name = "usb_otg_vbus 58 regulator-name = "usb_otg_vbus";
59 regulator-min-microvolt = <500 59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <500 60 regulator-max-microvolt = <5000000>;
61 gpio = <&gpio1 6 0>; 61 gpio = <&gpio1 6 0>;
62 }; 62 };
63 63
64 reg_brcm: regulator-brcm { 64 reg_brcm: regulator-brcm {
65 compatible = "regulator-fixed" 65 compatible = "regulator-fixed";
66 enable-active-high; 66 enable-active-high;
67 gpio = <&gpio4 8 GPIO_ACTIVE_H 67 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
68 pinctrl-names = "default"; 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_brcm_reg 69 pinctrl-0 = <&pinctrl_brcm_reg>;
70 regulator-name = "brcm_reg"; 70 regulator-name = "brcm_reg";
71 regulator-min-microvolt = <330 71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <330 72 regulator-max-microvolt = <3300000>;
73 startup-delay-us = <200000>; 73 startup-delay-us = <200000>;
74 }; 74 };
75 75
76 panel { 76 panel {
77 compatible = "vxt,vl050-8048nt 77 compatible = "vxt,vl050-8048nt-c01";
78 backlight = <&backlight>; 78 backlight = <&backlight>;
79 79
80 port { 80 port {
81 panel_in: endpoint { 81 panel_in: endpoint {
82 remote-endpoin 82 remote-endpoint = <&display_out>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 }; 86 };
87 87
88 &can1 { 88 &can1 {
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_flexcan1>; 90 pinctrl-0 = <&pinctrl_flexcan1>;
91 status = "okay"; 91 status = "okay";
92 }; 92 };
93 93
94 &can2 { 94 &can2 {
95 pinctrl-names = "default"; 95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_flexcan2>; 96 pinctrl-0 = <&pinctrl_flexcan2>;
97 status = "okay"; 97 status = "okay";
98 }; 98 };
99 99
100 &clks { 100 &clks {
101 assigned-clocks = <&clks IMX6UL_CLK_PL 101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
102 assigned-clock-rates = <786432000>; 102 assigned-clock-rates = <786432000>;
103 }; 103 };
104 104
105 &fec2 { 105 &fec2 {
106 pinctrl-names = "default"; 106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_enet2>; 107 pinctrl-0 = <&pinctrl_enet2>;
108 phy-mode = "rmii"; 108 phy-mode = "rmii";
109 phy-handle = <ðphy1>; 109 phy-handle = <ðphy1>;
110 status = "okay"; 110 status = "okay";
111 phy-reset-gpios = <&gpio1 28 GPIO_ACTI 111 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
112 phy-reset-duration = <1>; 112 phy-reset-duration = <1>;
113 113
114 mdio { 114 mdio {
115 #address-cells = <1>; 115 #address-cells = <1>;
116 #size-cells = <0>; 116 #size-cells = <0>;
117 117
118 ethphy1: ethernet-phy@1 { 118 ethphy1: ethernet-phy@1 {
119 compatible = "ethernet 119 compatible = "ethernet-phy-ieee802.3-c22";
120 reg = <1>; 120 reg = <1>;
121 max-speed = <100>; 121 max-speed = <100>;
122 interrupt-parent = <&g 122 interrupt-parent = <&gpio5>;
123 interrupts = <6 IRQ_TY 123 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
124 clocks = <&clks IMX6UL 124 clocks = <&clks IMX6UL_CLK_ENET_REF>;
125 clock-names = "rmii-re 125 clock-names = "rmii-ref";
126 }; 126 };
127 }; 127 };
128 }; 128 };
129 129
130 &i2c1 { 130 &i2c1 {
131 clock-frequency = <100000>; 131 clock-frequency = <100000>;
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>; 133 pinctrl-0 = <&pinctrl_i2c1>;
134 status = "okay"; 134 status = "okay";
135 135
136 pmic: pmic@8 { 136 pmic: pmic@8 {
137 compatible = "fsl,pfuze3000"; 137 compatible = "fsl,pfuze3000";
138 reg = <0x08>; 138 reg = <0x08>;
139 139
140 regulators { 140 regulators {
141 /* VDD_ARM_SOC_IN*/ 141 /* VDD_ARM_SOC_IN*/
142 sw1b_reg: sw1b { 142 sw1b_reg: sw1b {
143 regulator-min- 143 regulator-min-microvolt = <700000>;
144 regulator-max- 144 regulator-max-microvolt = <1475000>;
145 regulator-boot 145 regulator-boot-on;
146 regulator-alwa 146 regulator-always-on;
147 regulator-ramp 147 regulator-ramp-delay = <6250>;
148 }; 148 };
149 149
150 /* DRAM */ 150 /* DRAM */
151 sw3a_reg: sw3 { 151 sw3a_reg: sw3 {
152 regulator-min- 152 regulator-min-microvolt = <900000>;
153 regulator-max- 153 regulator-max-microvolt = <1650000>;
154 regulator-boot 154 regulator-boot-on;
155 regulator-alwa 155 regulator-always-on;
156 }; 156 };
157 157
158 /* DRAM */ 158 /* DRAM */
159 vref_reg: vrefddr { 159 vref_reg: vrefddr {
160 regulator-boot 160 regulator-boot-on;
161 regulator-alwa 161 regulator-always-on;
162 }; 162 };
163 }; 163 };
164 }; 164 };
165 }; 165 };
166 166
167 &lcdif { 167 &lcdif {
168 pinctrl-names = "default"; 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_lcdif_dat &pinct 169 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
170 status = "okay"; 170 status = "okay";
171 171
172 port { 172 port {
173 display_out: endpoint { 173 display_out: endpoint {
174 remote-endpoint = <&pa 174 remote-endpoint = <&panel_in>;
175 }; 175 };
176 }; 176 };
177 }; 177 };
178 178
179 &pwm3 { 179 &pwm3 {
180 pinctrl-names = "default"; 180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_pwm3>; 181 pinctrl-0 = <&pinctrl_pwm3>;
182 status = "okay"; 182 status = "okay";
183 }; 183 };
184 184
185 &pwm7 { 185 &pwm7 {
186 pinctrl-names = "default"; 186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_pwm7>; 187 pinctrl-0 = <&pinctrl_pwm7>;
188 status = "okay"; 188 status = "okay";
189 }; 189 };
190 190
191 &pwm8 { 191 &pwm8 {
192 pinctrl-names = "default"; 192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_pwm8>; 193 pinctrl-0 = <&pinctrl_pwm8>;
194 status = "okay"; 194 status = "okay";
195 }; 195 };
196 196
197 &sai1 { 197 &sai1 {
198 pinctrl-names = "default"; 198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_sai1>; 199 pinctrl-0 = <&pinctrl_sai1>;
200 status = "okay"; 200 status = "okay";
201 }; 201 };
202 202
203 &uart3 { 203 &uart3 {
204 pinctrl-names = "default"; 204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_uart3>; 205 pinctrl-0 = <&pinctrl_uart3>;
206 uart-has-rtscts; 206 uart-has-rtscts;
207 status = "okay"; 207 status = "okay";
208 }; 208 };
209 209
210 &uart6 { 210 &uart6 {
211 pinctrl-names = "default"; 211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_uart6>; 212 pinctrl-0 = <&pinctrl_uart6>;
213 status = "okay"; 213 status = "okay";
214 }; 214 };
215 215
216 &usbotg1 { 216 &usbotg1 {
217 vbus-supply = <®_usb_otg_vbus>; 217 vbus-supply = <®_usb_otg_vbus>;
218 pinctrl-names = "default"; 218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usb_otg1_id>; 219 pinctrl-0 = <&pinctrl_usb_otg1_id>;
220 dr_mode = "otg"; 220 dr_mode = "otg";
221 disable-over-current; 221 disable-over-current;
222 status = "okay"; 222 status = "okay";
223 }; 223 };
224 224
225 &usbotg2 { 225 &usbotg2 {
226 dr_mode = "host"; 226 dr_mode = "host";
227 disable-over-current; 227 disable-over-current;
228 status = "okay"; 228 status = "okay";
229 }; 229 };
230 230
231 &usdhc1 { 231 &usdhc1 {
232 pinctrl-names = "default"; 232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_usdhc1>; 233 pinctrl-0 = <&pinctrl_usdhc1>;
234 bus-width = <8>; 234 bus-width = <8>;
235 no-1-8-v; 235 no-1-8-v;
236 non-removable; 236 non-removable;
237 keep-power-in-suspend; 237 keep-power-in-suspend;
238 status = "okay"; 238 status = "okay";
239 }; 239 };
240 240
241 &usdhc2 { /* Wifi SDIO */ 241 &usdhc2 { /* Wifi SDIO */
242 pinctrl-names = "default"; 242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_usdhc2>; 243 pinctrl-0 = <&pinctrl_usdhc2>;
244 no-1-8-v; 244 no-1-8-v;
245 non-removable; 245 non-removable;
246 keep-power-in-suspend; 246 keep-power-in-suspend;
247 wakeup-source; 247 wakeup-source;
248 vmmc-supply = <®_brcm>; 248 vmmc-supply = <®_brcm>;
249 status = "okay"; 249 status = "okay";
250 }; 250 };
251 251
252 &wdog1 { 252 &wdog1 {
253 pinctrl-names = "default"; 253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_wdog>; 254 pinctrl-0 = <&pinctrl_wdog>;
255 fsl,ext-reset-output; 255 fsl,ext-reset-output;
256 }; 256 };
257 257
258 &iomuxc { 258 &iomuxc {
259 pinctrl_brcm_reg: brcmreggrp { 259 pinctrl_brcm_reg: brcmreggrp {
260 fsl,pins = < 260 fsl,pins = <
261 MX6UL_PAD_NAND_DATA06_ 261 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
262 MX6UL_PAD_NAND_DATA04_ 262 MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
263 >; 263 >;
264 }; 264 };
265 265
266 pinctrl_enet2: enet2grp { 266 pinctrl_enet2: enet2grp {
267 fsl,pins = < 267 fsl,pins = <
268 MX6UL_PAD_ENET1_TX_DAT 268 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
269 MX6UL_PAD_ENET1_TX_EN_ 269 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
270 MX6UL_PAD_ENET2_RX_EN_ 270 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
271 MX6UL_PAD_ENET2_RX_ER_ 271 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
272 MX6UL_PAD_ENET2_RX_DAT 272 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
273 MX6UL_PAD_ENET2_RX_DAT 273 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
274 MX6UL_PAD_ENET2_TX_EN_ 274 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
275 MX6UL_PAD_ENET2_TX_DAT 275 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
276 MX6UL_PAD_ENET2_TX_DAT 276 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
277 MX6UL_PAD_ENET2_TX_CLK 277 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
278 MX6UL_PAD_SNVS_TAMPER6 278 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
279 MX6UL_PAD_UART4_TX_DAT 279 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
280 >; 280 >;
281 }; 281 };
282 282
283 pinctrl_flexcan1: flexcan1grp { 283 pinctrl_flexcan1: flexcan1grp {
284 fsl,pins = < 284 fsl,pins = <
285 MX6UL_PAD_ENET1_RX_DAT 285 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
286 MX6UL_PAD_ENET1_RX_DAT 286 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
287 >; 287 >;
288 }; 288 };
289 289
290 pinctrl_flexcan2: flexcan2grp { 290 pinctrl_flexcan2: flexcan2grp {
291 fsl,pins = < 291 fsl,pins = <
292 MX6UL_PAD_ENET1_TX_DAT 292 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
293 MX6UL_PAD_ENET1_RX_EN_ 293 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
294 >; 294 >;
295 }; 295 };
296 296
297 pinctrl_i2c1: i2c1grp { 297 pinctrl_i2c1: i2c1grp {
298 fsl,pins = < 298 fsl,pins = <
299 MX6UL_PAD_GPIO1_IO02__ 299 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
300 MX6UL_PAD_GPIO1_IO03__ 300 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
301 >; 301 >;
302 }; 302 };
303 303
304 pinctrl_i2c2: i2c2grp { 304 pinctrl_i2c2: i2c2grp {
305 fsl,pins = < 305 fsl,pins = <
306 MX6UL_PAD_UART5_TX_DAT 306 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
307 MX6UL_PAD_UART5_RX_DAT 307 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
308 >; 308 >;
309 }; 309 };
310 310
311 pinctrl_i2c3: i2c3grp { 311 pinctrl_i2c3: i2c3grp {
312 fsl,pins = < 312 fsl,pins = <
313 MX6UL_PAD_UART1_TX_DAT 313 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
314 MX6UL_PAD_UART1_RX_DAT 314 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
315 >; 315 >;
316 }; 316 };
317 317
318 pinctrl_lcdif_dat: lcdifdatgrp { 318 pinctrl_lcdif_dat: lcdifdatgrp {
319 fsl,pins = < 319 fsl,pins = <
320 MX6UL_PAD_LCD_DATA00__ 320 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
321 MX6UL_PAD_LCD_DATA01__ 321 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
322 MX6UL_PAD_LCD_DATA02__ 322 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
323 MX6UL_PAD_LCD_DATA03__ 323 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
324 MX6UL_PAD_LCD_DATA04__ 324 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
325 MX6UL_PAD_LCD_DATA05__ 325 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
326 MX6UL_PAD_LCD_DATA06__ 326 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
327 MX6UL_PAD_LCD_DATA07__ 327 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
328 MX6UL_PAD_LCD_DATA08__ 328 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
329 MX6UL_PAD_LCD_DATA09__ 329 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
330 MX6UL_PAD_LCD_DATA10__ 330 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
331 MX6UL_PAD_LCD_DATA11__ 331 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
332 MX6UL_PAD_LCD_DATA12__ 332 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
333 MX6UL_PAD_LCD_DATA13__ 333 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
334 MX6UL_PAD_LCD_DATA14__ 334 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
335 MX6UL_PAD_LCD_DATA15__ 335 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
336 MX6UL_PAD_LCD_DATA16__ 336 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
337 MX6UL_PAD_LCD_DATA17__ 337 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
338 MX6UL_PAD_LCD_DATA18__ 338 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
339 MX6UL_PAD_LCD_DATA19__ 339 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
340 MX6UL_PAD_LCD_DATA20__ 340 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
341 MX6UL_PAD_LCD_DATA21__ 341 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
342 MX6UL_PAD_LCD_DATA22__ 342 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
343 MX6UL_PAD_LCD_DATA23__ 343 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
344 >; 344 >;
345 }; 345 };
346 346
347 pinctrl_lcdif_ctrl: lcdifctrlgrp { 347 pinctrl_lcdif_ctrl: lcdifctrlgrp {
348 fsl,pins = < 348 fsl,pins = <
349 MX6UL_PAD_LCD_CLK__LCD 349 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
350 MX6UL_PAD_LCD_ENABLE__ 350 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
351 MX6UL_PAD_LCD_HSYNC__L 351 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
352 MX6UL_PAD_LCD_VSYNC__L 352 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
353 /* LCD reset */ 353 /* LCD reset */
354 MX6UL_PAD_SNVS_TAMPER9 354 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
355 >; 355 >;
356 }; 356 };
357 357
358 pinctrl_pwm3: pwm3grp { 358 pinctrl_pwm3: pwm3grp {
359 fsl,pins = < 359 fsl,pins = <
360 MX6UL_PAD_NAND_ALE__PW 360 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
361 >; 361 >;
362 }; 362 };
363 363
364 pinctrl_pwm7: pwm7grp { 364 pinctrl_pwm7: pwm7grp {
365 fsl,pins = < 365 fsl,pins = <
366 MX6UL_PAD_ENET1_TX_CLK 366 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
367 >; 367 >;
368 }; 368 };
369 369
370 pinctrl_pwm8: pwm8grp { 370 pinctrl_pwm8: pwm8grp {
371 fsl,pins = < 371 fsl,pins = <
372 MX6UL_PAD_ENET1_RX_ER_ 372 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
373 >; 373 >;
374 }; 374 };
375 375
376 pinctrl_sai1: sai1grp { 376 pinctrl_sai1: sai1grp {
377 fsl,pins = < 377 fsl,pins = <
378 MX6UL_PAD_CSI_DATA04__ 378 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
379 MX6UL_PAD_CSI_DATA05__ 379 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
380 MX6UL_PAD_CSI_DATA06__ 380 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
381 MX6UL_PAD_CSI_DATA07__ 381 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
382 >; 382 >;
383 }; 383 };
384 384
385 pinctrl_uart3: uart3grp { 385 pinctrl_uart3: uart3grp {
386 fsl,pins = < 386 fsl,pins = <
387 MX6UL_PAD_UART3_TX_DAT 387 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
388 MX6UL_PAD_UART3_RX_DAT 388 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
389 MX6UL_PAD_UART3_RTS_B_ 389 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
390 MX6UL_PAD_UART3_CTS_B_ 390 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
391 >; 391 >;
392 }; 392 };
393 393
394 pinctrl_uart5: uart5grp { 394 pinctrl_uart5: uart5grp {
395 fsl,pins = < 395 fsl,pins = <
396 MX6UL_PAD_GPIO1_IO04__ 396 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
397 MX6UL_PAD_GPIO1_IO05__ 397 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
398 MX6UL_PAD_GPIO1_IO08__ 398 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
399 MX6UL_PAD_GPIO1_IO09__ 399 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
400 >; 400 >;
401 }; 401 };
402 402
403 pinctrl_uart6: uart6grp { 403 pinctrl_uart6: uart6grp {
404 fsl,pins = < 404 fsl,pins = <
405 MX6UL_PAD_CSI_MCLK__UA 405 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
406 MX6UL_PAD_CSI_PIXCLK__ 406 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
407 >; 407 >;
408 }; 408 };
409 409
410 pinctrl_usb_otg1: usbotg1grp { 410 pinctrl_usb_otg1: usbotg1grp {
411 fsl,pins = < 411 fsl,pins = <
412 MX6UL_PAD_GPIO1_IO06__ 412 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
413 >; 413 >;
414 }; 414 };
415 415
416 pinctrl_usb_otg1_id: usbotg1idgrp { 416 pinctrl_usb_otg1_id: usbotg1idgrp {
417 fsl,pins = < 417 fsl,pins = <
418 MX6UL_PAD_GPIO1_IO00__ 418 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
419 >; 419 >;
420 }; 420 };
421 421
422 pinctrl_usdhc1: usdhc1grp { 422 pinctrl_usdhc1: usdhc1grp {
423 fsl,pins = < 423 fsl,pins = <
424 MX6UL_PAD_SD1_CMD__USD 424 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
425 MX6UL_PAD_SD1_CLK__USD 425 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
426 MX6UL_PAD_SD1_DATA0__U 426 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
427 MX6UL_PAD_SD1_DATA1__U 427 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
428 MX6UL_PAD_SD1_DATA2__U 428 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
429 MX6UL_PAD_SD1_DATA3__U 429 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
430 MX6UL_PAD_UART1_RTS_B_ 430 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
431 MX6UL_PAD_NAND_READY_B 431 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
432 MX6UL_PAD_NAND_CE0_B__ 432 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
433 MX6UL_PAD_NAND_CE1_B__ 433 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
434 MX6UL_PAD_NAND_CLE__US 434 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
435 >; 435 >;
436 }; 436 };
437 437
438 pinctrl_usdhc2: usdhc2grp { 438 pinctrl_usdhc2: usdhc2grp {
439 fsl,pins = < 439 fsl,pins = <
440 MX6UL_PAD_NAND_WE_B__U 440 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
441 MX6UL_PAD_NAND_RE_B__U 441 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
442 MX6UL_PAD_NAND_DATA00_ 442 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
443 MX6UL_PAD_NAND_DATA01_ 443 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
444 MX6UL_PAD_NAND_DATA02_ 444 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
445 MX6UL_PAD_NAND_DATA03_ 445 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
446 >; 446 >;
447 }; 447 };
448 448
449 pinctrl_wdog: wdoggrp { 449 pinctrl_wdog: wdoggrp {
450 fsl,pins = < 450 fsl,pins = <
451 MX6UL_PAD_LCD_RESET__W 451 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
452 >; 452 >;
453 }; 453 };
454 }; 454 };
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