1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /* 2 /*
3 * Copyright 2018-2022 TQ-Systems GmbH 3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-grou 4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
5 */ 5 */
6 6
7 #include "imx6ul.dtsi" 7 #include "imx6ul.dtsi"
8 #include "imx6ul-tqma6ul-common.dtsi" 8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi" 9 #include "imx6ul-tqma6ulxl-common.dtsi"
10 10
11 / { 11 / {
12 model = "TQ-Systems TQMa6UL2L SoM"; 12 model = "TQ-Systems TQMa6UL2L SoM";
13 compatible = "tq,imx6ul-tqma6ul2l", "f 13 compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
14 }; 14 };
15 15
16 &usdhc2 { 16 &usdhc2 {
17 fsl,tuning-step = <6>; 17 fsl,tuning-step = <6>;
18 }; 18 };
19 19
20 &iomuxc { 20 &iomuxc {
21 pinctrl_usdhc2: usdhc2grp { 21 pinctrl_usdhc2: usdhc2grp {
22 fsl,pins = < 22 fsl,pins = <
23 MX6UL_PAD_NAND_RE_B__U 23 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
24 MX6UL_PAD_NAND_WE_B__U 24 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
25 MX6UL_PAD_NAND_DATA00_ 25 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
26 MX6UL_PAD_NAND_DATA01_ 26 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
27 MX6UL_PAD_NAND_DATA02_ 27 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
28 MX6UL_PAD_NAND_DATA03_ 28 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
29 MX6UL_PAD_NAND_DATA04_ 29 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
30 MX6UL_PAD_NAND_DATA05_ 30 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
31 MX6UL_PAD_NAND_DATA06_ 31 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
32 MX6UL_PAD_NAND_DATA07_ 32 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
33 /* rst */ 33 /* rst */
34 MX6UL_PAD_NAND_ALE__GP 34 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
35 >; 35 >;
36 }; 36 };
37 37
38 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 38 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
39 fsl,pins = < 39 fsl,pins = <
40 MX6UL_PAD_NAND_RE_B__U 40 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
41 MX6UL_PAD_NAND_WE_B__U 41 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
42 MX6UL_PAD_NAND_DATA00_ 42 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
43 MX6UL_PAD_NAND_DATA01_ 43 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
44 MX6UL_PAD_NAND_DATA02_ 44 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
45 MX6UL_PAD_NAND_DATA03_ 45 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
46 MX6UL_PAD_NAND_DATA04_ 46 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
47 MX6UL_PAD_NAND_DATA05_ 47 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
48 MX6UL_PAD_NAND_DATA06_ 48 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
49 MX6UL_PAD_NAND_DATA07_ 49 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
50 /* rst */ 50 /* rst */
51 MX6UL_PAD_NAND_ALE__GP 51 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
52 >; 52 >;
53 }; 53 };
54 54
55 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 55 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
56 fsl,pins = < 56 fsl,pins = <
57 MX6UL_PAD_NAND_RE_B__U 57 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9
58 MX6UL_PAD_NAND_WE_B__U 58 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
59 MX6UL_PAD_NAND_DATA00_ 59 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
60 MX6UL_PAD_NAND_DATA01_ 60 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
61 MX6UL_PAD_NAND_DATA02_ 61 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
62 MX6UL_PAD_NAND_DATA03_ 62 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
63 MX6UL_PAD_NAND_DATA04_ 63 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
64 MX6UL_PAD_NAND_DATA05_ 64 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
65 MX6UL_PAD_NAND_DATA06_ 65 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
66 MX6UL_PAD_NAND_DATA07_ 66 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
67 /* rst */ 67 /* rst */
68 MX6UL_PAD_NAND_ALE__GP 68 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
69 >; 69 >;
70 }; 70 };
71 }; 71 };
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