1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /* 2 /*
3 * Copyright 2018-2022 TQ-Systems GmbH 3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-grou 4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
5 */ 5 */
6 6
7 /* 7 /*
8 * Common for 8 * Common for
9 * - TQMa6ULxL 9 * - TQMa6ULxL
10 * - TQMa6ULLxL 10 * - TQMa6ULLxL
11 */ 11 */
12 12
13 / { 13 / {
14 reg_vin: reg-vin { 14 reg_vin: reg-vin {
15 compatible = "regulator-fixed" 15 compatible = "regulator-fixed";
16 regulator-name = "VIN"; 16 regulator-name = "VIN";
17 regulator-min-microvolt = <330 17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <330 18 regulator-max-microvolt = <3300000>;
19 regulator-always-on; 19 regulator-always-on;
20 }; 20 };
21 }; 21 };
22 22
23 &m24c64_50 { 23 &m24c64_50 {
24 vcc-supply = <®_vin>; 24 vcc-supply = <®_vin>;
25 }; 25 };
26 26
27 &m24c02_52 { 27 &m24c02_52 {
28 vcc-supply = <®_vin>; 28 vcc-supply = <®_vin>;
29 }; 29 };
30 30
31 /* eMMC */ 31 /* eMMC */
32 &usdhc2 { 32 &usdhc2 {
33 vmmc-supply = <®_vin>; 33 vmmc-supply = <®_vin>;
34 vqmmc-supply = <®_vldo4>; 34 vqmmc-supply = <®_vldo4>;
35 }; 35 };
36 36
37 &iomuxc { 37 &iomuxc {
38 pinctrl_qspi: qspigrp { 38 pinctrl_qspi: qspigrp {
39 fsl,pins = < 39 fsl,pins = <
40 MX6UL_PAD_NAND_WP_B__Q 40 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9
41 MX6UL_PAD_NAND_READY_B 41 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9
42 MX6UL_PAD_NAND_CE0_B__ 42 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9
43 MX6UL_PAD_NAND_CE1_B__ 43 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
44 MX6UL_PAD_NAND_CLE__QS 44 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
45 MX6UL_PAD_NAND_DQS__QS 45 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
46 >; 46 >;
47 }; 47 };
48 }; 48 };
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