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Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-phytec-segin.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-phytec-segin.dtsi (Architecture i386) and /scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-phytec-segin.dtsi (Architecture sparc64)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)       1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*                                                  2 /*
  3  * Copyright (C) 2019 PHYTEC Messtechnik GmbH       3  * Copyright (C) 2019 PHYTEC Messtechnik GmbH
  4  * Author: Stefan Riedmueller <s.riedmueller@ph      4  * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
  5  */                                                 5  */
  6                                                     6 
  7 #include "imx6ul-phytec-segin.dtsi"                 7 #include "imx6ul-phytec-segin.dtsi"
  8                                                     8 
  9 / {                                                 9 / {
 10         model = "PHYTEC phyBOARD-Segin i.MX6 U     10         model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
 11         compatible = "phytec,imx6ull-pbacd-10"     11         compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
 12 };                                                 12 };
 13                                                    13 
 14 &iomuxc {                                          14 &iomuxc {
 15         /delete-node/ flexcan1engrp;               15         /delete-node/ flexcan1engrp;
 16         /delete-node/ rtcintgrp;                   16         /delete-node/ rtcintgrp;
 17 };                                                 17 };
 18                                                    18 
 19 &iomuxc_snvs {                                     19 &iomuxc_snvs {
 20         princtrl_flexcan1_en: flexcan1engrp {      20         princtrl_flexcan1_en: flexcan1engrp {
 21                 fsl,pins = <                       21                 fsl,pins = <
 22                         MX6ULL_PAD_SNVS_TAMPER     22                         MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x17059
 23                 >;                                 23                 >;
 24         };                                         24         };
 25                                                    25 
 26         pinctrl_rtc_int: rtcintgrp {               26         pinctrl_rtc_int: rtcintgrp {
 27                 fsl,pins = <                       27                 fsl,pins = <
 28                         MX6ULL_PAD_SNVS_TAMPER     28                         MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x17059
 29                 >;                                 29                 >;
 30         };                                         30         };
 31 };                                                 31 };
                                                      

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