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Linux/scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-tqma6ull2l.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-tqma6ull2l.dtsi (Architecture i386) and /scripts/dtc/include-prefixes/arm/nxp/imx/imx6ull-tqma6ull2l.dtsi (Architecture m68k)


  1 // SPDX-License-Identifier: (GPL-2.0-or-later       1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
  2 /*                                                  2 /*
  3  * Copyright 2018-2022 TQ-Systems GmbH              3  * Copyright 2018-2022 TQ-Systems GmbH
  4  * Author: Markus Niebel <Markus.Niebel@tq-grou      4  * Author: Markus Niebel <Markus.Niebel@tq-group.com>
  5  */                                                 5  */
  6                                                     6 
  7 #include "imx6ull.dtsi"                             7 #include "imx6ull.dtsi"
  8 #include "imx6ul-tqma6ul-common.dtsi"               8 #include "imx6ul-tqma6ul-common.dtsi"
  9 #include "imx6ul-tqma6ulxl-common.dtsi"             9 #include "imx6ul-tqma6ulxl-common.dtsi"
 10                                                    10 
 11 / {                                                11 / {
 12         model = "TQ Systems TQMa6ULL2L SoM";       12         model = "TQ Systems TQMa6ULL2L SoM";
 13         compatible = "tq,imx6ull-tqma6ull2l",      13         compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
 14 };                                                 14 };
 15                                                    15 
 16 &usdhc2 {                                          16 &usdhc2 {
 17         fsl,tuning-step = <6>;                     17         fsl,tuning-step = <6>;
 18         /* Errata ERR010450 Workaround */          18         /* Errata ERR010450 Workaround */
 19         max-frequency = <99000000>;                19         max-frequency = <99000000>;
 20         assigned-clocks = <&clks IMX6UL_CLK_US     20         assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
 21         assigned-clock-parents = <&clks IMX6UL     21         assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 22         assigned-clock-rates = <0>, <198000000     22         assigned-clock-rates = <0>, <198000000>;
 23 };                                                 23 };
 24                                                    24 
 25 &iomuxc {                                          25 &iomuxc {
 26         pinctrl_usdhc2: usdhc2grp {                26         pinctrl_usdhc2: usdhc2grp {
 27                 fsl,pins = <                       27                 fsl,pins = <
 28                         MX6UL_PAD_NAND_RE_B__U     28                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x00017031
 29                         MX6UL_PAD_NAND_WE_B__U     29                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x00017039
 30                         MX6UL_PAD_NAND_DATA00_     30                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x00017039
 31                         MX6UL_PAD_NAND_DATA01_     31                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x00017039
 32                         MX6UL_PAD_NAND_DATA02_     32                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x00017039
 33                         MX6UL_PAD_NAND_DATA03_     33                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x00017039
 34                         MX6UL_PAD_NAND_DATA04_     34                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x00017039
 35                         MX6UL_PAD_NAND_DATA05_     35                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x00017039
 36                         MX6UL_PAD_NAND_DATA06_     36                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x00017039
 37                         MX6UL_PAD_NAND_DATA07_     37                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x00017039
 38                         /* rst */                  38                         /* rst */
 39                         MX6UL_PAD_NAND_ALE__GP     39                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
 40                 >;                                 40                 >;
 41         };                                         41         };
 42                                                    42 
 43         pinctrl_usdhc2_100mhz: usdhc2-100mhzgr     43         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 44                 fsl,pins = <                       44                 fsl,pins = <
 45                         MX6UL_PAD_NAND_RE_B__U     45                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170f1
 46                         MX6UL_PAD_NAND_WE_B__U     46                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
 47                         MX6UL_PAD_NAND_DATA00_     47                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
 48                         MX6UL_PAD_NAND_DATA01_     48                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
 49                         MX6UL_PAD_NAND_DATA02_     49                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
 50                         MX6UL_PAD_NAND_DATA03_     50                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
 51                         MX6UL_PAD_NAND_DATA04_     51                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
 52                         MX6UL_PAD_NAND_DATA05_     52                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
 53                         MX6UL_PAD_NAND_DATA06_     53                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
 54                         MX6UL_PAD_NAND_DATA07_     54                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
 55                         /* rst */                  55                         /* rst */
 56                         MX6UL_PAD_NAND_ALE__GP     56                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
 57                 >;                                 57                 >;
 58         };                                         58         };
 59                                                    59 
 60         pinctrl_usdhc2_200mhz: usdhc2-200mhzgr     60         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 61                 fsl,pins = <                       61                 fsl,pins = <
 62                         MX6UL_PAD_NAND_RE_B__U     62                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170f1
 63                         MX6UL_PAD_NAND_WE_B__U     63                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
 64                         MX6UL_PAD_NAND_DATA00_     64                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
 65                         MX6UL_PAD_NAND_DATA01_     65                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
 66                         MX6UL_PAD_NAND_DATA02_     66                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
 67                         MX6UL_PAD_NAND_DATA03_     67                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
 68                         MX6UL_PAD_NAND_DATA04_     68                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
 69                         MX6UL_PAD_NAND_DATA05_     69                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
 70                         MX6UL_PAD_NAND_DATA06_     70                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
 71                         MX6UL_PAD_NAND_DATA07_     71                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
 72                         /* rst */                  72                         /* rst */
 73                         MX6UL_PAD_NAND_ALE__GP     73                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
 74                 >;                                 74                 >;
 75         };                                         75         };
 76 };                                                 76 };
                                                      

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