1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 // 2 //
3 // Copyright (C) 2015 Freescale Semiconductor, 3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
4 4
5 /dts-v1/; 5 /dts-v1/;
6 6
7 #include "imx7d.dtsi" 7 #include "imx7d.dtsi"
8 8
9 / { 9 / {
10 model = "Freescale i.MX7 SabreSD Board 10 model = "Freescale i.MX7 SabreSD Board";
11 compatible = "fsl,imx7d-sdb", "fsl,imx 11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
12 12
13 aliases { 13 aliases {
14 ethernet0 = &fec1; 14 ethernet0 = &fec1;
15 ethernet1 = &fec2; 15 ethernet1 = &fec2;
16 }; 16 };
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 memory@80000000 { 22 memory@80000000 {
23 device_type = "memory"; 23 device_type = "memory";
24 reg = <0x80000000 0x80000000>; 24 reg = <0x80000000 0x80000000>;
25 }; 25 };
26 26
27 gpio-keys { 27 gpio-keys {
28 compatible = "gpio-keys"; 28 compatible = "gpio-keys";
29 pinctrl-names = "default"; 29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_key 30 pinctrl-0 = <&pinctrl_gpio_keys>;
31 31
32 key-volume-up { 32 key-volume-up {
33 label = "Volume Up"; 33 label = "Volume Up";
34 gpios = <&gpio5 11 GPI 34 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_VOLU 35 linux,code = <KEY_VOLUMEUP>;
36 wakeup-source; 36 wakeup-source;
37 }; 37 };
38 38
39 key-volume-down { 39 key-volume-down {
40 label = "Volume Down"; 40 label = "Volume Down";
41 gpios = <&gpio5 10 GPI 41 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLU 42 linux,code = <KEY_VOLUMEDOWN>;
43 wakeup-source; 43 wakeup-source;
44 }; 44 };
45 }; 45 };
46 46
47 spi-4 { 47 spi-4 {
48 compatible = "spi-gpio"; 48 compatible = "spi-gpio";
49 pinctrl-names = "default"; 49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_spi4>; 50 pinctrl-0 = <&pinctrl_spi4>;
51 sck-gpios = <&gpio1 13 GPIO_AC 51 sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
52 mosi-gpios = <&gpio1 9 GPIO_AC 52 mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
53 cs-gpios = <&gpio1 12 GPIO_ACT 53 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
54 num-chipselects = <1>; 54 num-chipselects = <1>;
55 #address-cells = <1>; 55 #address-cells = <1>;
56 #size-cells = <0>; 56 #size-cells = <0>;
57 57
58 extended_io: gpio-expander@0 { 58 extended_io: gpio-expander@0 {
59 compatible = "fairchil 59 compatible = "fairchild,74hc595";
60 gpio-controller; 60 gpio-controller;
61 #gpio-cells = <2>; 61 #gpio-cells = <2>;
62 reg = <0>; 62 reg = <0>;
63 registers-number = <1> 63 registers-number = <1>;
64 spi-max-frequency = <1 64 spi-max-frequency = <100000>;
65 }; 65 };
66 }; 66 };
67 67
68 reg_sd1_vmmc: regulator-sd1-vmmc { 68 reg_sd1_vmmc: regulator-sd1-vmmc {
69 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
70 regulator-name = "VDD_SD1"; 70 regulator-name = "VDD_SD1";
71 regulator-min-microvolt = <330 71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <330 72 regulator-max-microvolt = <3300000>;
73 gpio = <&gpio5 2 GPIO_ACTIVE_H 73 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
74 enable-active-high; 74 enable-active-high;
75 startup-delay-us = <200000>; 75 startup-delay-us = <200000>;
76 off-on-delay-us = <20000>; 76 off-on-delay-us = <20000>;
77 }; 77 };
78 78
79 reg_usb_otg1_vbus: regulator-usb-otg1- 79 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
80 compatible = "regulator-fixed" 80 compatible = "regulator-fixed";
81 regulator-name = "usb_otg1_vbu 81 regulator-name = "usb_otg1_vbus";
82 regulator-min-microvolt = <500 82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <500 83 regulator-max-microvolt = <5000000>;
84 gpio = <&gpio1 5 GPIO_ACTIVE_H 84 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
85 enable-active-high; 85 enable-active-high;
86 }; 86 };
87 87
88 reg_usb_otg2_vbus: regulator-usb-otg2- 88 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
89 compatible = "regulator-fixed" 89 compatible = "regulator-fixed";
90 regulator-name = "usb_otg2_vbu 90 regulator-name = "usb_otg2_vbus";
91 pinctrl-names = "default"; 91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_usb_otg2 92 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
93 regulator-min-microvolt = <500 93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <500 94 regulator-max-microvolt = <5000000>;
95 gpio = <&gpio1 7 GPIO_ACTIVE_H 95 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
96 enable-active-high; 96 enable-active-high;
97 }; 97 };
98 98
99 reg_vref_1v8: regulator-vref-1v8 { 99 reg_vref_1v8: regulator-vref-1v8 {
100 compatible = "regulator-fixed" 100 compatible = "regulator-fixed";
101 regulator-name = "vref-1v8"; 101 regulator-name = "vref-1v8";
102 regulator-min-microvolt = <180 102 regulator-min-microvolt = <1800000>;
103 regulator-max-microvolt = <180 103 regulator-max-microvolt = <1800000>;
104 }; 104 };
105 105
106 reg_brcm: regulator-brcm { 106 reg_brcm: regulator-brcm {
107 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
108 gpio = <&gpio4 21 GPIO_ACTIVE_ 108 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
109 enable-active-high; 109 enable-active-high;
110 regulator-name = "brcm_reg"; 110 regulator-name = "brcm_reg";
111 pinctrl-names = "default"; 111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_brcm_reg 112 pinctrl-0 = <&pinctrl_brcm_reg>;
113 regulator-min-microvolt = <330 113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <330 114 regulator-max-microvolt = <3300000>;
115 startup-delay-us = <200000>; 115 startup-delay-us = <200000>;
116 }; 116 };
117 117
118 reg_lcd_3v3: regulator-lcd-3v3 { 118 reg_lcd_3v3: regulator-lcd-3v3 {
119 compatible = "regulator-fixed" 119 compatible = "regulator-fixed";
120 regulator-name = "lcd-3v3"; 120 regulator-name = "lcd-3v3";
121 regulator-min-microvolt = <330 121 regulator-min-microvolt = <3300000>;
122 regulator-max-microvolt = <330 122 regulator-max-microvolt = <3300000>;
123 gpio = <&extended_io 7 GPIO_AC 123 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
124 }; 124 };
125 125
126 reg_can2_3v3: regulator-can2-3v3 { 126 reg_can2_3v3: regulator-can2-3v3 {
127 compatible = "regulator-fixed" 127 compatible = "regulator-fixed";
128 regulator-name = "can2-3v3"; 128 regulator-name = "can2-3v3";
129 pinctrl-names = "default"; 129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_flexcan2 130 pinctrl-0 = <&pinctrl_flexcan2_reg>;
131 regulator-min-microvolt = <330 131 regulator-min-microvolt = <3300000>;
132 regulator-max-microvolt = <330 132 regulator-max-microvolt = <3300000>;
133 gpio = <&gpio2 14 GPIO_ACTIVE_ 133 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
134 }; 134 };
135 135
136 reg_fec2_3v3: regulator-fec2-3v3 { 136 reg_fec2_3v3: regulator-fec2-3v3 {
137 compatible = "regulator-fixed" 137 compatible = "regulator-fixed";
138 regulator-name = "fec2-3v3"; 138 regulator-name = "fec2-3v3";
139 pinctrl-names = "default"; 139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_enet2_re 140 pinctrl-0 = <&pinctrl_enet2_reg>;
141 regulator-min-microvolt = <330 141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <330 142 regulator-max-microvolt = <3300000>;
143 gpio = <&gpio1 4 GPIO_ACTIVE_L 143 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
144 }; 144 };
145 145
146 backlight: backlight { 146 backlight: backlight {
147 compatible = "pwm-backlight"; 147 compatible = "pwm-backlight";
148 pwms = <&pwm1 0 5000000 0>; 148 pwms = <&pwm1 0 5000000 0>;
149 brightness-levels = <0 4 8 16 149 brightness-levels = <0 4 8 16 32 64 128 255>;
150 default-brightness-level = <6> 150 default-brightness-level = <6>;
151 status = "okay"; 151 status = "okay";
152 }; 152 };
153 153
154 panel { 154 panel {
155 compatible = "innolux,at043tn2 155 compatible = "innolux,at043tn24";
156 backlight = <&backlight>; 156 backlight = <&backlight>;
157 power-supply = <®_lcd_3v3>; 157 power-supply = <®_lcd_3v3>;
158 158
159 port { 159 port {
160 panel_in: endpoint { 160 panel_in: endpoint {
161 remote-endpoin 161 remote-endpoint = <&display_out>;
162 }; 162 };
163 }; 163 };
164 }; 164 };
165 165
166 sound { 166 sound {
167 compatible = "fsl,imx7d-evk-wm 167 compatible = "fsl,imx7d-evk-wm8960",
168 "fsl,imx-audio-wm 168 "fsl,imx-audio-wm8960";
169 model = "wm8960-audio"; 169 model = "wm8960-audio";
170 audio-cpu = <&sai1>; 170 audio-cpu = <&sai1>;
171 audio-codec = <&codec>; 171 audio-codec = <&codec>;
172 hp-det-gpio = <&gpio2 28 GPIO_ 172 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
173 audio-routing = 173 audio-routing =
174 "Headphone Jack", "HP_ 174 "Headphone Jack", "HP_L",
175 "Headphone Jack", "HP_ 175 "Headphone Jack", "HP_R",
176 "Ext Spk", "SPK_LP", 176 "Ext Spk", "SPK_LP",
177 "Ext Spk", "SPK_LN", 177 "Ext Spk", "SPK_LN",
178 "Ext Spk", "SPK_RP", 178 "Ext Spk", "SPK_RP",
179 "Ext Spk", "SPK_RN", 179 "Ext Spk", "SPK_RN",
180 "LINPUT1", "AMIC", 180 "LINPUT1", "AMIC",
181 "AMIC", "MICB"; 181 "AMIC", "MICB";
182 }; 182 };
183 183
184 sound-hdmi { 184 sound-hdmi {
185 compatible = "fsl,imx-audio-si 185 compatible = "fsl,imx-audio-sii902x";
186 model = "sii902x-audio"; 186 model = "sii902x-audio";
187 audio-cpu = <&sai3>; 187 audio-cpu = <&sai3>;
188 hdmi-out; 188 hdmi-out;
189 }; 189 };
190 }; 190 };
191 191
192 &adc1 { 192 &adc1 {
193 vref-supply = <®_vref_1v8>; 193 vref-supply = <®_vref_1v8>;
194 status = "okay"; 194 status = "okay";
195 }; 195 };
196 196
197 &adc2 { 197 &adc2 {
198 vref-supply = <®_vref_1v8>; 198 vref-supply = <®_vref_1v8>;
199 status = "okay"; 199 status = "okay";
200 }; 200 };
201 201
202 &cpu0 { 202 &cpu0 {
203 cpu-supply = <&sw1a_reg>; 203 cpu-supply = <&sw1a_reg>;
204 }; 204 };
205 205
206 &cpu1 { 206 &cpu1 {
207 cpu-supply = <&sw1a_reg>; 207 cpu-supply = <&sw1a_reg>;
208 }; 208 };
209 209
210 &ecspi3 { 210 &ecspi3 {
211 pinctrl-names = "default"; 211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_ecspi3>; 212 pinctrl-0 = <&pinctrl_ecspi3>;
213 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 213 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
214 status = "okay"; 214 status = "okay";
215 215
216 tsc2046@0 { 216 tsc2046@0 {
217 compatible = "ti,tsc2046"; 217 compatible = "ti,tsc2046";
218 reg = <0>; 218 reg = <0>;
219 spi-max-frequency = <1000000>; 219 spi-max-frequency = <1000000>;
220 pinctrl-names = "default"; 220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_tsc2046_ 221 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
222 interrupt-parent = <&gpio2>; 222 interrupt-parent = <&gpio2>;
223 interrupts = <29 0>; 223 interrupts = <29 0>;
224 pendown-gpio = <&gpio2 29 GPIO 224 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
225 touchscreen-max-pressure = <25 225 touchscreen-max-pressure = <255>;
226 wakeup-source; 226 wakeup-source;
227 }; 227 };
228 }; 228 };
229 229
230 &fec1 { 230 &fec1 {
231 pinctrl-names = "default"; 231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_enet1>; 232 pinctrl-0 = <&pinctrl_enet1>;
233 assigned-clocks = <&clks IMX7D_ENET1_T 233 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
234 <&clks IMX7D_ENET1_T 234 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
235 assigned-clock-parents = <&clks IMX7D_ 235 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
236 assigned-clock-rates = <0>, <100000000 236 assigned-clock-rates = <0>, <100000000>;
237 phy-mode = "rgmii"; 237 phy-mode = "rgmii";
238 phy-handle = <ðphy0>; 238 phy-handle = <ðphy0>;
239 fsl,magic-packet; 239 fsl,magic-packet;
240 phy-reset-gpios = <&extended_io 5 GPIO 240 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
241 status = "okay"; 241 status = "okay";
242 242
243 mdio { 243 mdio {
244 #address-cells = <1>; 244 #address-cells = <1>;
245 #size-cells = <0>; 245 #size-cells = <0>;
246 246
247 ethphy0: ethernet-phy@0 { 247 ethphy0: ethernet-phy@0 {
248 reg = <0>; 248 reg = <0>;
249 }; 249 };
250 250
251 ethphy1: ethernet-phy@1 { 251 ethphy1: ethernet-phy@1 {
252 reg = <1>; 252 reg = <1>;
253 }; 253 };
254 }; 254 };
255 }; 255 };
256 256
257 &fec2 { 257 &fec2 {
258 pinctrl-names = "default"; 258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_enet2>; 259 pinctrl-0 = <&pinctrl_enet2>;
260 assigned-clocks = <&clks IMX7D_ENET2_T 260 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
261 <&clks IMX7D_ENET2_T 261 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
262 assigned-clock-parents = <&clks IMX7D_ 262 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
263 assigned-clock-rates = <0>, <100000000 263 assigned-clock-rates = <0>, <100000000>;
264 phy-mode = "rgmii"; 264 phy-mode = "rgmii";
265 phy-handle = <ðphy1>; 265 phy-handle = <ðphy1>;
266 phy-supply = <®_fec2_3v3>; 266 phy-supply = <®_fec2_3v3>;
267 fsl,magic-packet; 267 fsl,magic-packet;
268 status = "okay"; 268 status = "okay";
269 }; 269 };
270 270
271 &flexcan2 { 271 &flexcan2 {
272 pinctrl-names = "default"; 272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_flexcan2>; 273 pinctrl-0 = <&pinctrl_flexcan2>;
274 xceiver-supply = <®_can2_3v3>; 274 xceiver-supply = <®_can2_3v3>;
275 status = "okay"; 275 status = "okay";
276 }; 276 };
277 277
278 &i2c1 { 278 &i2c1 {
279 pinctrl-names = "default"; 279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c1>; 280 pinctrl-0 = <&pinctrl_i2c1>;
281 status = "okay"; 281 status = "okay";
282 282
283 pmic: pmic@8 { 283 pmic: pmic@8 {
284 compatible = "fsl,pfuze3000"; 284 compatible = "fsl,pfuze3000";
285 reg = <0x08>; 285 reg = <0x08>;
286 286
287 regulators { 287 regulators {
288 sw1a_reg: sw1a { 288 sw1a_reg: sw1a {
289 regulator-min- 289 regulator-min-microvolt = <700000>;
290 regulator-max- 290 regulator-max-microvolt = <1475000>;
291 regulator-boot 291 regulator-boot-on;
292 regulator-alwa 292 regulator-always-on;
293 regulator-ramp 293 regulator-ramp-delay = <6250>;
294 }; 294 };
295 295
296 /* use sw1c_reg to ali 296 /* use sw1c_reg to align with pfuze100/pfuze200 */
297 sw1c_reg: sw1b { 297 sw1c_reg: sw1b {
298 regulator-min- 298 regulator-min-microvolt = <700000>;
299 regulator-max- 299 regulator-max-microvolt = <1475000>;
300 regulator-boot 300 regulator-boot-on;
301 regulator-alwa 301 regulator-always-on;
302 regulator-ramp 302 regulator-ramp-delay = <6250>;
303 }; 303 };
304 304
305 sw2_reg: sw2 { 305 sw2_reg: sw2 {
306 regulator-min- 306 regulator-min-microvolt = <1800000>;
307 regulator-max- 307 regulator-max-microvolt = <1800000>;
308 regulator-boot 308 regulator-boot-on;
309 regulator-alwa 309 regulator-always-on;
310 }; 310 };
311 311
312 sw3a_reg: sw3 { 312 sw3a_reg: sw3 {
313 regulator-min- 313 regulator-min-microvolt = <900000>;
314 regulator-max- 314 regulator-max-microvolt = <1650000>;
315 regulator-boot 315 regulator-boot-on;
316 regulator-alwa 316 regulator-always-on;
317 }; 317 };
318 318
319 swbst_reg: swbst { 319 swbst_reg: swbst {
320 regulator-min- 320 regulator-min-microvolt = <5000000>;
321 regulator-max- 321 regulator-max-microvolt = <5150000>;
322 }; 322 };
323 323
324 snvs_reg: vsnvs { 324 snvs_reg: vsnvs {
325 regulator-min- 325 regulator-min-microvolt = <1000000>;
326 regulator-max- 326 regulator-max-microvolt = <3000000>;
327 regulator-boot 327 regulator-boot-on;
328 regulator-alwa 328 regulator-always-on;
329 }; 329 };
330 330
331 vref_reg: vrefddr { 331 vref_reg: vrefddr {
332 regulator-boot 332 regulator-boot-on;
333 regulator-alwa 333 regulator-always-on;
334 }; 334 };
335 335
336 vgen1_reg: vldo1 { 336 vgen1_reg: vldo1 {
337 regulator-min- 337 regulator-min-microvolt = <1800000>;
338 regulator-max- 338 regulator-max-microvolt = <3300000>;
339 regulator-alwa 339 regulator-always-on;
340 }; 340 };
341 341
342 vgen2_reg: vldo2 { 342 vgen2_reg: vldo2 {
343 regulator-min- 343 regulator-min-microvolt = <800000>;
344 regulator-max- 344 regulator-max-microvolt = <1550000>;
345 }; 345 };
346 346
347 vgen3_reg: vccsd { 347 vgen3_reg: vccsd {
348 regulator-min- 348 regulator-min-microvolt = <2850000>;
349 regulator-max- 349 regulator-max-microvolt = <3300000>;
350 regulator-alwa 350 regulator-always-on;
351 }; 351 };
352 352
353 vgen4_reg: v33 { 353 vgen4_reg: v33 {
354 regulator-min- 354 regulator-min-microvolt = <2850000>;
355 regulator-max- 355 regulator-max-microvolt = <3300000>;
356 regulator-alwa 356 regulator-always-on;
357 }; 357 };
358 358
359 vgen5_reg: vldo3 { 359 vgen5_reg: vldo3 {
360 regulator-min- 360 regulator-min-microvolt = <1800000>;
361 regulator-max- 361 regulator-max-microvolt = <3300000>;
362 regulator-alwa 362 regulator-always-on;
363 }; 363 };
364 364
365 vgen6_reg: vldo4 { 365 vgen6_reg: vldo4 {
366 regulator-min- 366 regulator-min-microvolt = <2800000>;
367 regulator-max- 367 regulator-max-microvolt = <2800000>;
368 regulator-alwa 368 regulator-always-on;
369 }; 369 };
370 }; 370 };
371 }; 371 };
372 }; 372 };
373 373
374 &i2c2 { 374 &i2c2 {
375 pinctrl-names = "default"; 375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_i2c2>; 376 pinctrl-0 = <&pinctrl_i2c2>;
377 status = "okay"; 377 status = "okay";
378 378
379 mpl3115@60 { 379 mpl3115@60 {
380 compatible = "fsl,mpl3115"; 380 compatible = "fsl,mpl3115";
381 reg = <0x60>; 381 reg = <0x60>;
382 }; 382 };
383 }; 383 };
384 384
385 &i2c3 { 385 &i2c3 {
386 pinctrl-names = "default"; 386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_i2c3>; 387 pinctrl-0 = <&pinctrl_i2c3>;
388 status = "okay"; 388 status = "okay";
389 }; 389 };
390 390
391 &i2c4 { 391 &i2c4 {
392 pinctrl-names = "default"; 392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_i2c4>; 393 pinctrl-0 = <&pinctrl_i2c4>;
394 status = "okay"; 394 status = "okay";
395 395
396 codec: wm8960@1a { 396 codec: wm8960@1a {
397 compatible = "wlf,wm8960"; 397 compatible = "wlf,wm8960";
398 reg = <0x1a>; 398 reg = <0x1a>;
399 clocks = <&clks IMX7D_AUDIO_MC 399 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
400 clock-names = "mclk"; 400 clock-names = "mclk";
401 wlf,shared-lrclk; 401 wlf,shared-lrclk;
402 wlf,hp-cfg = <2 2 3>; 402 wlf,hp-cfg = <2 2 3>;
403 wlf,gpio-cfg = <1 3>; 403 wlf,gpio-cfg = <1 3>;
404 assigned-clocks = <&clks IMX7D 404 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
405 <&clks IMX7D 405 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
406 <&clks IMX7D 406 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
407 assigned-clock-parents = <&clk 407 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
408 assigned-clock-rates = <0>, <8 408 assigned-clock-rates = <0>, <884736000>, <12288000>;
409 }; 409 };
410 }; 410 };
411 411
412 &lcdif { 412 &lcdif {
413 pinctrl-names = "default"; 413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_lcdif>; 414 pinctrl-0 = <&pinctrl_lcdif>;
415 status = "okay"; 415 status = "okay";
416 416
417 port { 417 port {
418 display_out: endpoint { 418 display_out: endpoint {
419 remote-endpoint = <&pa 419 remote-endpoint = <&panel_in>;
420 }; 420 };
421 }; 421 };
422 }; 422 };
423 423
424 &pcie { 424 &pcie {
425 reset-gpio = <&extended_io 1 GPIO_ACTI 425 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
426 status = "okay"; 426 status = "okay";
427 }; 427 };
428 428
429 ®_1p0d { 429 ®_1p0d {
430 vin-supply = <&sw2_reg>; 430 vin-supply = <&sw2_reg>;
431 }; 431 };
432 432
433 ®_1p2 { 433 ®_1p2 {
434 vin-supply = <&sw2_reg>; 434 vin-supply = <&sw2_reg>;
435 }; 435 };
436 436
437 &sai1 { 437 &sai1 {
438 pinctrl-names = "default"; 438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_sai1>; 439 pinctrl-0 = <&pinctrl_sai1>;
440 assigned-clocks = <&clks IMX7D_SAI1_RO 440 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
441 <&clks IMX7D_PLL_AUD 441 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
442 <&clks IMX7D_SAI1_RO 442 <&clks IMX7D_SAI1_ROOT_CLK>;
443 assigned-clock-parents = <&clks IMX7D_ 443 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
444 assigned-clock-rates = <0>, <884736000 444 assigned-clock-rates = <0>, <884736000>, <36864000>;
445 status = "okay"; 445 status = "okay";
446 }; 446 };
447 447
448 &sai3 { 448 &sai3 {
449 pinctrl-names = "default"; 449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sa 450 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
451 assigned-clocks = <&clks IMX7D_SAI3_RO 451 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
452 <&clks IMX7D_PLL_AUD 452 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
453 <&clks IMX7D_SAI3_RO 453 <&clks IMX7D_SAI3_ROOT_CLK>;
454 assigned-clock-parents = <&clks IMX7D_ 454 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
455 assigned-clock-rates = <0>, <884736000 455 assigned-clock-rates = <0>, <884736000>, <36864000>;
456 status = "okay"; 456 status = "okay";
457 }; 457 };
458 458
459 &snvs_pwrkey { 459 &snvs_pwrkey {
460 status = "okay"; 460 status = "okay";
461 }; 461 };
462 462
463 &uart1 { 463 &uart1 {
464 pinctrl-names = "default"; 464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_uart1>; 465 pinctrl-0 = <&pinctrl_uart1>;
466 assigned-clocks = <&clks IMX7D_UART1_R 466 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
467 assigned-clock-parents = <&clks IMX7D_ 467 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
468 status = "okay"; 468 status = "okay";
469 }; 469 };
470 470
471 &uart6 { 471 &uart6 {
472 pinctrl-names = "default"; 472 pinctrl-names = "default";
473 pinctrl-0 = <&pinctrl_uart6>; 473 pinctrl-0 = <&pinctrl_uart6>;
474 assigned-clocks = <&clks IMX7D_UART6_R 474 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
475 assigned-clock-parents = <&clks IMX7D_ 475 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
476 uart-has-rtscts; 476 uart-has-rtscts;
477 status = "okay"; 477 status = "okay";
478 }; 478 };
479 479
480 &usbotg1 { 480 &usbotg1 {
481 vbus-supply = <®_usb_otg1_vbus>; 481 vbus-supply = <®_usb_otg1_vbus>;
482 status = "okay"; 482 status = "okay";
483 }; 483 };
484 484
485 &usbotg2 { 485 &usbotg2 {
486 vbus-supply = <®_usb_otg2_vbus>; 486 vbus-supply = <®_usb_otg2_vbus>;
487 dr_mode = "host"; 487 dr_mode = "host";
488 status = "okay"; 488 status = "okay";
489 }; 489 };
490 490
491 &usdhc1 { 491 &usdhc1 {
492 pinctrl-names = "default", "state_100m 492 pinctrl-names = "default", "state_100mhz", "state_200mhz";
493 pinctrl-0 = <&pinctrl_usdhc1>, <&pinct 493 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
494 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, 494 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
495 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, 495 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
496 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 496 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
497 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH> 497 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
498 vmmc-supply = <®_sd1_vmmc>; 498 vmmc-supply = <®_sd1_vmmc>;
499 wakeup-source; 499 wakeup-source;
500 keep-power-in-suspend; 500 keep-power-in-suspend;
501 status = "okay"; 501 status = "okay";
502 }; 502 };
503 503
504 &usdhc2 { 504 &usdhc2 {
505 pinctrl-names = "default", "state_100m 505 pinctrl-names = "default", "state_100mhz", "state_200mhz";
506 pinctrl-0 = <&pinctrl_usdhc2>; 506 pinctrl-0 = <&pinctrl_usdhc2>;
507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
509 wakeup-source; 509 wakeup-source;
510 keep-power-in-suspend; 510 keep-power-in-suspend;
511 non-removable; 511 non-removable;
512 vmmc-supply = <®_brcm>; 512 vmmc-supply = <®_brcm>;
513 fsl,tuning-step = <2>; 513 fsl,tuning-step = <2>;
514 status = "okay"; 514 status = "okay";
515 }; 515 };
516 516
517 &usdhc3 { 517 &usdhc3 {
518 pinctrl-names = "default", "state_100m 518 pinctrl-names = "default", "state_100mhz", "state_200mhz";
519 pinctrl-0 = <&pinctrl_usdhc3>; 519 pinctrl-0 = <&pinctrl_usdhc3>;
520 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 520 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
521 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 521 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
522 assigned-clocks = <&clks IMX7D_USDHC3_ 522 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
523 assigned-clock-rates = <400000000>; 523 assigned-clock-rates = <400000000>;
524 bus-width = <8>; 524 bus-width = <8>;
525 fsl,tuning-step = <2>; 525 fsl,tuning-step = <2>;
526 non-removable; 526 non-removable;
527 status = "okay"; 527 status = "okay";
528 }; 528 };
529 529
530 &wdog1 { 530 &wdog1 {
531 pinctrl-names = "default"; 531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_wdog>; 532 pinctrl-0 = <&pinctrl_wdog>;
533 fsl,ext-reset-output; 533 fsl,ext-reset-output;
534 }; 534 };
535 535
536 &iomuxc { 536 &iomuxc {
537 pinctrl-names = "default"; 537 pinctrl-names = "default";
538 pinctrl-0 = <&pinctrl_hog>; 538 pinctrl-0 = <&pinctrl_hog>;
539 539
540 pinctrl_brcm_reg: brcmreggrp { 540 pinctrl_brcm_reg: brcmreggrp {
541 fsl,pins = < 541 fsl,pins = <
542 MX7D_PAD_ECSPI2_MOSI__ 542 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
543 >; 543 >;
544 }; 544 };
545 545
546 pinctrl_ecspi3: ecspi3grp { 546 pinctrl_ecspi3: ecspi3grp {
547 fsl,pins = < 547 fsl,pins = <
548 MX7D_PAD_SAI2_TX_SYNC_ 548 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
549 MX7D_PAD_SAI2_TX_BCLK_ 549 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
550 MX7D_PAD_SAI2_RX_DATA_ 550 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
551 MX7D_PAD_SD2_CD_B__GPI 551 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
552 >; 552 >;
553 }; 553 };
554 554
555 pinctrl_enet1: enet1grp { 555 pinctrl_enet1: enet1grp {
556 fsl,pins = < 556 fsl,pins = <
557 MX7D_PAD_GPIO1_IO10__E 557 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
558 MX7D_PAD_GPIO1_IO11__E 558 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
559 MX7D_PAD_ENET1_RGMII_T 559 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
560 MX7D_PAD_ENET1_RGMII_T 560 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
561 MX7D_PAD_ENET1_RGMII_T 561 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
562 MX7D_PAD_ENET1_RGMII_T 562 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
563 MX7D_PAD_ENET1_RGMII_T 563 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
564 MX7D_PAD_ENET1_RGMII_T 564 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
565 MX7D_PAD_ENET1_RGMII_R 565 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
566 MX7D_PAD_ENET1_RGMII_R 566 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
567 MX7D_PAD_ENET1_RGMII_R 567 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
568 MX7D_PAD_ENET1_RGMII_R 568 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
569 MX7D_PAD_ENET1_RGMII_R 569 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
570 MX7D_PAD_ENET1_RGMII_R 570 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
571 >; 571 >;
572 }; 572 };
573 573
574 pinctrl_enet2: enet2grp { 574 pinctrl_enet2: enet2grp {
575 fsl,pins = < 575 fsl,pins = <
576 MX7D_PAD_EPDC_GDSP__EN 576 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
577 MX7D_PAD_EPDC_SDCE2__E 577 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
578 MX7D_PAD_EPDC_SDCE3__E 578 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
579 MX7D_PAD_EPDC_GDCLK__E 579 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
580 MX7D_PAD_EPDC_GDOE__EN 580 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
581 MX7D_PAD_EPDC_GDRL__EN 581 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
582 MX7D_PAD_EPDC_SDCE1__E 582 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
583 MX7D_PAD_EPDC_SDCLK__E 583 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
584 MX7D_PAD_EPDC_SDLE__EN 584 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
585 MX7D_PAD_EPDC_SDOE__EN 585 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
586 MX7D_PAD_EPDC_SDSHR__E 586 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
587 MX7D_PAD_EPDC_SDCE0__E 587 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
588 >; 588 >;
589 }; 589 };
590 590
591 pinctrl_enet2_reg: enet2reggrp { 591 pinctrl_enet2_reg: enet2reggrp {
592 fsl,pins = < 592 fsl,pins = <
593 MX7D_PAD_LPSR_GPIO1_IO 593 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
594 >; 594 >;
595 }; 595 };
596 596
597 pinctrl_flexcan2: flexcan2grp { 597 pinctrl_flexcan2: flexcan2grp {
598 fsl,pins = < 598 fsl,pins = <
599 MX7D_PAD_GPIO1_IO14__F 599 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
600 MX7D_PAD_GPIO1_IO15__F 600 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
601 >; 601 >;
602 }; 602 };
603 603
604 pinctrl_flexcan2_reg: flexcan2reggrp { 604 pinctrl_flexcan2_reg: flexcan2reggrp {
605 fsl,pins = < 605 fsl,pins = <
606 MX7D_PAD_EPDC_DATA14__ 606 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
607 >; 607 >;
608 }; 608 };
609 609
610 pinctrl_gpio_keys: gpio-keysgrp { 610 pinctrl_gpio_keys: gpio-keysgrp {
611 fsl,pins = < 611 fsl,pins = <
612 MX7D_PAD_SD2_RESET_B__ 612 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
613 MX7D_PAD_SD2_WP__GPIO5 613 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
614 >; 614 >;
615 }; 615 };
616 616
617 pinctrl_hog: hoggrp { 617 pinctrl_hog: hoggrp {
618 fsl,pins = < 618 fsl,pins = <
619 MX7D_PAD_ECSPI2_SS0__G 619 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
620 MX7D_PAD_EPDC_BDR0__GP 620 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
621 >; 621 >;
622 }; 622 };
623 623
624 pinctrl_i2c1: i2c1grp { 624 pinctrl_i2c1: i2c1grp {
625 fsl,pins = < 625 fsl,pins = <
626 MX7D_PAD_I2C1_SDA__I2C 626 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
627 MX7D_PAD_I2C1_SCL__I2C 627 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
628 >; 628 >;
629 }; 629 };
630 630
631 pinctrl_i2c2: i2c2grp { 631 pinctrl_i2c2: i2c2grp {
632 fsl,pins = < 632 fsl,pins = <
633 MX7D_PAD_I2C2_SDA__I2C 633 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
634 MX7D_PAD_I2C2_SCL__I2C 634 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
635 >; 635 >;
636 }; 636 };
637 637
638 pinctrl_i2c3: i2c3grp { 638 pinctrl_i2c3: i2c3grp {
639 fsl,pins = < 639 fsl,pins = <
640 MX7D_PAD_I2C3_SDA__I2C 640 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
641 MX7D_PAD_I2C3_SCL__I2C 641 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
642 >; 642 >;
643 }; 643 };
644 644
645 pinctrl_i2c4: i2c4grp { 645 pinctrl_i2c4: i2c4grp {
646 fsl,pins = < 646 fsl,pins = <
647 MX7D_PAD_SAI1_RX_BCLK_ 647 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
648 MX7D_PAD_SAI1_RX_SYNC_ 648 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
649 >; 649 >;
650 }; 650 };
651 651
652 pinctrl_lcdif: lcdifgrp { 652 pinctrl_lcdif: lcdifgrp {
653 fsl,pins = < 653 fsl,pins = <
654 MX7D_PAD_LCD_DATA00__L 654 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
655 MX7D_PAD_LCD_DATA01__L 655 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
656 MX7D_PAD_LCD_DATA02__L 656 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
657 MX7D_PAD_LCD_DATA03__L 657 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
658 MX7D_PAD_LCD_DATA04__L 658 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
659 MX7D_PAD_LCD_DATA05__L 659 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
660 MX7D_PAD_LCD_DATA06__L 660 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
661 MX7D_PAD_LCD_DATA07__L 661 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
662 MX7D_PAD_LCD_DATA08__L 662 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
663 MX7D_PAD_LCD_DATA09__L 663 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
664 MX7D_PAD_LCD_DATA10__L 664 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
665 MX7D_PAD_LCD_DATA11__L 665 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
666 MX7D_PAD_LCD_DATA12__L 666 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
667 MX7D_PAD_LCD_DATA13__L 667 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
668 MX7D_PAD_LCD_DATA14__L 668 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
669 MX7D_PAD_LCD_DATA15__L 669 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
670 MX7D_PAD_LCD_DATA16__L 670 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
671 MX7D_PAD_LCD_DATA17__L 671 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
672 MX7D_PAD_LCD_DATA18__L 672 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
673 MX7D_PAD_LCD_DATA19__L 673 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
674 MX7D_PAD_LCD_DATA20__L 674 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
675 MX7D_PAD_LCD_DATA21__L 675 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
676 MX7D_PAD_LCD_DATA22__L 676 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
677 MX7D_PAD_LCD_DATA23__L 677 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
678 MX7D_PAD_LCD_CLK__LCD_ 678 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
679 MX7D_PAD_LCD_ENABLE__L 679 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
680 MX7D_PAD_LCD_VSYNC__LC 680 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
681 MX7D_PAD_LCD_HSYNC__LC 681 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
682 MX7D_PAD_LCD_RESET__LC 682 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
683 >; 683 >;
684 }; 684 };
685 685
686 pinctrl_sai1: sai1grp { 686 pinctrl_sai1: sai1grp {
687 fsl,pins = < 687 fsl,pins = <
688 MX7D_PAD_SAI1_MCLK__SA 688 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
689 MX7D_PAD_ENET1_RX_CLK_ 689 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
690 MX7D_PAD_ENET1_CRS__SA 690 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
691 MX7D_PAD_ENET1_COL__SA 691 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
692 MX7D_PAD_ENET1_TX_CLK_ 692 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
693 >; 693 >;
694 }; 694 };
695 695
696 pinctrl_sai2: sai2grp { 696 pinctrl_sai2: sai2grp {
697 fsl,pins = < 697 fsl,pins = <
698 MX7D_PAD_SAI2_TX_BCLK_ 698 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
699 MX7D_PAD_SAI2_TX_SYNC_ 699 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
700 MX7D_PAD_SAI2_TX_DATA_ 700 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
701 MX7D_PAD_SAI2_RX_DATA_ 701 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
702 >; 702 >;
703 }; 703 };
704 704
705 pinctrl_sai3: sai3grp { 705 pinctrl_sai3: sai3grp {
706 fsl,pins = < 706 fsl,pins = <
707 MX7D_PAD_UART3_TX_DATA 707 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
708 MX7D_PAD_UART3_CTS_B__ 708 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
709 MX7D_PAD_UART3_RTS_B__ 709 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
710 >; 710 >;
711 }; 711 };
712 712
713 pinctrl_spi4: spi4grp { 713 pinctrl_spi4: spi4grp {
714 fsl,pins = < 714 fsl,pins = <
715 MX7D_PAD_GPIO1_IO09__G 715 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
716 MX7D_PAD_GPIO1_IO12__G 716 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
717 MX7D_PAD_GPIO1_IO13__G 717 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
718 >; 718 >;
719 }; 719 };
720 720
721 pinctrl_tsc2046_pendown: tsc2046-pendo 721 pinctrl_tsc2046_pendown: tsc2046-pendowngrp {
722 fsl,pins = < 722 fsl,pins = <
723 MX7D_PAD_EPDC_BDR1__GP 723 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
724 >; 724 >;
725 }; 725 };
726 726
727 pinctrl_uart1: uart1grp { 727 pinctrl_uart1: uart1grp {
728 fsl,pins = < 728 fsl,pins = <
729 MX7D_PAD_UART1_TX_DATA 729 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
730 MX7D_PAD_UART1_RX_DATA 730 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
731 >; 731 >;
732 }; 732 };
733 733
734 pinctrl_uart5: uart5grp { 734 pinctrl_uart5: uart5grp {
735 fsl,pins = < 735 fsl,pins = <
736 MX7D_PAD_SAI1_TX_BCLK_ 736 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
737 MX7D_PAD_SAI1_RX_DATA_ 737 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
738 MX7D_PAD_SAI1_TX_SYNC_ 738 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
739 MX7D_PAD_SAI1_TX_DATA_ 739 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
740 >; 740 >;
741 }; 741 };
742 742
743 pinctrl_uart6: uart6grp { 743 pinctrl_uart6: uart6grp {
744 fsl,pins = < 744 fsl,pins = <
745 MX7D_PAD_ECSPI1_MOSI__ 745 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
746 MX7D_PAD_ECSPI1_SCLK__ 746 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
747 MX7D_PAD_ECSPI1_SS0__U 747 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
748 MX7D_PAD_ECSPI1_MISO__ 748 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
749 >; 749 >;
750 }; 750 };
751 751
752 pinctrl_usdhc1_gpio: usdhc1-gpiogrp { 752 pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
753 fsl,pins = < 753 fsl,pins = <
754 MX7D_PAD_SD1_CD_B__GPI 754 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
755 MX7D_PAD_SD1_WP__GPIO5 755 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
756 MX7D_PAD_SD1_RESET_B__ 756 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
757 MX7D_PAD_GPIO1_IO08__S 757 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
758 >; 758 >;
759 }; 759 };
760 760
761 pinctrl_usdhc1: usdhc1grp { 761 pinctrl_usdhc1: usdhc1grp {
762 fsl,pins = < 762 fsl,pins = <
763 MX7D_PAD_SD1_CMD__SD1_ 763 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
764 MX7D_PAD_SD1_CLK__SD1_ 764 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
765 MX7D_PAD_SD1_DATA0__SD 765 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
766 MX7D_PAD_SD1_DATA1__SD 766 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
767 MX7D_PAD_SD1_DATA2__SD 767 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
768 MX7D_PAD_SD1_DATA3__SD 768 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
769 >; 769 >;
770 }; 770 };
771 771
772 pinctrl_usdhc1_100mhz: usdhc1-100mhz-g 772 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
773 fsl,pins = < 773 fsl,pins = <
774 MX7D_PAD_SD1_CMD__SD1_ 774 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
775 MX7D_PAD_SD1_CLK__SD1_ 775 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
776 MX7D_PAD_SD1_DATA0__SD 776 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
777 MX7D_PAD_SD1_DATA1__SD 777 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
778 MX7D_PAD_SD1_DATA2__SD 778 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
779 MX7D_PAD_SD1_DATA3__SD 779 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
780 >; 780 >;
781 }; 781 };
782 782
783 pinctrl_usdhc1_200mhz: usdhc1-200mhz-g 783 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
784 fsl,pins = < 784 fsl,pins = <
785 MX7D_PAD_SD1_CMD__SD1_ 785 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
786 MX7D_PAD_SD1_CLK__SD1_ 786 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
787 MX7D_PAD_SD1_DATA0__SD 787 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
788 MX7D_PAD_SD1_DATA1__SD 788 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
789 MX7D_PAD_SD1_DATA2__SD 789 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
790 MX7D_PAD_SD1_DATA3__SD 790 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
791 >; 791 >;
792 }; 792 };
793 793
794 pinctrl_usdhc2: usdhc2grp { 794 pinctrl_usdhc2: usdhc2grp {
795 fsl,pins = < 795 fsl,pins = <
796 MX7D_PAD_SD2_CMD__SD2_ 796 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
797 MX7D_PAD_SD2_CLK__SD2_ 797 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
798 MX7D_PAD_SD2_DATA0__SD 798 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
799 MX7D_PAD_SD2_DATA1__SD 799 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
800 MX7D_PAD_SD2_DATA2__SD 800 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
801 MX7D_PAD_SD2_DATA3__SD 801 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
802 >; 802 >;
803 }; 803 };
804 804
805 pinctrl_usdhc2_100mhz: usdhc2-100mhz-g 805 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
806 fsl,pins = < 806 fsl,pins = <
807 MX7D_PAD_SD2_CMD__SD2_ 807 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
808 MX7D_PAD_SD2_CLK__SD2_ 808 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
809 MX7D_PAD_SD2_DATA0__SD 809 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
810 MX7D_PAD_SD2_DATA1__SD 810 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
811 MX7D_PAD_SD2_DATA2__SD 811 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
812 MX7D_PAD_SD2_DATA3__SD 812 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
813 >; 813 >;
814 }; 814 };
815 815
816 pinctrl_usdhc2_200mhz: usdhc2-200mhz-g 816 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
817 fsl,pins = < 817 fsl,pins = <
818 MX7D_PAD_SD2_CMD__SD2_ 818 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
819 MX7D_PAD_SD2_CLK__SD2_ 819 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
820 MX7D_PAD_SD2_DATA0__SD 820 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
821 MX7D_PAD_SD2_DATA1__SD 821 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
822 MX7D_PAD_SD2_DATA2__SD 822 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
823 MX7D_PAD_SD2_DATA3__SD 823 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
824 >; 824 >;
825 }; 825 };
826 826
827 827
828 pinctrl_usdhc3: usdhc3grp { 828 pinctrl_usdhc3: usdhc3grp {
829 fsl,pins = < 829 fsl,pins = <
830 MX7D_PAD_SD3_CMD__SD3_ 830 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
831 MX7D_PAD_SD3_CLK__SD3_ 831 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
832 MX7D_PAD_SD3_DATA0__SD 832 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
833 MX7D_PAD_SD3_DATA1__SD 833 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
834 MX7D_PAD_SD3_DATA2__SD 834 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
835 MX7D_PAD_SD3_DATA3__SD 835 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
836 MX7D_PAD_SD3_DATA4__SD 836 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
837 MX7D_PAD_SD3_DATA5__SD 837 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
838 MX7D_PAD_SD3_DATA6__SD 838 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
839 MX7D_PAD_SD3_DATA7__SD 839 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
840 MX7D_PAD_SD3_STROBE__S 840 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
841 >; 841 >;
842 }; 842 };
843 843
844 pinctrl_usdhc3_100mhz: usdhc3-100mhz-g 844 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
845 fsl,pins = < 845 fsl,pins = <
846 MX7D_PAD_SD3_CMD__SD3_ 846 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
847 MX7D_PAD_SD3_CLK__SD3_ 847 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
848 MX7D_PAD_SD3_DATA0__SD 848 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
849 MX7D_PAD_SD3_DATA1__SD 849 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
850 MX7D_PAD_SD3_DATA2__SD 850 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
851 MX7D_PAD_SD3_DATA3__SD 851 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
852 MX7D_PAD_SD3_DATA4__SD 852 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
853 MX7D_PAD_SD3_DATA5__SD 853 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
854 MX7D_PAD_SD3_DATA6__SD 854 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
855 MX7D_PAD_SD3_DATA7__SD 855 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
856 MX7D_PAD_SD3_STROBE__S 856 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
857 >; 857 >;
858 }; 858 };
859 859
860 pinctrl_usdhc3_200mhz: usdhc3-200mhz-g 860 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
861 fsl,pins = < 861 fsl,pins = <
862 MX7D_PAD_SD3_CMD__SD3_ 862 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
863 MX7D_PAD_SD3_CLK__SD3_ 863 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
864 MX7D_PAD_SD3_DATA0__SD 864 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
865 MX7D_PAD_SD3_DATA1__SD 865 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
866 MX7D_PAD_SD3_DATA2__SD 866 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
867 MX7D_PAD_SD3_DATA3__SD 867 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
868 MX7D_PAD_SD3_DATA4__SD 868 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
869 MX7D_PAD_SD3_DATA5__SD 869 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
870 MX7D_PAD_SD3_DATA6__SD 870 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
871 MX7D_PAD_SD3_DATA7__SD 871 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
872 MX7D_PAD_SD3_STROBE__S 872 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
873 >; 873 >;
874 }; 874 };
875 }; 875 };
876 876
877 &pwm1 { 877 &pwm1 {
878 pinctrl-names = "default"; 878 pinctrl-names = "default";
879 pinctrl-0 = <&pinctrl_pwm1>; 879 pinctrl-0 = <&pinctrl_pwm1>;
880 status = "okay"; 880 status = "okay";
881 }; 881 };
882 882
883 &iomuxc_lpsr { 883 &iomuxc_lpsr {
884 pinctrl_wdog: wdoggrp { 884 pinctrl_wdog: wdoggrp {
885 fsl,pins = < 885 fsl,pins = <
886 MX7D_PAD_LPSR_GPIO1_IO 886 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
887 >; 887 >;
888 }; 888 };
889 889
890 pinctrl_pwm1: pwm1grp { 890 pinctrl_pwm1: pwm1grp {
891 fsl,pins = < 891 fsl,pins = <
892 MX7D_PAD_LPSR_GPIO1_IO 892 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
893 >; 893 >;
894 }; 894 };
895 895
896 pinctrl_usb_otg2_vbus_reg: usbotg2vbus 896 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
897 fsl,pins = < 897 fsl,pins = <
898 MX7D_PAD_LPSR_GPIO1_IO 898 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
899 >; 899 >;
900 }; 900 };
901 901
902 pinctrl_sai3_mclk: sai3-mclk-grp { 902 pinctrl_sai3_mclk: sai3-mclk-grp {
903 fsl,pins = < 903 fsl,pins = <
904 MX7D_PAD_LPSR_GPIO1_IO 904 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
905 >; 905 >;
906 }; 906 };
907 }; 907 };
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