1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 // 2 //
3 // Copyright 2015 Freescale Semiconductor, Inc 3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG 4 // Copyright 2016 Toradex AG
5 5
6 #include <dt-bindings/clock/imx7d-clock.h> 6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h> 7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h> 11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h" 12 #include "imx7d-pinfunc.h"
13 13
14 / { 14 / {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 /* 17 /*
18 * The decompressor and also some boot 18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be ava 19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS 20 * command line and merge other ATAGS info.
21 */ 21 */
22 chosen {}; 22 chosen {};
23 23
24 aliases { 24 aliases {
25 gpio0 = &gpio1; 25 gpio0 = &gpio1;
26 gpio1 = &gpio2; 26 gpio1 = &gpio2;
27 gpio2 = &gpio3; 27 gpio2 = &gpio3;
28 gpio3 = &gpio4; 28 gpio3 = &gpio4;
29 gpio4 = &gpio5; 29 gpio4 = &gpio5;
30 gpio5 = &gpio6; 30 gpio5 = &gpio6;
31 gpio6 = &gpio7; 31 gpio6 = &gpio7;
32 i2c0 = &i2c1; 32 i2c0 = &i2c1;
33 i2c1 = &i2c2; 33 i2c1 = &i2c2;
34 i2c2 = &i2c3; 34 i2c2 = &i2c3;
35 i2c3 = &i2c4; 35 i2c3 = &i2c4;
36 mmc0 = &usdhc1; 36 mmc0 = &usdhc1;
37 mmc1 = &usdhc2; 37 mmc1 = &usdhc2;
38 mmc2 = &usdhc3; 38 mmc2 = &usdhc3;
39 serial0 = &uart1; 39 serial0 = &uart1;
40 serial1 = &uart2; 40 serial1 = &uart2;
41 serial2 = &uart3; 41 serial2 = &uart3;
42 serial3 = &uart4; 42 serial3 = &uart4;
43 serial4 = &uart5; 43 serial4 = &uart5;
44 serial5 = &uart6; 44 serial5 = &uart6;
45 serial6 = &uart7; 45 serial6 = &uart7;
46 spi0 = &ecspi1; 46 spi0 = &ecspi1;
47 spi1 = &ecspi2; 47 spi1 = &ecspi2;
48 spi2 = &ecspi3; 48 spi2 = &ecspi3;
49 spi3 = &ecspi4; 49 spi3 = &ecspi4;
50 usb0 = &usbotg1; 50 usb0 = &usbotg1;
51 usb1 = &usbh; 51 usb1 = &usbh;
52 }; 52 };
53 53
54 cpus { 54 cpus {
55 #address-cells = <1>; 55 #address-cells = <1>;
56 #size-cells = <0>; 56 #size-cells = <0>;
57 57
58 idle-states { 58 idle-states {
59 entry-method = "psci"; 59 entry-method = "psci";
60 60
61 cpu_sleep_wait: cpu-sl 61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = " 62 compatible = "arm,idle-state";
63 arm,psci-suspe 63 arm,psci-suspend-param = <0x0010000>;
64 local-timer-st 64 local-timer-stop;
65 entry-latency- 65 entry-latency-us = <100>;
66 exit-latency-u 66 exit-latency-us = <50>;
67 min-residency- 67 min-residency-us = <1000>;
68 }; 68 };
69 }; 69 };
70 70
71 cpu0: cpu@0 { 71 cpu0: cpu@0 {
72 compatible = "arm,cort 72 compatible = "arm,cortex-a7";
73 device_type = "cpu"; 73 device_type = "cpu";
74 reg = <0>; 74 reg = <0>;
75 clock-frequency = <792 75 clock-frequency = <792000000>;
76 clock-latency = <61036 76 clock-latency = <61036>; /* two CLK32 periods */
77 clocks = <&clks IMX7D_ 77 clocks = <&clks IMX7D_CLK_ARM>;
78 cpu-idle-states = <&cp 78 cpu-idle-states = <&cpu_sleep_wait>;
79 operating-points-v2 = 79 operating-points-v2 = <&cpu0_opp_table>;
80 #cooling-cells = <2>; 80 #cooling-cells = <2>;
81 nvmem-cells = <&fuse_g 81 nvmem-cells = <&fuse_grade>;
82 nvmem-cell-names = "sp 82 nvmem-cell-names = "speed_grade";
83 }; 83 };
84 }; 84 };
85 85
86 cpu0_opp_table: opp-table { 86 cpu0_opp_table: opp-table {
87 compatible = "operating-points 87 compatible = "operating-points-v2";
88 opp-shared; 88 opp-shared;
89 89
90 opp-792000000 { 90 opp-792000000 {
91 opp-hz = /bits/ 64 <79 91 opp-hz = /bits/ 64 <792000000>;
92 opp-microvolt = <10000 92 opp-microvolt = <1000000>;
93 clock-latency-ns = <15 93 clock-latency-ns = <150000>;
94 opp-supported-hw = <0x 94 opp-supported-hw = <0xf>, <0xf>;
95 }; 95 };
96 }; 96 };
97 97
98 ckil: clock-cki { 98 ckil: clock-cki {
99 compatible = "fixed-clock"; 99 compatible = "fixed-clock";
100 #clock-cells = <0>; 100 #clock-cells = <0>;
101 clock-frequency = <32768>; 101 clock-frequency = <32768>;
102 clock-output-names = "ckil"; 102 clock-output-names = "ckil";
103 }; 103 };
104 104
105 osc: clock-osc { 105 osc: clock-osc {
106 compatible = "fixed-clock"; 106 compatible = "fixed-clock";
107 #clock-cells = <0>; 107 #clock-cells = <0>;
108 clock-frequency = <24000000>; 108 clock-frequency = <24000000>;
109 clock-output-names = "osc"; 109 clock-output-names = "osc";
110 }; 110 };
111 111
112 usbphynop1: usbphynop1 { 112 usbphynop1: usbphynop1 {
113 compatible = "usb-nop-xceiv"; 113 compatible = "usb-nop-xceiv";
114 clocks = <&clks IMX7D_USB_PHY1 114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
115 clock-names = "main_clk"; 115 clock-names = "main_clk";
116 #phy-cells = <0>; 116 #phy-cells = <0>;
117 }; 117 };
118 118
119 usbphynop3: usbphynop3 { 119 usbphynop3: usbphynop3 {
120 compatible = "usb-nop-xceiv"; 120 compatible = "usb-nop-xceiv";
121 clocks = <&clks IMX7D_USB_HSIC 121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
122 clock-names = "main_clk"; 122 clock-names = "main_clk";
123 power-domains = <&pgc_hsic_phy 123 power-domains = <&pgc_hsic_phy>;
124 #phy-cells = <0>; 124 #phy-cells = <0>;
125 }; 125 };
126 126
127 pmu { 127 pmu {
128 compatible = "arm,cortex-a7-pm 128 compatible = "arm,cortex-a7-pmu";
129 interrupt-parent = <&gpc>; 129 interrupt-parent = <&gpc>;
130 interrupts = <GIC_SPI 92 IRQ_T 130 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-affinity = <&cpu0>; 131 interrupt-affinity = <&cpu0>;
132 }; 132 };
133 133
134 replicator { 134 replicator {
135 /* 135 /*
136 * non-configurable replicator 136 * non-configurable replicators don't show up on the
137 * AMBA bus. As such no need 137 * AMBA bus. As such no need to add "arm,primecell"
138 */ 138 */
139 compatible = "arm,coresight-st 139 compatible = "arm,coresight-static-replicator";
140 140
141 out-ports { 141 out-ports {
142 #address-cells = <1>; 142 #address-cells = <1>;
143 #size-cells = <0>; 143 #size-cells = <0>;
144 /* replicator 144 /* replicator output ports */
145 port@0 { 145 port@0 {
146 reg = <0>; 146 reg = <0>;
147 replicator_out 147 replicator_out_port0: endpoint {
148 remote 148 remote-endpoint = <&tpiu_in_port>;
149 }; 149 };
150 }; 150 };
151 151
152 port@1 { 152 port@1 {
153 reg = <1>; 153 reg = <1>;
154 replicator_out 154 replicator_out_port1: endpoint {
155 remote 155 remote-endpoint = <&etr_in_port>;
156 }; 156 };
157 }; 157 };
158 }; 158 };
159 159
160 in-ports { 160 in-ports {
161 port { 161 port {
162 replicator_in_ 162 replicator_in_port0: endpoint {
163 remote 163 remote-endpoint = <&etf_out_port>;
164 }; 164 };
165 }; 165 };
166 }; 166 };
167 }; 167 };
168 168
169 timer { 169 timer {
170 compatible = "arm,armv7-timer" 170 compatible = "arm,armv7-timer";
171 arm,cpu-registers-not-fw-confi 171 arm,cpu-registers-not-fw-configured;
172 interrupt-parent = <&intc>; 172 interrupt-parent = <&intc>;
173 interrupts = <GIC_PPI 13 (GIC_ 173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
174 <GIC_PPI 14 (GIC_ 174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
175 <GIC_PPI 11 (GIC_ 175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
176 <GIC_PPI 10 (GIC_ 176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
177 }; 177 };
178 178
179 soc: soc { 179 soc: soc {
180 #address-cells = <1>; 180 #address-cells = <1>;
181 #size-cells = <1>; 181 #size-cells = <1>;
182 compatible = "simple-bus"; 182 compatible = "simple-bus";
183 interrupt-parent = <&gpc>; 183 interrupt-parent = <&gpc>;
184 ranges; 184 ranges;
185 185
186 ocram: sram@900000 { 186 ocram: sram@900000 {
187 compatible = "mmio-sra 187 compatible = "mmio-sram";
188 reg = <0x00900000 0x20 188 reg = <0x00900000 0x20000>;
189 ranges = <0 0x00900000 189 ranges = <0 0x00900000 0x20000>;
190 #address-cells = <1>; 190 #address-cells = <1>;
191 #size-cells = <1>; 191 #size-cells = <1>;
192 clocks = <&clks IMX7D_ 192 clocks = <&clks IMX7D_OCRAM_CLK>;
193 }; 193 };
194 194
195 funnel@30041000 { 195 funnel@30041000 {
196 compatible = "arm,core 196 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
197 reg = <0x30041000 0x10 197 reg = <0x30041000 0x1000>;
198 clocks = <&clks IMX7D_ 198 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
199 clock-names = "apb_pcl 199 clock-names = "apb_pclk";
200 200
201 ca_funnel_in_ports: in 201 ca_funnel_in_ports: in-ports {
202 #address-cells 202 #address-cells = <1>;
203 #size-cells = 203 #size-cells = <0>;
204 204
205 port@0 { 205 port@0 {
206 reg = 206 reg = <0>;
207 ca_fun 207 ca_funnel_in_port0: endpoint {
208 208 remote-endpoint = <&etm0_out_port>;
209 }; 209 };
210 }; 210 };
211 211
212 /* the other i 212 /* the other input ports are not connect to anything */
213 }; 213 };
214 214
215 out-ports { 215 out-ports {
216 port { 216 port {
217 ca_fun 217 ca_funnel_out_port0: endpoint {
218 218 remote-endpoint = <&hugo_funnel_in_port0>;
219 }; 219 };
220 }; 220 };
221 221
222 }; 222 };
223 }; 223 };
224 224
225 etm@3007c000 { 225 etm@3007c000 {
226 compatible = "arm,core 226 compatible = "arm,coresight-etm3x", "arm,primecell";
227 reg = <0x3007c000 0x10 227 reg = <0x3007c000 0x1000>;
228 cpu = <&cpu0>; 228 cpu = <&cpu0>;
229 clocks = <&clks IMX7D_ 229 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
230 clock-names = "apb_pcl 230 clock-names = "apb_pclk";
231 231
232 out-ports { 232 out-ports {
233 port { 233 port {
234 etm0_o 234 etm0_out_port: endpoint {
235 235 remote-endpoint = <&ca_funnel_in_port0>;
236 }; 236 };
237 }; 237 };
238 }; 238 };
239 }; 239 };
240 240
241 funnel@30083000 { 241 funnel@30083000 {
242 compatible = "arm,core 242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
243 reg = <0x30083000 0x10 243 reg = <0x30083000 0x1000>;
244 clocks = <&clks IMX7D_ 244 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
245 clock-names = "apb_pcl 245 clock-names = "apb_pclk";
246 246
247 in-ports { 247 in-ports {
248 #address-cells 248 #address-cells = <1>;
249 #size-cells = 249 #size-cells = <0>;
250 250
251 port@0 { 251 port@0 {
252 reg = 252 reg = <0>;
253 hugo_f 253 hugo_funnel_in_port0: endpoint {
254 254 remote-endpoint = <&ca_funnel_out_port0>;
255 }; 255 };
256 }; 256 };
257 257
258 port@1 { 258 port@1 {
259 reg = 259 reg = <1>;
260 hugo_f 260 hugo_funnel_in_port1: endpoint {
261 261 /* M4 input */
262 }; 262 };
263 }; 263 };
264 /* the other i 264 /* the other input ports are not connect to anything */
265 }; 265 };
266 266
267 out-ports { 267 out-ports {
268 port { 268 port {
269 hugo_f 269 hugo_funnel_out_port0: endpoint {
270 270 remote-endpoint = <&etf_in_port>;
271 }; 271 };
272 }; 272 };
273 }; 273 };
274 }; 274 };
275 275
276 etf@30084000 { 276 etf@30084000 {
277 compatible = "arm,core 277 compatible = "arm,coresight-tmc", "arm,primecell";
278 reg = <0x30084000 0x10 278 reg = <0x30084000 0x1000>;
279 clocks = <&clks IMX7D_ 279 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
280 clock-names = "apb_pcl 280 clock-names = "apb_pclk";
281 281
282 in-ports { 282 in-ports {
283 port { 283 port {
284 etf_in 284 etf_in_port: endpoint {
285 285 remote-endpoint = <&hugo_funnel_out_port0>;
286 }; 286 };
287 }; 287 };
288 }; 288 };
289 289
290 out-ports { 290 out-ports {
291 port { 291 port {
292 etf_ou 292 etf_out_port: endpoint {
293 293 remote-endpoint = <&replicator_in_port0>;
294 }; 294 };
295 }; 295 };
296 }; 296 };
297 }; 297 };
298 298
299 etr@30086000 { 299 etr@30086000 {
300 compatible = "arm,core 300 compatible = "arm,coresight-tmc", "arm,primecell";
301 reg = <0x30086000 0x10 301 reg = <0x30086000 0x1000>;
302 clocks = <&clks IMX7D_ 302 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
303 clock-names = "apb_pcl 303 clock-names = "apb_pclk";
304 304
305 in-ports { 305 in-ports {
306 port { 306 port {
307 etr_in 307 etr_in_port: endpoint {
308 308 remote-endpoint = <&replicator_out_port1>;
309 }; 309 };
310 }; 310 };
311 }; 311 };
312 }; 312 };
313 313
314 tpiu@30087000 { 314 tpiu@30087000 {
315 compatible = "arm,core 315 compatible = "arm,coresight-tpiu", "arm,primecell";
316 reg = <0x30087000 0x10 316 reg = <0x30087000 0x1000>;
317 clocks = <&clks IMX7D_ 317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
318 clock-names = "apb_pcl 318 clock-names = "apb_pclk";
319 319
320 in-ports { 320 in-ports {
321 port { 321 port {
322 tpiu_i 322 tpiu_in_port: endpoint {
323 323 remote-endpoint = <&replicator_out_port0>;
324 }; 324 };
325 }; 325 };
326 }; 326 };
327 }; 327 };
328 328
329 intc: interrupt-controller@310 329 intc: interrupt-controller@31001000 {
330 compatible = "arm,cort 330 compatible = "arm,cortex-a7-gic";
331 interrupts = <GIC_PPI 331 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
332 #interrupt-cells = <3> 332 #interrupt-cells = <3>;
333 interrupt-controller; 333 interrupt-controller;
334 interrupt-parent = <&i 334 interrupt-parent = <&intc>;
335 reg = <0x31001000 0x10 335 reg = <0x31001000 0x1000>,
336 <0x31002000 0x20 336 <0x31002000 0x2000>,
337 <0x31004000 0x20 337 <0x31004000 0x2000>,
338 <0x31006000 0x20 338 <0x31006000 0x2000>;
339 }; 339 };
340 340
341 aips1: bus@30000000 { 341 aips1: bus@30000000 {
342 compatible = "fsl,aips 342 compatible = "fsl,aips-bus", "simple-bus";
343 #address-cells = <1>; 343 #address-cells = <1>;
344 #size-cells = <1>; 344 #size-cells = <1>;
345 reg = <0x30000000 0x40 345 reg = <0x30000000 0x400000>;
346 ranges; 346 ranges;
347 347
348 gpio1: gpio@30200000 { 348 gpio1: gpio@30200000 {
349 compatible = " 349 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
350 reg = <0x30200 350 reg = <0x30200000 0x10000>;
351 interrupts = < 351 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
352 < 352 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
353 gpio-controlle 353 gpio-controller;
354 #gpio-cells = 354 #gpio-cells = <2>;
355 interrupt-cont 355 interrupt-controller;
356 #interrupt-cel 356 #interrupt-cells = <2>;
357 gpio-ranges = 357 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
358 }; 358 };
359 359
360 gpio2: gpio@30210000 { 360 gpio2: gpio@30210000 {
361 compatible = " 361 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
362 reg = <0x30210 362 reg = <0x30210000 0x10000>;
363 interrupts = < 363 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
364 < 364 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
365 gpio-controlle 365 gpio-controller;
366 #gpio-cells = 366 #gpio-cells = <2>;
367 interrupt-cont 367 interrupt-controller;
368 #interrupt-cel 368 #interrupt-cells = <2>;
369 gpio-ranges = 369 gpio-ranges = <&iomuxc 0 13 32>;
370 }; 370 };
371 371
372 gpio3: gpio@30220000 { 372 gpio3: gpio@30220000 {
373 compatible = " 373 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
374 reg = <0x30220 374 reg = <0x30220000 0x10000>;
375 interrupts = < 375 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
376 < 376 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
377 gpio-controlle 377 gpio-controller;
378 #gpio-cells = 378 #gpio-cells = <2>;
379 interrupt-cont 379 interrupt-controller;
380 #interrupt-cel 380 #interrupt-cells = <2>;
381 gpio-ranges = 381 gpio-ranges = <&iomuxc 0 45 29>;
382 }; 382 };
383 383
384 gpio4: gpio@30230000 { 384 gpio4: gpio@30230000 {
385 compatible = " 385 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
386 reg = <0x30230 386 reg = <0x30230000 0x10000>;
387 interrupts = < 387 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
388 < 388 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
389 gpio-controlle 389 gpio-controller;
390 #gpio-cells = 390 #gpio-cells = <2>;
391 interrupt-cont 391 interrupt-controller;
392 #interrupt-cel 392 #interrupt-cells = <2>;
393 gpio-ranges = 393 gpio-ranges = <&iomuxc 0 74 24>;
394 }; 394 };
395 395
396 gpio5: gpio@30240000 { 396 gpio5: gpio@30240000 {
397 compatible = " 397 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
398 reg = <0x30240 398 reg = <0x30240000 0x10000>;
399 interrupts = < 399 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
400 < 400 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
401 gpio-controlle 401 gpio-controller;
402 #gpio-cells = 402 #gpio-cells = <2>;
403 interrupt-cont 403 interrupt-controller;
404 #interrupt-cel 404 #interrupt-cells = <2>;
405 gpio-ranges = 405 gpio-ranges = <&iomuxc 0 98 18>;
406 }; 406 };
407 407
408 gpio6: gpio@30250000 { 408 gpio6: gpio@30250000 {
409 compatible = " 409 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
410 reg = <0x30250 410 reg = <0x30250000 0x10000>;
411 interrupts = < 411 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
412 < 412 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
413 gpio-controlle 413 gpio-controller;
414 #gpio-cells = 414 #gpio-cells = <2>;
415 interrupt-cont 415 interrupt-controller;
416 #interrupt-cel 416 #interrupt-cells = <2>;
417 gpio-ranges = 417 gpio-ranges = <&iomuxc 0 116 23>;
418 }; 418 };
419 419
420 gpio7: gpio@30260000 { 420 gpio7: gpio@30260000 {
421 compatible = " 421 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
422 reg = <0x30260 422 reg = <0x30260000 0x10000>;
423 interrupts = < 423 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
424 < 424 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
425 gpio-controlle 425 gpio-controller;
426 #gpio-cells = 426 #gpio-cells = <2>;
427 interrupt-cont 427 interrupt-controller;
428 #interrupt-cel 428 #interrupt-cells = <2>;
429 gpio-ranges = 429 gpio-ranges = <&iomuxc 0 139 16>;
430 }; 430 };
431 431
432 wdog1: watchdog@302800 432 wdog1: watchdog@30280000 {
433 compatible = " 433 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
434 reg = <0x30280 434 reg = <0x30280000 0x10000>;
435 interrupts = < 435 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clk 436 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
437 }; 437 };
438 438
439 wdog2: watchdog@302900 439 wdog2: watchdog@30290000 {
440 compatible = " 440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
441 reg = <0x30290 441 reg = <0x30290000 0x10000>;
442 interrupts = < 442 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clk 443 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
444 status = "disa 444 status = "disabled";
445 }; 445 };
446 446
447 wdog3: watchdog@302a00 447 wdog3: watchdog@302a0000 {
448 compatible = " 448 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
449 reg = <0x302a0 449 reg = <0x302a0000 0x10000>;
450 interrupts = < 450 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clk 451 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
452 status = "disa 452 status = "disabled";
453 }; 453 };
454 454
455 wdog4: watchdog@302b00 455 wdog4: watchdog@302b0000 {
456 compatible = " 456 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
457 reg = <0x302b0 457 reg = <0x302b0000 0x10000>;
458 interrupts = < 458 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clk 459 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
460 status = "disa 460 status = "disabled";
461 }; 461 };
462 462
463 iomuxc_lpsr: pinctrl@3 463 iomuxc_lpsr: pinctrl@302c0000 {
464 compatible = " 464 compatible = "fsl,imx7d-iomuxc-lpsr";
465 reg = <0x302c0 465 reg = <0x302c0000 0x10000>;
466 fsl,input-sel 466 fsl,input-sel = <&iomuxc>;
467 }; 467 };
468 468
469 gpt1: timer@302d0000 { 469 gpt1: timer@302d0000 {
470 compatible = " 470 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
471 reg = <0x302d0 471 reg = <0x302d0000 0x10000>;
472 interrupts = < 472 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clk 473 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
474 <&clk 474 <&clks IMX7D_GPT1_ROOT_CLK>;
475 clock-names = 475 clock-names = "ipg", "per";
476 }; 476 };
477 477
478 gpt2: timer@302e0000 { 478 gpt2: timer@302e0000 {
479 compatible = " 479 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
480 reg = <0x302e0 480 reg = <0x302e0000 0x10000>;
481 interrupts = < 481 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clk 482 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
483 <&clk 483 <&clks IMX7D_GPT2_ROOT_CLK>;
484 clock-names = 484 clock-names = "ipg", "per";
485 status = "disa 485 status = "disabled";
486 }; 486 };
487 487
488 gpt3: timer@302f0000 { 488 gpt3: timer@302f0000 {
489 compatible = " 489 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
490 reg = <0x302f0 490 reg = <0x302f0000 0x10000>;
491 interrupts = < 491 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clk 492 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
493 <&clk 493 <&clks IMX7D_GPT3_ROOT_CLK>;
494 clock-names = 494 clock-names = "ipg", "per";
495 status = "disa 495 status = "disabled";
496 }; 496 };
497 497
498 gpt4: timer@30300000 { 498 gpt4: timer@30300000 {
499 compatible = " 499 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
500 reg = <0x30300 500 reg = <0x30300000 0x10000>;
501 interrupts = < 501 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clk 502 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
503 <&clk 503 <&clks IMX7D_GPT4_ROOT_CLK>;
504 clock-names = 504 clock-names = "ipg", "per";
505 status = "disa 505 status = "disabled";
506 }; 506 };
507 507
508 kpp: keypad@30320000 { 508 kpp: keypad@30320000 {
509 compatible = " 509 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
510 reg = <0x30320 510 reg = <0x30320000 0x10000>;
511 interrupts = < 511 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clk 512 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
513 status = "disa 513 status = "disabled";
514 }; 514 };
515 515
516 iomuxc: pinctrl@303300 516 iomuxc: pinctrl@30330000 {
517 compatible = " 517 compatible = "fsl,imx7d-iomuxc";
518 reg = <0x30330 518 reg = <0x30330000 0x10000>;
519 }; 519 };
520 520
521 gpr: iomuxc-gpr@303400 521 gpr: iomuxc-gpr@30340000 {
522 compatible = " 522 compatible = "fsl,imx7d-iomuxc-gpr",
523 "fsl,i 523 "fsl,imx6q-iomuxc-gpr", "syscon",
524 "simpl 524 "simple-mfd";
525 reg = <0x30340 525 reg = <0x30340000 0x10000>;
526 526
527 mux: mux-contr 527 mux: mux-controller {
528 compat 528 compatible = "mmio-mux";
529 #mux-c 529 #mux-control-cells = <1>;
530 mux-re 530 mux-reg-masks = <0x14 0x00000010>;
531 }; 531 };
532 532
533 video_mux: csi 533 video_mux: csi-mux {
534 compat 534 compatible = "video-mux";
535 mux-co 535 mux-controls = <&mux 0>;
536 #addre 536 #address-cells = <1>;
537 #size- 537 #size-cells = <0>;
538 status 538 status = "disabled";
539 539
540 port@0 540 port@0 {
541 541 reg = <0>;
542 }; 542 };
543 543
544 port@1 544 port@1 {
545 545 reg = <1>;
546 546
547 547 csi_mux_from_mipi_vc0: endpoint {
548 548 remote-endpoint = <&mipi_vc0_to_csi_mux>;
549 549 };
550 }; 550 };
551 551
552 port@2 552 port@2 {
553 553 reg = <2>;
554 554
555 555 csi_mux_to_csi: endpoint {
556 556 remote-endpoint = <&csi_from_csi_mux>;
557 557 };
558 }; 558 };
559 }; 559 };
560 }; 560 };
561 561
562 ocotp: efuse@30350000 562 ocotp: efuse@30350000 {
563 #address-cells 563 #address-cells = <1>;
564 #size-cells = 564 #size-cells = <1>;
565 compatible = " 565 compatible = "fsl,imx7d-ocotp", "syscon";
566 reg = <0x30350 566 reg = <0x30350000 0x10000>;
567 clocks = <&clk 567 clocks = <&clks IMX7D_OCOTP_CLK>;
568 568
569 tempmon_calib: 569 tempmon_calib: calib@3c {
570 reg = 570 reg = <0x3c 0x4>;
571 }; 571 };
572 572
573 fuse_grade: fu 573 fuse_grade: fuse-grade@10 {
574 reg = 574 reg = <0x10 0x4>;
575 }; 575 };
576 }; 576 };
577 577
578 anatop: anatop@3036000 578 anatop: anatop@30360000 {
579 compatible = " 579 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
580 "sysco 580 "syscon", "simple-mfd";
581 reg = <0x30360 581 reg = <0x30360000 0x10000>;
582 interrupts = < 582 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_S 583 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
584 584
585 reg_1p0d: regu 585 reg_1p0d: regulator-vdd1p0d {
586 compat 586 compatible = "fsl,anatop-regulator";
587 regula 587 regulator-name = "vdd1p0d";
588 regula 588 regulator-min-microvolt = <800000>;
589 regula 589 regulator-max-microvolt = <1200000>;
590 anatop 590 anatop-reg-offset = <0x210>;
591 anatop 591 anatop-vol-bit-shift = <8>;
592 anatop 592 anatop-vol-bit-width = <5>;
593 anatop 593 anatop-min-bit-val = <8>;
594 anatop 594 anatop-min-voltage = <800000>;
595 anatop 595 anatop-max-voltage = <1200000>;
596 anatop 596 anatop-enable-bit = <0>;
597 }; 597 };
598 598
599 reg_1p2: regul 599 reg_1p2: regulator-vdd1p2 {
600 compat 600 compatible = "fsl,anatop-regulator";
601 regula 601 regulator-name = "vdd1p2";
602 regula 602 regulator-min-microvolt = <1100000>;
603 regula 603 regulator-max-microvolt = <1300000>;
604 anatop 604 anatop-reg-offset = <0x220>;
605 anatop 605 anatop-vol-bit-shift = <8>;
606 anatop 606 anatop-vol-bit-width = <5>;
607 anatop 607 anatop-min-bit-val = <0x14>;
608 anatop 608 anatop-min-voltage = <1100000>;
609 anatop 609 anatop-max-voltage = <1300000>;
610 anatop 610 anatop-enable-bit = <0>;
611 }; 611 };
612 612
613 tempmon: tempm 613 tempmon: tempmon {
614 compat 614 compatible = "fsl,imx7d-tempmon";
615 interr 615 interrupt-parent = <&gpc>;
616 interr 616 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
617 fsl,te 617 fsl,tempmon = <&anatop>;
618 nvmem- 618 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
619 nvmem- 619 nvmem-cell-names = "calib", "temp_grade";
620 clocks 620 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
621 #therm 621 #thermal-sensor-cells = <0>;
622 }; 622 };
623 }; 623 };
624 624
625 snvs: snvs@30370000 { 625 snvs: snvs@30370000 {
626 compatible = " 626 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
627 reg = <0x30370 627 reg = <0x30370000 0x10000>;
628 628
629 snvs_rtc: snvs 629 snvs_rtc: snvs-rtc-lp {
630 compat 630 compatible = "fsl,sec-v4.0-mon-rtc-lp";
631 regmap 631 regmap = <&snvs>;
632 offset 632 offset = <0x34>;
633 interr 633 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
634 634 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
635 clocks 635 clocks = <&clks IMX7D_SNVS_CLK>;
636 clock- 636 clock-names = "snvs-rtc";
637 }; 637 };
638 638
639 snvs_poweroff: 639 snvs_poweroff: snvs-poweroff {
640 compat 640 compatible = "syscon-poweroff";
641 regmap 641 regmap = <&snvs>;
642 offset 642 offset = <0x38>;
643 value 643 value = <0x60>;
644 mask = 644 mask = <0x60>;
645 status 645 status = "disabled";
646 }; 646 };
647 647
648 snvs_pwrkey: s 648 snvs_pwrkey: snvs-powerkey {
649 compat 649 compatible = "fsl,sec-v4.0-pwrkey";
650 regmap 650 regmap = <&snvs>;
651 interr 651 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
652 clocks 652 clocks = <&clks IMX7D_SNVS_CLK>;
653 clock- 653 clock-names = "snvs-pwrkey";
654 linux, 654 linux,keycode = <KEY_POWER>;
655 wakeup 655 wakeup-source;
656 status 656 status = "disabled";
657 }; 657 };
658 }; 658 };
659 659
660 clks: clock-controller 660 clks: clock-controller@30380000 {
661 compatible = " 661 compatible = "fsl,imx7d-ccm";
662 reg = <0x30380 662 reg = <0x30380000 0x10000>;
663 interrupts = < 663 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
664 < 664 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
665 #clock-cells = 665 #clock-cells = <1>;
666 clocks = <&cki 666 clocks = <&ckil>, <&osc>;
667 clock-names = 667 clock-names = "ckil", "osc";
668 }; 668 };
669 669
670 src: reset-controller@ 670 src: reset-controller@30390000 {
671 compatible = " 671 compatible = "fsl,imx7d-src", "syscon";
672 reg = <0x30390 672 reg = <0x30390000 0x10000>;
673 interrupts = < 673 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
674 #reset-cells = 674 #reset-cells = <1>;
675 }; 675 };
676 676
677 gpc: gpc@303a0000 { 677 gpc: gpc@303a0000 {
678 compatible = " 678 compatible = "fsl,imx7d-gpc";
679 reg = <0x303a0 679 reg = <0x303a0000 0x10000>;
680 interrupt-cont 680 interrupt-controller;
681 interrupts = < 681 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
682 #interrupt-cel 682 #interrupt-cells = <3>;
683 interrupt-pare 683 interrupt-parent = <&intc>;
684 684
685 pgc { 685 pgc {
686 #addre 686 #address-cells = <1>;
687 #size- 687 #size-cells = <0>;
688 688
689 pgc_mi 689 pgc_mipi_phy: power-domain@0 {
690 690 #power-domain-cells = <0>;
691 691 reg = <0>;
692 692 power-supply = <®_1p0d>;
693 }; 693 };
694 694
695 pgc_pc 695 pgc_pcie_phy: power-domain@1 {
696 696 #power-domain-cells = <0>;
697 697 reg = <1>;
698 698 power-supply = <®_1p0d>;
699 }; 699 };
700 700
701 pgc_hs 701 pgc_hsic_phy: power-domain@2 {
702 702 #power-domain-cells = <0>;
703 703 reg = <2>;
704 704 power-supply = <®_1p2>;
705 }; 705 };
706 }; 706 };
707 }; 707 };
708 }; 708 };
709 709
710 aips2: bus@30400000 { 710 aips2: bus@30400000 {
711 compatible = "fsl,aips 711 compatible = "fsl,aips-bus", "simple-bus";
712 #address-cells = <1>; 712 #address-cells = <1>;
713 #size-cells = <1>; 713 #size-cells = <1>;
714 reg = <0x30400000 0x40 714 reg = <0x30400000 0x400000>;
715 ranges; 715 ranges;
716 716
717 adc1: adc@30610000 { 717 adc1: adc@30610000 {
718 compatible = " 718 compatible = "fsl,imx7d-adc";
719 reg = <0x30610 719 reg = <0x30610000 0x10000>;
720 interrupts = < 720 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clk 721 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
722 clock-names = 722 clock-names = "adc";
723 #io-channel-ce 723 #io-channel-cells = <1>;
724 status = "disa 724 status = "disabled";
725 }; 725 };
726 726
727 adc2: adc@30620000 { 727 adc2: adc@30620000 {
728 compatible = " 728 compatible = "fsl,imx7d-adc";
729 reg = <0x30620 729 reg = <0x30620000 0x10000>;
730 interrupts = < 730 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&clk 731 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
732 clock-names = 732 clock-names = "adc";
733 #io-channel-ce 733 #io-channel-cells = <1>;
734 status = "disa 734 status = "disabled";
735 }; 735 };
736 736
737 ecspi4: spi@30630000 { 737 ecspi4: spi@30630000 {
738 #address-cells 738 #address-cells = <1>;
739 #size-cells = 739 #size-cells = <0>;
740 compatible = " 740 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
741 reg = <0x30630 741 reg = <0x30630000 0x10000>;
742 interrupts = < 742 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clk 743 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
744 <&clks 744 <&clks IMX7D_ECSPI4_ROOT_CLK>;
745 clock-names = 745 clock-names = "ipg", "per";
746 dma-names = "r 746 dma-names = "rx", "tx";
747 dmas = <&sdma 747 dmas = <&sdma 6 7 1>, <&sdma 7 7 2>;
748 status = "disa 748 status = "disabled";
749 }; 749 };
750 750
751 ftm1: pwm@30640000 { 751 ftm1: pwm@30640000 {
752 compatible = " 752 compatible = "fsl,vf610-ftm-pwm";
753 reg = <0x30640 753 reg = <0x30640000 0x10000>;
754 #pwm-cells = < 754 #pwm-cells = <3>;
755 interrupts = < 755 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
756 clock-names = 756 clock-names = "ftm_sys", "ftm_ext",
757 "ftm_fix", "ft 757 "ftm_fix", "ftm_cnt_clk_en";
758 clocks = <&clk 758 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
759 <&clks 759 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
760 <&clks 760 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
761 <&clks 761 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
762 status = "disa 762 status = "disabled";
763 }; 763 };
764 764
765 ftm2: pwm@30650000 { 765 ftm2: pwm@30650000 {
766 compatible = " 766 compatible = "fsl,vf610-ftm-pwm";
767 reg = <0x30650 767 reg = <0x30650000 0x10000>;
768 #pwm-cells = < 768 #pwm-cells = <3>;
769 interrupts = < 769 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
770 clock-names = 770 clock-names = "ftm_sys", "ftm_ext",
771 "ftm_fix", "ft 771 "ftm_fix", "ftm_cnt_clk_en";
772 clocks = <&clk 772 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
773 <&clks 773 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
774 <&clks 774 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
775 <&clks 775 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
776 status = "disa 776 status = "disabled";
777 }; 777 };
778 778
779 pwm1: pwm@30660000 { 779 pwm1: pwm@30660000 {
780 compatible = " 780 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
781 reg = <0x30660 781 reg = <0x30660000 0x10000>;
782 interrupts = < 782 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&clk 783 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
784 <&clk 784 <&clks IMX7D_PWM1_ROOT_CLK>;
785 clock-names = 785 clock-names = "ipg", "per";
786 #pwm-cells = < 786 #pwm-cells = <3>;
787 status = "disa 787 status = "disabled";
788 }; 788 };
789 789
790 pwm2: pwm@30670000 { 790 pwm2: pwm@30670000 {
791 compatible = " 791 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
792 reg = <0x30670 792 reg = <0x30670000 0x10000>;
793 interrupts = < 793 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clk 794 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
795 <&clk 795 <&clks IMX7D_PWM2_ROOT_CLK>;
796 clock-names = 796 clock-names = "ipg", "per";
797 #pwm-cells = < 797 #pwm-cells = <3>;
798 status = "disa 798 status = "disabled";
799 }; 799 };
800 800
801 pwm3: pwm@30680000 { 801 pwm3: pwm@30680000 {
802 compatible = " 802 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
803 reg = <0x30680 803 reg = <0x30680000 0x10000>;
804 interrupts = < 804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clk 805 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
806 <&clk 806 <&clks IMX7D_PWM3_ROOT_CLK>;
807 clock-names = 807 clock-names = "ipg", "per";
808 #pwm-cells = < 808 #pwm-cells = <3>;
809 status = "disa 809 status = "disabled";
810 }; 810 };
811 811
812 pwm4: pwm@30690000 { 812 pwm4: pwm@30690000 {
813 compatible = " 813 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
814 reg = <0x30690 814 reg = <0x30690000 0x10000>;
815 interrupts = < 815 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clk 816 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
817 <&clk 817 <&clks IMX7D_PWM4_ROOT_CLK>;
818 clock-names = 818 clock-names = "ipg", "per";
819 #pwm-cells = < 819 #pwm-cells = <3>;
820 status = "disa 820 status = "disabled";
821 }; 821 };
822 822
823 csi: csi@30710000 { 823 csi: csi@30710000 {
824 compatible = " 824 compatible = "fsl,imx7-csi";
825 reg = <0x30710 825 reg = <0x30710000 0x10000>;
826 interrupts = < 826 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&clk 827 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
828 clock-names = 828 clock-names = "mclk";
829 status = "disa 829 status = "disabled";
830 830
831 port { 831 port {
832 csi_fr 832 csi_from_csi_mux: endpoint {
833 833 remote-endpoint = <&csi_mux_to_csi>;
834 }; 834 };
835 }; 835 };
836 }; 836 };
837 837
838 lcdif: lcdif@30730000 838 lcdif: lcdif@30730000 {
839 compatible = " 839 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
840 reg = <0x30730 840 reg = <0x30730000 0x10000>;
841 interrupts = < 841 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clk 842 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
843 <&clks 843 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
844 clock-names = 844 clock-names = "pix", "axi";
845 status = "disa 845 status = "disabled";
846 }; 846 };
847 847
848 mipi_csi: mipi-csi@307 848 mipi_csi: mipi-csi@30750000 {
849 compatible = " 849 compatible = "fsl,imx7-mipi-csi2";
850 reg = <0x30750 850 reg = <0x30750000 0x10000>;
851 interrupts = < 851 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clk 852 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
853 <&clk 853 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
854 <&clk 854 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
855 clock-names = 855 clock-names = "pclk", "wrap", "phy";
856 power-domains 856 power-domains = <&pgc_mipi_phy>;
857 phy-supply = < 857 phy-supply = <®_1p0d>;
858 resets = <&src 858 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
859 status = "disa 859 status = "disabled";
860 860
861 ports { 861 ports {
862 #addre 862 #address-cells = <1>;
863 #size- 863 #size-cells = <0>;
864 864
865 port@0 865 port@0 {
866 866 reg = <0>;
867 }; 867 };
868 868
869 port@1 869 port@1 {
870 870 reg = <1>;
871 871
872 872 mipi_vc0_to_csi_mux: endpoint {
873 873 remote-endpoint = <&csi_mux_from_mipi_vc0>;
874 874 };
875 }; 875 };
876 }; 876 };
877 }; 877 };
878 878
879 mipi_dsi: dsi@30760000 879 mipi_dsi: dsi@30760000 {
880 compatible = " 880 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";
881 #address-cells 881 #address-cells = <1>;
882 #size-cells = 882 #size-cells = <0>;
883 reg = <0x30760 883 reg = <0x30760000 0x400>;
884 clocks = <&clk 884 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
885 <&clk 885 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
886 clock-names = 886 clock-names = "bus_clk", "sclk_mipi";
887 assigned-clock 887 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
888 888 <&clks IMX7D_PLL_SYS_PFD5_CLK>;
889 assigned-clock 889 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
890 assigned-clock 890 assigned-clock-rates = <0>, <333000000>;
891 power-domains 891 power-domains = <&pgc_mipi_phy>;
892 interrupts = < 892 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
893 samsung,burst- 893 samsung,burst-clock-frequency = <891000000>;
894 samsung,esc-cl 894 samsung,esc-clock-frequency = <20000000>;
895 samsung,pll-cl 895 samsung,pll-clock-frequency = <24000000>;
896 status = "disa 896 status = "disabled";
897 }; 897 };
898 }; 898 };
899 899
900 aips3: bus@30800000 { 900 aips3: bus@30800000 {
901 compatible = "fsl,aips 901 compatible = "fsl,aips-bus", "simple-bus";
902 #address-cells = <1>; 902 #address-cells = <1>;
903 #size-cells = <1>; 903 #size-cells = <1>;
904 reg = <0x30800000 0x40 904 reg = <0x30800000 0x400000>;
905 ranges; 905 ranges;
906 906
907 spba-bus@30800000 { 907 spba-bus@30800000 {
908 compatible = " 908 compatible = "fsl,spba-bus", "simple-bus";
909 #address-cells 909 #address-cells = <1>;
910 #size-cells = 910 #size-cells = <1>;
911 reg = <0x30800 911 reg = <0x30800000 0x100000>;
912 ranges; 912 ranges;
913 913
914 ecspi1: spi@30 914 ecspi1: spi@30820000 {
915 #addre 915 #address-cells = <1>;
916 #size- 916 #size-cells = <0>;
917 compat 917 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
918 reg = 918 reg = <0x30820000 0x10000>;
919 interr 919 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
920 clocks 920 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
921 921 <&clks IMX7D_ECSPI1_ROOT_CLK>;
922 clock- 922 clock-names = "ipg", "per";
923 dma-na 923 dma-names = "rx", "tx";
924 dmas = 924 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
925 status 925 status = "disabled";
926 }; 926 };
927 927
928 ecspi2: spi@30 928 ecspi2: spi@30830000 {
929 #addre 929 #address-cells = <1>;
930 #size- 930 #size-cells = <0>;
931 compat 931 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
932 reg = 932 reg = <0x30830000 0x10000>;
933 interr 933 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
934 clocks 934 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
935 935 <&clks IMX7D_ECSPI2_ROOT_CLK>;
936 clock- 936 clock-names = "ipg", "per";
937 dma-na 937 dma-names = "rx", "tx";
938 dmas = 938 dmas = <&sdma 2 7 1>, <&sdma 3 7 2>;
939 status 939 status = "disabled";
940 }; 940 };
941 941
942 ecspi3: spi@30 942 ecspi3: spi@30840000 {
943 #addre 943 #address-cells = <1>;
944 #size- 944 #size-cells = <0>;
945 compat 945 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
946 reg = 946 reg = <0x30840000 0x10000>;
947 interr 947 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
948 clocks 948 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
949 949 <&clks IMX7D_ECSPI3_ROOT_CLK>;
950 clock- 950 clock-names = "ipg", "per";
951 dma-na 951 dma-names = "rx", "tx";
952 dmas = 952 dmas = <&sdma 4 7 1>, <&sdma 5 7 2>;
953 status 953 status = "disabled";
954 }; 954 };
955 955
956 uart1: serial@ 956 uart1: serial@30860000 {
957 compat 957 compatible = "fsl,imx7d-uart",
958 958 "fsl,imx6q-uart";
959 reg = 959 reg = <0x30860000 0x10000>;
960 interr 960 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
961 clocks 961 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
962 962 <&clks IMX7D_UART1_ROOT_CLK>;
963 clock- 963 clock-names = "ipg", "per";
964 status 964 status = "disabled";
965 }; 965 };
966 966
967 uart2: serial@ 967 uart2: serial@30890000 {
968 compat 968 compatible = "fsl,imx7d-uart",
969 969 "fsl,imx6q-uart";
970 reg = 970 reg = <0x30890000 0x10000>;
971 interr 971 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
972 clocks 972 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
973 973 <&clks IMX7D_UART2_ROOT_CLK>;
974 clock- 974 clock-names = "ipg", "per";
975 status 975 status = "disabled";
976 }; 976 };
977 977
978 uart3: serial@ 978 uart3: serial@30880000 {
979 compat 979 compatible = "fsl,imx7d-uart",
980 980 "fsl,imx6q-uart";
981 reg = 981 reg = <0x30880000 0x10000>;
982 interr 982 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
983 clocks 983 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
984 984 <&clks IMX7D_UART3_ROOT_CLK>;
985 clock- 985 clock-names = "ipg", "per";
986 status 986 status = "disabled";
987 }; 987 };
988 988
989 sai1: sai@308a 989 sai1: sai@308a0000 {
990 #sound 990 #sound-dai-cells = <0>;
991 compat 991 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
992 reg = 992 reg = <0x308a0000 0x10000>;
993 interr 993 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
994 clocks 994 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
995 995 <&clks IMX7D_SAI1_ROOT_CLK>,
996 996 <&clks IMX7D_CLK_DUMMY>,
997 997 <&clks IMX7D_CLK_DUMMY>;
998 clock- 998 clock-names = "bus", "mclk1", "mclk2", "mclk3";
999 dma-na 999 dma-names = "rx", "tx";
1000 dmas 1000 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
1001 statu 1001 status = "disabled";
1002 }; 1002 };
1003 1003
1004 sai2: sai@308 1004 sai2: sai@308b0000 {
1005 #soun 1005 #sound-dai-cells = <0>;
1006 compa 1006 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1007 reg = 1007 reg = <0x308b0000 0x10000>;
1008 inter 1008 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1009 clock 1009 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
1010 1010 <&clks IMX7D_SAI2_ROOT_CLK>,
1011 1011 <&clks IMX7D_CLK_DUMMY>,
1012 1012 <&clks IMX7D_CLK_DUMMY>;
1013 clock 1013 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1014 dma-n 1014 dma-names = "rx", "tx";
1015 dmas 1015 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
1016 statu 1016 status = "disabled";
1017 }; 1017 };
1018 1018
1019 sai3: sai@308 1019 sai3: sai@308c0000 {
1020 #soun 1020 #sound-dai-cells = <0>;
1021 compa 1021 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1022 reg = 1022 reg = <0x308c0000 0x10000>;
1023 inter 1023 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1024 clock 1024 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
1025 1025 <&clks IMX7D_SAI3_ROOT_CLK>,
1026 1026 <&clks IMX7D_CLK_DUMMY>,
1027 1027 <&clks IMX7D_CLK_DUMMY>;
1028 clock 1028 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1029 dma-n 1029 dma-names = "rx", "tx";
1030 dmas 1030 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
1031 statu 1031 status = "disabled";
1032 }; 1032 };
1033 }; 1033 };
1034 1034
1035 crypto: crypto@309000 1035 crypto: crypto@30900000 {
1036 compatible = 1036 compatible = "fsl,sec-v4.0";
1037 #address-cell 1037 #address-cells = <1>;
1038 #size-cells = 1038 #size-cells = <1>;
1039 reg = <0x3090 1039 reg = <0x30900000 0x40000>;
1040 ranges = <0 0 1040 ranges = <0 0x30900000 0x40000>;
1041 interrupts = 1041 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&cl 1042 clocks = <&clks IMX7D_CAAM_CLK>,
1043 <&cl 1043 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1044 clock-names = 1044 clock-names = "ipg", "aclk";
1045 1045
1046 sec_jr0: jr@1 1046 sec_jr0: jr@1000 {
1047 compa 1047 compatible = "fsl,sec-v4.0-job-ring";
1048 reg = 1048 reg = <0x1000 0x1000>;
1049 inter 1049 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1050 }; 1050 };
1051 1051
1052 sec_jr1: jr@2 1052 sec_jr1: jr@2000 {
1053 compa 1053 compatible = "fsl,sec-v4.0-job-ring";
1054 reg = 1054 reg = <0x2000 0x1000>;
1055 inter 1055 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1056 }; 1056 };
1057 1057
1058 sec_jr2: jr@3 1058 sec_jr2: jr@3000 {
1059 compa 1059 compatible = "fsl,sec-v4.0-job-ring";
1060 reg = 1060 reg = <0x3000 0x1000>;
1061 inter 1061 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1062 }; 1062 };
1063 }; 1063 };
1064 1064
1065 flexcan1: can@30a0000 1065 flexcan1: can@30a00000 {
1066 compatible = 1066 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1067 reg = <0x30a0 1067 reg = <0x30a00000 0x10000>;
1068 interrupts = 1068 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&cl 1069 clocks = <&clks IMX7D_CLK_DUMMY>,
1070 <&clk 1070 <&clks IMX7D_CAN1_ROOT_CLK>;
1071 clock-names = 1071 clock-names = "ipg", "per";
1072 fsl,stop-mode 1072 fsl,stop-mode = <&gpr 0x10 1>;
1073 status = "dis 1073 status = "disabled";
1074 }; 1074 };
1075 1075
1076 flexcan2: can@30a1000 1076 flexcan2: can@30a10000 {
1077 compatible = 1077 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1078 reg = <0x30a1 1078 reg = <0x30a10000 0x10000>;
1079 interrupts = 1079 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&cl 1080 clocks = <&clks IMX7D_CLK_DUMMY>,
1081 <&clk 1081 <&clks IMX7D_CAN2_ROOT_CLK>;
1082 clock-names = 1082 clock-names = "ipg", "per";
1083 fsl,stop-mode 1083 fsl,stop-mode = <&gpr 0x10 2>;
1084 status = "dis 1084 status = "disabled";
1085 }; 1085 };
1086 1086
1087 i2c1: i2c@30a20000 { 1087 i2c1: i2c@30a20000 {
1088 #address-cell 1088 #address-cells = <1>;
1089 #size-cells = 1089 #size-cells = <0>;
1090 compatible = 1090 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1091 reg = <0x30a2 1091 reg = <0x30a20000 0x10000>;
1092 interrupts = 1092 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cl 1093 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1094 status = "dis 1094 status = "disabled";
1095 }; 1095 };
1096 1096
1097 i2c2: i2c@30a30000 { 1097 i2c2: i2c@30a30000 {
1098 #address-cell 1098 #address-cells = <1>;
1099 #size-cells = 1099 #size-cells = <0>;
1100 compatible = 1100 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1101 reg = <0x30a3 1101 reg = <0x30a30000 0x10000>;
1102 interrupts = 1102 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&cl 1103 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1104 status = "dis 1104 status = "disabled";
1105 }; 1105 };
1106 1106
1107 i2c3: i2c@30a40000 { 1107 i2c3: i2c@30a40000 {
1108 #address-cell 1108 #address-cells = <1>;
1109 #size-cells = 1109 #size-cells = <0>;
1110 compatible = 1110 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1111 reg = <0x30a4 1111 reg = <0x30a40000 0x10000>;
1112 interrupts = 1112 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&cl 1113 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1114 status = "dis 1114 status = "disabled";
1115 }; 1115 };
1116 1116
1117 i2c4: i2c@30a50000 { 1117 i2c4: i2c@30a50000 {
1118 #address-cell 1118 #address-cells = <1>;
1119 #size-cells = 1119 #size-cells = <0>;
1120 compatible = 1120 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1121 reg = <0x30a5 1121 reg = <0x30a50000 0x10000>;
1122 interrupts = 1122 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&cl 1123 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1124 status = "dis 1124 status = "disabled";
1125 }; 1125 };
1126 1126
1127 uart4: serial@30a6000 1127 uart4: serial@30a60000 {
1128 compatible = 1128 compatible = "fsl,imx7d-uart",
1129 1129 "fsl,imx6q-uart";
1130 reg = <0x30a6 1130 reg = <0x30a60000 0x10000>;
1131 interrupts = 1131 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&cl 1132 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1133 <&clk 1133 <&clks IMX7D_UART4_ROOT_CLK>;
1134 clock-names = 1134 clock-names = "ipg", "per";
1135 status = "dis 1135 status = "disabled";
1136 }; 1136 };
1137 1137
1138 uart5: serial@30a7000 1138 uart5: serial@30a70000 {
1139 compatible = 1139 compatible = "fsl,imx7d-uart",
1140 1140 "fsl,imx6q-uart";
1141 reg = <0x30a7 1141 reg = <0x30a70000 0x10000>;
1142 interrupts = 1142 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cl 1143 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1144 <&clk 1144 <&clks IMX7D_UART5_ROOT_CLK>;
1145 clock-names = 1145 clock-names = "ipg", "per";
1146 status = "dis 1146 status = "disabled";
1147 }; 1147 };
1148 1148
1149 uart6: serial@30a8000 1149 uart6: serial@30a80000 {
1150 compatible = 1150 compatible = "fsl,imx7d-uart",
1151 1151 "fsl,imx6q-uart";
1152 reg = <0x30a8 1152 reg = <0x30a80000 0x10000>;
1153 interrupts = 1153 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1154 clocks = <&cl 1154 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1155 <&clk 1155 <&clks IMX7D_UART6_ROOT_CLK>;
1156 clock-names = 1156 clock-names = "ipg", "per";
1157 status = "dis 1157 status = "disabled";
1158 }; 1158 };
1159 1159
1160 uart7: serial@30a9000 1160 uart7: serial@30a90000 {
1161 compatible = 1161 compatible = "fsl,imx7d-uart",
1162 1162 "fsl,imx6q-uart";
1163 reg = <0x30a9 1163 reg = <0x30a90000 0x10000>;
1164 interrupts = 1164 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&cl 1165 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1166 <&clk 1166 <&clks IMX7D_UART7_ROOT_CLK>;
1167 clock-names = 1167 clock-names = "ipg", "per";
1168 status = "dis 1168 status = "disabled";
1169 }; 1169 };
1170 1170
1171 mu0a: mailbox@30aa000 1171 mu0a: mailbox@30aa0000 {
1172 compatible = 1172 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1173 reg = <0x30aa 1173 reg = <0x30aa0000 0x10000>;
1174 interrupts = 1174 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&cl 1175 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1176 #mbox-cells = 1176 #mbox-cells = <2>;
1177 status = "dis 1177 status = "disabled";
1178 }; 1178 };
1179 1179
1180 mu0b: mailbox@30ab000 1180 mu0b: mailbox@30ab0000 {
1181 compatible = 1181 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1182 reg = <0x30ab 1182 reg = <0x30ab0000 0x10000>;
1183 interrupts = 1183 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&cl 1184 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1185 #mbox-cells = 1185 #mbox-cells = <2>;
1186 fsl,mu-side-b 1186 fsl,mu-side-b;
1187 status = "dis 1187 status = "disabled";
1188 }; 1188 };
1189 1189
1190 usbotg1: usb@30b10000 1190 usbotg1: usb@30b10000 {
1191 compatible = 1191 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1192 reg = <0x30b1 1192 reg = <0x30b10000 0x200>;
1193 interrupts = 1193 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cl 1194 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1195 fsl,usbphy = 1195 fsl,usbphy = <&usbphynop1>;
1196 fsl,usbmisc = 1196 fsl,usbmisc = <&usbmisc1 0>;
1197 phy-clkgate-d 1197 phy-clkgate-delay-us = <400>;
1198 status = "dis 1198 status = "disabled";
1199 }; 1199 };
1200 1200
1201 usbh: usb@30b30000 { 1201 usbh: usb@30b30000 {
1202 compatible = 1202 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1203 reg = <0x30b3 1203 reg = <0x30b30000 0x200>;
1204 interrupts = 1204 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&cl 1205 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1206 fsl,usbphy = 1206 fsl,usbphy = <&usbphynop3>;
1207 fsl,usbmisc = 1207 fsl,usbmisc = <&usbmisc3 0>;
1208 phy_type = "h 1208 phy_type = "hsic";
1209 dr_mode = "ho 1209 dr_mode = "host";
1210 phy-clkgate-d 1210 phy-clkgate-delay-us = <400>;
1211 status = "dis 1211 status = "disabled";
1212 }; 1212 };
1213 1213
1214 usbmisc1: usbmisc@30b 1214 usbmisc1: usbmisc@30b10200 {
1215 #index-cells 1215 #index-cells = <1>;
1216 compatible = 1216 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1217 reg = <0x30b1 1217 reg = <0x30b10200 0x200>;
1218 }; 1218 };
1219 1219
1220 usbmisc3: usbmisc@30b 1220 usbmisc3: usbmisc@30b30200 {
1221 #index-cells 1221 #index-cells = <1>;
1222 compatible = 1222 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1223 reg = <0x30b3 1223 reg = <0x30b30200 0x200>;
1224 }; 1224 };
1225 1225
1226 usdhc1: mmc@30b40000 1226 usdhc1: mmc@30b40000 {
1227 compatible = 1227 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1228 reg = <0x30b4 1228 reg = <0x30b40000 0x10000>;
1229 interrupts = 1229 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cl 1230 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1231 <&clk 1231 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1232 <&clk 1232 <&clks IMX7D_USDHC1_ROOT_CLK>;
1233 clock-names = 1233 clock-names = "ipg", "ahb", "per";
1234 bus-width = < 1234 bus-width = <4>;
1235 fsl,tuning-st 1235 fsl,tuning-step = <2>;
1236 fsl,tuning-st 1236 fsl,tuning-start-tap = <20>;
1237 status = "dis 1237 status = "disabled";
1238 }; 1238 };
1239 1239
1240 usdhc2: mmc@30b50000 1240 usdhc2: mmc@30b50000 {
1241 compatible = 1241 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1242 reg = <0x30b5 1242 reg = <0x30b50000 0x10000>;
1243 interrupts = 1243 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&cl 1244 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1245 <&clk 1245 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1246 <&clk 1246 <&clks IMX7D_USDHC2_ROOT_CLK>;
1247 clock-names = 1247 clock-names = "ipg", "ahb", "per";
1248 bus-width = < 1248 bus-width = <4>;
1249 fsl,tuning-st 1249 fsl,tuning-step = <2>;
1250 fsl,tuning-st 1250 fsl,tuning-start-tap = <20>;
1251 status = "dis 1251 status = "disabled";
1252 }; 1252 };
1253 1253
1254 usdhc3: mmc@30b60000 1254 usdhc3: mmc@30b60000 {
1255 compatible = 1255 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1256 reg = <0x30b6 1256 reg = <0x30b60000 0x10000>;
1257 interrupts = 1257 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cl 1258 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1259 <&clk 1259 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1260 <&clk 1260 <&clks IMX7D_USDHC3_ROOT_CLK>;
1261 clock-names = 1261 clock-names = "ipg", "ahb", "per";
1262 bus-width = < 1262 bus-width = <4>;
1263 fsl,tuning-st 1263 fsl,tuning-step = <2>;
1264 fsl,tuning-st 1264 fsl,tuning-start-tap = <20>;
1265 status = "dis 1265 status = "disabled";
1266 }; 1266 };
1267 1267
1268 qspi: spi@30bb0000 { 1268 qspi: spi@30bb0000 {
1269 compatible = 1269 compatible = "fsl,imx7d-qspi";
1270 reg = <0x30bb 1270 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1271 reg-names = " 1271 reg-names = "QuadSPI", "QuadSPI-memory";
1272 #address-cell 1272 #address-cells = <1>;
1273 #size-cells = 1273 #size-cells = <0>;
1274 interrupts = 1274 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&cl 1275 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1276 <&clk 1276 <&clks IMX7D_QSPI_ROOT_CLK>;
1277 clock-names = 1277 clock-names = "qspi_en", "qspi";
1278 status = "dis 1278 status = "disabled";
1279 }; 1279 };
1280 1280
1281 sdma: dma-controller@ 1281 sdma: dma-controller@30bd0000 {
1282 compatible = 1282 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1283 reg = <0x30bd 1283 reg = <0x30bd0000 0x10000>;
1284 interrupts = 1284 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1285 clocks = <&cl 1285 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1286 <&cl 1286 <&clks IMX7D_SDMA_CORE_CLK>;
1287 clock-names = 1287 clock-names = "ipg", "ahb";
1288 #dma-cells = 1288 #dma-cells = <3>;
1289 fsl,sdma-ram- 1289 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1290 }; 1290 };
1291 1291
1292 fec1: ethernet@30be00 1292 fec1: ethernet@30be0000 {
1293 compatible = 1293 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1294 reg = <0x30be 1294 reg = <0x30be0000 0x10000>;
1295 interrupt-nam 1295 interrupt-names = "int0", "int1", "int2", "pps";
1296 interrupts = 1296 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_ 1297 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1298 <GIC_ 1298 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_ 1299 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1300 clocks = <&cl 1300 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1301 <&clk 1301 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1302 <&clk 1302 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1303 <&clk 1303 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1304 <&clk 1304 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1305 clock-names = 1305 clock-names = "ipg", "ahb", "ptp",
1306 "enet 1306 "enet_clk_ref", "enet_out";
1307 fsl,num-tx-qu 1307 fsl,num-tx-queues = <3>;
1308 fsl,num-rx-qu 1308 fsl,num-rx-queues = <3>;
1309 fsl,stop-mode 1309 fsl,stop-mode = <&gpr 0x10 3>;
1310 status = "dis 1310 status = "disabled";
1311 }; 1311 };
1312 }; 1312 };
1313 1313
1314 dma_apbh: dma-controller@3300 1314 dma_apbh: dma-controller@33000000 {
1315 compatible = "fsl,imx 1315 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1316 reg = <0x33000000 0x2 1316 reg = <0x33000000 0x2000>;
1317 interrupts = <GIC_SPI 1317 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 1318 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 1319 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 1320 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1321 #dma-cells = <1>; 1321 #dma-cells = <1>;
1322 dma-channels = <4>; 1322 dma-channels = <4>;
1323 clocks = <&clks IMX7D 1323 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1324 }; 1324 };
1325 1325
1326 gpmi: nand-controller@3300200 1326 gpmi: nand-controller@33002000 {
1327 compatible = "fsl,imx 1327 compatible = "fsl,imx7d-gpmi-nand";
1328 #address-cells = <1>; 1328 #address-cells = <1>;
1329 #size-cells = <0>; 1329 #size-cells = <0>;
1330 reg = <0x33002000 0x2 1330 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1331 reg-names = "gpmi-nan 1331 reg-names = "gpmi-nand", "bch";
1332 interrupts = <GIC_SPI 1332 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1333 interrupt-names = "bc 1333 interrupt-names = "bch";
1334 clocks = <&clks IMX7D 1334 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1335 <&clks IMX7D_ 1335 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1336 clock-names = "gpmi_i 1336 clock-names = "gpmi_io", "gpmi_bch_apb";
1337 dmas = <&dma_apbh 0>; 1337 dmas = <&dma_apbh 0>;
1338 dma-names = "rx-tx"; 1338 dma-names = "rx-tx";
1339 status = "disabled"; 1339 status = "disabled";
1340 assigned-clocks = <&c 1340 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1341 assigned-clock-parent 1341 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1342 }; 1342 };
1343 }; 1343 };
1344 }; 1344 };
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