1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 2 /* 3 * Copyright (C) 2019 3 * Copyright (C) 2019 4 * Author(s): Giulio Benetti <giulio.benetti@b 4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> 5 */ 5 */ 6 6 7 #ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC 7 #ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H 8 #define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC 8 #define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H 9 9 10 #define IMX_PAD_SION 0x40000000 10 #define IMX_PAD_SION 0x40000000 11 11 12 /* 12 /* 13 * The pin function ID is a tuple of 13 * The pin function ID is a tuple of 14 * <mux_reg conf_reg input_reg mux_mode input_ 14 * <mux_reg conf_reg input_reg mux_mode input_val> 15 */ 15 */ 16 16 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_P 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 23 23 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_P 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 27 #define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT 27 #define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 28 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D0 28 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 29 #define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 29 #define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 30 30 31 #define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 31 #define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 32 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_P 32 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 33 #define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 33 #define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 34 #define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT 34 #define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 35 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D0 35 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 36 #define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 36 #define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 37 37 38 #define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 38 #define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 39 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_P 39 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 40 #define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 40 #define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 41 #define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT 41 #define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 42 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D0 42 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 43 #define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 43 #define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 44 44 45 #define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 45 #define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 46 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_P 46 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 47 #define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DA 47 #define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 48 #define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT 48 #define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 49 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D0 49 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 50 #define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 50 #define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 51 51 52 #define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 52 #define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 53 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_P 53 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 54 #define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SY 54 #define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 55 #define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT 55 #define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 56 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D0 56 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 57 #define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 57 #define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 58 58 59 #define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 59 #define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 60 #define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_P 60 #define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 61 #define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BC 61 #define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 62 #define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT 62 #define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 63 #define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D0 63 #define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 64 #define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 64 #define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 65 65 66 #define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 66 #define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 67 #define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_P 67 #define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 68 #define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 68 #define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 69 #define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT 69 #define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 70 #define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D0 70 #define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 71 #define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 71 #define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 72 72 73 #define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 73 #define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 74 #define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_P 74 #define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 75 #define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DA 75 #define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 76 #define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT 76 #define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 77 #define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D0 77 #define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 78 #define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 78 #define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 79 79 80 #define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR0 80 #define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 81 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_P 81 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 82 #define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SY 82 #define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 83 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_T 83 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 84 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D0 84 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 85 #define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 85 #define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 86 86 87 #define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR0 87 #define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 88 #define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_P 88 #define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 89 #define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BC 89 #define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 90 #define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_R 90 #define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 91 #define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D1 91 #define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 92 #define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 92 #define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 93 93 94 #define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR0 94 #define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 95 #define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_P 95 #define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 96 #define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 96 #define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 97 #define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RES 97 #define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 98 #define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D1 98 #define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 99 #define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 99 #define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 100 100 101 #define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR0 101 #define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 102 #define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT 102 #define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 103 #define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 103 #define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 104 #define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 104 #define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 105 #define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_P 105 #define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 106 #define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 106 #define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 107 107 108 #define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR0 108 #define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 109 #define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT 109 #define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 110 #define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TX 110 #define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 111 #define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 111 #define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 112 #define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_P 112 #define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 113 #define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 113 #define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 114 114 115 #define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR0 115 #define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 116 #define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT 116 #define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 117 #define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RX 117 #define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 118 #define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 118 #define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 119 #define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS 119 #define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 120 #define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 120 #define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 121 121 122 #define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR0 122 #define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 123 #define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT 123 #define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 124 #define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CT 124 #define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 125 #define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 125 #define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 126 #define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER 126 #define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 127 #define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 127 #define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 128 128 129 #define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR0 129 #define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 130 #define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT 130 #define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 131 #define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RT 131 #define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 132 #define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 132 #define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 133 #define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER 133 #define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 134 #define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 134 #define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 135 135 136 #define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR0 136 #define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 137 #define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_P 137 #define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 138 #define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CT 138 #define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 139 #define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_T 139 #define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 140 #define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER 140 #define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 141 #define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 141 #define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 142 142 143 #define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR0 143 #define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 144 #define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_P 144 #define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 145 #define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RT 145 #define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 146 #define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_R 146 #define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 147 #define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER 147 #define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 148 #define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 148 #define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 149 #define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5 149 #define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 150 150 151 #define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR1 151 #define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 152 #define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_P 152 #define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 153 #define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TX 153 #define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 154 #define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DA 154 #define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 155 #define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER 155 #define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 156 #define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 156 #define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 157 #define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 157 #define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 158 158 159 #define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR1 159 #define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 160 #define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_P 160 #define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 161 #define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RX 161 #define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 162 #define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DA 162 #define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 163 #define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER 163 #define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 164 #define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 164 #define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 165 165 166 #define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 166 #define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 167 #define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_P 167 #define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 168 #define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 168 #define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 169 #define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DA 169 #define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 170 #define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER 170 #define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 171 #define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 171 #define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 172 172 173 #define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 173 #define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 174 #define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_P 174 #define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 175 #define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 175 #define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 176 #define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DA 176 #define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 177 #define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER 177 #define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 178 #define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 178 #define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 179 179 180 #define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR1 180 #define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 181 #define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_P 181 #define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 182 #define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TX 182 #define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 183 #define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 183 #define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 184 #define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTU 184 #define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 185 #define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 185 #define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 186 186 187 #define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 187 #define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 188 #define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_P 188 #define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 189 #define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RX 189 #define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 190 #define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 190 #define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 191 #define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTU 191 #define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 192 #define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 192 #define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 193 193 194 #define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 194 #define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 195 #define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_P 195 #define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 196 #define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TX 196 #define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 197 #define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CL 197 #define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 198 #define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_C 198 #define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 199 #define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 199 #define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 200 200 201 #define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 201 #define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 202 #define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_P 202 #define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 203 #define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RX 203 #define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 204 #define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 204 #define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 205 #define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D1 205 #define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 206 #define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 206 #define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 207 207 208 #define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 208 #define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 209 #define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_P 209 #define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 210 #define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RT 210 #define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 211 #define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 211 #define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 212 #define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D1 212 #define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 213 #define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 213 #define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 214 214 215 #define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 215 #define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 216 #define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_P 216 #define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 217 #define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CT 217 #define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 218 #define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 218 #define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 219 #define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D1 219 #define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 220 #define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 220 #define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 221 221 222 #define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 222 #define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 223 #define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_P 223 #define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 224 #define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RT 224 #define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 225 #define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 225 #define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 226 #define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D1 226 #define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 227 #define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 227 #define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 228 228 229 #define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 229 #define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 230 #define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_P 230 #define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 231 #define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CT 231 #define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 232 #define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS 232 #define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 233 #define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 233 #define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 234 #define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 234 #define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 235 235 236 #define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 236 #define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 237 #define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_P 237 #define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 238 #define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TX 238 #define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 239 #define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS 239 #define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 240 #define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 240 #define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 241 #define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 241 #define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 242 242 243 #define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 243 #define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 244 #define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_P 244 #define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 245 #define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RX 245 #define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 246 #define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_R 246 #define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 247 #define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 247 #define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 248 #define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 248 #define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 249 249 250 #define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 250 #define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 251 #define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_P 251 #define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 252 #define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RES 252 #define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 253 #define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DA 253 #define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 254 #define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 254 #define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 255 #define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 255 #define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 256 256 257 #define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 257 #define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 258 #define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_P 258 #define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 259 #define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSE 259 #define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 260 #define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SY 260 #define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 261 #define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 261 #define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 262 #define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 262 #define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 263 263 264 #define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 264 #define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 265 #define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT 265 #define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 266 #define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPA 266 #define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 267 #define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BC 267 #define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 268 #define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 268 #define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 269 #define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 269 #define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 270 #define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_ 270 #define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 271 271 272 #define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 272 #define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 273 #define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT 273 #define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 274 #define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPA 274 #define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 275 #define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DA 275 #define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 276 #define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 276 #define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 277 #define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 277 #define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 278 #define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 278 #define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 279 279 280 #define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 280 #define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 281 #define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT 281 #define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 282 #define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPA 282 #define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 283 #define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 283 #define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 284 #define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 284 #define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 285 #define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 285 #define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 286 #define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 286 #define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 287 287 288 #define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 288 #define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 289 #define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_P 289 #define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 290 #define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TX 290 #define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 291 #define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BC 291 #define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 292 #define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 292 #define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 293 #define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 293 #define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 294 #define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSE 294 #define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 295 295 296 #define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 296 #define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 297 #define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_P 297 #define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 298 #define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RX 298 #define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 299 #define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SY 299 #define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 300 #define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 300 #define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 301 #define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 301 #define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 302 #define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_ 302 #define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 303 303 304 #define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 304 #define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 305 #define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTU 305 #define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 306 #define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS 306 #define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 307 #define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_O 307 #define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 308 #define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 308 #define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 309 #define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 309 #define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 310 #define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RES 310 #define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 311 311 312 #define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 312 #define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 313 #define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTU 313 #define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 314 #define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS 314 #define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 315 #define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_P 315 #define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 316 #define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 316 #define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 317 #define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 317 #define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 318 #define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSE 318 #define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 319 319 320 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2 320 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 321 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INO 321 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 322 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_ 322 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 323 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2 323 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 324 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_S 324 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 325 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO 325 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 326 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_R 326 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 327 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_S 327 #define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 328 328 329 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2 329 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 330 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INO 330 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 331 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_ 331 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 332 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1 332 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 333 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_S 333 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 334 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO 334 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 335 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_ 335 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 336 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_S 336 #define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 337 337 338 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2 338 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 339 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INO 339 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 340 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_ 340 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 341 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1 341 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 342 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1 342 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 343 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO 343 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 344 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_H 344 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 345 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_S 345 #define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 346 346 347 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2 347 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 348 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INO 348 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 349 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_ 349 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 350 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1 350 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 351 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1 351 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 352 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO 352 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 353 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_ 353 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 354 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_P 354 #define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 355 355 356 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT 356 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 357 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGH 357 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 358 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_ 358 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 359 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_ 359 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 360 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA 360 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 361 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO 361 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 362 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIG 362 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 363 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_P 363 #define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 364 364 365 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT 365 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 366 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 366 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 367 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_ 367 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 368 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_ 368 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 369 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA 369 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 370 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO 370 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 371 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INO 371 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 372 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_P 372 #define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 373 373 374 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 374 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 375 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COM 375 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 376 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_ 376 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 377 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_ 377 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 378 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA 378 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 379 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO 379 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 380 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INO 380 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 381 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_P 381 #define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 382 382 383 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 383 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 384 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COM 384 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 385 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ 385 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 386 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_ 386 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 387 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA 387 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 388 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO 388 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 389 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INO 389 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 390 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_158 390 #define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 391 391 392 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 392 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 393 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COM 393 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 394 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_ 394 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 395 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_ 395 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 396 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA 396 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 397 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO 397 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 398 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INO 398 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 399 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_158 399 #define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 400 400 401 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 401 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 402 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2 402 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 403 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_ 403 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 404 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_ 404 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 405 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA 405 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 406 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO 406 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 407 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INO 407 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 408 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 408 #define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 409 409 410 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 410 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 411 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1 411 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 412 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 412 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 413 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCL 413 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 414 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA 414 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 415 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO 415 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 416 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INO 416 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 417 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_158 417 #define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 418 418 419 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRS 419 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 420 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1 420 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 421 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 421 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 422 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 422 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 423 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA 423 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 424 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO 424 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 425 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INO 425 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 426 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_158 426 #define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 427 427 428 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_S 428 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 429 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC 429 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 430 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_ 430 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 431 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 431 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 432 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1 432 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 433 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO 433 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 434 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_158 434 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 435 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 435 #define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 436 436 437 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_S 437 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 438 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 438 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 439 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_ 439 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 440 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_ 440 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 441 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1 441 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 442 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO 442 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 443 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_158 443 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 444 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_ 444 #define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 445 445 446 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2 446 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 447 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INO 447 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 448 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_ 448 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 449 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_158 449 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 450 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYN 450 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 451 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO 451 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 452 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2 452 #define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 453 453 454 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2 454 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 455 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INO 455 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 456 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_ 456 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 457 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_158 457 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 458 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYN 458 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 459 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO 459 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 460 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2 460 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 461 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WD 461 #define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 462 462 463 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2 463 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 464 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIM 464 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 465 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_ 465 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 466 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_S 466 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 467 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 467 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 468 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO 468 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 469 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_W 469 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 470 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW0 470 #define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 471 471 472 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1 472 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 473 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIM 473 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 474 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_ 474 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 475 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_S 475 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 476 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC 476 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 477 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO 477 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 478 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_V 478 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 479 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL0 479 #define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 480 480 481 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1 481 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 482 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIM 482 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 483 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_ 483 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 484 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OU 484 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 485 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_158 485 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 486 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO 486 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 487 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_C 487 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 488 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW0 488 #define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 489 489 490 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1 490 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 491 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIM 491 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 492 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_ 492 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 493 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 493 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 494 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_158 494 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 495 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO 495 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 496 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_C 496 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 497 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL0 497 #define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 498 498 499 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_ 499 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 500 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 500 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 501 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_ 501 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 502 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR 502 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 503 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXC 503 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 504 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO 504 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 505 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_D 505 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 506 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW0 506 #define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 507 507 508 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_ 508 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 509 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDI 509 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 510 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_ 510 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 511 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OU 511 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 512 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 512 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 513 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO 513 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 514 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_D 514 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 515 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL0 515 #define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 516 516 517 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_ 517 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 518 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_S 518 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 519 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_ 519 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 520 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LO 520 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 521 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYN 521 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 522 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO 522 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 523 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_D 523 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 524 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW0 524 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 525 525 526 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_ 526 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 527 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_S 527 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 528 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_ 528 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 529 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EX 529 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 530 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYN 530 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 531 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO 531 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 532 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_D 532 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 533 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL0 533 #define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 534 534 535 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_ 535 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 536 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4 536 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 537 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1 537 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 538 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC 538 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 539 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA 539 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 540 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO 540 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 541 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_C 541 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 542 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW0 542 #define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 543 543 544 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_ 544 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 545 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4 545 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 546 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1 546 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 547 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCL 547 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 548 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA 548 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 549 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO 549 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 550 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_C 550 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 551 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL0 551 #define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 552 552 553 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_ 553 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 554 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 554 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 555 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_ 555 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 556 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_ 556 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 557 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA 557 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 558 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO 558 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 559 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_W 559 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 560 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW0 560 #define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 561 561 562 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_ 562 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 563 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_ 563 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 564 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_ 564 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 565 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_ 565 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 566 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA 566 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 567 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO 567 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 568 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_R 568 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 569 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL0 569 #define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 570 570 571 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_ 571 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 572 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OU 572 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 573 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_P 573 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 574 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_ 574 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 575 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA 575 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 576 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO 576 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 577 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_D 577 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 578 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW0 578 #define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 579 579 580 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_ 580 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 581 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OU 581 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 582 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_S 582 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 583 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_ 583 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 584 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA 584 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 585 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO 585 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 586 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_D 586 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 587 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL0 587 #define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 588 588 589 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_ 589 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 590 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OU 590 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 591 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_S 591 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 592 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_ 592 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 593 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA 593 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 594 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO 594 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 595 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_D 595 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 596 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW0 596 #define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 597 597 598 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_ 598 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 599 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OU 599 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 600 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_S 600 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 601 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_ 601 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 602 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA 602 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 603 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO 603 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 604 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_D 604 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 605 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL0 605 #define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 606 606 607 #define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 607 #define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 608 #define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 608 #define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 609 #define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 609 #define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 610 #define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 610 #define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 611 #define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 611 #define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 612 #define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 612 #define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 613 #define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 613 #define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 614 614 615 #define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 615 #define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 616 #define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 616 #define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 617 #define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 617 #define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 618 #define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 618 #define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 619 #define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 619 #define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 620 #define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 620 #define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 621 #define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 621 #define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 622 622 623 #define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 623 #define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 624 #define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 624 #define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 625 #define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 625 #define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 626 #define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 626 #define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 627 #define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 627 #define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 628 #define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 628 #define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 629 #define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 629 #define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 630 630 631 #define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 631 #define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 632 #define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 632 #define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 633 #define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 633 #define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 634 #define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 634 #define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 635 #define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 635 #define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 636 #define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 636 #define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 637 #define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET 637 #define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 638 638 639 #define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 639 #define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 640 #define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 640 #define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 641 #define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 641 #define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 642 #define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 642 #define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 643 #define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 643 #define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 644 #define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 644 #define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 645 #define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG0 645 #define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 646 646 647 #define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 647 #define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 648 #define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 648 #define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 649 #define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 649 #define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 650 #define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 650 #define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 651 #define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 651 #define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 652 #define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 652 #define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 653 #define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG0 653 #define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 654 654 655 #define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 655 #define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 656 #define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 656 #define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 657 #define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PW 657 #define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 658 #define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 658 #define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 659 #define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 659 #define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 660 #define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 660 #define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 661 #define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG0 661 #define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 662 662 663 #define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 663 #define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 664 #define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 664 #define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 665 #define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PW 665 #define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 666 #define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 666 #define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 667 #define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 667 #define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 668 #define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 668 #define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 669 #define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG0 669 #define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 670 670 671 #define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 671 #define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 672 #define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 672 #define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 673 #define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PW 673 #define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 674 #define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 674 #define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 675 #define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 675 #define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 676 #define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 676 #define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 677 #define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG0 677 #define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 678 678 679 #define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 679 #define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 680 #define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 680 #define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 681 #define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PW 681 #define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 682 #define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 682 #define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 683 #define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 683 #define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 684 #define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 684 #define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 685 #define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG0 685 #define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 686 686 687 #define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 687 #define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 688 #define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 688 #define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 689 #define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PW 689 #define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 690 #define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DAT 690 #define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 691 #define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 691 #define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 692 #define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 692 #define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 693 #define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG0 693 #define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 694 694 695 #define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 695 #define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 696 #define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 696 #define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 697 #define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PW 697 #define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 698 #define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DAT 698 #define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 699 #define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 699 #define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 700 #define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 700 #define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 701 #define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG0 701 #define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 702 702 703 #define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 703 #define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 704 #define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT1 704 #define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 705 #define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_C 705 #define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 706 #define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DAT 706 #define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 707 #define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 707 #define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 708 #define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 708 #define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 709 #define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG0 709 #define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 710 710 711 #define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 711 #define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 712 #define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT1 712 #define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 713 #define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_S 713 #define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 714 #define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 714 #define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 715 #define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 715 #define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 716 #define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 716 #define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 717 #define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG0 717 #define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 718 718 719 #define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 719 #define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 720 #define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT1 720 #define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 721 #define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXE 721 #define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 722 #define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYN 722 #define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 723 #define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 723 #define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 724 #define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 724 #define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 725 #define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG1 725 #define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 726 726 727 #define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 727 #define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 728 #define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT1 728 #define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 729 #define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXE 729 #define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 730 #define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCL 730 #define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 731 #define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 731 #define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 732 #define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 732 #define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 733 #define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG1 733 #define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 734 734 735 #define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 735 #define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 736 #define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT1 736 #define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 737 #define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 737 #define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 738 #define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DAT 738 #define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 739 #define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 739 #define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 740 #define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 740 #define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 741 #define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PW 741 #define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 742 742 743 #define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 743 #define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 744 #define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT1 744 #define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 745 #define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 745 #define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 746 #define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DAT 746 #define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 747 #define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 747 #define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 748 #define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 748 #define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 749 #define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PW 749 #define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 750 750 751 #define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 751 #define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 752 #define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT1 752 #define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 753 #define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 753 #define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 754 #define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCL 754 #define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 755 #define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 755 #define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 756 #define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 756 #define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 757 #define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PW 757 #define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 758 758 759 #define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 759 #define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 760 #define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT1 760 #define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 761 #define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 761 #define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 762 #define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYN 762 #define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 763 #define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 763 #define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 764 #define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 764 #define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 765 #define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PW 765 #define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 766 766 767 #define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 767 #define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 768 #define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 768 #define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 769 #define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 769 #define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 770 #define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DAT 770 #define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 771 #define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 771 #define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 772 #define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 772 #define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 773 773 774 #define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 774 #define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 775 #define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 775 #define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 776 #define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 776 #define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 777 #define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DAT 777 #define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 778 #define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 778 #define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 779 #define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 779 #define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 780 780 781 #define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 781 #define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 782 #define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 782 #define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 783 #define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 783 #define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 784 #define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 784 #define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 785 #define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 785 #define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 786 #define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 786 #define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 787 787 788 #define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 788 #define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 789 #define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 789 #define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 790 #define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 790 #define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 791 #define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DAT 791 #define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 792 #define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 792 #define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 793 #define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 793 #define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 794 794 795 #define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 795 #define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 796 #define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 796 #define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 797 #define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 797 #define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 798 #define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DAT 798 #define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 799 #define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 799 #define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 800 #define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 800 #define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 801 #define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 801 #define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 802 802 803 #define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 803 #define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 804 #define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 804 #define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 805 #define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 805 #define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 806 #define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 806 #define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 807 #define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 807 #define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 808 #define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 808 #define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 809 #define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 809 #define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 810 810 811 #define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 811 #define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 812 #define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 812 #define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 813 #define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 813 #define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 814 #define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 814 #define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 815 #define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 815 #define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 816 #define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 816 #define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 817 #define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CL 817 #define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 818 818 819 #define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 819 #define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 820 #define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 820 #define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 821 #define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 821 #define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 822 #define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 822 #define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 823 #define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 823 #define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 824 #define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 824 #define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 825 #define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 825 #define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 826 826 827 #define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 827 #define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 828 #define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 828 #define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 829 #define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_E 829 #define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 830 #define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 830 #define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 831 #define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 831 #define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 832 #define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 832 #define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 833 833 834 #define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 834 #define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 835 #define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 835 #define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 836 #define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 836 #define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 837 #define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_E 837 #define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 838 #define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 838 #define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 839 #define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 839 #define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 840 #define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 840 #define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 841 841 842 #define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 842 #define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 843 #define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PW 843 #define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 844 #define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 844 #define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 845 #define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT0 845 #define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 846 #define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 846 #define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 847 #define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 847 #define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 848 #define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSEL 848 #define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 849 849 850 #define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 850 #define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 851 #define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PW 851 #define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 852 #define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 852 #define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 853 #define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT0 853 #define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 854 #define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 854 #define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 855 #define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 855 #define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 856 #define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESE 856 #define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 857 857 858 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_C 858 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 859 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1 859 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 860 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_S 860 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 861 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INO 861 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 862 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_S 862 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 863 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO 863 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 864 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_ 864 #define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 865 865 866 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_C 866 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 867 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1 867 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 868 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_S 868 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 869 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INO 869 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 870 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_P 870 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 871 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO 871 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 872 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_ 872 #define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 873 873 874 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_D 874 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 875 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1 875 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 876 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_ 876 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 877 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INO 877 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 878 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_S 878 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 879 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO 879 #define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 880 880 881 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_D 881 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 882 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1 882 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 883 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_ 883 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 884 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INO 884 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 885 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_S 885 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 886 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO 886 #define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 887 887 888 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_D 888 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 889 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1 889 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 890 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_ 890 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 891 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INO 891 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 892 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_ 892 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 893 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO 893 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 894 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO 894 #define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 895 895 896 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_D 896 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 897 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1 897 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 898 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_ 898 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 899 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INO 899 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 900 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_ 900 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 901 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO 901 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 902 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO 902 #define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 903 903 904 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_D 904 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 905 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_ 905 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 906 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1 906 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 907 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_ 907 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 908 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_ 908 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 909 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO 909 #define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 910 910 911 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_D 911 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 912 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_ 912 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 913 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1 913 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 914 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_ 914 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 915 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_ 915 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 916 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO 916 #define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 917 917 918 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_D 918 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 919 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_ 919 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 920 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2 920 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 921 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_ 921 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 922 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1 922 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 923 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO 923 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 924 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 924 #define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 925 925 926 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_D 926 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 927 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_ 927 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 928 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2 928 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 929 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCL 929 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 930 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1 930 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 931 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO 931 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 932 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC 932 #define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 933 933 934 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_C 934 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 935 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_ 935 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 936 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_S 936 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 937 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_ 937 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 938 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1 938 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 939 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO 939 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 940 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 940 #define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 941 941 942 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_C 942 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 943 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_ 943 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 944 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_S 944 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 945 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_ 945 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 946 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1 946 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 947 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO 947 #define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 948 948 949 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_R 949 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 950 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_ 950 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 951 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_ 951 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 952 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_ 952 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 953 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_P 953 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 954 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO 954 #define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 955 955 956 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX 956 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 957 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_ 957 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 958 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_ 958 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 959 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_ 959 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 960 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_S 960 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 961 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO 961 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 962 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_ 962 #define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 963 963 964 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_D 964 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 965 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_ 965 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 966 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_ 966 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 967 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_ 967 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 968 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_S 968 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 969 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO 969 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 970 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX 970 #define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 971 971 972 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_D 972 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 973 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_ 973 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 974 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_ 974 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 975 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_ 975 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 976 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_S 976 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 977 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO 977 #define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 978 978 979 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_D 979 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 980 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_ 980 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 981 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_ 981 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 982 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_S 982 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 983 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_P 983 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 984 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO 984 #define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 985 985 986 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_D 986 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 987 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_ 987 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 988 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_ 988 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 989 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_S 989 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 990 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_P 990 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 991 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO 991 #define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 992 992 993 #endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFU 993 #endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ 994 994
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.