1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2013-2014 Freescale Semiconductor 3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h> 7 #include <dt-bindings/thermal/thermal.h>
8 8
9 / { 9 / {
10 #address-cells = <2>; 10 #address-cells = <2>;
11 #size-cells = <2>; 11 #size-cells = <2>;
12 interrupt-parent = <&gic>; 12 interrupt-parent = <&gic>;
13 13
14 aliases { 14 aliases {
15 crypto = &crypto; 15 crypto = &crypto;
16 ethernet0 = &enet0; 16 ethernet0 = &enet0;
17 ethernet1 = &enet1; 17 ethernet1 = &enet1;
18 ethernet2 = &enet2; 18 ethernet2 = &enet2;
19 rtc1 = &ftm_alarm0; 19 rtc1 = &ftm_alarm0;
20 serial0 = &lpuart0; 20 serial0 = &lpuart0;
21 serial1 = &lpuart1; 21 serial1 = &lpuart1;
22 serial2 = &lpuart2; 22 serial2 = &lpuart2;
23 serial3 = &lpuart3; 23 serial3 = &lpuart3;
24 serial4 = &lpuart4; 24 serial4 = &lpuart4;
25 serial5 = &lpuart5; 25 serial5 = &lpuart5;
26 sysclk = &sysclk; 26 sysclk = &sysclk;
27 }; 27 };
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 cpu0: cpu@f00 { 33 cpu0: cpu@f00 {
34 compatible = "arm,cort 34 compatible = "arm,cortex-a7";
35 device_type = "cpu"; 35 device_type = "cpu";
36 reg = <0xf00>; 36 reg = <0xf00>;
37 clocks = <&clockgen 1 37 clocks = <&clockgen 1 0>;
38 #cooling-cells = <2>; 38 #cooling-cells = <2>;
39 }; 39 };
40 40
41 cpu1: cpu@f01 { 41 cpu1: cpu@f01 {
42 compatible = "arm,cort 42 compatible = "arm,cortex-a7";
43 device_type = "cpu"; 43 device_type = "cpu";
44 reg = <0xf01>; 44 reg = <0xf01>;
45 clocks = <&clockgen 1 45 clocks = <&clockgen 1 0>;
46 #cooling-cells = <2>; 46 #cooling-cells = <2>;
47 }; 47 };
48 }; 48 };
49 49
50 memory@0 { 50 memory@0 {
51 device_type = "memory"; 51 device_type = "memory";
52 reg = <0x0 0x0 0x0 0x0>; 52 reg = <0x0 0x0 0x0 0x0>;
53 }; 53 };
54 54
55 sysclk: sysclk { 55 sysclk: sysclk {
56 compatible = "fixed-clock"; 56 compatible = "fixed-clock";
57 #clock-cells = <0>; 57 #clock-cells = <0>;
58 clock-frequency = <100000000>; 58 clock-frequency = <100000000>;
59 clock-output-names = "sysclk"; 59 clock-output-names = "sysclk";
60 }; 60 };
61 61
62 timer { 62 timer {
63 compatible = "arm,armv7-timer" 63 compatible = "arm,armv7-timer";
64 interrupts = <GIC_PPI 13 (GIC_ 64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 14 (GIC_ 65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 11 (GIC_ 66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 10 (GIC_ 67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
68 }; 68 };
69 69
70 pmu { 70 pmu {
71 compatible = "arm,cortex-a7-pm 71 compatible = "arm,cortex-a7-pmu";
72 interrupts = <GIC_SPI 138 IRQ_ 72 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 139 IRQ_ 73 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&cpu0>, 74 interrupt-affinity = <&cpu0>, <&cpu1>;
75 }; 75 };
76 76
77 reboot { 77 reboot {
78 compatible = "syscon-reboot"; 78 compatible = "syscon-reboot";
79 regmap = <&dcfg>; 79 regmap = <&dcfg>;
80 offset = <0xb0>; 80 offset = <0xb0>;
81 mask = <0x02>; 81 mask = <0x02>;
82 }; 82 };
83 83
84 soc { 84 soc {
85 compatible = "simple-bus"; 85 compatible = "simple-bus";
86 #address-cells = <2>; 86 #address-cells = <2>;
87 #size-cells = <2>; 87 #size-cells = <2>;
88 device_type = "soc"; 88 device_type = "soc";
89 interrupt-parent = <&gic>; 89 interrupt-parent = <&gic>;
90 ranges; 90 ranges;
91 91
92 ddr: memory-controller@1080000 92 ddr: memory-controller@1080000 {
93 compatible = "fsl,qori 93 compatible = "fsl,qoriq-memory-controller";
94 reg = <0x0 0x1080000 0 94 reg = <0x0 0x1080000 0x0 0x1000>;
95 interrupts = <GIC_SPI 95 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
96 big-endian; 96 big-endian;
97 }; 97 };
98 98
99 gic: interrupt-controller@1400 99 gic: interrupt-controller@1400000 {
100 compatible = "arm,gic- 100 compatible = "arm,gic-400", "arm,cortex-a7-gic";
101 #interrupt-cells = <3> 101 #interrupt-cells = <3>;
102 interrupt-controller; 102 interrupt-controller;
103 reg = <0x0 0x1401000 0 103 reg = <0x0 0x1401000 0x0 0x1000>,
104 <0x0 0x1402000 0 104 <0x0 0x1402000 0x0 0x2000>,
105 <0x0 0x1404000 0 105 <0x0 0x1404000 0x0 0x2000>,
106 <0x0 0x1406000 0 106 <0x0 0x1406000 0x0 0x2000>;
107 interrupts = <GIC_PPI 107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 108
109 }; 109 };
110 110
111 msi1: msi-controller@1570e00 { 111 msi1: msi-controller@1570e00 {
112 compatible = "fsl,ls10 112 compatible = "fsl,ls1021a-msi";
113 reg = <0x0 0x1570e00 0 113 reg = <0x0 0x1570e00 0x0 0x8>;
114 msi-controller; 114 msi-controller;
115 interrupts = <GIC_SPI 115 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
116 }; 116 };
117 117
118 msi2: msi-controller@1570e08 { 118 msi2: msi-controller@1570e08 {
119 compatible = "fsl,ls10 119 compatible = "fsl,ls1021a-msi";
120 reg = <0x0 0x1570e08 0 120 reg = <0x0 0x1570e08 0x0 0x8>;
121 msi-controller; 121 msi-controller;
122 interrupts = <GIC_SPI 122 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
123 }; 123 };
124 124
125 ifc: memory-controller@1530000 125 ifc: memory-controller@1530000 {
126 compatible = "fsl,ifc" 126 compatible = "fsl,ifc";
127 reg = <0x0 0x1530000 0 127 reg = <0x0 0x1530000 0x0 0x10000>;
128 interrupts = <GIC_SPI 128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
129 status = "disabled"; 129 status = "disabled";
130 }; 130 };
131 131
132 sfp: efuse@1e80000 { 132 sfp: efuse@1e80000 {
133 compatible = "fsl,ls10 133 compatible = "fsl,ls1021a-sfp";
134 reg = <0x0 0x1e80000 0 134 reg = <0x0 0x1e80000 0x0 0x10000>;
135 clocks = <&clockgen 4 135 clocks = <&clockgen 4 3>;
136 clock-names = "sfp"; 136 clock-names = "sfp";
137 }; 137 };
138 138
139 dcfg: dcfg@1ee0000 { 139 dcfg: dcfg@1ee0000 {
140 compatible = "fsl,ls10 140 compatible = "fsl,ls1021a-dcfg", "syscon";
141 reg = <0x0 0x1ee0000 0 141 reg = <0x0 0x1ee0000 0x0 0x1000>;
142 big-endian; 142 big-endian;
143 }; 143 };
144 144
145 qspi: spi@1550000 { 145 qspi: spi@1550000 {
146 compatible = "fsl,ls10 146 compatible = "fsl,ls1021a-qspi";
147 #address-cells = <1>; 147 #address-cells = <1>;
148 #size-cells = <0>; 148 #size-cells = <0>;
149 reg = <0x0 0x1550000 0 149 reg = <0x0 0x1550000 0x0 0x10000>,
150 <0x0 0x40000000 150 <0x0 0x40000000 0x0 0x20000000>;
151 reg-names = "QuadSPI", 151 reg-names = "QuadSPI", "QuadSPI-memory";
152 interrupts = <GIC_SPI 152 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "qspi_en 153 clock-names = "qspi_en", "qspi";
154 clocks = <&clockgen 4 154 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
155 status = "disabled"; 155 status = "disabled";
156 }; 156 };
157 157
158 esdhc: esdhc@1560000 { 158 esdhc: esdhc@1560000 {
159 compatible = "fsl,ls10 159 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
160 reg = <0x0 0x1560000 0 160 reg = <0x0 0x1560000 0x0 0x10000>;
161 interrupts = <GIC_SPI 161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
162 clock-frequency = <0>; 162 clock-frequency = <0>;
163 voltage-ranges = <1800 163 voltage-ranges = <1800 1800 3300 3300>;
164 sdhci,auto-cmd12; 164 sdhci,auto-cmd12;
165 big-endian; 165 big-endian;
166 bus-width = <4>; 166 bus-width = <4>;
167 status = "disabled"; 167 status = "disabled";
168 }; 168 };
169 169
170 sata: sata@3200000 { 170 sata: sata@3200000 {
171 compatible = "fsl,ls10 171 compatible = "fsl,ls1021a-ahci";
172 reg = <0x0 0x3200000 0 172 reg = <0x0 0x3200000 0x0 0x10000>,
173 <0x0 0x20220520 173 <0x0 0x20220520 0x0 0x4>;
174 reg-names = "ahci", "s 174 reg-names = "ahci", "sata-ecc";
175 interrupts = <GIC_SPI 175 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clockgen 4 176 clocks = <&clockgen 4 1>;
177 dma-coherent; 177 dma-coherent;
178 status = "disabled"; 178 status = "disabled";
179 }; 179 };
180 180
181 scfg: scfg@1570000 { 181 scfg: scfg@1570000 {
182 compatible = "fsl,ls10 182 compatible = "fsl,ls1021a-scfg", "syscon";
183 reg = <0x0 0x1570000 0 183 reg = <0x0 0x1570000 0x0 0x10000>;
184 big-endian; 184 big-endian;
185 #address-cells = <1>; 185 #address-cells = <1>;
186 #size-cells = <1>; 186 #size-cells = <1>;
187 ranges = <0x0 0x0 0x15 187 ranges = <0x0 0x0 0x1570000 0x10000>;
188 188
189 extirq: interrupt-cont 189 extirq: interrupt-controller@1ac {
190 compatible = " 190 compatible = "fsl,ls1021a-extirq";
191 #interrupt-cel 191 #interrupt-cells = <2>;
192 #address-cells 192 #address-cells = <0>;
193 interrupt-cont 193 interrupt-controller;
194 reg = <0x1ac 4 194 reg = <0x1ac 4>;
195 interrupt-map 195 interrupt-map =
196 <0 0 & 196 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
197 <1 0 & 197 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
198 <2 0 & 198 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
199 <3 0 & 199 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
200 <4 0 & 200 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
201 <5 0 & 201 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-map- 202 interrupt-map-mask = <0x7 0x0>;
203 }; 203 };
204 }; 204 };
205 205
206 crypto: crypto@1700000 { 206 crypto: crypto@1700000 {
207 compatible = "fsl,sec- 207 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
208 fsl,sec-era = <7>; 208 fsl,sec-era = <7>;
209 #address-cells = <1>; 209 #address-cells = <1>;
210 #size-cells = <1>; 210 #size-cells = <1>;
211 reg = <0x 211 reg = <0x0 0x1700000 0x0 0x100000>;
212 ranges = <0x 212 ranges = <0x0 0x0 0x1700000 0x100000>;
213 interrupts = <GI 213 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
214 dma-coherent; 214 dma-coherent;
215 215
216 sec_jr0: jr@10000 { 216 sec_jr0: jr@10000 {
217 compatible = " 217 compatible = "fsl,sec-v5.0-job-ring",
218 "fsl,sec- 218 "fsl,sec-v4.0-job-ring";
219 reg = <0x10000 219 reg = <0x10000 0x10000>;
220 interrupts = < 220 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
221 }; 221 };
222 222
223 sec_jr1: jr@20000 { 223 sec_jr1: jr@20000 {
224 compatible = " 224 compatible = "fsl,sec-v5.0-job-ring",
225 "fsl,sec- 225 "fsl,sec-v4.0-job-ring";
226 reg = <0x20000 226 reg = <0x20000 0x10000>;
227 interrupts = < 227 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
228 }; 228 };
229 229
230 sec_jr2: jr@30000 { 230 sec_jr2: jr@30000 {
231 compatible = " 231 compatible = "fsl,sec-v5.0-job-ring",
232 "fsl,sec- 232 "fsl,sec-v4.0-job-ring";
233 reg = <0x30000 233 reg = <0x30000 0x10000>;
234 interrupts = < 234 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
235 }; 235 };
236 236
237 sec_jr3: jr@40000 { 237 sec_jr3: jr@40000 {
238 compatible = " 238 compatible = "fsl,sec-v5.0-job-ring",
239 "fsl,sec- 239 "fsl,sec-v4.0-job-ring";
240 reg = <0x40000 240 reg = <0x40000 0x10000>;
241 interrupts = < 241 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
242 }; 242 };
243 243
244 }; 244 };
245 245
246 clockgen: clocking@1ee1000 { 246 clockgen: clocking@1ee1000 {
247 compatible = "fsl,ls10 247 compatible = "fsl,ls1021a-clockgen";
248 reg = <0x0 0x1ee1000 0 248 reg = <0x0 0x1ee1000 0x0 0x1000>;
249 #clock-cells = <2>; 249 #clock-cells = <2>;
250 clocks = <&sysclk>; 250 clocks = <&sysclk>;
251 }; 251 };
252 252
253 tmu: tmu@1f00000 { 253 tmu: tmu@1f00000 {
254 compatible = "fsl,qori 254 compatible = "fsl,qoriq-tmu";
255 reg = <0x0 0x1f00000 0 255 reg = <0x0 0x1f00000 0x0 0x10000>;
256 interrupts = <GIC_SPI 256 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
257 fsl,tmu-range = <0xb00 257 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
258 fsl,tmu-calibration = 258 fsl,tmu-calibration = <0x00000000 0x00000020>,
259 259 <0x00000001 0x00000024>,
260 260 <0x00000002 0x0000002a>,
261 261 <0x00000003 0x00000032>,
262 262 <0x00000004 0x00000038>,
263 263 <0x00000005 0x0000003e>,
264 264 <0x00000006 0x00000043>,
265 265 <0x00000007 0x0000004a>,
266 266 <0x00000008 0x00000050>,
267 267 <0x00000009 0x00000059>,
268 268 <0x0000000a 0x0000005f>,
269 269 <0x0000000b 0x00000066>,
270 270
271 271 <0x00010000 0x00000023>,
272 272 <0x00010001 0x0000002b>,
273 273 <0x00010002 0x00000033>,
274 274 <0x00010003 0x0000003a>,
275 275 <0x00010004 0x00000042>,
276 276 <0x00010005 0x0000004a>,
277 277 <0x00010006 0x00000054>,
278 278 <0x00010007 0x0000005c>,
279 279 <0x00010008 0x00000065>,
280 280 <0x00010009 0x0000006f>,
281 281
282 282 <0x00020000 0x00000029>,
283 283 <0x00020001 0x00000033>,
284 284 <0x00020002 0x0000003d>,
285 285 <0x00020003 0x00000048>,
286 286 <0x00020004 0x00000054>,
287 287 <0x00020005 0x00000060>,
288 288 <0x00020006 0x0000006c>,
289 289
290 290 <0x00030000 0x00000025>,
291 291 <0x00030001 0x00000033>,
292 292 <0x00030002 0x00000043>,
293 293 <0x00030003 0x00000055>;
294 #thermal-sensor-cells 294 #thermal-sensor-cells = <1>;
295 }; 295 };
296 296
297 dspi0: spi@2100000 { 297 dspi0: spi@2100000 {
298 compatible = "fsl,ls10 298 compatible = "fsl,ls1021a-v1.0-dspi";
299 #address-cells = <1>; 299 #address-cells = <1>;
300 #size-cells = <0>; 300 #size-cells = <0>;
301 reg = <0x0 0x2100000 0 301 reg = <0x0 0x2100000 0x0 0x10000>;
302 interrupts = <GIC_SPI 302 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
303 clock-names = "dspi"; 303 clock-names = "dspi";
304 clocks = <&clockgen 4 304 clocks = <&clockgen 4 1>;
305 spi-num-chipselects = 305 spi-num-chipselects = <6>;
306 big-endian; 306 big-endian;
307 status = "disabled"; 307 status = "disabled";
308 }; 308 };
309 309
310 dspi1: spi@2110000 { 310 dspi1: spi@2110000 {
311 compatible = "fsl,ls10 311 compatible = "fsl,ls1021a-v1.0-dspi";
312 #address-cells = <1>; 312 #address-cells = <1>;
313 #size-cells = <0>; 313 #size-cells = <0>;
314 reg = <0x0 0x2110000 0 314 reg = <0x0 0x2110000 0x0 0x10000>;
315 interrupts = <GIC_SPI 315 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
316 clock-names = "dspi"; 316 clock-names = "dspi";
317 clocks = <&clockgen 4 317 clocks = <&clockgen 4 1>;
318 spi-num-chipselects = 318 spi-num-chipselects = <6>;
319 big-endian; 319 big-endian;
320 status = "disabled"; 320 status = "disabled";
321 }; 321 };
322 322
323 i2c0: i2c@2180000 { 323 i2c0: i2c@2180000 {
324 compatible = "fsl,vf61 324 compatible = "fsl,vf610-i2c";
325 #address-cells = <1>; 325 #address-cells = <1>;
326 #size-cells = <0>; 326 #size-cells = <0>;
327 reg = <0x0 0x2180000 0 327 reg = <0x0 0x2180000 0x0 0x10000>;
328 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clockgen 4 329 clocks = <&clockgen 4 1>;
330 dma-names = "rx", "tx" 330 dma-names = "rx", "tx";
331 dmas = <&edma0 1 38>, 331 dmas = <&edma0 1 38>, <&edma0 1 39>;
332 status = "disabled"; 332 status = "disabled";
333 }; 333 };
334 334
335 i2c1: i2c@2190000 { 335 i2c1: i2c@2190000 {
336 compatible = "fsl,vf61 336 compatible = "fsl,vf610-i2c";
337 #address-cells = <1>; 337 #address-cells = <1>;
338 #size-cells = <0>; 338 #size-cells = <0>;
339 reg = <0x0 0x2190000 0 339 reg = <0x0 0x2190000 0x0 0x10000>;
340 interrupts = <GIC_SPI 340 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clockgen 4 341 clocks = <&clockgen 4 1>;
342 dma-names = "rx", "tx" 342 dma-names = "rx", "tx";
343 dmas = <&edma0 1 36>, 343 dmas = <&edma0 1 36>, <&edma0 1 37>;
344 status = "disabled"; 344 status = "disabled";
345 }; 345 };
346 346
347 i2c2: i2c@21a0000 { 347 i2c2: i2c@21a0000 {
348 compatible = "fsl,vf61 348 compatible = "fsl,vf610-i2c";
349 #address-cells = <1>; 349 #address-cells = <1>;
350 #size-cells = <0>; 350 #size-cells = <0>;
351 reg = <0x0 0x21a0000 0 351 reg = <0x0 0x21a0000 0x0 0x10000>;
352 interrupts = <GIC_SPI 352 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&clockgen 4 353 clocks = <&clockgen 4 1>;
354 dma-names = "rx", "tx" 354 dma-names = "rx", "tx";
355 dmas = <&edma0 1 34>, 355 dmas = <&edma0 1 34>, <&edma0 1 35>;
356 status = "disabled"; 356 status = "disabled";
357 }; 357 };
358 358
359 uart0: serial@21c0500 { 359 uart0: serial@21c0500 {
360 compatible = "fsl,1655 360 compatible = "fsl,16550-FIFO64", "ns16550a";
361 reg = <0x0 0x21c0500 0 361 reg = <0x0 0x21c0500 0x0 0x100>;
362 interrupts = <GIC_SPI 362 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
363 clock-frequency = <0>; 363 clock-frequency = <0>;
364 fifo-size = <15>; 364 fifo-size = <15>;
365 status = "disabled"; 365 status = "disabled";
366 }; 366 };
367 367
368 uart1: serial@21c0600 { 368 uart1: serial@21c0600 {
369 compatible = "fsl,1655 369 compatible = "fsl,16550-FIFO64", "ns16550a";
370 reg = <0x0 0x21c0600 0 370 reg = <0x0 0x21c0600 0x0 0x100>;
371 interrupts = <GIC_SPI 371 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
372 clock-frequency = <0>; 372 clock-frequency = <0>;
373 fifo-size = <15>; 373 fifo-size = <15>;
374 status = "disabled"; 374 status = "disabled";
375 }; 375 };
376 376
377 uart2: serial@21d0500 { 377 uart2: serial@21d0500 {
378 compatible = "fsl,1655 378 compatible = "fsl,16550-FIFO64", "ns16550a";
379 reg = <0x0 0x21d0500 0 379 reg = <0x0 0x21d0500 0x0 0x100>;
380 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
381 clock-frequency = <0>; 381 clock-frequency = <0>;
382 fifo-size = <15>; 382 fifo-size = <15>;
383 status = "disabled"; 383 status = "disabled";
384 }; 384 };
385 385
386 uart3: serial@21d0600 { 386 uart3: serial@21d0600 {
387 compatible = "fsl,1655 387 compatible = "fsl,16550-FIFO64", "ns16550a";
388 reg = <0x0 0x21d0600 0 388 reg = <0x0 0x21d0600 0x0 0x100>;
389 interrupts = <GIC_SPI 389 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
390 clock-frequency = <0>; 390 clock-frequency = <0>;
391 fifo-size = <15>; 391 fifo-size = <15>;
392 status = "disabled"; 392 status = "disabled";
393 }; 393 };
394 394
395 counter0: counter@29d0000 { 395 counter0: counter@29d0000 {
396 compatible = "fsl,ftm- 396 compatible = "fsl,ftm-quaddec";
397 reg = <0x0 0x29d0000 0 397 reg = <0x0 0x29d0000 0x0 0x10000>;
398 big-endian; 398 big-endian;
399 status = "disabled"; 399 status = "disabled";
400 }; 400 };
401 401
402 counter1: counter@29e0000 { 402 counter1: counter@29e0000 {
403 compatible = "fsl,ftm- 403 compatible = "fsl,ftm-quaddec";
404 reg = <0x0 0x29e0000 0 404 reg = <0x0 0x29e0000 0x0 0x10000>;
405 big-endian; 405 big-endian;
406 status = "disabled"; 406 status = "disabled";
407 }; 407 };
408 408
409 counter2: counter@29f0000 { 409 counter2: counter@29f0000 {
410 compatible = "fsl,ftm- 410 compatible = "fsl,ftm-quaddec";
411 reg = <0x0 0x29f0000 0 411 reg = <0x0 0x29f0000 0x0 0x10000>;
412 big-endian; 412 big-endian;
413 status = "disabled"; 413 status = "disabled";
414 }; 414 };
415 415
416 counter3: counter@2a00000 { 416 counter3: counter@2a00000 {
417 compatible = "fsl,ftm- 417 compatible = "fsl,ftm-quaddec";
418 reg = <0x0 0x2a00000 0 418 reg = <0x0 0x2a00000 0x0 0x10000>;
419 big-endian; 419 big-endian;
420 status = "disabled"; 420 status = "disabled";
421 }; 421 };
422 422
423 gpio0: gpio@2300000 { 423 gpio0: gpio@2300000 {
424 compatible = "fsl,ls10 424 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
425 reg = <0x0 0x2300000 0 425 reg = <0x0 0x2300000 0x0 0x10000>;
426 interrupts = <GIC_SPI 426 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
427 gpio-controller; 427 gpio-controller;
428 #gpio-cells = <2>; 428 #gpio-cells = <2>;
429 interrupt-controller; 429 interrupt-controller;
430 #interrupt-cells = <2> 430 #interrupt-cells = <2>;
431 }; 431 };
432 432
433 gpio1: gpio@2310000 { 433 gpio1: gpio@2310000 {
434 compatible = "fsl,ls10 434 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
435 reg = <0x0 0x2310000 0 435 reg = <0x0 0x2310000 0x0 0x10000>;
436 interrupts = <GIC_SPI 436 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
437 gpio-controller; 437 gpio-controller;
438 #gpio-cells = <2>; 438 #gpio-cells = <2>;
439 interrupt-controller; 439 interrupt-controller;
440 #interrupt-cells = <2> 440 #interrupt-cells = <2>;
441 }; 441 };
442 442
443 gpio2: gpio@2320000 { 443 gpio2: gpio@2320000 {
444 compatible = "fsl,ls10 444 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
445 reg = <0x0 0x2320000 0 445 reg = <0x0 0x2320000 0x0 0x10000>;
446 interrupts = <GIC_SPI 446 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
447 gpio-controller; 447 gpio-controller;
448 #gpio-cells = <2>; 448 #gpio-cells = <2>;
449 interrupt-controller; 449 interrupt-controller;
450 #interrupt-cells = <2> 450 #interrupt-cells = <2>;
451 }; 451 };
452 452
453 gpio3: gpio@2330000 { 453 gpio3: gpio@2330000 {
454 compatible = "fsl,ls10 454 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
455 reg = <0x0 0x2330000 0 455 reg = <0x0 0x2330000 0x0 0x10000>;
456 interrupts = <GIC_SPI 456 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller; 457 gpio-controller;
458 #gpio-cells = <2>; 458 #gpio-cells = <2>;
459 interrupt-controller; 459 interrupt-controller;
460 #interrupt-cells = <2> 460 #interrupt-cells = <2>;
461 }; 461 };
462 462
463 lpuart0: serial@2950000 { 463 lpuart0: serial@2950000 {
464 compatible = "fsl,ls10 464 compatible = "fsl,ls1021a-lpuart";
465 reg = <0x0 0x2950000 0 465 reg = <0x0 0x2950000 0x0 0x1000>;
466 interrupts = <GIC_SPI 466 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&sysclk>; 467 clocks = <&sysclk>;
468 clock-names = "ipg"; 468 clock-names = "ipg";
469 status = "disabled"; 469 status = "disabled";
470 }; 470 };
471 471
472 lpuart1: serial@2960000 { 472 lpuart1: serial@2960000 {
473 compatible = "fsl,ls10 473 compatible = "fsl,ls1021a-lpuart";
474 reg = <0x0 0x2960000 0 474 reg = <0x0 0x2960000 0x0 0x1000>;
475 interrupts = <GIC_SPI 475 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clockgen 4 476 clocks = <&clockgen 4 1>;
477 clock-names = "ipg"; 477 clock-names = "ipg";
478 status = "disabled"; 478 status = "disabled";
479 }; 479 };
480 480
481 lpuart2: serial@2970000 { 481 lpuart2: serial@2970000 {
482 compatible = "fsl,ls10 482 compatible = "fsl,ls1021a-lpuart";
483 reg = <0x0 0x2970000 0 483 reg = <0x0 0x2970000 0x0 0x1000>;
484 interrupts = <GIC_SPI 484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clockgen 4 485 clocks = <&clockgen 4 1>;
486 clock-names = "ipg"; 486 clock-names = "ipg";
487 status = "disabled"; 487 status = "disabled";
488 }; 488 };
489 489
490 lpuart3: serial@2980000 { 490 lpuart3: serial@2980000 {
491 compatible = "fsl,ls10 491 compatible = "fsl,ls1021a-lpuart";
492 reg = <0x0 0x2980000 0 492 reg = <0x0 0x2980000 0x0 0x1000>;
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clockgen 4 494 clocks = <&clockgen 4 1>;
495 clock-names = "ipg"; 495 clock-names = "ipg";
496 status = "disabled"; 496 status = "disabled";
497 }; 497 };
498 498
499 lpuart4: serial@2990000 { 499 lpuart4: serial@2990000 {
500 compatible = "fsl,ls10 500 compatible = "fsl,ls1021a-lpuart";
501 reg = <0x0 0x2990000 0 501 reg = <0x0 0x2990000 0x0 0x1000>;
502 interrupts = <GIC_SPI 502 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clockgen 4 503 clocks = <&clockgen 4 1>;
504 clock-names = "ipg"; 504 clock-names = "ipg";
505 status = "disabled"; 505 status = "disabled";
506 }; 506 };
507 507
508 lpuart5: serial@29a0000 { 508 lpuart5: serial@29a0000 {
509 compatible = "fsl,ls10 509 compatible = "fsl,ls1021a-lpuart";
510 reg = <0x0 0x29a0000 0 510 reg = <0x0 0x29a0000 0x0 0x1000>;
511 interrupts = <GIC_SPI 511 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clockgen 4 512 clocks = <&clockgen 4 1>;
513 clock-names = "ipg"; 513 clock-names = "ipg";
514 status = "disabled"; 514 status = "disabled";
515 }; 515 };
516 516
517 pwm0: pwm@29d0000 { 517 pwm0: pwm@29d0000 {
518 compatible = "fsl,vf61 518 compatible = "fsl,vf610-ftm-pwm";
519 #pwm-cells = <3>; 519 #pwm-cells = <3>;
520 reg = <0x0 0x29d0000 0 520 reg = <0x0 0x29d0000 0x0 0x10000>;
521 clock-names = "ftm_sys 521 clock-names = "ftm_sys", "ftm_ext",
522 "ftm_fix", "ft 522 "ftm_fix", "ftm_cnt_clk_en";
523 clocks = <&clockgen 4 523 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
524 <&clockgen 4 1 524 <&clockgen 4 1>, <&clockgen 4 1>;
525 big-endian; 525 big-endian;
526 status = "disabled"; 526 status = "disabled";
527 }; 527 };
528 528
529 pwm1: pwm@29e0000 { 529 pwm1: pwm@29e0000 {
530 compatible = "fsl,vf61 530 compatible = "fsl,vf610-ftm-pwm";
531 #pwm-cells = <3>; 531 #pwm-cells = <3>;
532 reg = <0x0 0x29e0000 0 532 reg = <0x0 0x29e0000 0x0 0x10000>;
533 clock-names = "ftm_sys 533 clock-names = "ftm_sys", "ftm_ext",
534 "ftm_fix", "ft 534 "ftm_fix", "ftm_cnt_clk_en";
535 clocks = <&clockgen 4 535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
536 <&clockgen 4 1 536 <&clockgen 4 1>, <&clockgen 4 1>;
537 big-endian; 537 big-endian;
538 status = "disabled"; 538 status = "disabled";
539 }; 539 };
540 540
541 pwm2: pwm@29f0000 { 541 pwm2: pwm@29f0000 {
542 compatible = "fsl,vf61 542 compatible = "fsl,vf610-ftm-pwm";
543 #pwm-cells = <3>; 543 #pwm-cells = <3>;
544 reg = <0x0 0x29f0000 0 544 reg = <0x0 0x29f0000 0x0 0x10000>;
545 clock-names = "ftm_sys 545 clock-names = "ftm_sys", "ftm_ext",
546 "ftm_fix", "ft 546 "ftm_fix", "ftm_cnt_clk_en";
547 clocks = <&clockgen 4 547 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
548 <&clockgen 4 1 548 <&clockgen 4 1>, <&clockgen 4 1>;
549 big-endian; 549 big-endian;
550 status = "disabled"; 550 status = "disabled";
551 }; 551 };
552 552
553 pwm3: pwm@2a00000 { 553 pwm3: pwm@2a00000 {
554 compatible = "fsl,vf61 554 compatible = "fsl,vf610-ftm-pwm";
555 #pwm-cells = <3>; 555 #pwm-cells = <3>;
556 reg = <0x0 0x2a00000 0 556 reg = <0x0 0x2a00000 0x0 0x10000>;
557 clock-names = "ftm_sys 557 clock-names = "ftm_sys", "ftm_ext",
558 "ftm_fix", "ft 558 "ftm_fix", "ftm_cnt_clk_en";
559 clocks = <&clockgen 4 559 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
560 <&clockgen 4 1 560 <&clockgen 4 1>, <&clockgen 4 1>;
561 big-endian; 561 big-endian;
562 status = "disabled"; 562 status = "disabled";
563 }; 563 };
564 564
565 pwm4: pwm@2a10000 { 565 pwm4: pwm@2a10000 {
566 compatible = "fsl,vf61 566 compatible = "fsl,vf610-ftm-pwm";
567 #pwm-cells = <3>; 567 #pwm-cells = <3>;
568 reg = <0x0 0x2a10000 0 568 reg = <0x0 0x2a10000 0x0 0x10000>;
569 clock-names = "ftm_sys 569 clock-names = "ftm_sys", "ftm_ext",
570 "ftm_fix", "ft 570 "ftm_fix", "ftm_cnt_clk_en";
571 clocks = <&clockgen 4 571 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
572 <&clockgen 4 1 572 <&clockgen 4 1>, <&clockgen 4 1>;
573 big-endian; 573 big-endian;
574 status = "disabled"; 574 status = "disabled";
575 }; 575 };
576 576
577 pwm5: pwm@2a20000 { 577 pwm5: pwm@2a20000 {
578 compatible = "fsl,vf61 578 compatible = "fsl,vf610-ftm-pwm";
579 #pwm-cells = <3>; 579 #pwm-cells = <3>;
580 reg = <0x0 0x2a20000 0 580 reg = <0x0 0x2a20000 0x0 0x10000>;
581 clock-names = "ftm_sys 581 clock-names = "ftm_sys", "ftm_ext",
582 "ftm_fix", "ft 582 "ftm_fix", "ftm_cnt_clk_en";
583 clocks = <&clockgen 4 583 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
584 <&clockgen 4 1 584 <&clockgen 4 1>, <&clockgen 4 1>;
585 big-endian; 585 big-endian;
586 status = "disabled"; 586 status = "disabled";
587 }; 587 };
588 588
589 pwm6: pwm@2a30000 { 589 pwm6: pwm@2a30000 {
590 compatible = "fsl,vf61 590 compatible = "fsl,vf610-ftm-pwm";
591 #pwm-cells = <3>; 591 #pwm-cells = <3>;
592 reg = <0x0 0x2a30000 0 592 reg = <0x0 0x2a30000 0x0 0x10000>;
593 clock-names = "ftm_sys 593 clock-names = "ftm_sys", "ftm_ext",
594 "ftm_fix", "ft 594 "ftm_fix", "ftm_cnt_clk_en";
595 clocks = <&clockgen 4 595 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
596 <&clockgen 4 1 596 <&clockgen 4 1>, <&clockgen 4 1>;
597 big-endian; 597 big-endian;
598 status = "disabled"; 598 status = "disabled";
599 }; 599 };
600 600
601 pwm7: pwm@2a40000 { 601 pwm7: pwm@2a40000 {
602 compatible = "fsl,vf61 602 compatible = "fsl,vf610-ftm-pwm";
603 #pwm-cells = <3>; 603 #pwm-cells = <3>;
604 reg = <0x0 0x2a40000 0 604 reg = <0x0 0x2a40000 0x0 0x10000>;
605 clock-names = "ftm_sys 605 clock-names = "ftm_sys", "ftm_ext",
606 "ftm_fix", "ft 606 "ftm_fix", "ftm_cnt_clk_en";
607 clocks = <&clockgen 4 607 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
608 <&clockgen 4 1 608 <&clockgen 4 1>, <&clockgen 4 1>;
609 big-endian; 609 big-endian;
610 status = "disabled"; 610 status = "disabled";
611 }; 611 };
612 612
613 wdog0: watchdog@2ad0000 { 613 wdog0: watchdog@2ad0000 {
614 compatible = "fsl,imx2 614 compatible = "fsl,imx21-wdt";
615 reg = <0x0 0x2ad0000 0 615 reg = <0x0 0x2ad0000 0x0 0x10000>;
616 interrupts = <GIC_SPI 616 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clockgen 4 617 clocks = <&clockgen 4 1>;
618 clock-names = "wdog-en 618 clock-names = "wdog-en";
619 big-endian; 619 big-endian;
620 }; 620 };
621 621
622 sai1: sai@2b50000 { 622 sai1: sai@2b50000 {
623 #sound-dai-cells = <0> 623 #sound-dai-cells = <0>;
624 compatible = "fsl,vf61 624 compatible = "fsl,vf610-sai";
625 reg = <0x0 0x2b50000 0 625 reg = <0x0 0x2b50000 0x0 0x10000>;
626 interrupts = <GIC_SPI 626 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clockgen 4 627 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
628 <&clockgen 4 628 <&clockgen 4 1>, <&clockgen 4 1>;
629 clock-names = "bus", " 629 clock-names = "bus", "mclk1", "mclk2", "mclk3";
630 dma-names = "tx", "rx" 630 dma-names = "tx", "rx";
631 dmas = <&edma0 1 47>, 631 dmas = <&edma0 1 47>,
632 <&edma0 1 46>; 632 <&edma0 1 46>;
633 status = "disabled"; 633 status = "disabled";
634 }; 634 };
635 635
636 sai2: sai@2b60000 { 636 sai2: sai@2b60000 {
637 #sound-dai-cells = <0> 637 #sound-dai-cells = <0>;
638 compatible = "fsl,vf61 638 compatible = "fsl,vf610-sai";
639 reg = <0x0 0x2b60000 0 639 reg = <0x0 0x2b60000 0x0 0x10000>;
640 interrupts = <GIC_SPI 640 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clockgen 4 641 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
642 <&clockgen 4 642 <&clockgen 4 1>, <&clockgen 4 1>;
643 clock-names = "bus", " 643 clock-names = "bus", "mclk1", "mclk2", "mclk3";
644 dma-names = "tx", "rx" 644 dma-names = "tx", "rx";
645 dmas = <&edma0 1 45>, 645 dmas = <&edma0 1 45>,
646 <&edma0 1 44>; 646 <&edma0 1 44>;
647 status = "disabled"; 647 status = "disabled";
648 }; 648 };
649 649
650 edma0: dma-controller@2c00000 650 edma0: dma-controller@2c00000 {
651 #dma-cells = <2>; 651 #dma-cells = <2>;
652 compatible = "fsl,vf61 652 compatible = "fsl,vf610-edma";
653 reg = <0x0 0x2c00000 0 653 reg = <0x0 0x2c00000 0x0 0x10000>,
654 <0x0 0x2c10000 0 654 <0x0 0x2c10000 0x0 0x10000>,
655 <0x0 0x2c20000 0 655 <0x0 0x2c20000 0x0 0x10000>;
656 interrupts = <GIC_SPI 656 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 657 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-names = "edm 658 interrupt-names = "edma-tx", "edma-err";
659 dma-channels = <32>; 659 dma-channels = <32>;
660 big-endian; 660 big-endian;
661 clock-names = "dmamux0 661 clock-names = "dmamux0", "dmamux1";
662 clocks = <&clockgen 4 662 clocks = <&clockgen 4 1>,
663 <&clockgen 4 663 <&clockgen 4 1>;
664 }; 664 };
665 665
666 dcu: dcu@2ce0000 { 666 dcu: dcu@2ce0000 {
667 compatible = "fsl,ls10 667 compatible = "fsl,ls1021a-dcu";
668 reg = <0x0 0x2ce0000 0 668 reg = <0x0 0x2ce0000 0x0 0x10000>;
669 interrupts = <GIC_SPI 669 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clockgen 4 670 clocks = <&clockgen 4 0>,
671 <&clockgen 4 0 671 <&clockgen 4 0>;
672 clock-names = "dcu", " 672 clock-names = "dcu", "pix";
673 big-endian; 673 big-endian;
674 status = "disabled"; 674 status = "disabled";
675 }; 675 };
676 676
677 mdio0: mdio@2d24000 { 677 mdio0: mdio@2d24000 {
678 compatible = "gianfar" 678 compatible = "gianfar";
679 device_type = "mdio"; 679 device_type = "mdio";
680 #address-cells = <1>; 680 #address-cells = <1>;
681 #size-cells = <0>; 681 #size-cells = <0>;
682 reg = <0x0 0x2d24000 0 682 reg = <0x0 0x2d24000 0x0 0x4000>,
683 <0x0 0x2d10030 0 683 <0x0 0x2d10030 0x0 0x4>;
684 }; 684 };
685 685
686 mdio1: mdio@2d64000 { 686 mdio1: mdio@2d64000 {
687 compatible = "gianfar" 687 compatible = "gianfar";
688 device_type = "mdio"; 688 device_type = "mdio";
689 #address-cells = <1>; 689 #address-cells = <1>;
690 #size-cells = <0>; 690 #size-cells = <0>;
691 reg = <0x0 0x2d64000 0 691 reg = <0x0 0x2d64000 0x0 0x4000>,
692 <0x0 0x2d50030 0 692 <0x0 0x2d50030 0x0 0x4>;
693 }; 693 };
694 694
695 ptp_clock@2d10e00 { 695 ptp_clock@2d10e00 {
696 compatible = "fsl,etse 696 compatible = "fsl,etsec-ptp";
697 reg = <0x0 0x2d10e00 0 697 reg = <0x0 0x2d10e00 0x0 0xb0>;
698 interrupts = <GIC_SPI 698 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
699 fsl,tclk-period = <5>; 699 fsl,tclk-period = <5>;
700 fsl,tmr-prsc = <2>; 700 fsl,tmr-prsc = <2>;
701 fsl,tmr-add = <0xa 701 fsl,tmr-add = <0xaaaaaaab>;
702 fsl,tmr-fiper1 = <999 702 fsl,tmr-fiper1 = <999999995>;
703 fsl,tmr-fiper2 = <999 703 fsl,tmr-fiper2 = <999999995>;
704 fsl,max-adj = <499 704 fsl,max-adj = <499999999>;
705 fsl,extts-fifo; 705 fsl,extts-fifo;
706 }; 706 };
707 707
708 enet0: ethernet@2d10000 { 708 enet0: ethernet@2d10000 {
709 compatible = "fsl,etse 709 compatible = "fsl,etsec2";
710 device_type = "network 710 device_type = "network";
711 #address-cells = <2>; 711 #address-cells = <2>;
712 #size-cells = <2>; 712 #size-cells = <2>;
713 interrupt-parent = <&g 713 interrupt-parent = <&gic>;
714 model = "eTSEC"; 714 model = "eTSEC";
715 fsl,magic-packet; 715 fsl,magic-packet;
716 ranges; 716 ranges;
717 dma-coherent; 717 dma-coherent;
718 718
719 queue-group@2d10000 { 719 queue-group@2d10000 {
720 #address-cells 720 #address-cells = <2>;
721 #size-cells = 721 #size-cells = <2>;
722 reg = <0x0 0x2 722 reg = <0x0 0x2d10000 0x0 0x1000>;
723 interrupts = < 723 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_S 724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_S 725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
726 }; 726 };
727 727
728 queue-group@2d14000 { 728 queue-group@2d14000 {
729 #address-cells 729 #address-cells = <2>;
730 #size-cells = 730 #size-cells = <2>;
731 reg = <0x0 0x2 731 reg = <0x0 0x2d14000 0x0 0x1000>;
732 interrupts = < 732 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_S 733 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_S 734 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
735 }; 735 };
736 }; 736 };
737 737
738 enet1: ethernet@2d50000 { 738 enet1: ethernet@2d50000 {
739 compatible = "fsl,etse 739 compatible = "fsl,etsec2";
740 device_type = "network 740 device_type = "network";
741 #address-cells = <2>; 741 #address-cells = <2>;
742 #size-cells = <2>; 742 #size-cells = <2>;
743 interrupt-parent = <&g 743 interrupt-parent = <&gic>;
744 model = "eTSEC"; 744 model = "eTSEC";
745 ranges; 745 ranges;
746 dma-coherent; 746 dma-coherent;
747 747
748 queue-group@2d50000 { 748 queue-group@2d50000 {
749 #address-cells 749 #address-cells = <2>;
750 #size-cells = 750 #size-cells = <2>;
751 reg = <0x0 0x2 751 reg = <0x0 0x2d50000 0x0 0x1000>;
752 interrupts = < 752 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_S 753 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_S 754 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
755 }; 755 };
756 756
757 queue-group@2d54000 { 757 queue-group@2d54000 {
758 #address-cells 758 #address-cells = <2>;
759 #size-cells = 759 #size-cells = <2>;
760 reg = <0x0 0x2 760 reg = <0x0 0x2d54000 0x0 0x1000>;
761 interrupts = < 761 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_S 762 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_S 763 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
764 }; 764 };
765 }; 765 };
766 766
767 enet2: ethernet@2d90000 { 767 enet2: ethernet@2d90000 {
768 compatible = "fsl,etse 768 compatible = "fsl,etsec2";
769 device_type = "network 769 device_type = "network";
770 #address-cells = <2>; 770 #address-cells = <2>;
771 #size-cells = <2>; 771 #size-cells = <2>;
772 interrupt-parent = <&g 772 interrupt-parent = <&gic>;
773 model = "eTSEC"; 773 model = "eTSEC";
774 ranges; 774 ranges;
775 dma-coherent; 775 dma-coherent;
776 776
777 queue-group@2d90000 { 777 queue-group@2d90000 {
778 #address-cells 778 #address-cells = <2>;
779 #size-cells = 779 #size-cells = <2>;
780 reg = <0x0 0x2 780 reg = <0x0 0x2d90000 0x0 0x1000>;
781 interrupts = < 781 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_S 782 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_S 783 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
784 }; 784 };
785 785
786 queue-group@2d94000 { 786 queue-group@2d94000 {
787 #address-cells 787 #address-cells = <2>;
788 #size-cells = 788 #size-cells = <2>;
789 reg = <0x0 0x2 789 reg = <0x0 0x2d94000 0x0 0x1000>;
790 interrupts = < 790 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_S 791 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_S 792 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
793 }; 793 };
794 }; 794 };
795 795
796 usb2: usb@8600000 { 796 usb2: usb@8600000 {
797 compatible = "fsl-usb2 797 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
798 reg = <0x0 0x8600000 0 798 reg = <0x0 0x8600000 0x0 0x1000>;
799 interrupts = <GIC_SPI 799 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
800 dr_mode = "host"; 800 dr_mode = "host";
801 phy_type = "ulpi"; 801 phy_type = "ulpi";
802 }; 802 };
803 803
804 usb3: usb@3100000 { 804 usb3: usb@3100000 {
805 compatible = "snps,dwc 805 compatible = "snps,dwc3";
806 reg = <0x0 0x3100000 0 806 reg = <0x0 0x3100000 0x0 0x10000>;
807 interrupts = <GIC_SPI 807 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
808 dr_mode = "host"; 808 dr_mode = "host";
809 snps,quirk-frame-lengt 809 snps,quirk-frame-length-adjustment = <0x20>;
810 snps,dis_rxdet_inp3_qu 810 snps,dis_rxdet_inp3_quirk;
811 usb3-lpm-capable; 811 usb3-lpm-capable;
812 snps,incr-burst-type-a 812 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
813 snps,host-vbus-glitche 813 snps,host-vbus-glitches;
814 }; 814 };
815 815
816 pcie@3400000 { 816 pcie@3400000 {
817 compatible = "fsl,ls10 817 compatible = "fsl,ls1021a-pcie";
818 reg = <0x00 0x03400000 818 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
819 <0x40 0x00000000 819 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
820 reg-names = "regs", "c 820 reg-names = "regs", "config";
821 interrupts = <GIC_SPI 821 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
822 fsl,pcie-scfg = <&scfg 822 fsl,pcie-scfg = <&scfg 0>;
823 #address-cells = <3>; 823 #address-cells = <3>;
824 #size-cells = <2>; 824 #size-cells = <2>;
825 device_type = "pci"; 825 device_type = "pci";
826 num-viewport = <6>; 826 num-viewport = <6>;
827 bus-range = <0x0 0xff> 827 bus-range = <0x0 0xff>;
828 ranges = <0x81000000 0 828 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
829 <0x82000000 0 829 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
830 msi-parent = <&msi1>, 830 msi-parent = <&msi1>, <&msi2>;
831 #interrupt-cells = <1> 831 #interrupt-cells = <1>;
832 interrupt-map-mask = < 832 interrupt-map-mask = <0 0 0 7>;
833 interrupt-map = <0000 833 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
834 <0000 834 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
835 <0000 835 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
836 <0000 836 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
837 status = "disabled"; 837 status = "disabled";
838 }; 838 };
839 839
840 pcie@3500000 { 840 pcie@3500000 {
841 compatible = "fsl,ls10 841 compatible = "fsl,ls1021a-pcie";
842 reg = <0x00 0x03500000 842 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
843 <0x48 0x00000000 843 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
844 reg-names = "regs", "c 844 reg-names = "regs", "config";
845 interrupts = <GIC_SPI 845 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
846 fsl,pcie-scfg = <&scfg 846 fsl,pcie-scfg = <&scfg 1>;
847 #address-cells = <3>; 847 #address-cells = <3>;
848 #size-cells = <2>; 848 #size-cells = <2>;
849 device_type = "pci"; 849 device_type = "pci";
850 num-viewport = <6>; 850 num-viewport = <6>;
851 bus-range = <0x0 0xff> 851 bus-range = <0x0 0xff>;
852 ranges = <0x81000000 0 852 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
853 <0x82000000 0 853 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
854 msi-parent = <&msi1>, 854 msi-parent = <&msi1>, <&msi2>;
855 #interrupt-cells = <1> 855 #interrupt-cells = <1>;
856 interrupt-map-mask = < 856 interrupt-map-mask = <0 0 0 7>;
857 interrupt-map = <0000 857 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
858 <0000 858 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
859 <0000 859 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
860 <0000 860 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
861 status = "disabled"; 861 status = "disabled";
862 }; 862 };
863 863
864 can0: can@2a70000 { 864 can0: can@2a70000 {
865 compatible = "fsl,ls10 865 compatible = "fsl,ls1021ar2-flexcan";
866 reg = <0x0 0x2a70000 0 866 reg = <0x0 0x2a70000 0x0 0x1000>;
867 interrupts = <GIC_SPI 867 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&clockgen 4 868 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
869 clock-names = "ipg", " 869 clock-names = "ipg", "per";
870 big-endian; 870 big-endian;
871 status = "disabled"; 871 status = "disabled";
872 }; 872 };
873 873
874 can1: can@2a80000 { 874 can1: can@2a80000 {
875 compatible = "fsl,ls10 875 compatible = "fsl,ls1021ar2-flexcan";
876 reg = <0x0 0x2a80000 0 876 reg = <0x0 0x2a80000 0x0 0x1000>;
877 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&clockgen 4 878 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
879 clock-names = "ipg", " 879 clock-names = "ipg", "per";
880 big-endian; 880 big-endian;
881 status = "disabled"; 881 status = "disabled";
882 }; 882 };
883 883
884 can2: can@2a90000 { 884 can2: can@2a90000 {
885 compatible = "fsl,ls10 885 compatible = "fsl,ls1021ar2-flexcan";
886 reg = <0x0 0x2a90000 0 886 reg = <0x0 0x2a90000 0x0 0x1000>;
887 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clockgen 4 888 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
889 clock-names = "ipg", " 889 clock-names = "ipg", "per";
890 big-endian; 890 big-endian;
891 status = "disabled"; 891 status = "disabled";
892 }; 892 };
893 893
894 can3: can@2aa0000 { 894 can3: can@2aa0000 {
895 compatible = "fsl,ls10 895 compatible = "fsl,ls1021ar2-flexcan";
896 reg = <0x0 0x2aa0000 0 896 reg = <0x0 0x2aa0000 0x0 0x1000>;
897 interrupts = <GIC_SPI 897 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clockgen 4 898 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
899 clock-names = "ipg", " 899 clock-names = "ipg", "per";
900 big-endian; 900 big-endian;
901 status = "disabled"; 901 status = "disabled";
902 }; 902 };
903 903
904 ocram1: sram@10000000 { 904 ocram1: sram@10000000 {
905 compatible = "mmio-sra 905 compatible = "mmio-sram";
906 reg = <0x0 0x10000000 906 reg = <0x0 0x10000000 0x0 0x10000>;
907 #address-cells = <1>; 907 #address-cells = <1>;
908 #size-cells = <1>; 908 #size-cells = <1>;
909 ranges = <0x0 0x0 0x10 909 ranges = <0x0 0x0 0x10000000 0x10000>;
910 }; 910 };
911 911
912 ocram2: sram@10010000 { 912 ocram2: sram@10010000 {
913 compatible = "mmio-sra 913 compatible = "mmio-sram";
914 reg = <0x0 0x10010000 914 reg = <0x0 0x10010000 0x0 0x10000>;
915 #address-cells = <1>; 915 #address-cells = <1>;
916 #size-cells = <1>; 916 #size-cells = <1>;
917 ranges = <0x0 0x0 0x10 917 ranges = <0x0 0x0 0x10010000 0x10000>;
918 }; 918 };
919 919
920 qdma: dma-controller@8390000 { 920 qdma: dma-controller@8390000 {
921 compatible = "fsl,ls10 921 compatible = "fsl,ls1021a-qdma";
922 reg = <0x0 0x8388000 0 922 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
923 <0x0 0x8389000 0 923 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
924 <0x0 0x838a000 0 924 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
925 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 926 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 927 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
928 interrupt-names = "qdm 928 interrupt-names = "qdma-error",
929 "qdma-queue0", 929 "qdma-queue0", "qdma-queue1";
930 #dma-cells = <2>; 930 #dma-cells = <2>;
931 dma-channels = <8>; 931 dma-channels = <8>;
932 block-number = <1>; 932 block-number = <1>;
933 block-offset = <0x1000 933 block-offset = <0x1000>;
934 fsl,dma-queues = <2>; 934 fsl,dma-queues = <2>;
935 status-sizes = <64>; 935 status-sizes = <64>;
936 queue-sizes = <64 64>; 936 queue-sizes = <64 64>;
937 big-endian; 937 big-endian;
938 }; 938 };
939 939
940 rcpm: power-controller@1ee2140 940 rcpm: power-controller@1ee2140 {
941 compatible = "fsl,ls10 941 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
942 reg = <0x0 0x1ee2140 0 942 reg = <0x0 0x1ee2140 0x0 0x8>;
943 #fsl,rcpm-wakeup-cells 943 #fsl,rcpm-wakeup-cells = <2>;
944 #power-domain-cells = 944 #power-domain-cells = <0>;
945 }; 945 };
946 946
947 ftm_alarm0: timer0@29d0000 { 947 ftm_alarm0: timer0@29d0000 {
948 compatible = "fsl,ls10 948 compatible = "fsl,ls1021a-ftm-alarm";
949 reg = <0x0 0x29d0000 0 949 reg = <0x0 0x29d0000 0x0 0x10000>;
950 reg-names = "ftm"; 950 reg-names = "ftm";
951 fsl,rcpm-wakeup = <&rc 951 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
952 interrupts = <GIC_SPI 952 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
953 big-endian; 953 big-endian;
954 }; 954 };
955 }; 955 };
956 956
957 thermal-zones { 957 thermal-zones {
958 cpu_thermal: cpu-thermal { 958 cpu_thermal: cpu-thermal {
959 polling-delay-passive 959 polling-delay-passive = <1000>;
960 polling-delay = <5000> 960 polling-delay = <5000>;
961 961
962 thermal-sensors = <&tm 962 thermal-sensors = <&tmu 0>;
963 963
964 trips { 964 trips {
965 cpu_alert: cpu 965 cpu_alert: cpu-alert {
966 temper 966 temperature = <85000>;
967 hyster 967 hysteresis = <2000>;
968 type = 968 type = "passive";
969 }; 969 };
970 cpu_crit: cpu- 970 cpu_crit: cpu-crit {
971 temper 971 temperature = <95000>;
972 hyster 972 hysteresis = <2000>;
973 type = 973 type = "critical";
974 }; 974 };
975 }; 975 };
976 976
977 cooling-maps { 977 cooling-maps {
978 map0 { 978 map0 {
979 trip = 979 trip = <&cpu_alert>;
980 coolin 980 cooling-device =
981 981 <&cpu0 THERMAL_NO_LIMIT
982 982 THERMAL_NO_LIMIT>,
983 983 <&cpu1 THERMAL_NO_LIMIT
984 984 THERMAL_NO_LIMIT>;
985 }; 985 };
986 }; 986 };
987 }; 987 };
988 }; 988 };
989 }; 989 };
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