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Linux/scripts/dtc/include-prefixes/arm/qcom/qcom-apq8064.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm/qcom/qcom-apq8064.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm/qcom/qcom-apq8064.dtsi (Version linux-4.20.17)


  1 // SPDX-License-Identifier: GPL-2.0               
  2 /dts-v1/;                                         
  3                                                   
  4 #include <dt-bindings/clock/qcom,gcc-msm8960.h    
  5 #include <dt-bindings/clock/qcom,lcc-msm8960.h    
  6 #include <dt-bindings/reset/qcom,gcc-msm8960.h    
  7 #include <dt-bindings/clock/qcom,mmcc-msm8960.    
  8 #include <dt-bindings/clock/qcom,rpmcc.h>         
  9 #include <dt-bindings/soc/qcom,gsbi.h>            
 10 #include <dt-bindings/interrupt-controller/irq    
 11 #include <dt-bindings/interrupt-controller/arm    
 12 / {                                               
 13         #address-cells = <1>;                     
 14         #size-cells = <1>;                        
 15         model = "Qualcomm APQ8064";               
 16         compatible = "qcom,apq8064";              
 17         interrupt-parent = <&intc>;               
 18                                                   
 19         reserved-memory {                         
 20                 #address-cells = <1>;             
 21                 #size-cells = <1>;                
 22                 ranges;                           
 23                                                   
 24                 smem_region: smem@80000000 {      
 25                         reg = <0x80000000 0x20    
 26                         no-map;                   
 27                 };                                
 28                                                   
 29                 wcnss_mem: wcnss@8f000000 {       
 30                         reg = <0x8f000000 0x70    
 31                         no-map;                   
 32                 };                                
 33         };                                        
 34                                                   
 35         cpus {                                    
 36                 #address-cells = <1>;             
 37                 #size-cells = <0>;                
 38                                                   
 39                 CPU0: cpu@0 {                     
 40                         compatible = "qcom,kra    
 41                         enable-method = "qcom,    
 42                         device_type = "cpu";      
 43                         reg = <0>;                
 44                         next-level-cache = <&L    
 45                         qcom,acc = <&acc0>;       
 46                         qcom,saw = <&saw0>;       
 47                         cpu-idle-states = <&CP    
 48                 };                                
 49                                                   
 50                 CPU1: cpu@1 {                     
 51                         compatible = "qcom,kra    
 52                         enable-method = "qcom,    
 53                         device_type = "cpu";      
 54                         reg = <1>;                
 55                         next-level-cache = <&L    
 56                         qcom,acc = <&acc1>;       
 57                         qcom,saw = <&saw1>;       
 58                         cpu-idle-states = <&CP    
 59                 };                                
 60                                                   
 61                 CPU2: cpu@2 {                     
 62                         compatible = "qcom,kra    
 63                         enable-method = "qcom,    
 64                         device_type = "cpu";      
 65                         reg = <2>;                
 66                         next-level-cache = <&L    
 67                         qcom,acc = <&acc2>;       
 68                         qcom,saw = <&saw2>;       
 69                         cpu-idle-states = <&CP    
 70                 };                                
 71                                                   
 72                 CPU3: cpu@3 {                     
 73                         compatible = "qcom,kra    
 74                         enable-method = "qcom,    
 75                         device_type = "cpu";      
 76                         reg = <3>;                
 77                         next-level-cache = <&L    
 78                         qcom,acc = <&acc3>;       
 79                         qcom,saw = <&saw3>;       
 80                         cpu-idle-states = <&CP    
 81                 };                                
 82                                                   
 83                 L2: l2-cache {                    
 84                         compatible = "cache";     
 85                         cache-level = <2>;        
 86                         cache-unified;            
 87                 };                                
 88                                                   
 89                 idle-states {                     
 90                         CPU_SPC: cpu-spc {        
 91                                 compatible = "    
 92                                                   
 93                                 entry-latency-    
 94                                 exit-latency-u    
 95                                 min-residency-    
 96                         };                        
 97                 };                                
 98         };                                        
 99                                                   
100         memory@0 {                                
101                 device_type = "memory";           
102                 reg = <0x0 0x0>;                  
103         };                                        
104                                                   
105         thermal-zones {                           
106                 cpu0-thermal {                    
107                         polling-delay-passive     
108                         polling-delay = <1000>    
109                                                   
110                         thermal-sensors = <&ts    
111                         coefficients = <1199 0    
112                                                   
113                         trips {                   
114                                 cpu_alert0: tr    
115                                         temper    
116                                         hyster    
117                                         type =    
118                                 };                
119                                 cpu_crit0: tri    
120                                         temper    
121                                         hyster    
122                                         type =    
123                                 };                
124                         };                        
125                 };                                
126                                                   
127                 cpu1-thermal {                    
128                         polling-delay-passive     
129                         polling-delay = <1000>    
130                                                   
131                         thermal-sensors = <&ts    
132                         coefficients = <1132 0    
133                                                   
134                         trips {                   
135                                 cpu_alert1: tr    
136                                         temper    
137                                         hyster    
138                                         type =    
139                                 };                
140                                 cpu_crit1: tri    
141                                         temper    
142                                         hyster    
143                                         type =    
144                                 };                
145                         };                        
146                 };                                
147                                                   
148                 cpu2-thermal {                    
149                         polling-delay-passive     
150                         polling-delay = <1000>    
151                                                   
152                         thermal-sensors = <&ts    
153                         coefficients = <1199 0    
154                                                   
155                         trips {                   
156                                 cpu_alert2: tr    
157                                         temper    
158                                         hyster    
159                                         type =    
160                                 };                
161                                 cpu_crit2: tri    
162                                         temper    
163                                         hyster    
164                                         type =    
165                                 };                
166                         };                        
167                 };                                
168                                                   
169                 cpu3-thermal {                    
170                         polling-delay-passive     
171                         polling-delay = <1000>    
172                                                   
173                         thermal-sensors = <&ts    
174                         coefficients = <1132 0    
175                                                   
176                         trips {                   
177                                 cpu_alert3: tr    
178                                         temper    
179                                         hyster    
180                                         type =    
181                                 };                
182                                 cpu_crit3: tri    
183                                         temper    
184                                         hyster    
185                                         type =    
186                                 };                
187                         };                        
188                 };                                
189         };                                        
190                                                   
191         cpu-pmu {                                 
192                 compatible = "qcom,krait-pmu";    
193                 interrupts = <GIC_PPI 10 (GIC_    
194         };                                        
195                                                   
196         clocks {                                  
197                 cxo_board: cxo_board {            
198                         compatible = "fixed-cl    
199                         #clock-cells = <0>;       
200                         clock-frequency = <192    
201                 };                                
202                                                   
203                 pxo_board: pxo_board {            
204                         compatible = "fixed-cl    
205                         #clock-cells = <0>;       
206                         clock-frequency = <270    
207                 };                                
208                                                   
209                 sleep_clk: sleep_clk {            
210                         compatible = "fixed-cl    
211                         #clock-cells = <0>;       
212                         clock-frequency = <327    
213                 };                                
214         };                                        
215                                                   
216         sfpb_mutex: hwmutex {                     
217                 compatible = "qcom,sfpb-mutex"    
218                 syscon = <&sfpb_wrapper_mutex     
219                 #hwlock-cells = <1>;              
220         };                                        
221                                                   
222         smem {                                    
223                 compatible = "qcom,smem";         
224                 memory-region = <&smem_region>    
225                                                   
226                 hwlocks = <&sfpb_mutex 3>;        
227         };                                        
228                                                   
229         smsm {                                    
230                 compatible = "qcom,smsm";         
231                                                   
232                 #address-cells = <1>;             
233                 #size-cells = <0>;                
234                                                   
235                 qcom,ipc-1 = <&l2cc 8 4>;         
236                 qcom,ipc-2 = <&l2cc 8 14>;        
237                 qcom,ipc-3 = <&l2cc 8 23>;        
238                 qcom,ipc-4 = <&sps_sic_non_sec    
239                                                   
240                 apps_smsm: apps@0 {               
241                         reg = <0>;                
242                         #qcom,smem-state-cells    
243                 };                                
244                                                   
245                 modem_smsm: modem@1 {             
246                         reg = <1>;                
247                         interrupts = <GIC_SPI     
248                                                   
249                         interrupt-controller;     
250                         #interrupt-cells = <2>    
251                 };                                
252                                                   
253                 q6_smsm: q6@2 {                   
254                         reg = <2>;                
255                         interrupts = <GIC_SPI     
256                                                   
257                         interrupt-controller;     
258                         #interrupt-cells = <2>    
259                 };                                
260                                                   
261                 wcnss_smsm: wcnss@3 {             
262                         reg = <3>;                
263                         interrupts = <GIC_SPI     
264                                                   
265                         interrupt-controller;     
266                         #interrupt-cells = <2>    
267                 };                                
268                                                   
269                 dsps_smsm: dsps@4 {               
270                         reg = <4>;                
271                         interrupts = <GIC_SPI     
272                                                   
273                         interrupt-controller;     
274                         #interrupt-cells = <2>    
275                 };                                
276         };                                        
277                                                   
278         firmware {                                
279                 scm {                             
280                         compatible = "qcom,scm    
281                                                   
282                         clocks = <&rpmcc RPM_D    
283                         clock-names = "core";     
284                 };                                
285         };                                        
286                                                   
287         soc: soc {                                
288                 #address-cells = <1>;             
289                 #size-cells = <1>;                
290                 ranges;                           
291                 compatible = "simple-bus";        
292                                                   
293                 tlmm_pinmux: pinctrl@800000 {     
294                         compatible = "qcom,apq    
295                         reg = <0x800000 0x4000    
296                                                   
297                         gpio-controller;          
298                         gpio-ranges = <&tlmm_p    
299                         #gpio-cells = <2>;        
300                         interrupt-controller;     
301                         #interrupt-cells = <2>    
302                         interrupts = <GIC_SPI     
303                                                   
304                         pinctrl-names = "defau    
305                         pinctrl-0 = <&ps_hold_    
306                 };                                
307                                                   
308                 sfpb_wrapper_mutex: syscon@120    
309                         compatible = "syscon";    
310                         reg = <0x01200000 0x80    
311                 };                                
312                                                   
313                 intc: interrupt-controller@200    
314                         compatible = "qcom,msm    
315                         interrupt-controller;     
316                         #interrupt-cells = <3>    
317                         reg = <0x02000000 0x10    
318                               <0x02002000 0x10    
319                 };                                
320                                                   
321                 timer@200a000 {                   
322                         compatible = "qcom,kps    
323                                      "qcom,msm    
324                         interrupts = <GIC_PPI     
325                                      <GIC_PPI     
326                                      <GIC_PPI     
327                         reg = <0x0200a000 0x10    
328                         clock-frequency = <270    
329                         cpu-offset = <0x80000>    
330                 };                                
331                                                   
332                 acc0: clock-controller@2088000    
333                         compatible = "qcom,kps    
334                         reg = <0x02088000 0x10    
335                         clocks = <&gcc PLL8_VO    
336                         clock-names = "pll8_vo    
337                         clock-output-names = "    
338                         #clock-cells = <0>;       
339                 };                                
340                                                   
341                 acc1: clock-controller@2098000    
342                         compatible = "qcom,kps    
343                         reg = <0x02098000 0x10    
344                         clocks = <&gcc PLL8_VO    
345                         clock-names = "pll8_vo    
346                         clock-output-names = "    
347                         #clock-cells = <0>;       
348                 };                                
349                                                   
350                 acc2: clock-controller@20a8000    
351                         compatible = "qcom,kps    
352                         reg = <0x020a8000 0x10    
353                         clocks = <&gcc PLL8_VO    
354                         clock-names = "pll8_vo    
355                         clock-output-names = "    
356                         #clock-cells = <0>;       
357                 };                                
358                                                   
359                 acc3: clock-controller@20b8000    
360                         compatible = "qcom,kps    
361                         reg = <0x020b8000 0x10    
362                         clocks = <&gcc PLL8_VO    
363                         clock-names = "pll8_vo    
364                         clock-output-names = "    
365                         #clock-cells = <0>;       
366                 };                                
367                                                   
368                 saw0: power-manager@2089000 {     
369                         compatible = "qcom,apq    
370                         reg = <0x02089000 0x10    
371                                                   
372                         saw0_vreg: regulator {    
373                                 regulator-min-    
374                                 regulator-max-    
375                         };                        
376                 };                                
377                                                   
378                 saw1: power-manager@2099000 {     
379                         compatible = "qcom,apq    
380                         reg = <0x02099000 0x10    
381                                                   
382                         saw1_vreg: regulator {    
383                                 regulator-min-    
384                                 regulator-max-    
385                         };                        
386                 };                                
387                                                   
388                 saw2: power-manager@20a9000 {     
389                         compatible = "qcom,apq    
390                         reg = <0x020a9000 0x10    
391                                                   
392                         saw2_vreg: regulator {    
393                                 regulator-min-    
394                                 regulator-max-    
395                         };                        
396                 };                                
397                                                   
398                 saw3: power-manager@20b9000 {     
399                         compatible = "qcom,apq    
400                         reg = <0x020b9000 0x10    
401                                                   
402                         saw3_vreg: regulator {    
403                                 regulator-min-    
404                                 regulator-max-    
405                         };                        
406                 };                                
407                                                   
408                 sps_sic_non_secure: sps-sic-no    
409                         compatible = "syscon";    
410                         reg = <0x12100000 0x10    
411                 };                                
412                                                   
413                 gsbi1: gsbi@12440000 {            
414                         status = "disabled";      
415                         compatible = "qcom,gsb    
416                         cell-index = <1>;         
417                         reg = <0x12440000 0x10    
418                         clocks = <&gcc GSBI1_H    
419                         clock-names = "iface";    
420                         #address-cells = <1>;     
421                         #size-cells = <1>;        
422                         ranges;                   
423                                                   
424                         syscon-tcsr = <&tcsr>;    
425                                                   
426                         gsbi1_serial: serial@1    
427                                 compatible = "    
428                                 reg = <0x12450    
429                                       <0x12400    
430                                 interrupts = <    
431                                 clocks = <&gcc    
432                                 clock-names =     
433                                 status = "disa    
434                         };                        
435                                                   
436                         gsbi1_i2c: i2c@1246000    
437                                 compatible = "    
438                                 pinctrl-0 = <&    
439                                 pinctrl-1 = <&    
440                                 pinctrl-names     
441                                 reg = <0x12460    
442                                 interrupts = <    
443                                 clocks = <&gcc    
444                                 clock-names =     
445                                 #address-cells    
446                                 #size-cells =     
447                                 status = "disa    
448                         };                        
449                                                   
450                 };                                
451                                                   
452                 gsbi2: gsbi@12480000 {            
453                         status = "disabled";      
454                         compatible = "qcom,gsb    
455                         cell-index = <2>;         
456                         reg = <0x12480000 0x10    
457                         clocks = <&gcc GSBI2_H    
458                         clock-names = "iface";    
459                         #address-cells = <1>;     
460                         #size-cells = <1>;        
461                         ranges;                   
462                                                   
463                         syscon-tcsr = <&tcsr>;    
464                                                   
465                         gsbi2_i2c: i2c@124a000    
466                                 compatible = "    
467                                 reg = <0x124a0    
468                                 pinctrl-0 = <&    
469                                 pinctrl-1 = <&    
470                                 pinctrl-names     
471                                 interrupts = <    
472                                 clocks = <&gcc    
473                                 clock-names =     
474                                 #address-cells    
475                                 #size-cells =     
476                                 status = "disa    
477                         };                        
478                 };                                
479                                                   
480                 gsbi3: gsbi@16200000 {            
481                         status = "disabled";      
482                         compatible = "qcom,gsb    
483                         cell-index = <3>;         
484                         reg = <0x16200000 0x10    
485                         clocks = <&gcc GSBI3_H    
486                         clock-names = "iface";    
487                         #address-cells = <1>;     
488                         #size-cells = <1>;        
489                         ranges;                   
490                         gsbi3_i2c: i2c@1628000    
491                                 compatible = "    
492                                 pinctrl-0 = <&    
493                                 pinctrl-1 = <&    
494                                 pinctrl-names     
495                                 reg = <0x16280    
496                                 interrupts = <    
497                                 clocks = <&gcc    
498                                          <&gcc    
499                                 clock-names =     
500                                 #address-cells    
501                                 #size-cells =     
502                                 status = "disa    
503                         };                        
504                 };                                
505                                                   
506                 gsbi4: gsbi@16300000 {            
507                         status = "disabled";      
508                         compatible = "qcom,gsb    
509                         cell-index = <4>;         
510                         reg = <0x16300000 0x03    
511                         clocks = <&gcc GSBI4_H    
512                         clock-names = "iface";    
513                         #address-cells = <1>;     
514                         #size-cells = <1>;        
515                         ranges;                   
516                                                   
517                         gsbi4_serial: serial@1    
518                                 compatible = "    
519                                 reg = <0x16340    
520                                       <0x16300    
521                                 interrupts = <    
522                                 pinctrl-0 = <&    
523                                 pinctrl-names     
524                                 clocks = <&gcc    
525                                 clock-names =     
526                                 status = "disa    
527                         };                        
528                                                   
529                         gsbi4_i2c: i2c@1638000    
530                                 compatible = "    
531                                 pinctrl-0 = <&    
532                                 pinctrl-1 = <&    
533                                 pinctrl-names     
534                                 reg = <0x16380    
535                                 interrupts = <    
536                                 clocks = <&gcc    
537                                          <&gcc    
538                                 clock-names =     
539                                 status = "disa    
540                         };                        
541                 };                                
542                                                   
543                 gsbi5: gsbi@1a200000 {            
544                         status = "disabled";      
545                         compatible = "qcom,gsb    
546                         cell-index = <5>;         
547                         reg = <0x1a200000 0x03    
548                         clocks = <&gcc GSBI5_H    
549                         clock-names = "iface";    
550                         #address-cells = <1>;     
551                         #size-cells = <1>;        
552                         ranges;                   
553                                                   
554                         gsbi5_serial: serial@1    
555                                 compatible = "    
556                                 reg = <0x1a240    
557                                       <0x1a200    
558                                 interrupts = <    
559                                 clocks = <&gcc    
560                                 clock-names =     
561                                 status = "disa    
562                         };                        
563                                                   
564                         gsbi5_spi: spi@1a28000    
565                                 compatible = "    
566                                 reg = <0x1a280    
567                                 interrupts = <    
568                                 pinctrl-0 = <&    
569                                 pinctrl-1 = <&    
570                                 pinctrl-names     
571                                 clocks = <&gcc    
572                                 clock-names =     
573                                 status = "disa    
574                                 #address-cells    
575                                 #size-cells =     
576                         };                        
577                 };                                
578                                                   
579                 gsbi6: gsbi@16500000 {            
580                         status = "disabled";      
581                         compatible = "qcom,gsb    
582                         cell-index = <6>;         
583                         reg = <0x16500000 0x03    
584                         clocks = <&gcc GSBI6_H    
585                         clock-names = "iface";    
586                         #address-cells = <1>;     
587                         #size-cells = <1>;        
588                         ranges;                   
589                                                   
590                         gsbi6_serial: serial@1    
591                                 compatible = "    
592                                 reg = <0x16540    
593                                       <0x16500    
594                                 interrupts = <    
595                                 clocks = <&gcc    
596                                 clock-names =     
597                                 status = "disa    
598                         };                        
599                                                   
600                         gsbi6_i2c: i2c@1658000    
601                                 compatible = "    
602                                 pinctrl-0 = <&    
603                                 pinctrl-1 = <&    
604                                 pinctrl-names     
605                                 reg = <0x16580    
606                                 interrupts = <    
607                                 clocks = <&gcc    
608                                          <&gcc    
609                                 clock-names =     
610                                 status = "disa    
611                         };                        
612                 };                                
613                                                   
614                 gsbi7: gsbi@16600000 {            
615                         status = "disabled";      
616                         compatible = "qcom,gsb    
617                         cell-index = <7>;         
618                         reg = <0x16600000 0x10    
619                         clocks = <&gcc GSBI7_H    
620                         clock-names = "iface";    
621                         #address-cells = <1>;     
622                         #size-cells = <1>;        
623                         ranges;                   
624                         syscon-tcsr = <&tcsr>;    
625                                                   
626                         gsbi7_serial: serial@1    
627                                 compatible = "    
628                                 reg = <0x16640    
629                                       <0x16600    
630                                 interrupts = <    
631                                 clocks = <&gcc    
632                                 clock-names =     
633                                 status = "disa    
634                         };                        
635                                                   
636                         gsbi7_i2c: i2c@1668000    
637                                 compatible = "    
638                                 pinctrl-0 = <&    
639                                 pinctrl-1 = <&    
640                                 pinctrl-names     
641                                 reg = <0x16680    
642                                 interrupts = <    
643                                 clocks = <&gcc    
644                                          <&gcc    
645                                 clock-names =     
646                                 status = "disa    
647                         };                        
648                 };                                
649                                                   
650                 rng@1a500000 {                    
651                         compatible = "qcom,prn    
652                         reg = <0x1a500000 0x20    
653                         clocks = <&gcc PRNG_CL    
654                         clock-names = "core";     
655                 };                                
656                                                   
657                 ssbi2: ssbi@c00000 {              
658                         compatible = "qcom,ssb    
659                         reg = <0x00c00000 0x10    
660                         qcom,controller-type =    
661                 };                                
662                                                   
663                 ssbi: ssbi@500000 {               
664                         compatible = "qcom,ssb    
665                         reg = <0x00500000 0x10    
666                         qcom,controller-type =    
667                 };                                
668                                                   
669                 qfprom: efuse@700000 {            
670                         compatible = "qcom,apq    
671                         reg = <0x00700000 0x10    
672                         #address-cells = <1>;     
673                         #size-cells = <1>;        
674                                                   
675                         tsens_calib: calib@404    
676                                 reg = <0x404 0    
677                         };                        
678                         tsens_backup: backup_c    
679                                 reg = <0x414 0    
680                         };                        
681                 };                                
682                                                   
683                 gcc: clock-controller@900000 {    
684                         compatible = "qcom,gcc    
685                         reg = <0x00900000 0x40    
686                         #clock-cells = <1>;       
687                         #reset-cells = <1>;       
688                         clocks = <&cxo_board>,    
689                                  <&pxo_board>,    
690                                  <&lcc PLL4>;     
691                         clock-names = "cxo", "    
692                                                   
693                         tsens: thermal-sensor     
694                                 compatible = "    
695                                                   
696                                 nvmem-cells =     
697                                 nvmem-cell-nam    
698                                 interrupts = <    
699                                 interrupt-name    
700                                                   
701                                 #qcom,sensors     
702                                 #thermal-senso    
703                         };                        
704                 };                                
705                                                   
706                 lcc: clock-controller@28000000    
707                         compatible = "qcom,lcc    
708                         reg = <0x28000000 0x10    
709                         #clock-cells = <1>;       
710                         #reset-cells = <1>;       
711                         clocks = <&pxo_board>,    
712                                  <&gcc PLL4_VO    
713                                  <0>,             
714                                  <0>, <0>,        
715                                  <0>, <0>,        
716                                  <0>;             
717                         clock-names = "pxo",      
718                                       "pll4_vo    
719                                       "mi2s_co    
720                                       "codec_i    
721                                       "spare_i    
722                                       "codec_i    
723                                       "spare_i    
724                                       "pcm_cod    
725                 };                                
726                                                   
727                 mmcc: clock-controller@4000000    
728                         compatible = "qcom,mmc    
729                         reg = <0x4000000 0x100    
730                         #clock-cells = <1>;       
731                         #power-domain-cells =     
732                         #reset-cells = <1>;       
733                         clocks = <&pxo_board>,    
734                                  <&gcc PLL3>,     
735                                  <&gcc PLL8_VO    
736                                  <&dsi0_phy 1>    
737                                  <&dsi0_phy 0>    
738                                  <&dsi1_phy 1>    
739                                  <&dsi1_phy 0>    
740                                  <&hdmi_phy>;     
741                         clock-names = "pxo",      
742                                       "pll3",     
743                                       "pll8_vo    
744                                       "dsi1pll    
745                                       "dsi1pll    
746                                       "dsi2pll    
747                                       "dsi2pll    
748                                       "hdmipll    
749                 };                                
750                                                   
751                 l2cc: clock-controller@2011000    
752                         compatible = "qcom,kps    
753                         reg = <0x2011000 0x100    
754                         clocks = <&gcc PLL8_VO    
755                         clock-names = "pll8_vo    
756                         #clock-cells = <0>;       
757                 };                                
758                                                   
759                 rpm: rpm@108000 {                 
760                         compatible = "qcom,rpm    
761                         reg = <0x108000 0x1000    
762                         qcom,ipc = <&l2cc 0x8     
763                                                   
764                         interrupts = <GIC_SPI     
765                                      <GIC_SPI     
766                                      <GIC_SPI     
767                         interrupt-names = "ack    
768                                                   
769                         rpmcc: clock-controlle    
770                                 compatible = "    
771                                 #clock-cells =    
772                                 clocks = <&pxo    
773                                 clock-names =     
774                         };                        
775                 };                                
776                                                   
777                 usb1: usb@12500000 {              
778                         compatible = "qcom,ci-    
779                         reg = <0x12500000 0x20    
780                               <0x12500200 0x20    
781                         interrupts = <GIC_SPI     
782                         clocks = <&gcc USB_HS1    
783                         clock-names = "core",     
784                         assigned-clocks = <&gc    
785                         assigned-clock-rates =    
786                         resets = <&gcc USB_HS1    
787                         reset-names = "core";     
788                         phy_type = "ulpi";        
789                         ahb-burst-config = <0>    
790                         phys = <&usb_hs1_phy>;    
791                         phy-names = "usb-phy";    
792                         status = "disabled";      
793                         #reset-cells = <1>;       
794                                                   
795                         ulpi {                    
796                                 usb_hs1_phy: p    
797                                         compat    
798                                                   
799                                         clocks    
800                                         clock-    
801                                         resets    
802                                         reset-    
803                                         #phy-c    
804                                 };                
805                         };                        
806                 };                                
807                                                   
808                 usb3: usb@12520000 {              
809                         compatible = "qcom,ci-    
810                         reg = <0x12520000 0x20    
811                               <0x12520200 0x20    
812                         interrupts = <GIC_SPI     
813                         clocks = <&gcc USB_HS3    
814                         clock-names = "core",     
815                         assigned-clocks = <&gc    
816                         assigned-clock-rates =    
817                         resets = <&gcc USB_HS3    
818                         reset-names = "core";     
819                         phy_type = "ulpi";        
820                         ahb-burst-config = <0>    
821                         phys = <&usb_hs3_phy>;    
822                         phy-names = "usb-phy";    
823                         status = "disabled";      
824                         #reset-cells = <1>;       
825                                                   
826                         ulpi {                    
827                                 usb_hs3_phy: p    
828                                         compat    
829                                                   
830                                         #phy-c    
831                                         clocks    
832                                         clock-    
833                                         resets    
834                                         reset-    
835                                 };                
836                         };                        
837                 };                                
838                                                   
839                 usb4: usb@12530000 {              
840                         compatible = "qcom,ci-    
841                         reg = <0x12530000 0x20    
842                               <0x12530200 0x20    
843                         interrupts = <GIC_SPI     
844                         clocks = <&gcc USB_HS4    
845                         clock-names = "core",     
846                         assigned-clocks = <&gc    
847                         assigned-clock-rates =    
848                         resets = <&gcc USB_HS4    
849                         reset-names = "core";     
850                         phy_type = "ulpi";        
851                         ahb-burst-config = <0>    
852                         phys = <&usb_hs4_phy>;    
853                         phy-names = "usb-phy";    
854                         status = "disabled";      
855                         #reset-cells = <1>;       
856                                                   
857                         ulpi {                    
858                                 usb_hs4_phy: p    
859                                         compat    
860                                                   
861                                         #phy-c    
862                                         clocks    
863                                         clock-    
864                                         resets    
865                                         reset-    
866                                 };                
867                         };                        
868                 };                                
869                                                   
870                 sata_phy0: phy@1b400000 {         
871                         compatible = "qcom,apq    
872                         status = "disabled";      
873                         reg = <0x1b400000 0x20    
874                         clocks = <&gcc SATA_PH    
875                         clock-names = "cfg";      
876                         #phy-cells = <0>;         
877                 };                                
878                                                   
879                 sata0: sata@29000000 {            
880                         compatible = "qcom,apq    
881                         status   = "disabled";    
882                         reg      = <0x29000000    
883                         interrupts = <GIC_SPI     
884                                                   
885                         clocks = <&gcc SFAB_SA    
886                                  <&gcc SATA_H_    
887                                  <&gcc SATA_A_    
888                                  <&gcc SATA_RX    
889                                  <&gcc SATA_PM    
890                         clock-names = "slave_i    
891                                       "iface",    
892                                       "core",     
893                                       "rxoob",    
894                                       "pmalive    
895                                                   
896                         assigned-clocks = <&gc    
897                                           <&gc    
898                         assigned-clock-rates =    
899                                                   
900                         phys = <&sata_phy0>;      
901                         phy-names = "sata-phy"    
902                         ports-implemented = <0    
903                 };                                
904                                                   
905                 sdcc3: mmc@12180000 {             
906                         compatible = "arm,pl18    
907                         arm,primecell-periphid    
908                         status = "disabled";      
909                         reg = <0x12180000 0x20    
910                         interrupts = <GIC_SPI     
911                         clocks = <&gcc SDC3_CL    
912                         clock-names = "mclk",     
913                         bus-width = <4>;          
914                         cap-sd-highspeed;         
915                         cap-mmc-highspeed;        
916                         max-frequency = <19200    
917                         no-1-8-v;                 
918                         dmas = <&sdcc3bam 2>,     
919                         dma-names = "tx", "rx"    
920                 };                                
921                                                   
922                 sdcc3bam: dma-controller@12182    
923                         compatible = "qcom,bam    
924                         reg = <0x12182000 0x80    
925                         interrupts = <GIC_SPI     
926                         clocks = <&gcc SDC3_H_    
927                         clock-names = "bam_clk    
928                         #dma-cells = <1>;         
929                         qcom,ee = <0>;            
930                 };                                
931                                                   
932                 sdcc4: mmc@121c0000 {             
933                         compatible = "arm,pl18    
934                         arm,primecell-periphid    
935                         status = "disabled";      
936                         reg = <0x121c0000 0x20    
937                         interrupts = <GIC_SPI     
938                         clocks = <&gcc SDC4_CL    
939                         clock-names = "mclk",     
940                         bus-width = <4>;          
941                         cap-sd-highspeed;         
942                         cap-mmc-highspeed;        
943                         max-frequency = <48000    
944                         dmas = <&sdcc4bam 2>,     
945                         dma-names = "tx", "rx"    
946                         pinctrl-names = "defau    
947                         pinctrl-0 = <&sdc4_def    
948                 };                                
949                                                   
950                 sdcc4bam: dma-controller@121c2    
951                         compatible = "qcom,bam    
952                         reg = <0x121c2000 0x80    
953                         interrupts = <GIC_SPI     
954                         clocks = <&gcc SDC4_H_    
955                         clock-names = "bam_clk    
956                         #dma-cells = <1>;         
957                         qcom,ee = <0>;            
958                 };                                
959                                                   
960                 sdcc1: mmc@12400000 {             
961                         status = "disabled";      
962                         compatible = "arm,pl18    
963                         pinctrl-names = "defau    
964                         pinctrl-0 = <&sdcc1_de    
965                         arm,primecell-periphid    
966                         reg = <0x12400000 0x20    
967                         interrupts = <GIC_SPI     
968                         clocks = <&gcc SDC1_CL    
969                         clock-names = "mclk",     
970                         bus-width = <8>;          
971                         max-frequency = <96000    
972                         non-removable;            
973                         cap-sd-highspeed;         
974                         cap-mmc-highspeed;        
975                         dmas = <&sdcc1bam 2>,     
976                         dma-names = "tx", "rx"    
977                 };                                
978                                                   
979                 sdcc1bam: dma-controller@12402    
980                         compatible = "qcom,bam    
981                         reg = <0x12402000 0x80    
982                         interrupts = <GIC_SPI     
983                         clocks = <&gcc SDC1_H_    
984                         clock-names = "bam_clk    
985                         #dma-cells = <1>;         
986                         qcom,ee = <0>;            
987                 };                                
988                                                   
989                 tcsr: syscon@1a400000 {           
990                         compatible = "qcom,tcs    
991                         reg = <0x1a400000 0x10    
992                 };                                
993                                                   
994                 gpu: gpu@4300000 {                
995                         compatible = "qcom,adr    
996                         reg = <0x04300000 0x20    
997                         reg-names = "kgsl_3d0_    
998                         interrupts = <GIC_SPI     
999                         interrupt-names = "kgs    
1000                         clock-names =            
1001                             "core",              
1002                             "iface",             
1003                             "mem",               
1004                             "mem_iface";         
1005                         clocks =                 
1006                             <&mmcc GFX3D_CLK>    
1007                             <&mmcc GFX3D_AHB_    
1008                             <&mmcc GFX3D_AXI_    
1009                             <&mmcc MMSS_IMEM_    
1010                                                  
1011                         iommus = <&gfx3d 0       
1012                                   &gfx3d 1       
1013                                   &gfx3d 2       
1014                                   &gfx3d 3       
1015                                   &gfx3d 4       
1016                                   &gfx3d 5       
1017                                   &gfx3d 6       
1018                                   &gfx3d 7       
1019                                   &gfx3d 8       
1020                                   &gfx3d 9       
1021                                   &gfx3d 10      
1022                                   &gfx3d 11      
1023                                   &gfx3d 12      
1024                                   &gfx3d 13      
1025                                   &gfx3d 14      
1026                                   &gfx3d 15      
1027                                   &gfx3d 16      
1028                                   &gfx3d 17      
1029                                   &gfx3d 18      
1030                                   &gfx3d 19      
1031                                   &gfx3d 20      
1032                                   &gfx3d 21      
1033                                   &gfx3d 22      
1034                                   &gfx3d 23      
1035                                   &gfx3d 24      
1036                                   &gfx3d 25      
1037                                   &gfx3d 26      
1038                                   &gfx3d 27      
1039                                   &gfx3d 28      
1040                                   &gfx3d 29      
1041                                   &gfx3d 30      
1042                                   &gfx3d 31      
1043                                   &gfx3d1 0      
1044                                   &gfx3d1 1      
1045                                   &gfx3d1 2      
1046                                   &gfx3d1 3      
1047                                   &gfx3d1 4      
1048                                   &gfx3d1 5      
1049                                   &gfx3d1 6      
1050                                   &gfx3d1 7      
1051                                   &gfx3d1 8      
1052                                   &gfx3d1 9      
1053                                   &gfx3d1 10     
1054                                   &gfx3d1 11     
1055                                   &gfx3d1 12     
1056                                   &gfx3d1 13     
1057                                   &gfx3d1 14     
1058                                   &gfx3d1 15     
1059                                   &gfx3d1 16     
1060                                   &gfx3d1 17     
1061                                   &gfx3d1 18     
1062                                   &gfx3d1 19     
1063                                   &gfx3d1 20     
1064                                   &gfx3d1 21     
1065                                   &gfx3d1 22     
1066                                   &gfx3d1 23     
1067                                   &gfx3d1 24     
1068                                   &gfx3d1 25     
1069                                   &gfx3d1 26     
1070                                   &gfx3d1 27     
1071                                   &gfx3d1 28     
1072                                   &gfx3d1 29     
1073                                   &gfx3d1 30     
1074                                   &gfx3d1 31>    
1075                                                  
1076                         operating-points-v2 =    
1077                                                  
1078                         gpu_opp_table: opp-ta    
1079                                 compatible =     
1080                                                  
1081                                 opp-450000000    
1082                                         opp-h    
1083                                 };               
1084                                                  
1085                                 opp-27000000     
1086                                         opp-h    
1087                                 };               
1088                         };                       
1089                 };                               
1090                                                  
1091                 mmss_sfpb: syscon@5700000 {      
1092                         compatible = "syscon"    
1093                         reg = <0x5700000 0x70    
1094                 };                               
1095                                                  
1096                 dsi0: dsi@4700000 {              
1097                         compatible = "qcom,ap    
1098                                      "qcom,md    
1099                         #address-cells = <1>;    
1100                         #size-cells = <0>;       
1101                         interrupts = <GIC_SPI    
1102                         reg = <0x04700000 0x2    
1103                         reg-names = "dsi_ctrl    
1104                                                  
1105                         clocks = <&mmcc DSI_M    
1106                                 <&mmcc DSI_S_    
1107                                 <&mmcc AMP_AH    
1108                                 <&mmcc DSI_CL    
1109                                 <&mmcc DSI1_B    
1110                                 <&mmcc DSI_PI    
1111                                 <&mmcc DSI1_E    
1112                         clock-names = "iface"    
1113                                         "src"    
1114                                         "core    
1115                                                  
1116                         assigned-clocks = <&m    
1117                                         <&mmc    
1118                                         <&mmc    
1119                                         <&mmc    
1120                         assigned-clock-parent    
1121                                                  
1122                                                  
1123                                                  
1124                         syscon-sfpb = <&mmss_    
1125                         phys = <&dsi0_phy>;      
1126                         status = "disabled";     
1127                                                  
1128                         ports {                  
1129                                 #address-cell    
1130                                 #size-cells =    
1131                                                  
1132                                 port@0 {         
1133                                         reg =    
1134                                         dsi0_    
1135                                         };       
1136                                 };               
1137                                                  
1138                                 port@1 {         
1139                                         reg =    
1140                                         dsi0_    
1141                                         };       
1142                                 };               
1143                         };                       
1144                 };                               
1145                                                  
1146                                                  
1147                 dsi0_phy: phy@4700200 {          
1148                         compatible = "qcom,ds    
1149                         #clock-cells = <1>;      
1150                         #phy-cells = <0>;        
1151                                                  
1152                         reg = <0x04700200 0x1    
1153                                 <0x04700300 0    
1154                                 <0x04700500 0    
1155                         reg-names = "dsi_pll"    
1156                         clock-names = "iface"    
1157                         clocks = <&mmcc DSI_M    
1158                                  <&pxo_board>    
1159                         status = "disabled";     
1160                 };                               
1161                                                  
1162                 dsi1: dsi@5800000 {              
1163                         compatible = "qcom,md    
1164                         interrupts = <GIC_SPI    
1165                         reg = <0x05800000 0x2    
1166                         reg-names = "dsi_ctrl    
1167                                                  
1168                         clocks = <&mmcc DSI2_    
1169                                  <&mmcc DSI2_    
1170                                  <&mmcc AMP_A    
1171                                  <&mmcc DSI2_    
1172                                  <&mmcc DSI2_    
1173                                  <&mmcc DSI2_    
1174                                  <&mmcc DSI2_    
1175                         clock-names = "iface"    
1176                                       "bus",     
1177                                       "core_m    
1178                                       "src",     
1179                                       "byte",    
1180                                       "pixel"    
1181                                       "core";    
1182                                                  
1183                         assigned-clocks = <&m    
1184                                           <&m    
1185                                           <&m    
1186                                           <&m    
1187                         assigned-clock-parent    
1188                                                  
1189                                                  
1190                                                  
1191                                                  
1192                         syscon-sfpb = <&mmss_    
1193                         phys = <&dsi1_phy>;      
1194                                                  
1195                         #address-cells = <1>;    
1196                         #size-cells = <0>;       
1197                                                  
1198                         status = "disabled";     
1199                                                  
1200                         ports {                  
1201                                 #address-cell    
1202                                 #size-cells =    
1203                                                  
1204                                 port@0 {         
1205                                         reg =    
1206                                         dsi1_    
1207                                         };       
1208                                 };               
1209                                                  
1210                                 port@1 {         
1211                                         reg =    
1212                                         dsi1_    
1213                                         };       
1214                                 };               
1215                         };                       
1216                 };                               
1217                                                  
1218                                                  
1219                 dsi1_phy: dsi-phy@5800200 {      
1220                         compatible = "qcom,ds    
1221                         reg = <0x05800200 0x1    
1222                               <0x05800300 0x2    
1223                               <0x05800500 0x5    
1224                         reg-names = "dsi_pll"    
1225                                     "dsi_phy"    
1226                                     "dsi_phy_    
1227                         clock-names = "iface"    
1228                                       "ref";     
1229                         clocks = <&mmcc DSI2_    
1230                                  <&pxo_board>    
1231                         #clock-cells = <1>;      
1232                         #phy-cells = <0>;        
1233                                                  
1234                         status = "disabled";     
1235                 };                               
1236                                                  
1237                 mdp_port0: iommu@7500000 {       
1238                         compatible = "qcom,ap    
1239                         #iommu-cells = <1>;      
1240                         clock-names =            
1241                             "smmu_pclk",         
1242                             "iommu_clk";         
1243                         clocks =                 
1244                             <&mmcc SMMU_AHB_C    
1245                             <&mmcc MDP_AXI_CL    
1246                         reg = <0x07500000 0x1    
1247                         interrupts =             
1248                             <GIC_SPI 63 IRQ_T    
1249                             <GIC_SPI 64 IRQ_T    
1250                         qcom,ncb = <2>;          
1251                 };                               
1252                                                  
1253                 mdp_port1: iommu@7600000 {       
1254                         compatible = "qcom,ap    
1255                         #iommu-cells = <1>;      
1256                         clock-names =            
1257                             "smmu_pclk",         
1258                             "iommu_clk";         
1259                         clocks =                 
1260                             <&mmcc SMMU_AHB_C    
1261                             <&mmcc MDP_AXI_CL    
1262                         reg = <0x07600000 0x1    
1263                         interrupts =             
1264                             <GIC_SPI 61 IRQ_T    
1265                             <GIC_SPI 62 IRQ_T    
1266                         qcom,ncb = <2>;          
1267                 };                               
1268                                                  
1269                 gfx3d: iommu@7c00000 {           
1270                         compatible = "qcom,ap    
1271                         #iommu-cells = <1>;      
1272                         clock-names =            
1273                             "smmu_pclk",         
1274                             "iommu_clk";         
1275                         clocks =                 
1276                             <&mmcc SMMU_AHB_C    
1277                             <&mmcc GFX3D_AXI_    
1278                         reg = <0x07c00000 0x1    
1279                         interrupts =             
1280                             <GIC_SPI 69 IRQ_T    
1281                             <GIC_SPI 70 IRQ_T    
1282                         qcom,ncb = <3>;          
1283                 };                               
1284                                                  
1285                 gfx3d1: iommu@7d00000 {          
1286                         compatible = "qcom,ap    
1287                         #iommu-cells = <1>;      
1288                         clock-names =            
1289                             "smmu_pclk",         
1290                             "iommu_clk";         
1291                         clocks =                 
1292                             <&mmcc SMMU_AHB_C    
1293                             <&mmcc GFX3D_AXI_    
1294                         reg = <0x07d00000 0x1    
1295                         interrupts =             
1296                             <GIC_SPI 210 IRQ_    
1297                             <GIC_SPI 211 IRQ_    
1298                         qcom,ncb = <3>;          
1299                 };                               
1300                                                  
1301                 pcie: pcie@1b500000 {            
1302                         compatible = "qcom,pc    
1303                         reg = <0x1b500000 0x1    
1304                               <0x1b502000 0x8    
1305                               <0x1b600000 0x1    
1306                               <0x0ff00000 0x1    
1307                         reg-names = "dbi", "e    
1308                         device_type = "pci";     
1309                         linux,pci-domain = <0    
1310                         bus-range = <0x00 0xf    
1311                         num-lanes = <1>;         
1312                         #address-cells = <3>;    
1313                         #size-cells = <2>;       
1314                         ranges = <0x81000000     
1315                                  <0x82000000     
1316                         interrupts = <GIC_SPI    
1317                         interrupt-names = "ms    
1318                         #interrupt-cells = <1    
1319                         interrupt-map-mask =     
1320                         interrupt-map = <0 0     
1321                                         <0 0     
1322                                         <0 0     
1323                                         <0 0     
1324                         clocks = <&gcc PCIE_A    
1325                                  <&gcc PCIE_H    
1326                                  <&gcc PCIE_P    
1327                         clock-names = "core",    
1328                         resets = <&gcc PCIE_A    
1329                                  <&gcc PCIE_H    
1330                                  <&gcc PCIE_P    
1331                                  <&gcc PCIE_P    
1332                                  <&gcc PCIE_P    
1333                         reset-names = "axi",     
1334                         status = "disabled";     
1335                                                  
1336                         pcie@0 {                 
1337                                 device_type =    
1338                                 reg = <0x0 0x    
1339                                 bus-range = <    
1340                                                  
1341                                 #address-cell    
1342                                 #size-cells =    
1343                                 ranges;          
1344                         };                       
1345                 };                               
1346                                                  
1347                 hdmi: hdmi-tx@4a00000 {          
1348                         compatible = "qcom,hd    
1349                         pinctrl-names = "defa    
1350                         pinctrl-0 = <&hdmi_pi    
1351                         reg = <0x04a00000 0x2    
1352                         reg-names = "core_phy    
1353                         interrupts = <GIC_SPI    
1354                         clocks = <&mmcc HDMI_    
1355                                  <&mmcc HDMI_    
1356                                  <&mmcc HDMI_    
1357                         clock-names = "core",    
1358                                       "master    
1359                                       "slave_    
1360                                                  
1361                         phys = <&hdmi_phy>;      
1362                                                  
1363                         status = "disabled";     
1364                                                  
1365                         ports {                  
1366                                 #address-cell    
1367                                 #size-cells =    
1368                                                  
1369                                 port@0 {         
1370                                         reg =    
1371                                         hdmi_    
1372                                         };       
1373                                 };               
1374                                                  
1375                                 port@1 {         
1376                                         reg =    
1377                                         hdmi_    
1378                                         };       
1379                                 };               
1380                         };                       
1381                 };                               
1382                                                  
1383                 hdmi_phy: phy@4a00400 {          
1384                         compatible = "qcom,hd    
1385                         reg = <0x4a00400 0x60    
1386                               <0x4a00500 0x10    
1387                         reg-names = "hdmi_phy    
1388                                     "hdmi_pll    
1389                                                  
1390                         clocks = <&mmcc HDMI_    
1391                         clock-names = "slave_    
1392                         #phy-cells = <0>;        
1393                         #clock-cells = <0>;      
1394                                                  
1395                         status = "disabled";     
1396                 };                               
1397                                                  
1398                 mdp: display-controller@51000    
1399                         compatible = "qcom,md    
1400                         reg = <0x05100000 0xf    
1401                         interrupts = <GIC_SPI    
1402                         clocks = <&mmcc MDP_C    
1403                                  <&mmcc MDP_A    
1404                                  <&mmcc MDP_A    
1405                                  <&mmcc MDP_L    
1406                                  <&mmcc HDMI_    
1407                                  <&mmcc MDP_T    
1408                         clock-names = "core_c    
1409                                       "iface_    
1410                                       "bus_cl    
1411                                       "lut_cl    
1412                                       "hdmi_c    
1413                                       "tv_clk    
1414                                                  
1415                         iommus = <&mdp_port0     
1416                                   &mdp_port0     
1417                                   &mdp_port1     
1418                                   &mdp_port1     
1419                                                  
1420                         ports {                  
1421                                 #address-cell    
1422                                 #size-cells =    
1423                                                  
1424                                 port@0 {         
1425                                         reg =    
1426                                         mdp_l    
1427                                         };       
1428                                 };               
1429                                                  
1430                                 port@1 {         
1431                                         reg =    
1432                                         mdp_d    
1433                                         };       
1434                                 };               
1435                                                  
1436                                 port@2 {         
1437                                         reg =    
1438                                         mdp_d    
1439                                         };       
1440                                 };               
1441                                                  
1442                                 port@3 {         
1443                                         reg =    
1444                                         mdp_d    
1445                                         };       
1446                                 };               
1447                         };                       
1448                 };                               
1449                                                  
1450                 riva: riva-pil@3200800 {         
1451                         compatible = "qcom,ri    
1452                                                  
1453                         reg = <0x03200800 0x1    
1454                         reg-names = "ccu", "d    
1455                                                  
1456                         interrupts-extended =    
1457                                                  
1458                         interrupt-names = "wd    
1459                                                  
1460                         memory-region = <&wcn    
1461                                                  
1462                         status = "disabled";     
1463                                                  
1464                         iris {                   
1465                                 compatible =     
1466                                                  
1467                                 clocks = <&cx    
1468                                 clock-names =    
1469                         };                       
1470                                                  
1471                         smd-edge {               
1472                                 interrupts =     
1473                                                  
1474                                 qcom,ipc = <&    
1475                                 qcom,smd-edge    
1476                                                  
1477                                 label = "riva    
1478                                                  
1479                                 wcnss {          
1480                                         compa    
1481                                         qcom,    
1482                                                  
1483                                         qcom,    
1484                                                  
1485                                         bluet    
1486                                                  
1487                                         };       
1488                                                  
1489                                         wifi     
1490                                                  
1491                                                  
1492                                                  
1493                                                  
1494                                                  
1495                                                  
1496                                                  
1497                                                  
1498                                         };       
1499                                 };               
1500                         };                       
1501                 };                               
1502                                                  
1503                 etb@1a01000 {                    
1504                         compatible = "arm,cor    
1505                         reg = <0x1a01000 0x10    
1506                                                  
1507                         clocks = <&rpmcc RPM_    
1508                         clock-names = "apb_pc    
1509                                                  
1510                         in-ports {               
1511                                 port {           
1512                                         etb_i    
1513                                                  
1514                                         };       
1515                                 };               
1516                         };                       
1517                 };                               
1518                                                  
1519                 tpiu@1a03000 {                   
1520                         compatible = "arm,cor    
1521                         reg = <0x1a03000 0x10    
1522                                                  
1523                         clocks = <&rpmcc RPM_    
1524                         clock-names = "apb_pc    
1525                                                  
1526                         in-ports {               
1527                                 port {           
1528                                         tpiu_    
1529                                                  
1530                                         };       
1531                                 };               
1532                         };                       
1533                 };                               
1534                                                  
1535                 replicator {                     
1536                         compatible = "arm,cor    
1537                                                  
1538                         clocks = <&rpmcc RPM_    
1539                         clock-names = "apb_pc    
1540                                                  
1541                         out-ports {              
1542                                 #address-cell    
1543                                 #size-cells =    
1544                                                  
1545                                 port@0 {         
1546                                         reg =    
1547                                         repli    
1548                                                  
1549                                         };       
1550                                 };               
1551                                 port@1 {         
1552                                         reg =    
1553                                         repli    
1554                                                  
1555                                         };       
1556                                 };               
1557                         };                       
1558                                                  
1559                         in-ports {               
1560                                 port {           
1561                                         repli    
1562                                                  
1563                                         };       
1564                                 };               
1565                         };                       
1566                 };                               
1567                                                  
1568                 funnel@1a04000 {                 
1569                         compatible = "arm,cor    
1570                         reg = <0x1a04000 0x10    
1571                                                  
1572                         clocks = <&rpmcc RPM_    
1573                         clock-names = "apb_pc    
1574                                                  
1575                         in-ports {               
1576                                 #address-cell    
1577                                 #size-cells =    
1578                                                  
1579                                 /*               
1580                                  * Not descri    
1581                                  * 2 - connec    
1582                                  * 3 - not-co    
1583                                  * 6 - not-co    
1584                                  * 7 - not-co    
1585                                  */              
1586                                 port@0 {         
1587                                         reg =    
1588                                         funne    
1589                                                  
1590                                         };       
1591                                 };               
1592                                 port@1 {         
1593                                         reg =    
1594                                         funne    
1595                                                  
1596                                         };       
1597                                 };               
1598                                 port@4 {         
1599                                         reg =    
1600                                         funne    
1601                                                  
1602                                         };       
1603                                 };               
1604                                 port@5 {         
1605                                         reg =    
1606                                         funne    
1607                                                  
1608                                         };       
1609                                 };               
1610                         };                       
1611                                                  
1612                         out-ports {              
1613                                 port {           
1614                                         funne    
1615                                                  
1616                                         };       
1617                                 };               
1618                         };                       
1619                 };                               
1620                                                  
1621                 etm@1a1c000 {                    
1622                         compatible = "arm,cor    
1623                         reg = <0x1a1c000 0x10    
1624                                                  
1625                         clocks = <&rpmcc RPM_    
1626                         clock-names = "apb_pc    
1627                                                  
1628                         cpu = <&CPU0>;           
1629                                                  
1630                         out-ports {              
1631                                 port {           
1632                                         etm0_    
1633                                                  
1634                                         };       
1635                                 };               
1636                         };                       
1637                 };                               
1638                                                  
1639                 etm@1a1d000 {                    
1640                         compatible = "arm,cor    
1641                         reg = <0x1a1d000 0x10    
1642                                                  
1643                         clocks = <&rpmcc RPM_    
1644                         clock-names = "apb_pc    
1645                                                  
1646                         cpu = <&CPU1>;           
1647                                                  
1648                         out-ports {              
1649                                 port {           
1650                                         etm1_    
1651                                                  
1652                                         };       
1653                                 };               
1654                         };                       
1655                 };                               
1656                                                  
1657                 etm@1a1e000 {                    
1658                         compatible = "arm,cor    
1659                         reg = <0x1a1e000 0x10    
1660                                                  
1661                         clocks = <&rpmcc RPM_    
1662                         clock-names = "apb_pc    
1663                                                  
1664                         cpu = <&CPU2>;           
1665                                                  
1666                         out-ports {              
1667                                 port {           
1668                                         etm2_    
1669                                                  
1670                                         };       
1671                                 };               
1672                         };                       
1673                 };                               
1674                                                  
1675                 etm@1a1f000 {                    
1676                         compatible = "arm,cor    
1677                         reg = <0x1a1f000 0x10    
1678                                                  
1679                         clocks = <&rpmcc RPM_    
1680                         clock-names = "apb_pc    
1681                                                  
1682                         cpu = <&CPU3>;           
1683                                                  
1684                         out-ports {              
1685                                 port {           
1686                                         etm3_    
1687                                                  
1688                                         };       
1689                                 };               
1690                         };                       
1691                 };                               
1692         };                                       
1693 };                                               
1694 #include "qcom-apq8064-pins.dtsi"                
                                                      

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