1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h 4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h 5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960. 7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h> 9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 / { 12 / {
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 model = "Qualcomm APQ8064"; 15 model = "Qualcomm APQ8064";
16 compatible = "qcom,apq8064"; 16 compatible = "qcom,apq8064";
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 18
19 reserved-memory { 19 reserved-memory {
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 ranges; 22 ranges;
23 23
24 smem_region: smem@80000000 { 24 smem_region: smem@80000000 {
25 reg = <0x80000000 0x20 25 reg = <0x80000000 0x200000>;
26 no-map; 26 no-map;
27 }; 27 };
28 28
29 wcnss_mem: wcnss@8f000000 { 29 wcnss_mem: wcnss@8f000000 {
30 reg = <0x8f000000 0x70 30 reg = <0x8f000000 0x700000>;
31 no-map; 31 no-map;
32 }; 32 };
33 }; 33 };
34 34
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 38
39 CPU0: cpu@0 { 39 CPU0: cpu@0 {
40 compatible = "qcom,kra 40 compatible = "qcom,krait";
41 enable-method = "qcom, 41 enable-method = "qcom,kpss-acc-v1";
42 device_type = "cpu"; 42 device_type = "cpu";
43 reg = <0>; 43 reg = <0>;
44 next-level-cache = <&L 44 next-level-cache = <&L2>;
45 qcom,acc = <&acc0>; 45 qcom,acc = <&acc0>;
46 qcom,saw = <&saw0>; 46 qcom,saw = <&saw0>;
47 cpu-idle-states = <&CP 47 cpu-idle-states = <&CPU_SPC>;
48 }; 48 };
49 49
50 CPU1: cpu@1 { 50 CPU1: cpu@1 {
51 compatible = "qcom,kra 51 compatible = "qcom,krait";
52 enable-method = "qcom, 52 enable-method = "qcom,kpss-acc-v1";
53 device_type = "cpu"; 53 device_type = "cpu";
54 reg = <1>; 54 reg = <1>;
55 next-level-cache = <&L 55 next-level-cache = <&L2>;
56 qcom,acc = <&acc1>; 56 qcom,acc = <&acc1>;
57 qcom,saw = <&saw1>; 57 qcom,saw = <&saw1>;
58 cpu-idle-states = <&CP 58 cpu-idle-states = <&CPU_SPC>;
59 }; 59 };
60 60
61 CPU2: cpu@2 { 61 CPU2: cpu@2 {
62 compatible = "qcom,kra 62 compatible = "qcom,krait";
63 enable-method = "qcom, 63 enable-method = "qcom,kpss-acc-v1";
64 device_type = "cpu"; 64 device_type = "cpu";
65 reg = <2>; 65 reg = <2>;
66 next-level-cache = <&L 66 next-level-cache = <&L2>;
67 qcom,acc = <&acc2>; 67 qcom,acc = <&acc2>;
68 qcom,saw = <&saw2>; 68 qcom,saw = <&saw2>;
69 cpu-idle-states = <&CP 69 cpu-idle-states = <&CPU_SPC>;
70 }; 70 };
71 71
72 CPU3: cpu@3 { 72 CPU3: cpu@3 {
73 compatible = "qcom,kra 73 compatible = "qcom,krait";
74 enable-method = "qcom, 74 enable-method = "qcom,kpss-acc-v1";
75 device_type = "cpu"; 75 device_type = "cpu";
76 reg = <3>; 76 reg = <3>;
77 next-level-cache = <&L 77 next-level-cache = <&L2>;
78 qcom,acc = <&acc3>; 78 qcom,acc = <&acc3>;
79 qcom,saw = <&saw3>; 79 qcom,saw = <&saw3>;
80 cpu-idle-states = <&CP 80 cpu-idle-states = <&CPU_SPC>;
81 }; 81 };
82 82
83 L2: l2-cache { 83 L2: l2-cache {
84 compatible = "cache"; 84 compatible = "cache";
85 cache-level = <2>; 85 cache-level = <2>;
86 cache-unified; 86 cache-unified;
87 }; 87 };
88 88
89 idle-states { 89 idle-states {
90 CPU_SPC: cpu-spc { !! 90 CPU_SPC: spc {
91 compatible = " 91 compatible = "qcom,idle-state-spc",
92 92 "arm,idle-state";
93 entry-latency- 93 entry-latency-us = <400>;
94 exit-latency-u 94 exit-latency-us = <900>;
95 min-residency- 95 min-residency-us = <3000>;
96 }; 96 };
97 }; 97 };
98 }; 98 };
99 99
100 memory@0 { 100 memory@0 {
101 device_type = "memory"; 101 device_type = "memory";
102 reg = <0x0 0x0>; 102 reg = <0x0 0x0>;
103 }; 103 };
104 104
105 thermal-zones { 105 thermal-zones {
106 cpu0-thermal { 106 cpu0-thermal {
107 polling-delay-passive 107 polling-delay-passive = <250>;
108 polling-delay = <1000> 108 polling-delay = <1000>;
109 109
110 thermal-sensors = <&ts 110 thermal-sensors = <&tsens 7>;
111 coefficients = <1199 0 111 coefficients = <1199 0>;
112 112
113 trips { 113 trips {
114 cpu_alert0: tr 114 cpu_alert0: trip0 {
115 temper 115 temperature = <75000>;
116 hyster 116 hysteresis = <2000>;
117 type = 117 type = "passive";
118 }; 118 };
119 cpu_crit0: tri 119 cpu_crit0: trip1 {
120 temper 120 temperature = <110000>;
121 hyster 121 hysteresis = <2000>;
122 type = 122 type = "critical";
123 }; 123 };
124 }; 124 };
125 }; 125 };
126 126
127 cpu1-thermal { 127 cpu1-thermal {
128 polling-delay-passive 128 polling-delay-passive = <250>;
129 polling-delay = <1000> 129 polling-delay = <1000>;
130 130
131 thermal-sensors = <&ts 131 thermal-sensors = <&tsens 8>;
132 coefficients = <1132 0 132 coefficients = <1132 0>;
133 133
134 trips { 134 trips {
135 cpu_alert1: tr 135 cpu_alert1: trip0 {
136 temper 136 temperature = <75000>;
137 hyster 137 hysteresis = <2000>;
138 type = 138 type = "passive";
139 }; 139 };
140 cpu_crit1: tri 140 cpu_crit1: trip1 {
141 temper 141 temperature = <110000>;
142 hyster 142 hysteresis = <2000>;
143 type = 143 type = "critical";
144 }; 144 };
145 }; 145 };
146 }; 146 };
147 147
148 cpu2-thermal { 148 cpu2-thermal {
149 polling-delay-passive 149 polling-delay-passive = <250>;
150 polling-delay = <1000> 150 polling-delay = <1000>;
151 151
152 thermal-sensors = <&ts 152 thermal-sensors = <&tsens 9>;
153 coefficients = <1199 0 153 coefficients = <1199 0>;
154 154
155 trips { 155 trips {
156 cpu_alert2: tr 156 cpu_alert2: trip0 {
157 temper 157 temperature = <75000>;
158 hyster 158 hysteresis = <2000>;
159 type = 159 type = "passive";
160 }; 160 };
161 cpu_crit2: tri 161 cpu_crit2: trip1 {
162 temper 162 temperature = <110000>;
163 hyster 163 hysteresis = <2000>;
164 type = 164 type = "critical";
165 }; 165 };
166 }; 166 };
167 }; 167 };
168 168
169 cpu3-thermal { 169 cpu3-thermal {
170 polling-delay-passive 170 polling-delay-passive = <250>;
171 polling-delay = <1000> 171 polling-delay = <1000>;
172 172
173 thermal-sensors = <&ts 173 thermal-sensors = <&tsens 10>;
174 coefficients = <1132 0 174 coefficients = <1132 0>;
175 175
176 trips { 176 trips {
177 cpu_alert3: tr 177 cpu_alert3: trip0 {
178 temper 178 temperature = <75000>;
179 hyster 179 hysteresis = <2000>;
180 type = 180 type = "passive";
181 }; 181 };
182 cpu_crit3: tri 182 cpu_crit3: trip1 {
183 temper 183 temperature = <110000>;
184 hyster 184 hysteresis = <2000>;
185 type = 185 type = "critical";
186 }; 186 };
187 }; 187 };
188 }; 188 };
189 }; 189 };
190 190
191 cpu-pmu { 191 cpu-pmu {
192 compatible = "qcom,krait-pmu"; 192 compatible = "qcom,krait-pmu";
193 interrupts = <GIC_PPI 10 (GIC_ !! 193 interrupts = <1 10 0x304>;
194 }; 194 };
195 195
196 clocks { 196 clocks {
197 cxo_board: cxo_board { 197 cxo_board: cxo_board {
198 compatible = "fixed-cl 198 compatible = "fixed-clock";
199 #clock-cells = <0>; 199 #clock-cells = <0>;
200 clock-frequency = <192 200 clock-frequency = <19200000>;
201 }; 201 };
202 202
203 pxo_board: pxo_board { 203 pxo_board: pxo_board {
204 compatible = "fixed-cl 204 compatible = "fixed-clock";
205 #clock-cells = <0>; 205 #clock-cells = <0>;
206 clock-frequency = <270 206 clock-frequency = <27000000>;
207 }; 207 };
208 208
209 sleep_clk: sleep_clk { 209 sleep_clk: sleep_clk {
210 compatible = "fixed-cl 210 compatible = "fixed-clock";
211 #clock-cells = <0>; 211 #clock-cells = <0>;
212 clock-frequency = <327 212 clock-frequency = <32768>;
213 }; 213 };
214 }; 214 };
215 215
216 sfpb_mutex: hwmutex { 216 sfpb_mutex: hwmutex {
217 compatible = "qcom,sfpb-mutex" 217 compatible = "qcom,sfpb-mutex";
218 syscon = <&sfpb_wrapper_mutex 218 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
219 #hwlock-cells = <1>; 219 #hwlock-cells = <1>;
220 }; 220 };
221 221
222 smem { 222 smem {
223 compatible = "qcom,smem"; 223 compatible = "qcom,smem";
224 memory-region = <&smem_region> 224 memory-region = <&smem_region>;
225 225
226 hwlocks = <&sfpb_mutex 3>; 226 hwlocks = <&sfpb_mutex 3>;
227 }; 227 };
228 228
229 smsm { 229 smsm {
230 compatible = "qcom,smsm"; 230 compatible = "qcom,smsm";
231 231
232 #address-cells = <1>; 232 #address-cells = <1>;
233 #size-cells = <0>; 233 #size-cells = <0>;
234 234
235 qcom,ipc-1 = <&l2cc 8 4>; 235 qcom,ipc-1 = <&l2cc 8 4>;
236 qcom,ipc-2 = <&l2cc 8 14>; 236 qcom,ipc-2 = <&l2cc 8 14>;
237 qcom,ipc-3 = <&l2cc 8 23>; 237 qcom,ipc-3 = <&l2cc 8 23>;
238 qcom,ipc-4 = <&sps_sic_non_sec 238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
239 239
240 apps_smsm: apps@0 { 240 apps_smsm: apps@0 {
241 reg = <0>; 241 reg = <0>;
242 #qcom,smem-state-cells 242 #qcom,smem-state-cells = <1>;
243 }; 243 };
244 244
245 modem_smsm: modem@1 { 245 modem_smsm: modem@1 {
246 reg = <1>; 246 reg = <1>;
247 interrupts = <GIC_SPI !! 247 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
248 248
249 interrupt-controller; 249 interrupt-controller;
250 #interrupt-cells = <2> 250 #interrupt-cells = <2>;
251 }; 251 };
252 252
253 q6_smsm: q6@2 { 253 q6_smsm: q6@2 {
254 reg = <2>; 254 reg = <2>;
255 interrupts = <GIC_SPI !! 255 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
256 256
257 interrupt-controller; 257 interrupt-controller;
258 #interrupt-cells = <2> 258 #interrupt-cells = <2>;
259 }; 259 };
260 260
261 wcnss_smsm: wcnss@3 { 261 wcnss_smsm: wcnss@3 {
262 reg = <3>; 262 reg = <3>;
263 interrupts = <GIC_SPI !! 263 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
264 264
265 interrupt-controller; 265 interrupt-controller;
266 #interrupt-cells = <2> 266 #interrupt-cells = <2>;
267 }; 267 };
268 268
269 dsps_smsm: dsps@4 { 269 dsps_smsm: dsps@4 {
270 reg = <4>; 270 reg = <4>;
271 interrupts = <GIC_SPI !! 271 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
272 272
273 interrupt-controller; 273 interrupt-controller;
274 #interrupt-cells = <2> 274 #interrupt-cells = <2>;
275 }; 275 };
276 }; 276 };
277 277
278 firmware { 278 firmware {
279 scm { 279 scm {
280 compatible = "qcom,scm 280 compatible = "qcom,scm-apq8064", "qcom,scm";
281 281
282 clocks = <&rpmcc RPM_D 282 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
283 clock-names = "core"; 283 clock-names = "core";
284 }; 284 };
285 }; 285 };
286 286
>> 287
>> 288 /*
>> 289 * These channels from the ADC are simply hardware monitors.
>> 290 * That is why the ADC is referred to as "HKADC" - HouseKeeping
>> 291 * ADC.
>> 292 */
>> 293 iio-hwmon {
>> 294 compatible = "iio-hwmon";
>> 295 io-channels = <&xoadc 0x00 0x01>, /* Battery */
>> 296 <&xoadc 0x00 0x02>, /* DC in (charger) */
>> 297 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
>> 298 <&xoadc 0x00 0x0b>, /* Die temperature */
>> 299 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
>> 300 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
>> 301 <&xoadc 0x00 0x0e>; /* Charger temperature */
>> 302 };
>> 303
287 soc: soc { 304 soc: soc {
288 #address-cells = <1>; 305 #address-cells = <1>;
289 #size-cells = <1>; 306 #size-cells = <1>;
290 ranges; 307 ranges;
291 compatible = "simple-bus"; 308 compatible = "simple-bus";
292 309
293 tlmm_pinmux: pinctrl@800000 { 310 tlmm_pinmux: pinctrl@800000 {
294 compatible = "qcom,apq 311 compatible = "qcom,apq8064-pinctrl";
295 reg = <0x800000 0x4000 312 reg = <0x800000 0x4000>;
296 313
297 gpio-controller; 314 gpio-controller;
298 gpio-ranges = <&tlmm_p 315 gpio-ranges = <&tlmm_pinmux 0 0 90>;
299 #gpio-cells = <2>; 316 #gpio-cells = <2>;
300 interrupt-controller; 317 interrupt-controller;
301 #interrupt-cells = <2> 318 #interrupt-cells = <2>;
302 interrupts = <GIC_SPI !! 319 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
303 320
304 pinctrl-names = "defau 321 pinctrl-names = "default";
305 pinctrl-0 = <&ps_hold_ !! 322 pinctrl-0 = <&ps_hold>;
306 }; 323 };
307 324
308 sfpb_wrapper_mutex: syscon@120 325 sfpb_wrapper_mutex: syscon@1200000 {
309 compatible = "syscon"; 326 compatible = "syscon";
310 reg = <0x01200000 0x80 327 reg = <0x01200000 0x8000>;
311 }; 328 };
312 329
313 intc: interrupt-controller@200 330 intc: interrupt-controller@2000000 {
314 compatible = "qcom,msm 331 compatible = "qcom,msm-qgic2";
315 interrupt-controller; 332 interrupt-controller;
316 #interrupt-cells = <3> 333 #interrupt-cells = <3>;
317 reg = <0x02000000 0x10 334 reg = <0x02000000 0x1000>,
318 <0x02002000 0x10 335 <0x02002000 0x1000>;
319 }; 336 };
320 337
321 timer@200a000 { 338 timer@200a000 {
322 compatible = "qcom,kps 339 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
323 "qcom,msm 340 "qcom,msm-timer";
324 interrupts = <GIC_PPI !! 341 interrupts = <1 1 0x301>,
325 <GIC_PPI !! 342 <1 2 0x301>,
326 <GIC_PPI !! 343 <1 3 0x301>;
327 reg = <0x0200a000 0x10 344 reg = <0x0200a000 0x100>;
328 clock-frequency = <270 345 clock-frequency = <27000000>;
329 cpu-offset = <0x80000> 346 cpu-offset = <0x80000>;
330 }; 347 };
331 348
332 acc0: clock-controller@2088000 349 acc0: clock-controller@2088000 {
333 compatible = "qcom,kps 350 compatible = "qcom,kpss-acc-v1";
334 reg = <0x02088000 0x10 351 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
335 clocks = <&gcc PLL8_VO 352 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
336 clock-names = "pll8_vo 353 clock-names = "pll8_vote", "pxo";
337 clock-output-names = " 354 clock-output-names = "acpu0_aux";
338 #clock-cells = <0>; 355 #clock-cells = <0>;
339 }; 356 };
340 357
341 acc1: clock-controller@2098000 358 acc1: clock-controller@2098000 {
342 compatible = "qcom,kps 359 compatible = "qcom,kpss-acc-v1";
343 reg = <0x02098000 0x10 360 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
344 clocks = <&gcc PLL8_VO 361 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
345 clock-names = "pll8_vo 362 clock-names = "pll8_vote", "pxo";
346 clock-output-names = " 363 clock-output-names = "acpu1_aux";
347 #clock-cells = <0>; 364 #clock-cells = <0>;
348 }; 365 };
349 366
350 acc2: clock-controller@20a8000 367 acc2: clock-controller@20a8000 {
351 compatible = "qcom,kps 368 compatible = "qcom,kpss-acc-v1";
352 reg = <0x020a8000 0x10 369 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
353 clocks = <&gcc PLL8_VO 370 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
354 clock-names = "pll8_vo 371 clock-names = "pll8_vote", "pxo";
355 clock-output-names = " 372 clock-output-names = "acpu2_aux";
356 #clock-cells = <0>; 373 #clock-cells = <0>;
357 }; 374 };
358 375
359 acc3: clock-controller@20b8000 376 acc3: clock-controller@20b8000 {
360 compatible = "qcom,kps 377 compatible = "qcom,kpss-acc-v1";
361 reg = <0x020b8000 0x10 378 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
362 clocks = <&gcc PLL8_VO 379 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
363 clock-names = "pll8_vo 380 clock-names = "pll8_vote", "pxo";
364 clock-output-names = " 381 clock-output-names = "acpu3_aux";
365 #clock-cells = <0>; 382 #clock-cells = <0>;
366 }; 383 };
367 384
368 saw0: power-manager@2089000 { !! 385 saw0: power-controller@2089000 {
369 compatible = "qcom,apq 386 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
370 reg = <0x02089000 0x10 387 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
371 !! 388 regulator;
372 saw0_vreg: regulator { <<
373 regulator-min- <<
374 regulator-max- <<
375 }; <<
376 }; 389 };
377 390
378 saw1: power-manager@2099000 { !! 391 saw1: power-controller@2099000 {
379 compatible = "qcom,apq 392 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
380 reg = <0x02099000 0x10 393 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
381 !! 394 regulator;
382 saw1_vreg: regulator { <<
383 regulator-min- <<
384 regulator-max- <<
385 }; <<
386 }; 395 };
387 396
388 saw2: power-manager@20a9000 { !! 397 saw2: power-controller@20a9000 {
389 compatible = "qcom,apq 398 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
390 reg = <0x020a9000 0x10 399 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
391 !! 400 regulator;
392 saw2_vreg: regulator { <<
393 regulator-min- <<
394 regulator-max- <<
395 }; <<
396 }; 401 };
397 402
398 saw3: power-manager@20b9000 { !! 403 saw3: power-controller@20b9000 {
399 compatible = "qcom,apq 404 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
400 reg = <0x020b9000 0x10 405 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
401 !! 406 regulator;
402 saw3_vreg: regulator { <<
403 regulator-min- <<
404 regulator-max- <<
405 }; <<
406 }; 407 };
407 408
408 sps_sic_non_secure: sps-sic-no 409 sps_sic_non_secure: sps-sic-non-secure@12100000 {
409 compatible = "syscon"; 410 compatible = "syscon";
410 reg = <0x12100000 0x10 411 reg = <0x12100000 0x10000>;
411 }; 412 };
412 413
413 gsbi1: gsbi@12440000 { 414 gsbi1: gsbi@12440000 {
414 status = "disabled"; 415 status = "disabled";
415 compatible = "qcom,gsb 416 compatible = "qcom,gsbi-v1.0.0";
416 cell-index = <1>; 417 cell-index = <1>;
417 reg = <0x12440000 0x10 418 reg = <0x12440000 0x100>;
418 clocks = <&gcc GSBI1_H 419 clocks = <&gcc GSBI1_H_CLK>;
419 clock-names = "iface"; 420 clock-names = "iface";
420 #address-cells = <1>; 421 #address-cells = <1>;
421 #size-cells = <1>; 422 #size-cells = <1>;
422 ranges; 423 ranges;
423 424
424 syscon-tcsr = <&tcsr>; 425 syscon-tcsr = <&tcsr>;
425 426
426 gsbi1_serial: serial@1 427 gsbi1_serial: serial@12450000 {
427 compatible = " 428 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
428 reg = <0x12450 429 reg = <0x12450000 0x100>,
429 <0x12400 430 <0x12400000 0x03>;
430 interrupts = < !! 431 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&gcc 432 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
432 clock-names = 433 clock-names = "core", "iface";
433 status = "disa 434 status = "disabled";
434 }; 435 };
435 436
436 gsbi1_i2c: i2c@1246000 437 gsbi1_i2c: i2c@12460000 {
437 compatible = " 438 compatible = "qcom,i2c-qup-v1.1.1";
438 pinctrl-0 = <& !! 439 pinctrl-0 = <&i2c1_pins>;
439 pinctrl-1 = <& !! 440 pinctrl-1 = <&i2c1_pins_sleep>;
440 pinctrl-names 441 pinctrl-names = "default", "sleep";
441 reg = <0x12460 442 reg = <0x12460000 0x1000>;
442 interrupts = < !! 443 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&gcc 444 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
444 clock-names = 445 clock-names = "core", "iface";
445 #address-cells 446 #address-cells = <1>;
446 #size-cells = 447 #size-cells = <0>;
447 status = "disa 448 status = "disabled";
448 }; 449 };
449 450
450 }; 451 };
451 452
452 gsbi2: gsbi@12480000 { 453 gsbi2: gsbi@12480000 {
453 status = "disabled"; 454 status = "disabled";
454 compatible = "qcom,gsb 455 compatible = "qcom,gsbi-v1.0.0";
455 cell-index = <2>; 456 cell-index = <2>;
456 reg = <0x12480000 0x10 457 reg = <0x12480000 0x100>;
457 clocks = <&gcc GSBI2_H 458 clocks = <&gcc GSBI2_H_CLK>;
458 clock-names = "iface"; 459 clock-names = "iface";
459 #address-cells = <1>; 460 #address-cells = <1>;
460 #size-cells = <1>; 461 #size-cells = <1>;
461 ranges; 462 ranges;
462 463
463 syscon-tcsr = <&tcsr>; 464 syscon-tcsr = <&tcsr>;
464 465
465 gsbi2_i2c: i2c@124a000 466 gsbi2_i2c: i2c@124a0000 {
466 compatible = " 467 compatible = "qcom,i2c-qup-v1.1.1";
467 reg = <0x124a0 468 reg = <0x124a0000 0x1000>;
468 pinctrl-0 = <& !! 469 pinctrl-0 = <&i2c2_pins>;
469 pinctrl-1 = <& !! 470 pinctrl-1 = <&i2c2_pins_sleep>;
470 pinctrl-names 471 pinctrl-names = "default", "sleep";
471 interrupts = < !! 472 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&gcc 473 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
473 clock-names = 474 clock-names = "core", "iface";
474 #address-cells 475 #address-cells = <1>;
475 #size-cells = 476 #size-cells = <0>;
476 status = "disa 477 status = "disabled";
477 }; 478 };
478 }; 479 };
479 480
480 gsbi3: gsbi@16200000 { 481 gsbi3: gsbi@16200000 {
481 status = "disabled"; 482 status = "disabled";
482 compatible = "qcom,gsb 483 compatible = "qcom,gsbi-v1.0.0";
483 cell-index = <3>; 484 cell-index = <3>;
484 reg = <0x16200000 0x10 485 reg = <0x16200000 0x100>;
485 clocks = <&gcc GSBI3_H 486 clocks = <&gcc GSBI3_H_CLK>;
486 clock-names = "iface"; 487 clock-names = "iface";
487 #address-cells = <1>; 488 #address-cells = <1>;
488 #size-cells = <1>; 489 #size-cells = <1>;
489 ranges; 490 ranges;
490 gsbi3_i2c: i2c@1628000 491 gsbi3_i2c: i2c@16280000 {
491 compatible = " 492 compatible = "qcom,i2c-qup-v1.1.1";
492 pinctrl-0 = <& !! 493 pinctrl-0 = <&i2c3_pins>;
493 pinctrl-1 = <& !! 494 pinctrl-1 = <&i2c3_pins_sleep>;
494 pinctrl-names 495 pinctrl-names = "default", "sleep";
495 reg = <0x16280 496 reg = <0x16280000 0x1000>;
496 interrupts = < 497 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&gcc 498 clocks = <&gcc GSBI3_QUP_CLK>,
498 <&gcc 499 <&gcc GSBI3_H_CLK>;
499 clock-names = 500 clock-names = "core", "iface";
500 #address-cells 501 #address-cells = <1>;
501 #size-cells = 502 #size-cells = <0>;
502 status = "disa 503 status = "disabled";
503 }; 504 };
504 }; 505 };
505 506
506 gsbi4: gsbi@16300000 { 507 gsbi4: gsbi@16300000 {
507 status = "disabled"; 508 status = "disabled";
508 compatible = "qcom,gsb 509 compatible = "qcom,gsbi-v1.0.0";
509 cell-index = <4>; 510 cell-index = <4>;
510 reg = <0x16300000 0x03 511 reg = <0x16300000 0x03>;
511 clocks = <&gcc GSBI4_H 512 clocks = <&gcc GSBI4_H_CLK>;
512 clock-names = "iface"; 513 clock-names = "iface";
513 #address-cells = <1>; 514 #address-cells = <1>;
514 #size-cells = <1>; 515 #size-cells = <1>;
515 ranges; 516 ranges;
516 517
517 gsbi4_serial: serial@1 518 gsbi4_serial: serial@16340000 {
518 compatible = " 519 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
519 reg = <0x16340 520 reg = <0x16340000 0x100>,
520 <0x16300 521 <0x16300000 0x3>;
521 interrupts = < 522 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
522 pinctrl-0 = <& 523 pinctrl-0 = <&gsbi4_uart_pin_a>;
523 pinctrl-names 524 pinctrl-names = "default";
524 clocks = <&gcc 525 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
525 clock-names = 526 clock-names = "core", "iface";
526 status = "disa 527 status = "disabled";
527 }; 528 };
528 529
529 gsbi4_i2c: i2c@1638000 530 gsbi4_i2c: i2c@16380000 {
530 compatible = " 531 compatible = "qcom,i2c-qup-v1.1.1";
531 pinctrl-0 = <& !! 532 pinctrl-0 = <&i2c4_pins>;
532 pinctrl-1 = <& !! 533 pinctrl-1 = <&i2c4_pins_sleep>;
533 pinctrl-names 534 pinctrl-names = "default", "sleep";
534 reg = <0x16380 535 reg = <0x16380000 0x1000>;
535 interrupts = < 536 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&gcc 537 clocks = <&gcc GSBI4_QUP_CLK>,
537 <&gcc 538 <&gcc GSBI4_H_CLK>;
538 clock-names = 539 clock-names = "core", "iface";
539 status = "disa 540 status = "disabled";
540 }; 541 };
541 }; 542 };
542 543
543 gsbi5: gsbi@1a200000 { 544 gsbi5: gsbi@1a200000 {
544 status = "disabled"; 545 status = "disabled";
545 compatible = "qcom,gsb 546 compatible = "qcom,gsbi-v1.0.0";
546 cell-index = <5>; 547 cell-index = <5>;
547 reg = <0x1a200000 0x03 548 reg = <0x1a200000 0x03>;
548 clocks = <&gcc GSBI5_H 549 clocks = <&gcc GSBI5_H_CLK>;
549 clock-names = "iface"; 550 clock-names = "iface";
550 #address-cells = <1>; 551 #address-cells = <1>;
551 #size-cells = <1>; 552 #size-cells = <1>;
552 ranges; 553 ranges;
553 554
554 gsbi5_serial: serial@1 555 gsbi5_serial: serial@1a240000 {
555 compatible = " 556 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
556 reg = <0x1a240 557 reg = <0x1a240000 0x100>,
557 <0x1a200 558 <0x1a200000 0x03>;
558 interrupts = < !! 559 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&gcc 560 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
560 clock-names = 561 clock-names = "core", "iface";
561 status = "disa 562 status = "disabled";
562 }; 563 };
563 564
564 gsbi5_spi: spi@1a28000 565 gsbi5_spi: spi@1a280000 {
565 compatible = " 566 compatible = "qcom,spi-qup-v1.1.1";
566 reg = <0x1a280 567 reg = <0x1a280000 0x1000>;
567 interrupts = < !! 568 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
568 pinctrl-0 = <& !! 569 pinctrl-0 = <&spi5_default>;
569 pinctrl-1 = <& !! 570 pinctrl-1 = <&spi5_sleep>;
570 pinctrl-names 571 pinctrl-names = "default", "sleep";
571 clocks = <&gcc 572 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
572 clock-names = 573 clock-names = "core", "iface";
573 status = "disa 574 status = "disabled";
574 #address-cells 575 #address-cells = <1>;
575 #size-cells = 576 #size-cells = <0>;
576 }; 577 };
577 }; 578 };
578 579
579 gsbi6: gsbi@16500000 { 580 gsbi6: gsbi@16500000 {
580 status = "disabled"; 581 status = "disabled";
581 compatible = "qcom,gsb 582 compatible = "qcom,gsbi-v1.0.0";
582 cell-index = <6>; 583 cell-index = <6>;
583 reg = <0x16500000 0x03 584 reg = <0x16500000 0x03>;
584 clocks = <&gcc GSBI6_H 585 clocks = <&gcc GSBI6_H_CLK>;
585 clock-names = "iface"; 586 clock-names = "iface";
586 #address-cells = <1>; 587 #address-cells = <1>;
587 #size-cells = <1>; 588 #size-cells = <1>;
588 ranges; 589 ranges;
589 590
590 gsbi6_serial: serial@1 591 gsbi6_serial: serial@16540000 {
591 compatible = " 592 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
592 reg = <0x16540 593 reg = <0x16540000 0x100>,
593 <0x16500 594 <0x16500000 0x03>;
594 interrupts = < !! 595 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&gcc 596 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
596 clock-names = 597 clock-names = "core", "iface";
597 status = "disa 598 status = "disabled";
598 }; 599 };
599 600
600 gsbi6_i2c: i2c@1658000 601 gsbi6_i2c: i2c@16580000 {
601 compatible = " 602 compatible = "qcom,i2c-qup-v1.1.1";
602 pinctrl-0 = <& !! 603 pinctrl-0 = <&i2c6_pins>;
603 pinctrl-1 = <& !! 604 pinctrl-1 = <&i2c6_pins_sleep>;
604 pinctrl-names 605 pinctrl-names = "default", "sleep";
605 reg = <0x16580 606 reg = <0x16580000 0x1000>;
606 interrupts = < 607 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc 608 clocks = <&gcc GSBI6_QUP_CLK>,
608 <&gcc 609 <&gcc GSBI6_H_CLK>;
609 clock-names = 610 clock-names = "core", "iface";
610 status = "disa 611 status = "disabled";
611 }; 612 };
612 }; 613 };
613 614
614 gsbi7: gsbi@16600000 { 615 gsbi7: gsbi@16600000 {
615 status = "disabled"; 616 status = "disabled";
616 compatible = "qcom,gsb 617 compatible = "qcom,gsbi-v1.0.0";
617 cell-index = <7>; 618 cell-index = <7>;
618 reg = <0x16600000 0x10 619 reg = <0x16600000 0x100>;
619 clocks = <&gcc GSBI7_H 620 clocks = <&gcc GSBI7_H_CLK>;
620 clock-names = "iface"; 621 clock-names = "iface";
621 #address-cells = <1>; 622 #address-cells = <1>;
622 #size-cells = <1>; 623 #size-cells = <1>;
623 ranges; 624 ranges;
624 syscon-tcsr = <&tcsr>; 625 syscon-tcsr = <&tcsr>;
625 626
626 gsbi7_serial: serial@1 627 gsbi7_serial: serial@16640000 {
627 compatible = " 628 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
628 reg = <0x16640 629 reg = <0x16640000 0x1000>,
629 <0x16600 630 <0x16600000 0x1000>;
630 interrupts = < !! 631 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&gcc 632 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
632 clock-names = 633 clock-names = "core", "iface";
633 status = "disa 634 status = "disabled";
634 }; 635 };
635 636
636 gsbi7_i2c: i2c@1668000 637 gsbi7_i2c: i2c@16680000 {
637 compatible = " 638 compatible = "qcom,i2c-qup-v1.1.1";
638 pinctrl-0 = <& !! 639 pinctrl-0 = <&i2c7_pins>;
639 pinctrl-1 = <& !! 640 pinctrl-1 = <&i2c7_pins_sleep>;
640 pinctrl-names 641 pinctrl-names = "default", "sleep";
641 reg = <0x16680 642 reg = <0x16680000 0x1000>;
642 interrupts = < 643 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&gcc 644 clocks = <&gcc GSBI7_QUP_CLK>,
644 <&gcc 645 <&gcc GSBI7_H_CLK>;
645 clock-names = 646 clock-names = "core", "iface";
646 status = "disa 647 status = "disabled";
647 }; 648 };
648 }; 649 };
649 650
650 rng@1a500000 { 651 rng@1a500000 {
651 compatible = "qcom,prn 652 compatible = "qcom,prng";
652 reg = <0x1a500000 0x20 653 reg = <0x1a500000 0x200>;
653 clocks = <&gcc PRNG_CL 654 clocks = <&gcc PRNG_CLK>;
654 clock-names = "core"; 655 clock-names = "core";
655 }; 656 };
656 657
657 ssbi2: ssbi@c00000 { !! 658 ssbi@c00000 {
658 compatible = "qcom,ssb 659 compatible = "qcom,ssbi";
659 reg = <0x00c00000 0x10 660 reg = <0x00c00000 0x1000>;
660 qcom,controller-type = 661 qcom,controller-type = "pmic-arbiter";
>> 662
>> 663 pm8821: pmic {
>> 664 compatible = "qcom,pm8821";
>> 665 interrupt-parent = <&tlmm_pinmux>;
>> 666 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
>> 667 #interrupt-cells = <2>;
>> 668 interrupt-controller;
>> 669 #address-cells = <1>;
>> 670 #size-cells = <0>;
>> 671
>> 672 pm8821_mpps: mpps@50 {
>> 673 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
>> 674 reg = <0x50>;
>> 675 interrupt-controller;
>> 676 #interrupt-cells = <2>;
>> 677 gpio-controller;
>> 678 #gpio-cells = <2>;
>> 679 gpio-ranges = <&pm8821_mpps 0 0 4>;
>> 680 };
>> 681 };
661 }; 682 };
662 683
663 ssbi: ssbi@500000 { !! 684 ssbi@500000 {
664 compatible = "qcom,ssb 685 compatible = "qcom,ssbi";
665 reg = <0x00500000 0x10 686 reg = <0x00500000 0x1000>;
666 qcom,controller-type = 687 qcom,controller-type = "pmic-arbiter";
>> 688
>> 689 pmicintc: pmic {
>> 690 compatible = "qcom,pm8921";
>> 691 interrupt-parent = <&tlmm_pinmux>;
>> 692 interrupts = <74 8>;
>> 693 #interrupt-cells = <2>;
>> 694 interrupt-controller;
>> 695 #address-cells = <1>;
>> 696 #size-cells = <0>;
>> 697
>> 698 pm8921_gpio: gpio@150 {
>> 699
>> 700 compatible = "qcom,pm8921-gpio",
>> 701 "qcom,ssbi-gpio";
>> 702 reg = <0x150>;
>> 703 interrupt-controller;
>> 704 #interrupt-cells = <2>;
>> 705 gpio-controller;
>> 706 gpio-ranges = <&pm8921_gpio 0 0 44>;
>> 707 #gpio-cells = <2>;
>> 708
>> 709 };
>> 710
>> 711 pm8921_mpps: mpps@50 {
>> 712 compatible = "qcom,pm8921-mpp",
>> 713 "qcom,ssbi-mpp";
>> 714 reg = <0x50>;
>> 715 gpio-controller;
>> 716 #gpio-cells = <2>;
>> 717 gpio-ranges = <&pm8921_mpps 0 0 12>;
>> 718 interrupt-controller;
>> 719 #interrupt-cells = <2>;
>> 720 };
>> 721
>> 722 rtc@11d {
>> 723 compatible = "qcom,pm8921-rtc";
>> 724 interrupt-parent = <&pmicintc>;
>> 725 interrupts = <39 1>;
>> 726 reg = <0x11d>;
>> 727 allow-set-time;
>> 728 };
>> 729
>> 730 pwrkey@1c {
>> 731 compatible = "qcom,pm8921-pwrkey";
>> 732 reg = <0x1c>;
>> 733 interrupt-parent = <&pmicintc>;
>> 734 interrupts = <50 1>, <51 1>;
>> 735 debounce = <15625>;
>> 736 pull-up;
>> 737 };
>> 738
>> 739 xoadc: xoadc@197 {
>> 740 compatible = "qcom,pm8921-adc";
>> 741 reg = <0x197>;
>> 742 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
>> 743 #address-cells = <2>;
>> 744 #size-cells = <0>;
>> 745 #io-channel-cells = <2>;
>> 746
>> 747 vcoin: adc-channel@0 {
>> 748 reg = <0x00 0x00>;
>> 749 };
>> 750 vbat: adc-channel@1 {
>> 751 reg = <0x00 0x01>;
>> 752 };
>> 753 dcin: adc-channel@2 {
>> 754 reg = <0x00 0x02>;
>> 755 };
>> 756 vph_pwr: adc-channel@4 {
>> 757 reg = <0x00 0x04>;
>> 758 };
>> 759 batt_therm: adc-channel@8 {
>> 760 reg = <0x00 0x08>;
>> 761 };
>> 762 batt_id: adc-channel@9 {
>> 763 reg = <0x00 0x09>;
>> 764 };
>> 765 usb_vbus: adc-channel@a {
>> 766 reg = <0x00 0x0a>;
>> 767 };
>> 768 die_temp: adc-channel@b {
>> 769 reg = <0x00 0x0b>;
>> 770 };
>> 771 ref_625mv: adc-channel@c {
>> 772 reg = <0x00 0x0c>;
>> 773 };
>> 774 ref_1250mv: adc-channel@d {
>> 775 reg = <0x00 0x0d>;
>> 776 };
>> 777 chg_temp: adc-channel@e {
>> 778 reg = <0x00 0x0e>;
>> 779 };
>> 780 ref_muxoff: adc-channel@f {
>> 781 reg = <0x00 0x0f>;
>> 782 };
>> 783 };
>> 784 };
667 }; 785 };
668 786
669 qfprom: efuse@700000 { !! 787 qfprom: qfprom@700000 {
670 compatible = "qcom,apq 788 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
671 reg = <0x00700000 0x10 789 reg = <0x00700000 0x1000>;
672 #address-cells = <1>; 790 #address-cells = <1>;
673 #size-cells = <1>; 791 #size-cells = <1>;
674 !! 792 ranges;
675 tsens_calib: calib@404 793 tsens_calib: calib@404 {
676 reg = <0x404 0 794 reg = <0x404 0x10>;
677 }; 795 };
678 tsens_backup: backup_c 796 tsens_backup: backup_calib@414 {
679 reg = <0x414 0 797 reg = <0x414 0x10>;
680 }; 798 };
681 }; 799 };
682 800
683 gcc: clock-controller@900000 { 801 gcc: clock-controller@900000 {
684 compatible = "qcom,gcc 802 compatible = "qcom,gcc-apq8064", "syscon";
685 reg = <0x00900000 0x40 803 reg = <0x00900000 0x4000>;
686 #clock-cells = <1>; 804 #clock-cells = <1>;
>> 805 #power-domain-cells = <1>;
687 #reset-cells = <1>; 806 #reset-cells = <1>;
688 clocks = <&cxo_board>, 807 clocks = <&cxo_board>,
689 <&pxo_board>, 808 <&pxo_board>,
690 <&lcc PLL4>; 809 <&lcc PLL4>;
691 clock-names = "cxo", " 810 clock-names = "cxo", "pxo", "pll4";
692 811
693 tsens: thermal-sensor 812 tsens: thermal-sensor {
694 compatible = " 813 compatible = "qcom,msm8960-tsens";
695 814
696 nvmem-cells = 815 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
697 nvmem-cell-nam 816 nvmem-cell-names = "calib", "calib_backup";
698 interrupts = < 817 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-name 818 interrupt-names = "uplow";
700 819
701 #qcom,sensors 820 #qcom,sensors = <11>;
702 #thermal-senso 821 #thermal-sensor-cells = <1>;
703 }; 822 };
704 }; 823 };
705 824
706 lcc: clock-controller@28000000 825 lcc: clock-controller@28000000 {
707 compatible = "qcom,lcc 826 compatible = "qcom,lcc-apq8064";
708 reg = <0x28000000 0x10 827 reg = <0x28000000 0x1000>;
709 #clock-cells = <1>; 828 #clock-cells = <1>;
710 #reset-cells = <1>; 829 #reset-cells = <1>;
711 clocks = <&pxo_board>, 830 clocks = <&pxo_board>,
712 <&gcc PLL4_VO 831 <&gcc PLL4_VOTE>,
713 <0>, 832 <0>,
714 <0>, <0>, 833 <0>, <0>,
715 <0>, <0>, 834 <0>, <0>,
716 <0>; 835 <0>;
717 clock-names = "pxo", 836 clock-names = "pxo",
718 "pll4_vo 837 "pll4_vote",
719 "mi2s_co 838 "mi2s_codec_clk",
720 "codec_i 839 "codec_i2s_mic_codec_clk",
721 "spare_i 840 "spare_i2s_mic_codec_clk",
722 "codec_i 841 "codec_i2s_spkr_codec_clk",
723 "spare_i 842 "spare_i2s_spkr_codec_clk",
724 "pcm_cod 843 "pcm_codec_clk";
725 }; 844 };
726 845
727 mmcc: clock-controller@4000000 846 mmcc: clock-controller@4000000 {
728 compatible = "qcom,mmc 847 compatible = "qcom,mmcc-apq8064";
729 reg = <0x4000000 0x100 848 reg = <0x4000000 0x1000>;
730 #clock-cells = <1>; 849 #clock-cells = <1>;
731 #power-domain-cells = 850 #power-domain-cells = <1>;
732 #reset-cells = <1>; 851 #reset-cells = <1>;
733 clocks = <&pxo_board>, 852 clocks = <&pxo_board>,
734 <&gcc PLL3>, 853 <&gcc PLL3>,
735 <&gcc PLL8_VO 854 <&gcc PLL8_VOTE>,
736 <&dsi0_phy 1> 855 <&dsi0_phy 1>,
737 <&dsi0_phy 0> 856 <&dsi0_phy 0>,
738 <&dsi1_phy 1> 857 <&dsi1_phy 1>,
739 <&dsi1_phy 0> 858 <&dsi1_phy 0>,
740 <&hdmi_phy>; 859 <&hdmi_phy>;
741 clock-names = "pxo", 860 clock-names = "pxo",
742 "pll3", 861 "pll3",
743 "pll8_vo 862 "pll8_vote",
744 "dsi1pll 863 "dsi1pll",
745 "dsi1pll 864 "dsi1pllbyte",
746 "dsi2pll 865 "dsi2pll",
747 "dsi2pll 866 "dsi2pllbyte",
748 "hdmipll 867 "hdmipll";
749 }; 868 };
750 869
751 l2cc: clock-controller@2011000 870 l2cc: clock-controller@2011000 {
752 compatible = "qcom,kps 871 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
753 reg = <0x2011000 0x100 872 reg = <0x2011000 0x1000>;
754 clocks = <&gcc PLL8_VO 873 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
755 clock-names = "pll8_vo 874 clock-names = "pll8_vote", "pxo";
756 #clock-cells = <0>; 875 #clock-cells = <0>;
757 }; 876 };
758 877
759 rpm: rpm@108000 { 878 rpm: rpm@108000 {
760 compatible = "qcom,rpm 879 compatible = "qcom,rpm-apq8064";
761 reg = <0x108000 0x1000 880 reg = <0x108000 0x1000>;
762 qcom,ipc = <&l2cc 0x8 881 qcom,ipc = <&l2cc 0x8 2>;
763 882
764 interrupts = <GIC_SPI 883 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
765 <GIC_SPI 884 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
766 <GIC_SPI 885 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
767 interrupt-names = "ack 886 interrupt-names = "ack", "err", "wakeup";
768 887
769 rpmcc: clock-controlle 888 rpmcc: clock-controller {
770 compatible = " 889 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
771 #clock-cells = 890 #clock-cells = <1>;
772 clocks = <&pxo 891 clocks = <&pxo_board>, <&cxo_board>;
773 clock-names = 892 clock-names = "pxo", "cxo";
774 }; 893 };
>> 894
>> 895 regulators {
>> 896 compatible = "qcom,rpm-pm8921-regulators";
>> 897
>> 898 pm8921_s1: s1 {};
>> 899 pm8921_s2: s2 {};
>> 900 pm8921_s3: s3 {};
>> 901 pm8921_s4: s4 {};
>> 902 pm8921_s7: s7 {};
>> 903 pm8921_s8: s8 {};
>> 904
>> 905 pm8921_l1: l1 {};
>> 906 pm8921_l2: l2 {};
>> 907 pm8921_l3: l3 {};
>> 908 pm8921_l4: l4 {};
>> 909 pm8921_l5: l5 {};
>> 910 pm8921_l6: l6 {};
>> 911 pm8921_l7: l7 {};
>> 912 pm8921_l8: l8 {};
>> 913 pm8921_l9: l9 {};
>> 914 pm8921_l10: l10 {};
>> 915 pm8921_l11: l11 {};
>> 916 pm8921_l12: l12 {};
>> 917 pm8921_l14: l14 {};
>> 918 pm8921_l15: l15 {};
>> 919 pm8921_l16: l16 {};
>> 920 pm8921_l17: l17 {};
>> 921 pm8921_l18: l18 {};
>> 922 pm8921_l21: l21 {};
>> 923 pm8921_l22: l22 {};
>> 924 pm8921_l23: l23 {};
>> 925 pm8921_l24: l24 {};
>> 926 pm8921_l25: l25 {};
>> 927 pm8921_l26: l26 {};
>> 928 pm8921_l27: l27 {};
>> 929 pm8921_l28: l28 {};
>> 930 pm8921_l29: l29 {};
>> 931
>> 932 pm8921_lvs1: lvs1 {};
>> 933 pm8921_lvs2: lvs2 {};
>> 934 pm8921_lvs3: lvs3 {};
>> 935 pm8921_lvs4: lvs4 {};
>> 936 pm8921_lvs5: lvs5 {};
>> 937 pm8921_lvs6: lvs6 {};
>> 938 pm8921_lvs7: lvs7 {};
>> 939
>> 940 pm8921_usb_switch: usb-switch {};
>> 941
>> 942 pm8921_hdmi_switch: hdmi-switch {
>> 943 bias-pull-down;
>> 944 };
>> 945
>> 946 pm8921_ncp: ncp {};
>> 947 };
775 }; 948 };
776 949
777 usb1: usb@12500000 { 950 usb1: usb@12500000 {
778 compatible = "qcom,ci- 951 compatible = "qcom,ci-hdrc";
779 reg = <0x12500000 0x20 952 reg = <0x12500000 0x200>,
780 <0x12500200 0x20 953 <0x12500200 0x200>;
781 interrupts = <GIC_SPI 954 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&gcc USB_HS1 955 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
783 clock-names = "core", 956 clock-names = "core", "iface";
784 assigned-clocks = <&gc 957 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
785 assigned-clock-rates = 958 assigned-clock-rates = <60000000>;
786 resets = <&gcc USB_HS1 959 resets = <&gcc USB_HS1_RESET>;
787 reset-names = "core"; 960 reset-names = "core";
788 phy_type = "ulpi"; 961 phy_type = "ulpi";
789 ahb-burst-config = <0> 962 ahb-burst-config = <0>;
790 phys = <&usb_hs1_phy>; 963 phys = <&usb_hs1_phy>;
791 phy-names = "usb-phy"; 964 phy-names = "usb-phy";
792 status = "disabled"; 965 status = "disabled";
793 #reset-cells = <1>; 966 #reset-cells = <1>;
794 967
795 ulpi { 968 ulpi {
796 usb_hs1_phy: p 969 usb_hs1_phy: phy {
797 compat 970 compatible = "qcom,usb-hs-phy-apq8064",
798 971 "qcom,usb-hs-phy";
799 clocks 972 clocks = <&sleep_clk>, <&cxo_board>;
800 clock- 973 clock-names = "sleep", "ref";
801 resets 974 resets = <&usb1 0>;
802 reset- 975 reset-names = "por";
803 #phy-c 976 #phy-cells = <0>;
804 }; 977 };
805 }; 978 };
806 }; 979 };
807 980
808 usb3: usb@12520000 { 981 usb3: usb@12520000 {
809 compatible = "qcom,ci- 982 compatible = "qcom,ci-hdrc";
810 reg = <0x12520000 0x20 983 reg = <0x12520000 0x200>,
811 <0x12520200 0x20 984 <0x12520200 0x200>;
812 interrupts = <GIC_SPI 985 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&gcc USB_HS3 986 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
814 clock-names = "core", 987 clock-names = "core", "iface";
815 assigned-clocks = <&gc 988 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
816 assigned-clock-rates = 989 assigned-clock-rates = <60000000>;
817 resets = <&gcc USB_HS3 990 resets = <&gcc USB_HS3_RESET>;
818 reset-names = "core"; 991 reset-names = "core";
819 phy_type = "ulpi"; 992 phy_type = "ulpi";
820 ahb-burst-config = <0> 993 ahb-burst-config = <0>;
821 phys = <&usb_hs3_phy>; 994 phys = <&usb_hs3_phy>;
822 phy-names = "usb-phy"; 995 phy-names = "usb-phy";
823 status = "disabled"; 996 status = "disabled";
824 #reset-cells = <1>; 997 #reset-cells = <1>;
825 998
826 ulpi { 999 ulpi {
827 usb_hs3_phy: p 1000 usb_hs3_phy: phy {
828 compat 1001 compatible = "qcom,usb-hs-phy-apq8064",
829 1002 "qcom,usb-hs-phy";
830 #phy-c 1003 #phy-cells = <0>;
831 clocks 1004 clocks = <&sleep_clk>, <&cxo_board>;
832 clock- 1005 clock-names = "sleep", "ref";
833 resets 1006 resets = <&usb3 0>;
834 reset- 1007 reset-names = "por";
835 }; 1008 };
836 }; 1009 };
837 }; 1010 };
838 1011
839 usb4: usb@12530000 { 1012 usb4: usb@12530000 {
840 compatible = "qcom,ci- 1013 compatible = "qcom,ci-hdrc";
841 reg = <0x12530000 0x20 1014 reg = <0x12530000 0x200>,
842 <0x12530200 0x20 1015 <0x12530200 0x200>;
843 interrupts = <GIC_SPI 1016 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&gcc USB_HS4 1017 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
845 clock-names = "core", 1018 clock-names = "core", "iface";
846 assigned-clocks = <&gc 1019 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
847 assigned-clock-rates = 1020 assigned-clock-rates = <60000000>;
848 resets = <&gcc USB_HS4 1021 resets = <&gcc USB_HS4_RESET>;
849 reset-names = "core"; 1022 reset-names = "core";
850 phy_type = "ulpi"; 1023 phy_type = "ulpi";
851 ahb-burst-config = <0> 1024 ahb-burst-config = <0>;
852 phys = <&usb_hs4_phy>; 1025 phys = <&usb_hs4_phy>;
853 phy-names = "usb-phy"; 1026 phy-names = "usb-phy";
854 status = "disabled"; 1027 status = "disabled";
855 #reset-cells = <1>; 1028 #reset-cells = <1>;
856 1029
857 ulpi { 1030 ulpi {
858 usb_hs4_phy: p 1031 usb_hs4_phy: phy {
859 compat 1032 compatible = "qcom,usb-hs-phy-apq8064",
860 1033 "qcom,usb-hs-phy";
861 #phy-c 1034 #phy-cells = <0>;
862 clocks 1035 clocks = <&sleep_clk>, <&cxo_board>;
863 clock- 1036 clock-names = "sleep", "ref";
864 resets 1037 resets = <&usb4 0>;
865 reset- 1038 reset-names = "por";
866 }; 1039 };
867 }; 1040 };
868 }; 1041 };
869 1042
870 sata_phy0: phy@1b400000 { 1043 sata_phy0: phy@1b400000 {
871 compatible = "qcom,apq 1044 compatible = "qcom,apq8064-sata-phy";
872 status = "disabled"; 1045 status = "disabled";
873 reg = <0x1b400000 0x20 1046 reg = <0x1b400000 0x200>;
>> 1047 reg-names = "phy_mem";
874 clocks = <&gcc SATA_PH 1048 clocks = <&gcc SATA_PHY_CFG_CLK>;
875 clock-names = "cfg"; 1049 clock-names = "cfg";
876 #phy-cells = <0>; 1050 #phy-cells = <0>;
877 }; 1051 };
878 1052
879 sata0: sata@29000000 { 1053 sata0: sata@29000000 {
880 compatible = "qcom,apq 1054 compatible = "qcom,apq8064-ahci", "generic-ahci";
881 status = "disabled"; 1055 status = "disabled";
882 reg = <0x29000000 1056 reg = <0x29000000 0x180>;
883 interrupts = <GIC_SPI 1057 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
884 1058
885 clocks = <&gcc SFAB_SA 1059 clocks = <&gcc SFAB_SATA_S_H_CLK>,
886 <&gcc SATA_H_ 1060 <&gcc SATA_H_CLK>,
887 <&gcc SATA_A_ 1061 <&gcc SATA_A_CLK>,
888 <&gcc SATA_RX 1062 <&gcc SATA_RXOOB_CLK>,
889 <&gcc SATA_PM 1063 <&gcc SATA_PMALIVE_CLK>;
890 clock-names = "slave_i 1064 clock-names = "slave_iface",
891 "iface", 1065 "iface",
892 "core", !! 1066 "bus",
893 "rxoob", 1067 "rxoob",
894 "pmalive !! 1068 "core_pmalive";
895 1069
896 assigned-clocks = <&gc 1070 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
897 <&gc 1071 <&gcc SATA_PMALIVE_CLK>;
898 assigned-clock-rates = 1072 assigned-clock-rates = <100000000>, <100000000>;
899 1073
900 phys = <&sata_phy0>; 1074 phys = <&sata_phy0>;
901 phy-names = "sata-phy" 1075 phy-names = "sata-phy";
902 ports-implemented = <0 1076 ports-implemented = <0x1>;
903 }; 1077 };
904 1078
905 sdcc3: mmc@12180000 { 1079 sdcc3: mmc@12180000 {
906 compatible = "arm,pl18 1080 compatible = "arm,pl18x", "arm,primecell";
907 arm,primecell-periphid 1081 arm,primecell-periphid = <0x00051180>;
908 status = "disabled"; 1082 status = "disabled";
909 reg = <0x12180000 0x20 1083 reg = <0x12180000 0x2000>;
910 interrupts = <GIC_SPI 1084 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&gcc SDC3_CL 1085 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
912 clock-names = "mclk", 1086 clock-names = "mclk", "apb_pclk";
913 bus-width = <4>; 1087 bus-width = <4>;
914 cap-sd-highspeed; 1088 cap-sd-highspeed;
915 cap-mmc-highspeed; 1089 cap-mmc-highspeed;
916 max-frequency = <19200 1090 max-frequency = <192000000>;
917 no-1-8-v; 1091 no-1-8-v;
918 dmas = <&sdcc3bam 2>, 1092 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
919 dma-names = "tx", "rx" 1093 dma-names = "tx", "rx";
920 }; 1094 };
921 1095
922 sdcc3bam: dma-controller@12182 1096 sdcc3bam: dma-controller@12182000 {
923 compatible = "qcom,bam 1097 compatible = "qcom,bam-v1.3.0";
924 reg = <0x12182000 0x80 1098 reg = <0x12182000 0x8000>;
925 interrupts = <GIC_SPI !! 1099 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&gcc SDC3_H_ 1100 clocks = <&gcc SDC3_H_CLK>;
927 clock-names = "bam_clk 1101 clock-names = "bam_clk";
928 #dma-cells = <1>; 1102 #dma-cells = <1>;
929 qcom,ee = <0>; 1103 qcom,ee = <0>;
930 }; 1104 };
931 1105
932 sdcc4: mmc@121c0000 { 1106 sdcc4: mmc@121c0000 {
933 compatible = "arm,pl18 1107 compatible = "arm,pl18x", "arm,primecell";
934 arm,primecell-periphid 1108 arm,primecell-periphid = <0x00051180>;
935 status = "disabled"; 1109 status = "disabled";
936 reg = <0x121c0000 0x20 1110 reg = <0x121c0000 0x2000>;
937 interrupts = <GIC_SPI 1111 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&gcc SDC4_CL 1112 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
939 clock-names = "mclk", 1113 clock-names = "mclk", "apb_pclk";
940 bus-width = <4>; 1114 bus-width = <4>;
941 cap-sd-highspeed; 1115 cap-sd-highspeed;
942 cap-mmc-highspeed; 1116 cap-mmc-highspeed;
943 max-frequency = <48000 1117 max-frequency = <48000000>;
944 dmas = <&sdcc4bam 2>, 1118 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
945 dma-names = "tx", "rx" 1119 dma-names = "tx", "rx";
946 pinctrl-names = "defau 1120 pinctrl-names = "default";
947 pinctrl-0 = <&sdc4_def !! 1121 pinctrl-0 = <&sdc4_gpios>;
948 }; 1122 };
949 1123
950 sdcc4bam: dma-controller@121c2 1124 sdcc4bam: dma-controller@121c2000 {
951 compatible = "qcom,bam 1125 compatible = "qcom,bam-v1.3.0";
952 reg = <0x121c2000 0x80 1126 reg = <0x121c2000 0x8000>;
953 interrupts = <GIC_SPI !! 1127 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&gcc SDC4_H_ 1128 clocks = <&gcc SDC4_H_CLK>;
955 clock-names = "bam_clk 1129 clock-names = "bam_clk";
956 #dma-cells = <1>; 1130 #dma-cells = <1>;
957 qcom,ee = <0>; 1131 qcom,ee = <0>;
958 }; 1132 };
959 1133
960 sdcc1: mmc@12400000 { 1134 sdcc1: mmc@12400000 {
961 status = "disabled"; 1135 status = "disabled";
962 compatible = "arm,pl18 1136 compatible = "arm,pl18x", "arm,primecell";
963 pinctrl-names = "defau 1137 pinctrl-names = "default";
964 pinctrl-0 = <&sdcc1_de !! 1138 pinctrl-0 = <&sdcc1_pins>;
965 arm,primecell-periphid 1139 arm,primecell-periphid = <0x00051180>;
966 reg = <0x12400000 0x20 1140 reg = <0x12400000 0x2000>;
967 interrupts = <GIC_SPI 1141 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&gcc SDC1_CL 1142 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
969 clock-names = "mclk", 1143 clock-names = "mclk", "apb_pclk";
970 bus-width = <8>; 1144 bus-width = <8>;
971 max-frequency = <96000 1145 max-frequency = <96000000>;
972 non-removable; 1146 non-removable;
973 cap-sd-highspeed; 1147 cap-sd-highspeed;
974 cap-mmc-highspeed; 1148 cap-mmc-highspeed;
975 dmas = <&sdcc1bam 2>, 1149 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
976 dma-names = "tx", "rx" 1150 dma-names = "tx", "rx";
977 }; 1151 };
978 1152
979 sdcc1bam: dma-controller@12402 1153 sdcc1bam: dma-controller@12402000 {
980 compatible = "qcom,bam 1154 compatible = "qcom,bam-v1.3.0";
981 reg = <0x12402000 0x80 1155 reg = <0x12402000 0x8000>;
982 interrupts = <GIC_SPI !! 1156 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&gcc SDC1_H_ 1157 clocks = <&gcc SDC1_H_CLK>;
984 clock-names = "bam_clk 1158 clock-names = "bam_clk";
985 #dma-cells = <1>; 1159 #dma-cells = <1>;
986 qcom,ee = <0>; 1160 qcom,ee = <0>;
987 }; 1161 };
988 1162
989 tcsr: syscon@1a400000 { 1163 tcsr: syscon@1a400000 {
990 compatible = "qcom,tcs 1164 compatible = "qcom,tcsr-apq8064", "syscon";
991 reg = <0x1a400000 0x10 1165 reg = <0x1a400000 0x100>;
992 }; 1166 };
993 1167
994 gpu: gpu@4300000 { !! 1168 gpu: adreno-3xx@4300000 {
995 compatible = "qcom,adr 1169 compatible = "qcom,adreno-320.2", "qcom,adreno";
996 reg = <0x04300000 0x20 1170 reg = <0x04300000 0x20000>;
997 reg-names = "kgsl_3d0_ 1171 reg-names = "kgsl_3d0_reg_memory";
998 interrupts = <GIC_SPI 1172 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
999 interrupt-names = "kgs 1173 interrupt-names = "kgsl_3d0_irq";
1000 clock-names = 1174 clock-names =
1001 "core", 1175 "core",
1002 "iface", 1176 "iface",
1003 "mem", 1177 "mem",
1004 "mem_iface"; 1178 "mem_iface";
1005 clocks = 1179 clocks =
1006 <&mmcc GFX3D_CLK> 1180 <&mmcc GFX3D_CLK>,
1007 <&mmcc GFX3D_AHB_ 1181 <&mmcc GFX3D_AHB_CLK>,
1008 <&mmcc GFX3D_AXI_ 1182 <&mmcc GFX3D_AXI_CLK>,
1009 <&mmcc MMSS_IMEM_ 1183 <&mmcc MMSS_IMEM_AHB_CLK>;
1010 1184
1011 iommus = <&gfx3d 0 1185 iommus = <&gfx3d 0
1012 &gfx3d 1 1186 &gfx3d 1
1013 &gfx3d 2 1187 &gfx3d 2
1014 &gfx3d 3 1188 &gfx3d 3
1015 &gfx3d 4 1189 &gfx3d 4
1016 &gfx3d 5 1190 &gfx3d 5
1017 &gfx3d 6 1191 &gfx3d 6
1018 &gfx3d 7 1192 &gfx3d 7
1019 &gfx3d 8 1193 &gfx3d 8
1020 &gfx3d 9 1194 &gfx3d 9
1021 &gfx3d 10 1195 &gfx3d 10
1022 &gfx3d 11 1196 &gfx3d 11
1023 &gfx3d 12 1197 &gfx3d 12
1024 &gfx3d 13 1198 &gfx3d 13
1025 &gfx3d 14 1199 &gfx3d 14
1026 &gfx3d 15 1200 &gfx3d 15
1027 &gfx3d 16 1201 &gfx3d 16
1028 &gfx3d 17 1202 &gfx3d 17
1029 &gfx3d 18 1203 &gfx3d 18
1030 &gfx3d 19 1204 &gfx3d 19
1031 &gfx3d 20 1205 &gfx3d 20
1032 &gfx3d 21 1206 &gfx3d 21
1033 &gfx3d 22 1207 &gfx3d 22
1034 &gfx3d 23 1208 &gfx3d 23
1035 &gfx3d 24 1209 &gfx3d 24
1036 &gfx3d 25 1210 &gfx3d 25
1037 &gfx3d 26 1211 &gfx3d 26
1038 &gfx3d 27 1212 &gfx3d 27
1039 &gfx3d 28 1213 &gfx3d 28
1040 &gfx3d 29 1214 &gfx3d 29
1041 &gfx3d 30 1215 &gfx3d 30
1042 &gfx3d 31 1216 &gfx3d 31
1043 &gfx3d1 0 1217 &gfx3d1 0
1044 &gfx3d1 1 1218 &gfx3d1 1
1045 &gfx3d1 2 1219 &gfx3d1 2
1046 &gfx3d1 3 1220 &gfx3d1 3
1047 &gfx3d1 4 1221 &gfx3d1 4
1048 &gfx3d1 5 1222 &gfx3d1 5
1049 &gfx3d1 6 1223 &gfx3d1 6
1050 &gfx3d1 7 1224 &gfx3d1 7
1051 &gfx3d1 8 1225 &gfx3d1 8
1052 &gfx3d1 9 1226 &gfx3d1 9
1053 &gfx3d1 10 1227 &gfx3d1 10
1054 &gfx3d1 11 1228 &gfx3d1 11
1055 &gfx3d1 12 1229 &gfx3d1 12
1056 &gfx3d1 13 1230 &gfx3d1 13
1057 &gfx3d1 14 1231 &gfx3d1 14
1058 &gfx3d1 15 1232 &gfx3d1 15
1059 &gfx3d1 16 1233 &gfx3d1 16
1060 &gfx3d1 17 1234 &gfx3d1 17
1061 &gfx3d1 18 1235 &gfx3d1 18
1062 &gfx3d1 19 1236 &gfx3d1 19
1063 &gfx3d1 20 1237 &gfx3d1 20
1064 &gfx3d1 21 1238 &gfx3d1 21
1065 &gfx3d1 22 1239 &gfx3d1 22
1066 &gfx3d1 23 1240 &gfx3d1 23
1067 &gfx3d1 24 1241 &gfx3d1 24
1068 &gfx3d1 25 1242 &gfx3d1 25
1069 &gfx3d1 26 1243 &gfx3d1 26
1070 &gfx3d1 27 1244 &gfx3d1 27
1071 &gfx3d1 28 1245 &gfx3d1 28
1072 &gfx3d1 29 1246 &gfx3d1 29
1073 &gfx3d1 30 1247 &gfx3d1 30
1074 &gfx3d1 31> 1248 &gfx3d1 31>;
1075 1249
1076 operating-points-v2 = 1250 operating-points-v2 = <&gpu_opp_table>;
1077 1251
1078 gpu_opp_table: opp-ta 1252 gpu_opp_table: opp-table {
1079 compatible = 1253 compatible = "operating-points-v2";
1080 1254
1081 opp-450000000 1255 opp-450000000 {
1082 opp-h 1256 opp-hz = /bits/ 64 <450000000>;
1083 }; 1257 };
1084 1258
1085 opp-27000000 1259 opp-27000000 {
1086 opp-h 1260 opp-hz = /bits/ 64 <27000000>;
1087 }; 1261 };
1088 }; 1262 };
1089 }; 1263 };
1090 1264
1091 mmss_sfpb: syscon@5700000 { 1265 mmss_sfpb: syscon@5700000 {
1092 compatible = "syscon" 1266 compatible = "syscon";
1093 reg = <0x5700000 0x70 1267 reg = <0x5700000 0x70>;
1094 }; 1268 };
1095 1269
1096 dsi0: dsi@4700000 { 1270 dsi0: dsi@4700000 {
1097 compatible = "qcom,ap 1271 compatible = "qcom,apq8064-dsi-ctrl",
1098 "qcom,md 1272 "qcom,mdss-dsi-ctrl";
>> 1273 label = "MDSS DSI CTRL->0";
1099 #address-cells = <1>; 1274 #address-cells = <1>;
1100 #size-cells = <0>; 1275 #size-cells = <0>;
1101 interrupts = <GIC_SPI 1276 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1102 reg = <0x04700000 0x2 1277 reg = <0x04700000 0x200>;
1103 reg-names = "dsi_ctrl 1278 reg-names = "dsi_ctrl";
1104 1279
1105 clocks = <&mmcc DSI_M 1280 clocks = <&mmcc DSI_M_AHB_CLK>,
1106 <&mmcc DSI_S_ 1281 <&mmcc DSI_S_AHB_CLK>,
1107 <&mmcc AMP_AH 1282 <&mmcc AMP_AHB_CLK>,
1108 <&mmcc DSI_CL 1283 <&mmcc DSI_CLK>,
1109 <&mmcc DSI1_B 1284 <&mmcc DSI1_BYTE_CLK>,
1110 <&mmcc DSI_PI 1285 <&mmcc DSI_PIXEL_CLK>,
1111 <&mmcc DSI1_E 1286 <&mmcc DSI1_ESC_CLK>;
1112 clock-names = "iface" 1287 clock-names = "iface", "bus", "core_mmss",
1113 "src" 1288 "src", "byte", "pixel",
1114 "core 1289 "core";
1115 1290
1116 assigned-clocks = <&m 1291 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1117 <&mmc 1292 <&mmcc DSI1_ESC_SRC>,
1118 <&mmc 1293 <&mmcc DSI_SRC>,
1119 <&mmc 1294 <&mmcc DSI_PIXEL_SRC>;
1120 assigned-clock-parent 1295 assigned-clock-parents = <&dsi0_phy 0>,
1121 1296 <&dsi0_phy 0>,
1122 1297 <&dsi0_phy 1>,
1123 1298 <&dsi0_phy 1>;
1124 syscon-sfpb = <&mmss_ 1299 syscon-sfpb = <&mmss_sfpb>;
1125 phys = <&dsi0_phy>; 1300 phys = <&dsi0_phy>;
1126 status = "disabled"; 1301 status = "disabled";
1127 1302
1128 ports { 1303 ports {
1129 #address-cell 1304 #address-cells = <1>;
1130 #size-cells = 1305 #size-cells = <0>;
1131 1306
1132 port@0 { 1307 port@0 {
1133 reg = 1308 reg = <0>;
1134 dsi0_ 1309 dsi0_in: endpoint {
1135 }; 1310 };
1136 }; 1311 };
1137 1312
1138 port@1 { 1313 port@1 {
1139 reg = 1314 reg = <1>;
1140 dsi0_ 1315 dsi0_out: endpoint {
1141 }; 1316 };
1142 }; 1317 };
1143 }; 1318 };
1144 }; 1319 };
1145 1320
1146 1321
1147 dsi0_phy: phy@4700200 { 1322 dsi0_phy: phy@4700200 {
1148 compatible = "qcom,ds 1323 compatible = "qcom,dsi-phy-28nm-8960";
1149 #clock-cells = <1>; 1324 #clock-cells = <1>;
1150 #phy-cells = <0>; 1325 #phy-cells = <0>;
1151 1326
1152 reg = <0x04700200 0x1 1327 reg = <0x04700200 0x100>,
1153 <0x04700300 0 1328 <0x04700300 0x200>,
1154 <0x04700500 0 1329 <0x04700500 0x5c>;
1155 reg-names = "dsi_pll" 1330 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1156 clock-names = "iface" 1331 clock-names = "iface", "ref";
1157 clocks = <&mmcc DSI_M 1332 clocks = <&mmcc DSI_M_AHB_CLK>,
1158 <&pxo_board> 1333 <&pxo_board>;
1159 status = "disabled"; 1334 status = "disabled";
1160 }; 1335 };
1161 1336
1162 dsi1: dsi@5800000 { 1337 dsi1: dsi@5800000 {
1163 compatible = "qcom,md 1338 compatible = "qcom,mdss-dsi-ctrl";
1164 interrupts = <GIC_SPI 1339 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1165 reg = <0x05800000 0x2 1340 reg = <0x05800000 0x200>;
1166 reg-names = "dsi_ctrl 1341 reg-names = "dsi_ctrl";
1167 1342
1168 clocks = <&mmcc DSI2_ 1343 clocks = <&mmcc DSI2_M_AHB_CLK>,
1169 <&mmcc DSI2_ 1344 <&mmcc DSI2_S_AHB_CLK>,
1170 <&mmcc AMP_A 1345 <&mmcc AMP_AHB_CLK>,
1171 <&mmcc DSI2_ 1346 <&mmcc DSI2_CLK>,
1172 <&mmcc DSI2_ 1347 <&mmcc DSI2_BYTE_CLK>,
1173 <&mmcc DSI2_ 1348 <&mmcc DSI2_PIXEL_CLK>,
1174 <&mmcc DSI2_ 1349 <&mmcc DSI2_ESC_CLK>;
1175 clock-names = "iface" 1350 clock-names = "iface",
1176 "bus", 1351 "bus",
1177 "core_m 1352 "core_mmss",
1178 "src", 1353 "src",
1179 "byte", 1354 "byte",
1180 "pixel" 1355 "pixel",
1181 "core"; 1356 "core";
1182 1357
1183 assigned-clocks = <&m 1358 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1184 <&m 1359 <&mmcc DSI2_ESC_SRC>,
1185 <&m 1360 <&mmcc DSI2_SRC>,
1186 <&m 1361 <&mmcc DSI2_PIXEL_SRC>;
1187 assigned-clock-parent 1362 assigned-clock-parents = <&dsi1_phy 0>,
1188 1363 <&dsi1_phy 0>,
1189 1364 <&dsi1_phy 1>,
1190 1365 <&dsi1_phy 1>;
1191 1366
1192 syscon-sfpb = <&mmss_ 1367 syscon-sfpb = <&mmss_sfpb>;
1193 phys = <&dsi1_phy>; 1368 phys = <&dsi1_phy>;
1194 1369
1195 #address-cells = <1>; 1370 #address-cells = <1>;
1196 #size-cells = <0>; 1371 #size-cells = <0>;
1197 1372
1198 status = "disabled"; 1373 status = "disabled";
1199 1374
1200 ports { 1375 ports {
1201 #address-cell 1376 #address-cells = <1>;
1202 #size-cells = 1377 #size-cells = <0>;
1203 1378
1204 port@0 { 1379 port@0 {
1205 reg = 1380 reg = <0>;
1206 dsi1_ 1381 dsi1_in: endpoint {
1207 }; 1382 };
1208 }; 1383 };
1209 1384
1210 port@1 { 1385 port@1 {
1211 reg = 1386 reg = <1>;
1212 dsi1_ 1387 dsi1_out: endpoint {
1213 }; 1388 };
1214 }; 1389 };
1215 }; 1390 };
1216 }; 1391 };
1217 1392
1218 1393
1219 dsi1_phy: dsi-phy@5800200 { 1394 dsi1_phy: dsi-phy@5800200 {
1220 compatible = "qcom,ds 1395 compatible = "qcom,dsi-phy-28nm-8960";
1221 reg = <0x05800200 0x1 1396 reg = <0x05800200 0x100>,
1222 <0x05800300 0x2 1397 <0x05800300 0x200>,
1223 <0x05800500 0x5 1398 <0x05800500 0x5c>;
1224 reg-names = "dsi_pll" 1399 reg-names = "dsi_pll",
1225 "dsi_phy" 1400 "dsi_phy",
1226 "dsi_phy_ 1401 "dsi_phy_regulator";
1227 clock-names = "iface" 1402 clock-names = "iface",
1228 "ref"; 1403 "ref";
1229 clocks = <&mmcc DSI2_ 1404 clocks = <&mmcc DSI2_M_AHB_CLK>,
1230 <&pxo_board> 1405 <&pxo_board>;
1231 #clock-cells = <1>; 1406 #clock-cells = <1>;
1232 #phy-cells = <0>; 1407 #phy-cells = <0>;
1233 1408
1234 status = "disabled"; 1409 status = "disabled";
1235 }; 1410 };
1236 1411
1237 mdp_port0: iommu@7500000 { 1412 mdp_port0: iommu@7500000 {
1238 compatible = "qcom,ap 1413 compatible = "qcom,apq8064-iommu";
1239 #iommu-cells = <1>; 1414 #iommu-cells = <1>;
1240 clock-names = 1415 clock-names =
1241 "smmu_pclk", 1416 "smmu_pclk",
1242 "iommu_clk"; 1417 "iommu_clk";
1243 clocks = 1418 clocks =
1244 <&mmcc SMMU_AHB_C 1419 <&mmcc SMMU_AHB_CLK>,
1245 <&mmcc MDP_AXI_CL 1420 <&mmcc MDP_AXI_CLK>;
1246 reg = <0x07500000 0x1 1421 reg = <0x07500000 0x100000>;
1247 interrupts = 1422 interrupts =
1248 <GIC_SPI 63 IRQ_T 1423 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 64 IRQ_T 1424 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1250 qcom,ncb = <2>; 1425 qcom,ncb = <2>;
1251 }; 1426 };
1252 1427
1253 mdp_port1: iommu@7600000 { 1428 mdp_port1: iommu@7600000 {
1254 compatible = "qcom,ap 1429 compatible = "qcom,apq8064-iommu";
1255 #iommu-cells = <1>; 1430 #iommu-cells = <1>;
1256 clock-names = 1431 clock-names =
1257 "smmu_pclk", 1432 "smmu_pclk",
1258 "iommu_clk"; 1433 "iommu_clk";
1259 clocks = 1434 clocks =
1260 <&mmcc SMMU_AHB_C 1435 <&mmcc SMMU_AHB_CLK>,
1261 <&mmcc MDP_AXI_CL 1436 <&mmcc MDP_AXI_CLK>;
1262 reg = <0x07600000 0x1 1437 reg = <0x07600000 0x100000>;
1263 interrupts = 1438 interrupts =
1264 <GIC_SPI 61 IRQ_T 1439 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 62 IRQ_T 1440 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1266 qcom,ncb = <2>; 1441 qcom,ncb = <2>;
1267 }; 1442 };
1268 1443
1269 gfx3d: iommu@7c00000 { 1444 gfx3d: iommu@7c00000 {
1270 compatible = "qcom,ap 1445 compatible = "qcom,apq8064-iommu";
1271 #iommu-cells = <1>; 1446 #iommu-cells = <1>;
1272 clock-names = 1447 clock-names =
1273 "smmu_pclk", 1448 "smmu_pclk",
1274 "iommu_clk"; 1449 "iommu_clk";
1275 clocks = 1450 clocks =
1276 <&mmcc SMMU_AHB_C 1451 <&mmcc SMMU_AHB_CLK>,
1277 <&mmcc GFX3D_AXI_ 1452 <&mmcc GFX3D_AXI_CLK>;
1278 reg = <0x07c00000 0x1 1453 reg = <0x07c00000 0x100000>;
1279 interrupts = 1454 interrupts =
1280 <GIC_SPI 69 IRQ_T 1455 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 70 IRQ_T 1456 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1282 qcom,ncb = <3>; 1457 qcom,ncb = <3>;
1283 }; 1458 };
1284 1459
1285 gfx3d1: iommu@7d00000 { 1460 gfx3d1: iommu@7d00000 {
1286 compatible = "qcom,ap 1461 compatible = "qcom,apq8064-iommu";
1287 #iommu-cells = <1>; 1462 #iommu-cells = <1>;
1288 clock-names = 1463 clock-names =
1289 "smmu_pclk", 1464 "smmu_pclk",
1290 "iommu_clk"; 1465 "iommu_clk";
1291 clocks = 1466 clocks =
1292 <&mmcc SMMU_AHB_C 1467 <&mmcc SMMU_AHB_CLK>,
1293 <&mmcc GFX3D_AXI_ 1468 <&mmcc GFX3D_AXI_CLK>;
1294 reg = <0x07d00000 0x1 1469 reg = <0x07d00000 0x100000>;
1295 interrupts = 1470 interrupts =
1296 <GIC_SPI 210 IRQ_ 1471 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 211 IRQ_ 1472 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1298 qcom,ncb = <3>; 1473 qcom,ncb = <3>;
1299 }; 1474 };
1300 1475
1301 pcie: pcie@1b500000 { !! 1476 pcie: pci@1b500000 {
1302 compatible = "qcom,pc 1477 compatible = "qcom,pcie-apq8064";
1303 reg = <0x1b500000 0x1 1478 reg = <0x1b500000 0x1000>,
1304 <0x1b502000 0x8 1479 <0x1b502000 0x80>,
1305 <0x1b600000 0x1 1480 <0x1b600000 0x100>,
1306 <0x0ff00000 0x1 1481 <0x0ff00000 0x100000>;
1307 reg-names = "dbi", "e 1482 reg-names = "dbi", "elbi", "parf", "config";
1308 device_type = "pci"; 1483 device_type = "pci";
1309 linux,pci-domain = <0 1484 linux,pci-domain = <0>;
1310 bus-range = <0x00 0xf 1485 bus-range = <0x00 0xff>;
1311 num-lanes = <1>; 1486 num-lanes = <1>;
1312 #address-cells = <3>; 1487 #address-cells = <3>;
1313 #size-cells = <2>; 1488 #size-cells = <2>;
1314 ranges = <0x81000000 1489 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1315 <0x82000000 1490 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1316 interrupts = <GIC_SPI 1491 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1317 interrupt-names = "ms 1492 interrupt-names = "msi";
1318 #interrupt-cells = <1 1493 #interrupt-cells = <1>;
1319 interrupt-map-mask = 1494 interrupt-map-mask = <0 0 0 0x7>;
1320 interrupt-map = <0 0 1495 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1321 <0 0 1496 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1322 <0 0 1497 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1323 <0 0 1498 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1324 clocks = <&gcc PCIE_A 1499 clocks = <&gcc PCIE_A_CLK>,
1325 <&gcc PCIE_H 1500 <&gcc PCIE_H_CLK>,
1326 <&gcc PCIE_P 1501 <&gcc PCIE_PHY_REF_CLK>;
1327 clock-names = "core", 1502 clock-names = "core", "iface", "phy";
1328 resets = <&gcc PCIE_A 1503 resets = <&gcc PCIE_ACLK_RESET>,
1329 <&gcc PCIE_H 1504 <&gcc PCIE_HCLK_RESET>,
1330 <&gcc PCIE_P 1505 <&gcc PCIE_POR_RESET>,
1331 <&gcc PCIE_P 1506 <&gcc PCIE_PCI_RESET>,
1332 <&gcc PCIE_P 1507 <&gcc PCIE_PHY_RESET>;
1333 reset-names = "axi", 1508 reset-names = "axi", "ahb", "por", "pci", "phy";
1334 status = "disabled"; 1509 status = "disabled";
1335 <<
1336 pcie@0 { <<
1337 device_type = <<
1338 reg = <0x0 0x <<
1339 bus-range = < <<
1340 <<
1341 #address-cell <<
1342 #size-cells = <<
1343 ranges; <<
1344 }; <<
1345 }; 1510 };
1346 1511
1347 hdmi: hdmi-tx@4a00000 { 1512 hdmi: hdmi-tx@4a00000 {
1348 compatible = "qcom,hd 1513 compatible = "qcom,hdmi-tx-8960";
1349 pinctrl-names = "defa 1514 pinctrl-names = "default";
1350 pinctrl-0 = <&hdmi_pi 1515 pinctrl-0 = <&hdmi_pinctrl>;
1351 reg = <0x04a00000 0x2 1516 reg = <0x04a00000 0x2f0>;
1352 reg-names = "core_phy 1517 reg-names = "core_physical";
1353 interrupts = <GIC_SPI 1518 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&mmcc HDMI_ 1519 clocks = <&mmcc HDMI_APP_CLK>,
1355 <&mmcc HDMI_ 1520 <&mmcc HDMI_M_AHB_CLK>,
1356 <&mmcc HDMI_ 1521 <&mmcc HDMI_S_AHB_CLK>;
1357 clock-names = "core", 1522 clock-names = "core",
1358 "master 1523 "master_iface",
1359 "slave_ 1524 "slave_iface";
1360 1525
1361 phys = <&hdmi_phy>; 1526 phys = <&hdmi_phy>;
1362 1527
1363 status = "disabled"; 1528 status = "disabled";
1364 1529
1365 ports { 1530 ports {
1366 #address-cell 1531 #address-cells = <1>;
1367 #size-cells = 1532 #size-cells = <0>;
1368 1533
1369 port@0 { 1534 port@0 {
1370 reg = 1535 reg = <0>;
1371 hdmi_ 1536 hdmi_in: endpoint {
1372 }; 1537 };
1373 }; 1538 };
1374 1539
1375 port@1 { 1540 port@1 {
1376 reg = 1541 reg = <1>;
1377 hdmi_ 1542 hdmi_out: endpoint {
1378 }; 1543 };
1379 }; 1544 };
1380 }; 1545 };
1381 }; 1546 };
1382 1547
1383 hdmi_phy: phy@4a00400 { 1548 hdmi_phy: phy@4a00400 {
1384 compatible = "qcom,hd 1549 compatible = "qcom,hdmi-phy-8960";
1385 reg = <0x4a00400 0x60 1550 reg = <0x4a00400 0x60>,
1386 <0x4a00500 0x10 1551 <0x4a00500 0x100>;
1387 reg-names = "hdmi_phy 1552 reg-names = "hdmi_phy",
1388 "hdmi_pll 1553 "hdmi_pll";
1389 1554
1390 clocks = <&mmcc HDMI_ 1555 clocks = <&mmcc HDMI_S_AHB_CLK>;
1391 clock-names = "slave_ 1556 clock-names = "slave_iface";
1392 #phy-cells = <0>; 1557 #phy-cells = <0>;
1393 #clock-cells = <0>; 1558 #clock-cells = <0>;
1394 1559
1395 status = "disabled"; 1560 status = "disabled";
1396 }; 1561 };
1397 1562
1398 mdp: display-controller@51000 1563 mdp: display-controller@5100000 {
1399 compatible = "qcom,md 1564 compatible = "qcom,mdp4";
1400 reg = <0x05100000 0xf 1565 reg = <0x05100000 0xf0000>;
1401 interrupts = <GIC_SPI 1566 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1402 clocks = <&mmcc MDP_C 1567 clocks = <&mmcc MDP_CLK>,
1403 <&mmcc MDP_A 1568 <&mmcc MDP_AHB_CLK>,
1404 <&mmcc MDP_A 1569 <&mmcc MDP_AXI_CLK>,
1405 <&mmcc MDP_L 1570 <&mmcc MDP_LUT_CLK>,
1406 <&mmcc HDMI_ 1571 <&mmcc HDMI_TV_CLK>,
1407 <&mmcc MDP_T 1572 <&mmcc MDP_TV_CLK>;
1408 clock-names = "core_c 1573 clock-names = "core_clk",
1409 "iface_ 1574 "iface_clk",
1410 "bus_cl 1575 "bus_clk",
1411 "lut_cl 1576 "lut_clk",
1412 "hdmi_c 1577 "hdmi_clk",
1413 "tv_clk 1578 "tv_clk";
1414 1579
1415 iommus = <&mdp_port0 1580 iommus = <&mdp_port0 0
1416 &mdp_port0 1581 &mdp_port0 2
1417 &mdp_port1 1582 &mdp_port1 0
1418 &mdp_port1 1583 &mdp_port1 2>;
1419 1584
1420 ports { 1585 ports {
1421 #address-cell 1586 #address-cells = <1>;
1422 #size-cells = 1587 #size-cells = <0>;
1423 1588
1424 port@0 { 1589 port@0 {
1425 reg = 1590 reg = <0>;
1426 mdp_l 1591 mdp_lvds_out: endpoint {
1427 }; 1592 };
1428 }; 1593 };
1429 1594
1430 port@1 { 1595 port@1 {
1431 reg = 1596 reg = <1>;
1432 mdp_d 1597 mdp_dsi1_out: endpoint {
1433 }; 1598 };
1434 }; 1599 };
1435 1600
1436 port@2 { 1601 port@2 {
1437 reg = 1602 reg = <2>;
1438 mdp_d 1603 mdp_dsi2_out: endpoint {
1439 }; 1604 };
1440 }; 1605 };
1441 1606
1442 port@3 { 1607 port@3 {
1443 reg = 1608 reg = <3>;
1444 mdp_d 1609 mdp_dtv_out: endpoint {
1445 }; 1610 };
1446 }; 1611 };
1447 }; 1612 };
1448 }; 1613 };
1449 1614
1450 riva: riva-pil@3200800 { 1615 riva: riva-pil@3200800 {
1451 compatible = "qcom,ri 1616 compatible = "qcom,riva-pil";
1452 1617
1453 reg = <0x03200800 0x1 1618 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1454 reg-names = "ccu", "d 1619 reg-names = "ccu", "dxe", "pmu";
1455 1620
1456 interrupts-extended = 1621 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1457 1622 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1458 interrupt-names = "wd 1623 interrupt-names = "wdog", "fatal";
1459 1624
1460 memory-region = <&wcn 1625 memory-region = <&wcnss_mem>;
1461 1626
>> 1627 vddcx-supply = <&pm8921_s3>;
>> 1628 vddmx-supply = <&pm8921_l24>;
>> 1629 vddpx-supply = <&pm8921_s4>;
>> 1630
1462 status = "disabled"; 1631 status = "disabled";
1463 1632
1464 iris { 1633 iris {
1465 compatible = 1634 compatible = "qcom,wcn3660";
1466 1635
1467 clocks = <&cx 1636 clocks = <&cxo_board>;
1468 clock-names = 1637 clock-names = "xo";
>> 1638
>> 1639 vddxo-supply = <&pm8921_l4>;
>> 1640 vddrfa-supply = <&pm8921_s2>;
>> 1641 vddpa-supply = <&pm8921_l10>;
>> 1642 vdddig-supply = <&pm8921_lvs2>;
1469 }; 1643 };
1470 1644
1471 smd-edge { 1645 smd-edge {
1472 interrupts = 1646 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1473 1647
1474 qcom,ipc = <& 1648 qcom,ipc = <&l2cc 8 25>;
1475 qcom,smd-edge 1649 qcom,smd-edge = <6>;
1476 1650
1477 label = "riva 1651 label = "riva";
1478 1652
1479 wcnss { 1653 wcnss {
1480 compa 1654 compatible = "qcom,wcnss";
1481 qcom, 1655 qcom,smd-channels = "WCNSS_CTRL";
1482 1656
1483 qcom, 1657 qcom,mmio = <&riva>;
1484 1658
1485 bluet 1659 bluetooth {
1486 1660 compatible = "qcom,wcnss-bt";
1487 }; 1661 };
1488 1662
1489 wifi 1663 wifi {
1490 1664 compatible = "qcom,wcnss-wlan";
1491 1665
1492 1666 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1493 1667 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1494 1668 interrupt-names = "tx", "rx";
1495 1669
1496 1670 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1497 1671 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1498 }; 1672 };
1499 }; 1673 };
1500 }; 1674 };
1501 }; 1675 };
1502 1676
1503 etb@1a01000 { 1677 etb@1a01000 {
1504 compatible = "arm,cor 1678 compatible = "arm,coresight-etb10", "arm,primecell";
1505 reg = <0x1a01000 0x10 1679 reg = <0x1a01000 0x1000>;
1506 1680
1507 clocks = <&rpmcc RPM_ 1681 clocks = <&rpmcc RPM_QDSS_CLK>;
1508 clock-names = "apb_pc 1682 clock-names = "apb_pclk";
1509 1683
1510 in-ports { 1684 in-ports {
1511 port { 1685 port {
1512 etb_i 1686 etb_in: endpoint {
1513 1687 remote-endpoint = <&replicator_out0>;
1514 }; 1688 };
1515 }; 1689 };
1516 }; 1690 };
1517 }; 1691 };
1518 1692
1519 tpiu@1a03000 { 1693 tpiu@1a03000 {
1520 compatible = "arm,cor 1694 compatible = "arm,coresight-tpiu", "arm,primecell";
1521 reg = <0x1a03000 0x10 1695 reg = <0x1a03000 0x1000>;
1522 1696
1523 clocks = <&rpmcc RPM_ 1697 clocks = <&rpmcc RPM_QDSS_CLK>;
1524 clock-names = "apb_pc 1698 clock-names = "apb_pclk";
1525 1699
1526 in-ports { 1700 in-ports {
1527 port { 1701 port {
1528 tpiu_ 1702 tpiu_in: endpoint {
1529 1703 remote-endpoint = <&replicator_out1>;
1530 }; 1704 };
1531 }; 1705 };
1532 }; 1706 };
1533 }; 1707 };
1534 1708
1535 replicator { 1709 replicator {
1536 compatible = "arm,cor 1710 compatible = "arm,coresight-static-replicator";
1537 1711
1538 clocks = <&rpmcc RPM_ 1712 clocks = <&rpmcc RPM_QDSS_CLK>;
1539 clock-names = "apb_pc 1713 clock-names = "apb_pclk";
1540 1714
1541 out-ports { 1715 out-ports {
1542 #address-cell 1716 #address-cells = <1>;
1543 #size-cells = 1717 #size-cells = <0>;
1544 1718
1545 port@0 { 1719 port@0 {
1546 reg = 1720 reg = <0>;
1547 repli 1721 replicator_out0: endpoint {
1548 1722 remote-endpoint = <&etb_in>;
1549 }; 1723 };
1550 }; 1724 };
1551 port@1 { 1725 port@1 {
1552 reg = 1726 reg = <1>;
1553 repli 1727 replicator_out1: endpoint {
1554 1728 remote-endpoint = <&tpiu_in>;
1555 }; 1729 };
1556 }; 1730 };
1557 }; 1731 };
1558 1732
1559 in-ports { 1733 in-ports {
1560 port { 1734 port {
1561 repli 1735 replicator_in: endpoint {
1562 1736 remote-endpoint = <&funnel_out>;
1563 }; 1737 };
1564 }; 1738 };
1565 }; 1739 };
1566 }; 1740 };
1567 1741
1568 funnel@1a04000 { 1742 funnel@1a04000 {
1569 compatible = "arm,cor 1743 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1570 reg = <0x1a04000 0x10 1744 reg = <0x1a04000 0x1000>;
1571 1745
1572 clocks = <&rpmcc RPM_ 1746 clocks = <&rpmcc RPM_QDSS_CLK>;
1573 clock-names = "apb_pc 1747 clock-names = "apb_pclk";
1574 1748
1575 in-ports { 1749 in-ports {
1576 #address-cell 1750 #address-cells = <1>;
1577 #size-cells = 1751 #size-cells = <0>;
1578 1752
1579 /* 1753 /*
1580 * Not descri 1754 * Not described input ports:
1581 * 2 - connec 1755 * 2 - connected to STM component
1582 * 3 - not-co 1756 * 3 - not-connected
1583 * 6 - not-co 1757 * 6 - not-connected
1584 * 7 - not-co 1758 * 7 - not-connected
1585 */ 1759 */
1586 port@0 { 1760 port@0 {
1587 reg = 1761 reg = <0>;
1588 funne 1762 funnel_in0: endpoint {
1589 1763 remote-endpoint = <&etm0_out>;
1590 }; 1764 };
1591 }; 1765 };
1592 port@1 { 1766 port@1 {
1593 reg = 1767 reg = <1>;
1594 funne 1768 funnel_in1: endpoint {
1595 1769 remote-endpoint = <&etm1_out>;
1596 }; 1770 };
1597 }; 1771 };
1598 port@4 { 1772 port@4 {
1599 reg = 1773 reg = <4>;
1600 funne 1774 funnel_in4: endpoint {
1601 1775 remote-endpoint = <&etm2_out>;
1602 }; 1776 };
1603 }; 1777 };
1604 port@5 { 1778 port@5 {
1605 reg = 1779 reg = <5>;
1606 funne 1780 funnel_in5: endpoint {
1607 1781 remote-endpoint = <&etm3_out>;
1608 }; 1782 };
1609 }; 1783 };
1610 }; 1784 };
1611 1785
1612 out-ports { 1786 out-ports {
1613 port { 1787 port {
1614 funne 1788 funnel_out: endpoint {
1615 1789 remote-endpoint = <&replicator_in>;
1616 }; 1790 };
1617 }; 1791 };
1618 }; 1792 };
1619 }; 1793 };
1620 1794
1621 etm@1a1c000 { 1795 etm@1a1c000 {
1622 compatible = "arm,cor 1796 compatible = "arm,coresight-etm3x", "arm,primecell";
1623 reg = <0x1a1c000 0x10 1797 reg = <0x1a1c000 0x1000>;
1624 1798
1625 clocks = <&rpmcc RPM_ 1799 clocks = <&rpmcc RPM_QDSS_CLK>;
1626 clock-names = "apb_pc 1800 clock-names = "apb_pclk";
1627 1801
1628 cpu = <&CPU0>; 1802 cpu = <&CPU0>;
1629 1803
1630 out-ports { 1804 out-ports {
1631 port { 1805 port {
1632 etm0_ 1806 etm0_out: endpoint {
1633 1807 remote-endpoint = <&funnel_in0>;
1634 }; 1808 };
1635 }; 1809 };
1636 }; 1810 };
1637 }; 1811 };
1638 1812
1639 etm@1a1d000 { 1813 etm@1a1d000 {
1640 compatible = "arm,cor 1814 compatible = "arm,coresight-etm3x", "arm,primecell";
1641 reg = <0x1a1d000 0x10 1815 reg = <0x1a1d000 0x1000>;
1642 1816
1643 clocks = <&rpmcc RPM_ 1817 clocks = <&rpmcc RPM_QDSS_CLK>;
1644 clock-names = "apb_pc 1818 clock-names = "apb_pclk";
1645 1819
1646 cpu = <&CPU1>; 1820 cpu = <&CPU1>;
1647 1821
1648 out-ports { 1822 out-ports {
1649 port { 1823 port {
1650 etm1_ 1824 etm1_out: endpoint {
1651 1825 remote-endpoint = <&funnel_in1>;
1652 }; 1826 };
1653 }; 1827 };
1654 }; 1828 };
1655 }; 1829 };
1656 1830
1657 etm@1a1e000 { 1831 etm@1a1e000 {
1658 compatible = "arm,cor 1832 compatible = "arm,coresight-etm3x", "arm,primecell";
1659 reg = <0x1a1e000 0x10 1833 reg = <0x1a1e000 0x1000>;
1660 1834
1661 clocks = <&rpmcc RPM_ 1835 clocks = <&rpmcc RPM_QDSS_CLK>;
1662 clock-names = "apb_pc 1836 clock-names = "apb_pclk";
1663 1837
1664 cpu = <&CPU2>; 1838 cpu = <&CPU2>;
1665 1839
1666 out-ports { 1840 out-ports {
1667 port { 1841 port {
1668 etm2_ 1842 etm2_out: endpoint {
1669 1843 remote-endpoint = <&funnel_in4>;
1670 }; 1844 };
1671 }; 1845 };
1672 }; 1846 };
1673 }; 1847 };
1674 1848
1675 etm@1a1f000 { 1849 etm@1a1f000 {
1676 compatible = "arm,cor 1850 compatible = "arm,coresight-etm3x", "arm,primecell";
1677 reg = <0x1a1f000 0x10 1851 reg = <0x1a1f000 0x1000>;
1678 1852
1679 clocks = <&rpmcc RPM_ 1853 clocks = <&rpmcc RPM_QDSS_CLK>;
1680 clock-names = "apb_pc 1854 clock-names = "apb_pclk";
1681 1855
1682 cpu = <&CPU3>; 1856 cpu = <&CPU3>;
1683 1857
1684 out-ports { 1858 out-ports {
1685 port { 1859 port {
1686 etm3_ 1860 etm3_out: endpoint {
1687 1861 remote-endpoint = <&funnel_in5>;
1688 }; 1862 };
1689 }; 1863 };
1690 }; 1864 };
1691 }; 1865 };
1692 }; 1866 };
1693 }; 1867 };
1694 #include "qcom-apq8064-pins.dtsi" 1868 #include "qcom-apq8064-pins.dtsi"
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