1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/interrupt-controller/arm
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h
11 #include <dt-bindings/soc/qcom,gsbi.h>
12 #include <dt-bindings/interrupt-controller/arm
13
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Qualcomm IPQ8064";
18 compatible = "qcom,ipq8064";
19 interrupt-parent = <&intc>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "qcom,kra
27 enable-method = "qcom,
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L
31 qcom,acc = <&acc0>;
32 qcom,saw = <&saw0>;
33 };
34
35 cpu1: cpu@1 {
36 compatible = "qcom,kra
37 enable-method = "qcom,
38 device_type = "cpu";
39 reg = <1>;
40 next-level-cache = <&L
41 qcom,acc = <&acc1>;
42 qcom,saw = <&saw1>;
43 };
44
45 L2: l2-cache {
46 compatible = "cache";
47 cache-level = <2>;
48 cache-unified;
49 };
50 };
51
52 thermal-zones {
53 sensor0-thermal {
54 polling-delay-passive
55 polling-delay = <0>;
56 thermal-sensors = <&ts
57
58 trips {
59 cpu-critical {
60 temper
61 hyster
62 type =
63 };
64
65 cpu-hot {
66 temper
67 hyster
68 type =
69 };
70 };
71 };
72
73 sensor1-thermal {
74 polling-delay-passive
75 polling-delay = <0>;
76 thermal-sensors = <&ts
77
78 trips {
79 cpu-critical {
80 temper
81 hyster
82 type =
83 };
84
85 cpu-hot {
86 temper
87 hyster
88 type =
89 };
90 };
91 };
92
93 sensor2-thermal {
94 polling-delay-passive
95 polling-delay = <0>;
96 thermal-sensors = <&ts
97
98 trips {
99 cpu-critical {
100 temper
101 hyster
102 type =
103 };
104
105 cpu-hot {
106 temper
107 hyster
108 type =
109 };
110 };
111 };
112
113 sensor3-thermal {
114 polling-delay-passive
115 polling-delay = <0>;
116 thermal-sensors = <&ts
117
118 trips {
119 cpu-critical {
120 temper
121 hyster
122 type =
123 };
124
125 cpu-hot {
126 temper
127 hyster
128 type =
129 };
130 };
131 };
132
133 sensor4-thermal {
134 polling-delay-passive
135 polling-delay = <0>;
136 thermal-sensors = <&ts
137
138 trips {
139 cpu-critical {
140 temper
141 hyster
142 type =
143 };
144
145 cpu-hot {
146 temper
147 hyster
148 type =
149 };
150 };
151 };
152
153 sensor5-thermal {
154 polling-delay-passive
155 polling-delay = <0>;
156 thermal-sensors = <&ts
157
158 trips {
159 cpu-critical {
160 temper
161 hyster
162 type =
163 };
164
165 cpu-hot {
166 temper
167 hyster
168 type =
169 };
170 };
171 };
172
173 sensor6-thermal {
174 polling-delay-passive
175 polling-delay = <0>;
176 thermal-sensors = <&ts
177
178 trips {
179 cpu-critical {
180 temper
181 hyster
182 type =
183 };
184
185 cpu-hot {
186 temper
187 hyster
188 type =
189 };
190 };
191 };
192
193 sensor7-thermal {
194 polling-delay-passive
195 polling-delay = <0>;
196 thermal-sensors = <&ts
197
198 trips {
199 cpu-critical {
200 temper
201 hyster
202 type =
203 };
204
205 cpu-hot {
206 temper
207 hyster
208 type =
209 };
210 };
211 };
212
213 sensor8-thermal {
214 polling-delay-passive
215 polling-delay = <0>;
216 thermal-sensors = <&ts
217
218 trips {
219 cpu-critical {
220 temper
221 hyster
222 type =
223 };
224
225 cpu-hot {
226 temper
227 hyster
228 type =
229 };
230 };
231 };
232
233 sensor9-thermal {
234 polling-delay-passive
235 polling-delay = <0>;
236 thermal-sensors = <&ts
237
238 trips {
239 cpu-critical {
240 temper
241 hyster
242 type =
243 };
244
245 cpu-hot {
246 temper
247 hyster
248 type =
249 };
250 };
251 };
252
253 sensor10-thermal {
254 polling-delay-passive
255 polling-delay = <0>;
256 thermal-sensors = <&ts
257
258 trips {
259 cpu-critical {
260 temper
261 hyster
262 type =
263 };
264
265 cpu-hot {
266 temper
267 hyster
268 type =
269 };
270 };
271 };
272 };
273
274 memory {
275 device_type = "memory";
276 reg = <0x0 0x0>;
277 };
278
279 cpu-pmu {
280 compatible = "qcom,krait-pmu";
281 interrupts = <GIC_PPI 10 (GIC_
282 IRQ_
283 };
284
285 reserved-memory {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges;
289
290 nss@40000000 {
291 reg = <0x40000000 0x10
292 no-map;
293 };
294
295 smem: smem@41000000 {
296 compatible = "qcom,sme
297 reg = <0x41000000 0x20
298 no-map;
299
300 hwlocks = <&sfpb_mutex
301 };
302 };
303
304 clocks {
305 cxo_board: cxo_board {
306 compatible = "fixed-cl
307 #clock-cells = <0>;
308 clock-frequency = <250
309 };
310
311 pxo_board: pxo_board {
312 compatible = "fixed-cl
313 #clock-cells = <0>;
314 clock-frequency = <250
315 };
316
317 sleep_clk: sleep_clk {
318 compatible = "fixed-cl
319 clock-frequency = <327
320 #clock-cells = <0>;
321 };
322 };
323
324 firmware {
325 scm {
326 compatible = "qcom,scm
327 };
328 };
329
330 stmmac_axi_setup: stmmac-axi-config {
331 snps,wr_osr_lmt = <7>;
332 snps,rd_osr_lmt = <7>;
333 snps,blen = <16 0 0 0 0 0 0>;
334 };
335
336 vsdcc_fixed: vsdcc-regulator {
337 compatible = "regulator-fixed"
338 regulator-name = "SDCC Power";
339 regulator-min-microvolt = <330
340 regulator-max-microvolt = <330
341 regulator-always-on;
342 };
343
344 soc: soc {
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges;
348 compatible = "simple-bus";
349
350 rpm: rpm@108000 {
351 compatible = "qcom,rpm
352 reg = <0x00108000 0x10
353 qcom,ipc = <&l2cc 0x8
354
355 interrupts = <GIC_SPI
356 <GIC_S
357 <GIC_S
358 interrupt-names = "ack
359
360 clocks = <&gcc RPM_MSG
361 clock-names = "ram";
362
363 rpmcc: clock-controlle
364 compatible = "
365 #clock-cells =
366 };
367 };
368
369 ssbi@500000 {
370 compatible = "qcom,ssb
371 reg = <0x00500000 0x10
372 qcom,controller-type =
373 };
374
375 qfprom: efuse@700000 {
376 compatible = "qcom,ipq
377 reg = <0x00700000 0x10
378 #address-cells = <1>;
379 #size-cells = <1>;
380 speedbin_efuse: speedb
381 reg = <0xc0 0x
382 };
383 tsens_calib: calib@400
384 reg = <0x400 0
385 };
386 tsens_calib_backup: ca
387 reg = <0x410 0
388 };
389 };
390
391 qcom_pinmux: pinmux@800000 {
392 compatible = "qcom,ipq
393 reg = <0x00800000 0x40
394
395 gpio-controller;
396 gpio-ranges = <&qcom_p
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>
400 interrupts = <GIC_SPI
401
402 pcie0_pins: pcie0-stat
403 pins = "gpio3"
404 function = "pc
405 drive-strength
406 bias-disable;
407 };
408
409 pcie1_pins: pcie1-stat
410 pins = "gpio48
411 function = "pc
412 drive-strength
413 bias-disable;
414 };
415
416 pcie2_pins: pcie2-stat
417 pins = "gpio63
418 function = "pc
419 drive-strength
420 bias-disable;
421 };
422
423 i2c4_pins: i2c4-state
424 pins = "gpio12
425 function = "gs
426 drive-strength
427 bias-disable;
428 };
429
430 spi_pins: spi-state {
431 pins = "gpio18
432 function = "gs
433 drive-strength
434 bias-disable;
435 };
436
437 leds_pins: leds-state
438 pins = "gpio7"
439 "gpio2
440 function = "gp
441 drive-strength
442 bias-pull-down
443 output-low;
444 };
445
446 buttons_pins: buttons-
447 pins = "gpio54
448 drive-strength
449 bias-pull-up;
450 };
451
452 nand_pins: nand-state
453 nand-pins {
454 pins =
455
456
457
458
459 functi
460 drive-
461 bias-d
462 };
463
464 nand-pullup-pi
465 pins =
466 functi
467 drive-
468 bias-p
469 };
470
471 nand-hold-pins
472 pins =
473
474
475 functi
476 drive-
477 bias-b
478 };
479 };
480
481 mdio0_pins: mdio0-stat
482 pins = "gpio0"
483 function = "md
484 drive-strength
485 bias-disable;
486 };
487
488 rgmii2_pins: rgmii2-st
489 pins = "gpio27
490 "gpio3
491 "gpio5
492 "gpio6
493 function = "rg
494 drive-strength
495 bias-disable;
496 };
497 };
498
499 gcc: clock-controller@900000 {
500 compatible = "qcom,gcc
501 clocks = <&pxo_board>,
502 clock-names = "pxo", "
503 reg = <0x00900000 0x40
504 #clock-cells = <1>;
505 #reset-cells = <1>;
506
507 tsens: thermal-sensor
508 compatible = "
509
510 nvmem-cells =
511 nvmem-cell-nam
512 interrupts = <
513 interrupt-name
514
515 #qcom,sensors
516 #thermal-senso
517 };
518 };
519
520 sfpb_mutex: hwlock@1200600 {
521 compatible = "qcom,sfp
522 reg = <0x01200600 0x10
523
524 #hwlock-cells = <1>;
525 };
526
527 intc: interrupt-controller@200
528 compatible = "qcom,msm
529 interrupt-controller;
530 #interrupt-cells = <3>
531 reg = <0x02000000 0x10
532 <0x02002000 0x10
533 };
534
535 timer@200a000 {
536 compatible = "qcom,kps
537 "qcom,msm
538 interrupts = <GIC_PPI
539
540 <GIC_PPI
541
542 <GIC_PPI
543
544 <GIC_PPI
545
546 <GIC_PPI
547
548 reg = <0x0200a000 0x10
549 clock-frequency = <250
550 clocks = <&sleep_clk>;
551 clock-names = "sleep";
552 cpu-offset = <0x80000>
553 };
554
555 l2cc: clock-controller@2011000
556 compatible = "qcom,kps
557 reg = <0x02011000 0x10
558 clocks = <&gcc PLL8_VO
559 clock-names = "pll8_vo
560 #clock-cells = <0>;
561 };
562
563 acc0: clock-controller@2088000
564 compatible = "qcom,kps
565 reg = <0x02088000 0x10
566 clocks = <&gcc PLL8_VO
567 clock-names = "pll8_vo
568 clock-output-names = "
569 #clock-cells = <0>;
570 };
571
572 saw0: power-manager@2089000 {
573 compatible = "qcom,ipq
574 reg = <0x02089000 0x10
575 };
576
577 acc1: clock-controller@2098000
578 compatible = "qcom,kps
579 reg = <0x02098000 0x10
580 clocks = <&gcc PLL8_VO
581 clock-names = "pll8_vo
582 clock-output-names = "
583 #clock-cells = <0>;
584 };
585
586 saw1: power-manager@2099000 {
587 compatible = "qcom,ipq
588 reg = <0x02099000 0x10
589 };
590
591 nss_common: syscon@3000000 {
592 compatible = "syscon";
593 reg = <0x03000000 0x00
594 };
595
596 usb3_0: usb@100f8800 {
597 compatible = "qcom,ipq
598 #address-cells = <1>;
599 #size-cells = <1>;
600 reg = <0x100f8800 0x80
601 clocks = <&gcc USB30_0
602 clock-names = "core";
603
604 ranges;
605
606 resets = <&gcc USB30_0
607
608 status = "disabled";
609
610 dwc3_0: usb@10000000 {
611 compatible = "
612 reg = <0x10000
613 interrupts = <
614 phys = <&hs_ph
615 phy-names = "u
616 dr_mode = "hos
617 snps,dis_u3_su
618 };
619 };
620
621 hs_phy_0: phy@100f8800 {
622 compatible = "qcom,ipq
623 reg = <0x100f8800 0x30
624 clocks = <&gcc USB30_0
625 clock-names = "ref";
626 #phy-cells = <0>;
627
628 status = "disabled";
629 };
630
631 ss_phy_0: phy@100f8830 {
632 compatible = "qcom,ipq
633 reg = <0x100f8830 0x30
634 clocks = <&gcc USB30_0
635 clock-names = "ref";
636 #phy-cells = <0>;
637
638 status = "disabled";
639 };
640
641 usb3_1: usb@110f8800 {
642 compatible = "qcom,ipq
643 #address-cells = <1>;
644 #size-cells = <1>;
645 reg = <0x110f8800 0x80
646 clocks = <&gcc USB30_1
647 clock-names = "core";
648
649 ranges;
650
651 resets = <&gcc USB30_1
652
653 status = "disabled";
654
655 dwc3_1: usb@11000000 {
656 compatible = "
657 reg = <0x11000
658 interrupts = <
659 phys = <&hs_ph
660 phy-names = "u
661 dr_mode = "hos
662 snps,dis_u3_su
663 };
664 };
665
666 hs_phy_1: phy@110f8800 {
667 compatible = "qcom,ipq
668 reg = <0x110f8800 0x30
669 clocks = <&gcc USB30_1
670 clock-names = "ref";
671 #phy-cells = <0>;
672
673 status = "disabled";
674 };
675
676 ss_phy_1: phy@110f8830 {
677 compatible = "qcom,ipq
678 reg = <0x110f8830 0x30
679 clocks = <&gcc USB30_1
680 clock-names = "ref";
681 #phy-cells = <0>;
682
683 status = "disabled";
684 };
685
686 sdcc3bam: dma-controller@12182
687 compatible = "qcom,bam
688 reg = <0x12182000 0x80
689 interrupts = <GIC_SPI
690 clocks = <&gcc SDC3_H_
691 clock-names = "bam_clk
692 #dma-cells = <1>;
693 qcom,ee = <0>;
694 };
695
696 sdcc1bam: dma-controller@12402
697 compatible = "qcom,bam
698 reg = <0x12402000 0x80
699 interrupts = <GIC_SPI
700 clocks = <&gcc SDC1_H_
701 clock-names = "bam_clk
702 #dma-cells = <1>;
703 qcom,ee = <0>;
704 };
705
706 amba: amba {
707 compatible = "simple-b
708 #address-cells = <1>;
709 #size-cells = <1>;
710 ranges;
711
712 sdcc3: mmc@12180000 {
713 compatible = "
714 arm,primecell-
715 status = "disa
716 reg = <0x12180
717 interrupts = <
718 clocks = <&gcc
719 clock-names =
720 bus-width = <8
721 cap-sd-highspe
722 cap-mmc-highsp
723 max-frequency
724 sd-uhs-sdr104;
725 sd-uhs-ddr50;
726 vqmmc-supply =
727 dmas = <&sdcc3
728 dma-names = "t
729 };
730
731 sdcc1: mmc@12400000 {
732 status = "disa
733 compatible = "
734 arm,primecell-
735 reg = <0x12400
736 interrupts = <
737 clocks = <&gcc
738 clock-names =
739 bus-width = <8
740 max-frequency
741 non-removable;
742 cap-sd-highspe
743 cap-mmc-highsp
744 vmmc-supply =
745 dmas = <&sdcc1
746 dma-names = "t
747 };
748 };
749
750 gsbi1: gsbi@12440000 {
751 compatible = "qcom,gsb
752 reg = <0x12440000 0x10
753 cell-index = <1>;
754 clocks = <&gcc GSBI1_H
755 clock-names = "iface";
756 #address-cells = <1>;
757 #size-cells = <1>;
758 ranges;
759
760 syscon-tcsr = <&tcsr>;
761
762 status = "disabled";
763
764 gsbi1_serial: serial@1
765 compatible = "
766 reg = <0x12450
767 <0x12400
768 interrupts = <
769 clocks = <&gcc
770 clock-names =
771
772 status = "disa
773 };
774
775 gsbi1_i2c: i2c@1246000
776 compatible = "
777 reg = <0x12460
778 interrupts = <
779 clocks = <&gcc
780 clock-names =
781 #address-cells
782 #size-cells =
783
784 status = "disa
785 };
786 };
787
788 gsbi2: gsbi@12480000 {
789 compatible = "qcom,gsb
790 cell-index = <2>;
791 reg = <0x12480000 0x10
792 clocks = <&gcc GSBI2_H
793 clock-names = "iface";
794 #address-cells = <1>;
795 #size-cells = <1>;
796 ranges;
797 status = "disabled";
798
799 syscon-tcsr = <&tcsr>;
800
801 gsbi2_serial: serial@1
802 compatible = "
803 reg = <0x12490
804 <0x12480
805 interrupts = <
806 clocks = <&gcc
807 clock-names =
808 status = "disa
809 };
810
811 gsbi2_i2c: i2c@124a000
812 compatible = "
813 reg = <0x124a0
814 interrupts = <
815
816 clocks = <&gcc
817 clock-names =
818 status = "disa
819
820 #address-cells
821 #size-cells =
822 };
823 };
824
825 gsbi4: gsbi@16300000 {
826 compatible = "qcom,gsb
827 cell-index = <4>;
828 reg = <0x16300000 0x10
829 clocks = <&gcc GSBI4_H
830 clock-names = "iface";
831 #address-cells = <1>;
832 #size-cells = <1>;
833 ranges;
834 status = "disabled";
835
836 syscon-tcsr = <&tcsr>;
837
838 gsbi4_serial: serial@1
839 compatible = "
840 reg = <0x16340
841 <0x16300
842 interrupts = <
843 clocks = <&gcc
844 clock-names =
845 status = "disa
846 };
847
848 i2c@16380000 {
849 compatible = "
850 reg = <0x16380
851 interrupts = <
852
853 clocks = <&gcc
854 clock-names =
855 status = "disa
856
857 #address-cells
858 #size-cells =
859 };
860 };
861
862 gsbi6: gsbi@16500000 {
863 compatible = "qcom,gsb
864 reg = <0x16500000 0x10
865 cell-index = <6>;
866 clocks = <&gcc GSBI6_H
867 clock-names = "iface";
868 #address-cells = <1>;
869 #size-cells = <1>;
870 ranges;
871
872 syscon-tcsr = <&tcsr>;
873
874 status = "disabled";
875
876 gsbi6_i2c: i2c@1658000
877 compatible = "
878 reg = <0x16580
879 interrupts = <
880
881 clocks = <&gcc
882 clock-names =
883
884 #address-cells
885 #size-cells =
886
887 status = "disa
888 };
889
890 gsbi6_spi: spi@1658000
891 compatible = "
892 reg = <0x16580
893 interrupts = <
894
895 clocks = <&gcc
896 clock-names =
897
898 #address-cells
899 #size-cells =
900
901 status = "disa
902 };
903 };
904
905 gsbi7: gsbi@16600000 {
906 status = "disabled";
907 compatible = "qcom,gsb
908 cell-index = <7>;
909 reg = <0x16600000 0x10
910 clocks = <&gcc GSBI7_H
911 clock-names = "iface";
912 #address-cells = <1>;
913 #size-cells = <1>;
914 ranges;
915 syscon-tcsr = <&tcsr>;
916
917 gsbi7_serial: serial@1
918 compatible = "
919 reg = <0x16640
920 <0x16600
921 interrupts = <
922 clocks = <&gcc
923 clock-names =
924 status = "disa
925 };
926
927 gsbi7_i2c: i2c@1668000
928 compatible = "
929 reg = <0x16680
930 interrupts = <
931
932 clocks = <&gcc
933 clock-names =
934
935 #address-cells
936 #size-cells =
937
938 status = "disa
939 };
940 };
941
942 adm_dma: dma-controller@183000
943 compatible = "qcom,adm
944 reg = <0x18300000 0x10
945 interrupts = <GIC_SPI
946 #dma-cells = <1>;
947
948 clocks = <&gcc ADM0_CL
949 clock-names = "core",
950
951 resets = <&gcc ADM0_RE
952 <&gcc ADM0_PB
953 <&gcc ADM0_C0
954 <&gcc ADM0_C1
955 <&gcc ADM0_C2
956 reset-names = "clk", "
957 qcom,ee = <0>;
958
959 status = "disabled";
960 };
961
962 gsbi5: gsbi@1a200000 {
963 compatible = "qcom,gsb
964 cell-index = <5>;
965 reg = <0x1a200000 0x10
966 clocks = <&gcc GSBI5_H
967 clock-names = "iface";
968 #address-cells = <1>;
969
970 #size-cells = <1>;
971 ranges;
972 status = "disabled";
973
974 syscon-tcsr = <&tcsr>;
975
976 gsbi5_serial: serial@1
977 compatible = "
978 reg = <0x1a240
979 <0x1a200
980 interrupts = <
981 clocks = <&gcc
982 clock-names =
983 status = "disa
984 };
985
986 i2c@1a280000 {
987 compatible = "
988 reg = <0x1a280
989 interrupts = <
990
991 clocks = <&gcc
992 clock-names =
993 status = "disa
994
995 #address-cells
996 #size-cells =
997 };
998
999 spi@1a280000 {
1000 compatible =
1001 reg = <0x1a28
1002 interrupts =
1003
1004 clocks = <&gc
1005 clock-names =
1006 status = "dis
1007
1008 #address-cell
1009 #size-cells =
1010 };
1011 };
1012
1013 tcsr: syscon@1a400000 {
1014 compatible = "qcom,tc
1015 reg = <0x1a400000 0x1
1016 };
1017
1018 rng@1a500000 {
1019 compatible = "qcom,pr
1020 reg = <0x1a500000 0x2
1021 clocks = <&gcc PRNG_C
1022 clock-names = "core";
1023 };
1024
1025 nand: nand-controller@1ac0000
1026 compatible = "qcom,ip
1027 reg = <0x1ac00000 0x8
1028
1029 pinctrl-0 = <&nand_pi
1030 pinctrl-names = "defa
1031
1032 clocks = <&gcc EBI2_C
1033 <&gcc EBI2_A
1034 clock-names = "core",
1035
1036 dmas = <&adm_dma 3>;
1037 dma-names = "rxtx";
1038 qcom,cmd-crci = <15>;
1039 qcom,data-crci = <3>;
1040
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043
1044 status = "disabled";
1045 };
1046
1047 sata_phy: sata-phy@1b400000 {
1048 compatible = "qcom,ip
1049 reg = <0x1b400000 0x2
1050
1051 clocks = <&gcc SATA_P
1052 clock-names = "cfg";
1053
1054 #phy-cells = <0>;
1055 status = "disabled";
1056 };
1057
1058 pcie0: pcie@1b500000 {
1059 compatible = "qcom,pc
1060 reg = <0x1b500000 0x1
1061 0x1b502000 0x8
1062 0x1b600000 0x1
1063 0x0ff00000 0x1
1064 reg-names = "dbi", "e
1065 device_type = "pci";
1066 linux,pci-domain = <0
1067 bus-range = <0x00 0xf
1068 num-lanes = <1>;
1069 #address-cells = <3>;
1070 #size-cells = <2>;
1071
1072 ranges = <0x81000000
1073 0x82000000
1074
1075 interrupts = <GIC_SPI
1076 interrupt-names = "ms
1077 #interrupt-cells = <1
1078 interrupt-map-mask =
1079 interrupt-map = <0 0
1080 <0 0
1081 <0 0
1082 <0 0
1083
1084 clocks = <&gcc PCIE_A
1085 <&gcc PCIE_H
1086 <&gcc PCIE_P
1087 <&gcc PCIE_A
1088 <&gcc PCIE_A
1089 clock-names = "core",
1090
1091 assigned-clocks = <&g
1092 assigned-clock-rates
1093
1094 resets = <&gcc PCIE_A
1095 <&gcc PCIE_H
1096 <&gcc PCIE_P
1097 <&gcc PCIE_P
1098 <&gcc PCIE_P
1099 <&gcc PCIE_E
1100 reset-names = "axi",
1101
1102 pinctrl-0 = <&pcie0_p
1103 pinctrl-names = "defa
1104
1105 status = "disabled";
1106 perst-gpios = <&qcom_
1107
1108 pcie@0 {
1109 device_type =
1110 reg = <0x0 0x
1111 bus-range = <
1112
1113 #address-cell
1114 #size-cells =
1115 ranges;
1116 };
1117 };
1118
1119 pcie1: pcie@1b700000 {
1120 compatible = "qcom,pc
1121 reg = <0x1b700000 0x1
1122 0x1b702000 0x8
1123 0x1b800000 0x1
1124 0x31f00000 0x1
1125 reg-names = "dbi", "e
1126 device_type = "pci";
1127 linux,pci-domain = <1
1128 bus-range = <0x00 0xf
1129 num-lanes = <1>;
1130 #address-cells = <3>;
1131 #size-cells = <2>;
1132
1133 ranges = <0x81000000
1134 0x82000000
1135
1136 interrupts = <GIC_SPI
1137 interrupt-names = "ms
1138 #interrupt-cells = <1
1139 interrupt-map-mask =
1140 interrupt-map = <0 0
1141 <0 0
1142 <0 0
1143 <0 0
1144
1145 clocks = <&gcc PCIE_1
1146 <&gcc PCIE_1
1147 <&gcc PCIE_1
1148 <&gcc PCIE_1
1149 <&gcc PCIE_1
1150 clock-names = "core",
1151
1152 assigned-clocks = <&g
1153 assigned-clock-rates
1154
1155 resets = <&gcc PCIE_1
1156 <&gcc PCIE_1
1157 <&gcc PCIE_1
1158 <&gcc PCIE_1
1159 <&gcc PCIE_1
1160 <&gcc PCIE_1
1161 reset-names = "axi",
1162
1163 pinctrl-0 = <&pcie1_p
1164 pinctrl-names = "defa
1165
1166 status = "disabled";
1167 perst-gpios = <&qcom_
1168
1169 pcie@0 {
1170 device_type =
1171 reg = <0x0 0x
1172 bus-range = <
1173
1174 #address-cell
1175 #size-cells =
1176 ranges;
1177 };
1178 };
1179
1180 pcie2: pcie@1b900000 {
1181 compatible = "qcom,pc
1182 reg = <0x1b900000 0x1
1183 0x1b902000 0x8
1184 0x1ba00000 0x1
1185 0x35f00000 0x1
1186 reg-names = "dbi", "e
1187 device_type = "pci";
1188 linux,pci-domain = <2
1189 bus-range = <0x00 0xf
1190 num-lanes = <1>;
1191 #address-cells = <3>;
1192 #size-cells = <2>;
1193
1194 ranges = <0x81000000
1195 0x82000000
1196
1197 interrupts = <GIC_SPI
1198 interrupt-names = "ms
1199 #interrupt-cells = <1
1200 interrupt-map-mask =
1201 interrupt-map = <0 0
1202 <0 0
1203 <0 0
1204 <0 0
1205
1206 clocks = <&gcc PCIE_2
1207 <&gcc PCIE_2
1208 <&gcc PCIE_2
1209 <&gcc PCIE_2
1210 <&gcc PCIE_2
1211 clock-names = "core",
1212
1213 assigned-clocks = <&g
1214 assigned-clock-rates
1215
1216 resets = <&gcc PCIE_2
1217 <&gcc PCIE_2
1218 <&gcc PCIE_2
1219 <&gcc PCIE_2
1220 <&gcc PCIE_2
1221 <&gcc PCIE_2
1222 reset-names = "axi",
1223
1224 pinctrl-0 = <&pcie2_p
1225 pinctrl-names = "defa
1226
1227 status = "disabled";
1228 perst-gpios = <&qcom_
1229
1230 pcie@0 {
1231 device_type =
1232 reg = <0x0 0x
1233 bus-range = <
1234
1235 #address-cell
1236 #size-cells =
1237 ranges;
1238 };
1239 };
1240
1241 qsgmii_csr: syscon@1bb00000 {
1242 compatible = "syscon"
1243 reg = <0x1bb00000 0x0
1244 };
1245
1246 lcc: clock-controller@2800000
1247 compatible = "qcom,lc
1248 reg = <0x28000000 0x1
1249 #clock-cells = <1>;
1250 #reset-cells = <1>;
1251 };
1252
1253 lpass@28100000 {
1254 compatible = "qcom,lp
1255 status = "disabled";
1256 clocks = <&lcc AHBIX_
1257 <&lcc
1258 <&lcc
1259 clock-names = "ahbix-
1260 "mi2s
1261 "mi2s
1262 interrupts = <GIC_SPI
1263 interrupt-names = "lp
1264 reg = <0x28100000 0x1
1265 reg-names = "lpass-lp
1266 };
1267
1268 sata: sata@29000000 {
1269 compatible = "qcom,ip
1270 reg = <0x29000000 0x1
1271
1272 interrupts = <GIC_SPI
1273
1274 clocks = <&gcc SFAB_S
1275 <&gcc SATA_H
1276 <&gcc SATA_A
1277 <&gcc SATA_R
1278 <&gcc SATA_P
1279 clock-names = "slave_
1280 "rxoo
1281
1282 assigned-clocks = <&g
1283 assigned-clock-rates
1284
1285 phys = <&sata_phy>;
1286 phy-names = "sata-phy
1287 status = "disabled";
1288 };
1289
1290 gmac0: ethernet@37000000 {
1291 device_type = "networ
1292 compatible = "qcom,ip
1293 reg = <0x37000000 0x2
1294 interrupts = <GIC_SPI
1295 interrupt-names = "ma
1296
1297 snps,axi-config = <&s
1298 snps,pbl = <32>;
1299 snps,aal;
1300
1301 qcom,nss-common = <&n
1302 qcom,qsgmii-csr = <&q
1303
1304 clocks = <&gcc GMAC_C
1305 clock-names = "stmmac
1306
1307 resets = <&gcc GMAC_C
1308 <&gcc GMAC_A
1309 reset-names = "stmmac
1310
1311 status = "disabled";
1312 };
1313
1314 gmac1: ethernet@37200000 {
1315 device_type = "networ
1316 compatible = "qcom,ip
1317 reg = <0x37200000 0x2
1318 interrupts = <GIC_SPI
1319 interrupt-names = "ma
1320
1321 snps,axi-config = <&s
1322 snps,pbl = <32>;
1323 snps,aal;
1324
1325 qcom,nss-common = <&n
1326 qcom,qsgmii-csr = <&q
1327
1328 clocks = <&gcc GMAC_C
1329 clock-names = "stmmac
1330
1331 resets = <&gcc GMAC_C
1332 <&gcc GMAC_A
1333 reset-names = "stmmac
1334
1335 status = "disabled";
1336 };
1337
1338 gmac2: ethernet@37400000 {
1339 device_type = "networ
1340 compatible = "qcom,ip
1341 reg = <0x37400000 0x2
1342 interrupts = <GIC_SPI
1343 interrupt-names = "ma
1344
1345 snps,axi-config = <&s
1346 snps,pbl = <32>;
1347 snps,aal;
1348
1349 qcom,nss-common = <&n
1350 qcom,qsgmii-csr = <&q
1351
1352 clocks = <&gcc GMAC_C
1353 clock-names = "stmmac
1354
1355 resets = <&gcc GMAC_C
1356 <&gcc GMAC_A
1357 reset-names = "stmmac
1358
1359 status = "disabled";
1360 };
1361
1362 gmac3: ethernet@37600000 {
1363 device_type = "networ
1364 compatible = "qcom,ip
1365 reg = <0x37600000 0x2
1366 interrupts = <GIC_SPI
1367 interrupt-names = "ma
1368
1369 snps,axi-config = <&s
1370 snps,pbl = <32>;
1371 snps,aal;
1372
1373 qcom,nss-common = <&n
1374 qcom,qsgmii-csr = <&q
1375
1376 clocks = <&gcc GMAC_C
1377 clock-names = "stmmac
1378
1379 resets = <&gcc GMAC_C
1380 <&gcc GMAC_A
1381 reset-names = "stmmac
1382
1383 status = "disabled";
1384 };
1385 };
1386 };
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