1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h> 5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h> 6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h 7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h 8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h 10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h> 11 #include <dt-bindings/soc/qcom,gsbi.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 13
14 / { 14 / {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 model = "Qualcomm IPQ8064"; 17 model = "Qualcomm IPQ8064";
18 compatible = "qcom,ipq8064"; 18 compatible = "qcom,ipq8064";
19 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
20 20
21 cpus { 21 cpus {
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <0>; 23 #size-cells = <0>;
24 24
25 cpu0: cpu@0 { 25 cpu0: cpu@0 {
26 compatible = "qcom,kra 26 compatible = "qcom,krait";
27 enable-method = "qcom, 27 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu"; 28 device_type = "cpu";
29 reg = <0>; 29 reg = <0>;
30 next-level-cache = <&L 30 next-level-cache = <&L2>;
31 qcom,acc = <&acc0>; 31 qcom,acc = <&acc0>;
32 qcom,saw = <&saw0>; 32 qcom,saw = <&saw0>;
33 }; 33 };
34 34
35 cpu1: cpu@1 { 35 cpu1: cpu@1 {
36 compatible = "qcom,kra 36 compatible = "qcom,krait";
37 enable-method = "qcom, 37 enable-method = "qcom,kpss-acc-v1";
38 device_type = "cpu"; 38 device_type = "cpu";
39 reg = <1>; 39 reg = <1>;
40 next-level-cache = <&L 40 next-level-cache = <&L2>;
41 qcom,acc = <&acc1>; 41 qcom,acc = <&acc1>;
42 qcom,saw = <&saw1>; 42 qcom,saw = <&saw1>;
43 }; 43 };
44 44
45 L2: l2-cache { 45 L2: l2-cache {
46 compatible = "cache"; 46 compatible = "cache";
47 cache-level = <2>; 47 cache-level = <2>;
48 cache-unified; 48 cache-unified;
49 }; 49 };
50 }; 50 };
51 51
52 thermal-zones { 52 thermal-zones {
53 sensor0-thermal { 53 sensor0-thermal {
54 polling-delay-passive 54 polling-delay-passive = <0>;
55 polling-delay = <0>; 55 polling-delay = <0>;
56 thermal-sensors = <&ts 56 thermal-sensors = <&tsens 0>;
57 57
58 trips { 58 trips {
59 cpu-critical { 59 cpu-critical {
60 temper 60 temperature = <105000>;
61 hyster 61 hysteresis = <2000>;
62 type = 62 type = "critical";
63 }; 63 };
64 64
65 cpu-hot { 65 cpu-hot {
66 temper 66 temperature = <95000>;
67 hyster 67 hysteresis = <2000>;
68 type = 68 type = "hot";
69 }; 69 };
70 }; 70 };
71 }; 71 };
72 72
73 sensor1-thermal { 73 sensor1-thermal {
74 polling-delay-passive 74 polling-delay-passive = <0>;
75 polling-delay = <0>; 75 polling-delay = <0>;
76 thermal-sensors = <&ts 76 thermal-sensors = <&tsens 1>;
77 77
78 trips { 78 trips {
79 cpu-critical { 79 cpu-critical {
80 temper 80 temperature = <105000>;
81 hyster 81 hysteresis = <2000>;
82 type = 82 type = "critical";
83 }; 83 };
84 84
85 cpu-hot { 85 cpu-hot {
86 temper 86 temperature = <95000>;
87 hyster 87 hysteresis = <2000>;
88 type = 88 type = "hot";
89 }; 89 };
90 }; 90 };
91 }; 91 };
92 92
93 sensor2-thermal { 93 sensor2-thermal {
94 polling-delay-passive 94 polling-delay-passive = <0>;
95 polling-delay = <0>; 95 polling-delay = <0>;
96 thermal-sensors = <&ts 96 thermal-sensors = <&tsens 2>;
97 97
98 trips { 98 trips {
99 cpu-critical { 99 cpu-critical {
100 temper 100 temperature = <105000>;
101 hyster 101 hysteresis = <2000>;
102 type = 102 type = "critical";
103 }; 103 };
104 104
105 cpu-hot { 105 cpu-hot {
106 temper 106 temperature = <95000>;
107 hyster 107 hysteresis = <2000>;
108 type = 108 type = "hot";
109 }; 109 };
110 }; 110 };
111 }; 111 };
112 112
113 sensor3-thermal { 113 sensor3-thermal {
114 polling-delay-passive 114 polling-delay-passive = <0>;
115 polling-delay = <0>; 115 polling-delay = <0>;
116 thermal-sensors = <&ts 116 thermal-sensors = <&tsens 3>;
117 117
118 trips { 118 trips {
119 cpu-critical { 119 cpu-critical {
120 temper 120 temperature = <105000>;
121 hyster 121 hysteresis = <2000>;
122 type = 122 type = "critical";
123 }; 123 };
124 124
125 cpu-hot { 125 cpu-hot {
126 temper 126 temperature = <95000>;
127 hyster 127 hysteresis = <2000>;
128 type = 128 type = "hot";
129 }; 129 };
130 }; 130 };
131 }; 131 };
132 132
133 sensor4-thermal { 133 sensor4-thermal {
134 polling-delay-passive 134 polling-delay-passive = <0>;
135 polling-delay = <0>; 135 polling-delay = <0>;
136 thermal-sensors = <&ts 136 thermal-sensors = <&tsens 4>;
137 137
138 trips { 138 trips {
139 cpu-critical { 139 cpu-critical {
140 temper 140 temperature = <105000>;
141 hyster 141 hysteresis = <2000>;
142 type = 142 type = "critical";
143 }; 143 };
144 144
145 cpu-hot { 145 cpu-hot {
146 temper 146 temperature = <95000>;
147 hyster 147 hysteresis = <2000>;
148 type = 148 type = "hot";
149 }; 149 };
150 }; 150 };
151 }; 151 };
152 152
153 sensor5-thermal { 153 sensor5-thermal {
154 polling-delay-passive 154 polling-delay-passive = <0>;
155 polling-delay = <0>; 155 polling-delay = <0>;
156 thermal-sensors = <&ts 156 thermal-sensors = <&tsens 5>;
157 157
158 trips { 158 trips {
159 cpu-critical { 159 cpu-critical {
160 temper 160 temperature = <105000>;
161 hyster 161 hysteresis = <2000>;
162 type = 162 type = "critical";
163 }; 163 };
164 164
165 cpu-hot { 165 cpu-hot {
166 temper 166 temperature = <95000>;
167 hyster 167 hysteresis = <2000>;
168 type = 168 type = "hot";
169 }; 169 };
170 }; 170 };
171 }; 171 };
172 172
173 sensor6-thermal { 173 sensor6-thermal {
174 polling-delay-passive 174 polling-delay-passive = <0>;
175 polling-delay = <0>; 175 polling-delay = <0>;
176 thermal-sensors = <&ts 176 thermal-sensors = <&tsens 6>;
177 177
178 trips { 178 trips {
179 cpu-critical { 179 cpu-critical {
180 temper 180 temperature = <105000>;
181 hyster 181 hysteresis = <2000>;
182 type = 182 type = "critical";
183 }; 183 };
184 184
185 cpu-hot { 185 cpu-hot {
186 temper 186 temperature = <95000>;
187 hyster 187 hysteresis = <2000>;
188 type = 188 type = "hot";
189 }; 189 };
190 }; 190 };
191 }; 191 };
192 192
193 sensor7-thermal { 193 sensor7-thermal {
194 polling-delay-passive 194 polling-delay-passive = <0>;
195 polling-delay = <0>; 195 polling-delay = <0>;
196 thermal-sensors = <&ts 196 thermal-sensors = <&tsens 7>;
197 197
198 trips { 198 trips {
199 cpu-critical { 199 cpu-critical {
200 temper 200 temperature = <105000>;
201 hyster 201 hysteresis = <2000>;
202 type = 202 type = "critical";
203 }; 203 };
204 204
205 cpu-hot { 205 cpu-hot {
206 temper 206 temperature = <95000>;
207 hyster 207 hysteresis = <2000>;
208 type = 208 type = "hot";
209 }; 209 };
210 }; 210 };
211 }; 211 };
212 212
213 sensor8-thermal { 213 sensor8-thermal {
214 polling-delay-passive 214 polling-delay-passive = <0>;
215 polling-delay = <0>; 215 polling-delay = <0>;
216 thermal-sensors = <&ts 216 thermal-sensors = <&tsens 8>;
217 217
218 trips { 218 trips {
219 cpu-critical { 219 cpu-critical {
220 temper 220 temperature = <105000>;
221 hyster 221 hysteresis = <2000>;
222 type = 222 type = "critical";
223 }; 223 };
224 224
225 cpu-hot { 225 cpu-hot {
226 temper 226 temperature = <95000>;
227 hyster 227 hysteresis = <2000>;
228 type = 228 type = "hot";
229 }; 229 };
230 }; 230 };
231 }; 231 };
232 232
233 sensor9-thermal { 233 sensor9-thermal {
234 polling-delay-passive 234 polling-delay-passive = <0>;
235 polling-delay = <0>; 235 polling-delay = <0>;
236 thermal-sensors = <&ts 236 thermal-sensors = <&tsens 9>;
237 237
238 trips { 238 trips {
239 cpu-critical { 239 cpu-critical {
240 temper 240 temperature = <105000>;
241 hyster 241 hysteresis = <2000>;
242 type = 242 type = "critical";
243 }; 243 };
244 244
245 cpu-hot { 245 cpu-hot {
246 temper 246 temperature = <95000>;
247 hyster 247 hysteresis = <2000>;
248 type = 248 type = "hot";
249 }; 249 };
250 }; 250 };
251 }; 251 };
252 252
253 sensor10-thermal { 253 sensor10-thermal {
254 polling-delay-passive 254 polling-delay-passive = <0>;
255 polling-delay = <0>; 255 polling-delay = <0>;
256 thermal-sensors = <&ts 256 thermal-sensors = <&tsens 10>;
257 257
258 trips { 258 trips {
259 cpu-critical { 259 cpu-critical {
260 temper 260 temperature = <105000>;
261 hyster 261 hysteresis = <2000>;
262 type = 262 type = "critical";
263 }; 263 };
264 264
265 cpu-hot { 265 cpu-hot {
266 temper 266 temperature = <95000>;
267 hyster 267 hysteresis = <2000>;
268 type = 268 type = "hot";
269 }; 269 };
270 }; 270 };
271 }; 271 };
272 }; 272 };
273 273
274 memory { 274 memory {
275 device_type = "memory"; 275 device_type = "memory";
276 reg = <0x0 0x0>; 276 reg = <0x0 0x0>;
277 }; 277 };
278 278
279 cpu-pmu { 279 cpu-pmu {
280 compatible = "qcom,krait-pmu"; 280 compatible = "qcom,krait-pmu";
281 interrupts = <GIC_PPI 10 (GIC_ 281 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
282 IRQ_ 282 IRQ_TYPE_LEVEL_HIGH)>;
283 }; 283 };
284 284
285 reserved-memory { 285 reserved-memory {
286 #address-cells = <1>; 286 #address-cells = <1>;
287 #size-cells = <1>; 287 #size-cells = <1>;
288 ranges; 288 ranges;
289 289
290 nss@40000000 { 290 nss@40000000 {
291 reg = <0x40000000 0x10 291 reg = <0x40000000 0x1000000>;
292 no-map; 292 no-map;
293 }; 293 };
294 294
295 smem: smem@41000000 { 295 smem: smem@41000000 {
296 compatible = "qcom,sme 296 compatible = "qcom,smem";
297 reg = <0x41000000 0x20 297 reg = <0x41000000 0x200000>;
298 no-map; 298 no-map;
299 299
300 hwlocks = <&sfpb_mutex 300 hwlocks = <&sfpb_mutex 3>;
301 }; 301 };
302 }; 302 };
303 303
304 clocks { 304 clocks {
305 cxo_board: cxo_board { 305 cxo_board: cxo_board {
306 compatible = "fixed-cl 306 compatible = "fixed-clock";
307 #clock-cells = <0>; 307 #clock-cells = <0>;
308 clock-frequency = <250 308 clock-frequency = <25000000>;
309 }; 309 };
310 310
311 pxo_board: pxo_board { 311 pxo_board: pxo_board {
312 compatible = "fixed-cl 312 compatible = "fixed-clock";
313 #clock-cells = <0>; 313 #clock-cells = <0>;
314 clock-frequency = <250 314 clock-frequency = <25000000>;
315 }; 315 };
316 316
317 sleep_clk: sleep_clk { 317 sleep_clk: sleep_clk {
318 compatible = "fixed-cl 318 compatible = "fixed-clock";
319 clock-frequency = <327 319 clock-frequency = <32768>;
320 #clock-cells = <0>; 320 #clock-cells = <0>;
321 }; 321 };
322 }; 322 };
323 323
324 firmware { 324 firmware {
325 scm { 325 scm {
326 compatible = "qcom,scm 326 compatible = "qcom,scm-ipq806x", "qcom,scm";
327 }; 327 };
328 }; 328 };
329 329
330 stmmac_axi_setup: stmmac-axi-config { 330 stmmac_axi_setup: stmmac-axi-config {
331 snps,wr_osr_lmt = <7>; 331 snps,wr_osr_lmt = <7>;
332 snps,rd_osr_lmt = <7>; 332 snps,rd_osr_lmt = <7>;
333 snps,blen = <16 0 0 0 0 0 0>; 333 snps,blen = <16 0 0 0 0 0 0>;
334 }; 334 };
335 335
336 vsdcc_fixed: vsdcc-regulator { 336 vsdcc_fixed: vsdcc-regulator {
337 compatible = "regulator-fixed" 337 compatible = "regulator-fixed";
338 regulator-name = "SDCC Power"; 338 regulator-name = "SDCC Power";
339 regulator-min-microvolt = <330 339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <330 340 regulator-max-microvolt = <3300000>;
341 regulator-always-on; 341 regulator-always-on;
342 }; 342 };
343 343
344 soc: soc { 344 soc: soc {
345 #address-cells = <1>; 345 #address-cells = <1>;
346 #size-cells = <1>; 346 #size-cells = <1>;
347 ranges; 347 ranges;
348 compatible = "simple-bus"; 348 compatible = "simple-bus";
349 349
350 rpm: rpm@108000 { 350 rpm: rpm@108000 {
351 compatible = "qcom,rpm 351 compatible = "qcom,rpm-ipq8064";
352 reg = <0x00108000 0x10 352 reg = <0x00108000 0x1000>;
353 qcom,ipc = <&l2cc 0x8 353 qcom,ipc = <&l2cc 0x8 2>;
354 354
355 interrupts = <GIC_SPI 355 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_S 356 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_S 357 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-names = "ack 358 interrupt-names = "ack", "err", "wakeup";
359 359
360 clocks = <&gcc RPM_MSG 360 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
361 clock-names = "ram"; 361 clock-names = "ram";
362 362
363 rpmcc: clock-controlle 363 rpmcc: clock-controller {
364 compatible = " 364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
365 #clock-cells = 365 #clock-cells = <1>;
366 }; 366 };
367 }; 367 };
368 368
369 ssbi@500000 { 369 ssbi@500000 {
370 compatible = "qcom,ssb 370 compatible = "qcom,ssbi";
371 reg = <0x00500000 0x10 371 reg = <0x00500000 0x1000>;
372 qcom,controller-type = 372 qcom,controller-type = "pmic-arbiter";
373 }; 373 };
374 374
375 qfprom: efuse@700000 { !! 375 qfprom: qfprom@700000 {
376 compatible = "qcom,ipq 376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
377 reg = <0x00700000 0x10 377 reg = <0x00700000 0x1000>;
378 #address-cells = <1>; 378 #address-cells = <1>;
379 #size-cells = <1>; 379 #size-cells = <1>;
380 speedbin_efuse: speedb 380 speedbin_efuse: speedbin@c0 {
381 reg = <0xc0 0x 381 reg = <0xc0 0x4>;
382 }; 382 };
383 tsens_calib: calib@400 383 tsens_calib: calib@400 {
384 reg = <0x400 0 384 reg = <0x400 0xb>;
385 }; 385 };
386 tsens_calib_backup: ca 386 tsens_calib_backup: calib_backup@410 {
387 reg = <0x410 0 387 reg = <0x410 0xb>;
388 }; 388 };
389 }; 389 };
390 390
391 qcom_pinmux: pinmux@800000 { 391 qcom_pinmux: pinmux@800000 {
392 compatible = "qcom,ipq 392 compatible = "qcom,ipq8064-pinctrl";
393 reg = <0x00800000 0x40 393 reg = <0x00800000 0x4000>;
394 394
395 gpio-controller; 395 gpio-controller;
396 gpio-ranges = <&qcom_p 396 gpio-ranges = <&qcom_pinmux 0 0 69>;
397 #gpio-cells = <2>; 397 #gpio-cells = <2>;
398 interrupt-controller; 398 interrupt-controller;
399 #interrupt-cells = <2> 399 #interrupt-cells = <2>;
400 interrupts = <GIC_SPI 400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
401 401
402 pcie0_pins: pcie0-stat !! 402 pcie0_pins: pcie0_pinmux {
403 pins = "gpio3" !! 403 mux {
404 function = "pc !! 404 pins = "gpio3";
405 drive-strength !! 405 function = "pcie1_rst";
406 bias-disable; !! 406 drive-strength = <12>;
>> 407 bias-disable;
>> 408 };
407 }; 409 };
408 410
409 pcie1_pins: pcie1-stat !! 411 pcie1_pins: pcie1_pinmux {
410 pins = "gpio48 !! 412 mux {
411 function = "pc !! 413 pins = "gpio48";
412 drive-strength !! 414 function = "pcie2_rst";
413 bias-disable; !! 415 drive-strength = <12>;
>> 416 bias-disable;
>> 417 };
414 }; 418 };
415 419
416 pcie2_pins: pcie2-stat !! 420 pcie2_pins: pcie2_pinmux {
417 pins = "gpio63 !! 421 mux {
418 function = "pc !! 422 pins = "gpio63";
419 drive-strength !! 423 function = "pcie3_rst";
420 bias-disable; !! 424 drive-strength = <12>;
>> 425 bias-disable;
>> 426 };
421 }; 427 };
422 428
423 i2c4_pins: i2c4-state !! 429 i2c4_pins: i2c4-default {
424 pins = "gpio12 430 pins = "gpio12", "gpio13";
425 function = "gs 431 function = "gsbi4";
426 drive-strength 432 drive-strength = <12>;
427 bias-disable; 433 bias-disable;
428 }; 434 };
429 435
430 spi_pins: spi-state { !! 436 spi_pins: spi_pins {
431 pins = "gpio18 !! 437 mux {
432 function = "gs !! 438 pins = "gpio18", "gpio19", "gpio21";
433 drive-strength !! 439 function = "gsbi5";
434 bias-disable; !! 440 drive-strength = <10>;
>> 441 bias-none;
>> 442 };
>> 443 };
>> 444
>> 445 leds_pins: leds_pins {
>> 446 mux {
>> 447 pins = "gpio7", "gpio8", "gpio9",
>> 448 "gpio26", "gpio53";
>> 449 function = "gpio";
>> 450 drive-strength = <2>;
>> 451 bias-pull-down;
>> 452 output-low;
>> 453 };
435 }; 454 };
436 455
437 leds_pins: leds-state !! 456 buttons_pins: buttons_pins {
438 pins = "gpio7" !! 457 mux {
439 "gpio2 !! 458 pins = "gpio54";
440 function = "gp !! 459 drive-strength = <2>;
441 drive-strength !! 460 bias-pull-up;
442 bias-pull-down !! 461 };
443 output-low; <<
444 }; <<
445 <<
446 buttons_pins: buttons- <<
447 pins = "gpio54 <<
448 drive-strength <<
449 bias-pull-up; <<
450 }; 462 };
451 463
452 nand_pins: nand-state !! 464 nand_pins: nand_pins {
453 nand-pins { !! 465 mux {
454 pins = 466 pins = "gpio34", "gpio35", "gpio36",
455 467 "gpio37", "gpio38", "gpio39",
456 468 "gpio40", "gpio41", "gpio42",
457 469 "gpio43", "gpio44", "gpio45",
458 470 "gpio46", "gpio47";
459 functi 471 function = "nand";
460 drive- 472 drive-strength = <10>;
461 bias-d 473 bias-disable;
462 }; 474 };
463 475
464 nand-pullup-pi !! 476 pullups {
465 pins = 477 pins = "gpio39";
466 functi 478 function = "nand";
467 drive- 479 drive-strength = <10>;
468 bias-p 480 bias-pull-up;
469 }; 481 };
470 482
471 nand-hold-pins !! 483 hold {
472 pins = 484 pins = "gpio40", "gpio41", "gpio42",
473 485 "gpio43", "gpio44", "gpio45",
474 486 "gpio46", "gpio47";
475 functi 487 function = "nand";
476 drive- 488 drive-strength = <10>;
477 bias-b 489 bias-bus-hold;
478 }; 490 };
479 }; 491 };
480 492
481 mdio0_pins: mdio0-stat !! 493 mdio0_pins: mdio0-pins {
482 pins = "gpio0" !! 494 mux {
483 function = "md !! 495 pins = "gpio0", "gpio1";
484 drive-strength !! 496 function = "mdio";
485 bias-disable; !! 497 drive-strength = <8>;
>> 498 bias-disable;
>> 499 };
486 }; 500 };
487 501
488 rgmii2_pins: rgmii2-st !! 502 rgmii2_pins: rgmii2-pins {
489 pins = "gpio27 !! 503 mux {
490 "gpio3 !! 504 pins = "gpio27", "gpio28", "gpio29",
491 "gpio5 !! 505 "gpio30", "gpio31", "gpio32",
492 "gpio6 !! 506 "gpio51", "gpio52", "gpio59",
493 function = "rg !! 507 "gpio60", "gpio61", "gpio62";
494 drive-strength !! 508 function = "rgmii2";
495 bias-disable; !! 509 drive-strength = <8>;
>> 510 bias-disable;
>> 511 };
496 }; 512 };
497 }; 513 };
498 514
499 gcc: clock-controller@900000 { 515 gcc: clock-controller@900000 {
500 compatible = "qcom,gcc 516 compatible = "qcom,gcc-ipq8064", "syscon";
501 clocks = <&pxo_board>, 517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
502 clock-names = "pxo", " 518 clock-names = "pxo", "cxo", "pll4";
503 reg = <0x00900000 0x40 519 reg = <0x00900000 0x4000>;
504 #clock-cells = <1>; 520 #clock-cells = <1>;
505 #reset-cells = <1>; 521 #reset-cells = <1>;
>> 522 #power-domain-cells = <1>;
506 523
507 tsens: thermal-sensor 524 tsens: thermal-sensor {
508 compatible = " 525 compatible = "qcom,ipq8064-tsens";
509 526
510 nvmem-cells = 527 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
511 nvmem-cell-nam 528 nvmem-cell-names = "calib", "calib_backup";
512 interrupts = < 529 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
513 interrupt-name 530 interrupt-names = "uplow";
514 531
515 #qcom,sensors 532 #qcom,sensors = <11>;
516 #thermal-senso 533 #thermal-sensor-cells = <1>;
517 }; 534 };
518 }; 535 };
519 536
520 sfpb_mutex: hwlock@1200600 { 537 sfpb_mutex: hwlock@1200600 {
521 compatible = "qcom,sfp 538 compatible = "qcom,sfpb-mutex";
522 reg = <0x01200600 0x10 539 reg = <0x01200600 0x100>;
523 540
524 #hwlock-cells = <1>; 541 #hwlock-cells = <1>;
525 }; 542 };
526 543
527 intc: interrupt-controller@200 544 intc: interrupt-controller@2000000 {
528 compatible = "qcom,msm 545 compatible = "qcom,msm-qgic2";
529 interrupt-controller; 546 interrupt-controller;
530 #interrupt-cells = <3> 547 #interrupt-cells = <3>;
531 reg = <0x02000000 0x10 548 reg = <0x02000000 0x1000>,
532 <0x02002000 0x10 549 <0x02002000 0x1000>;
533 }; 550 };
534 551
535 timer@200a000 { 552 timer@200a000 {
536 compatible = "qcom,kps 553 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
537 "qcom,msm 554 "qcom,msm-timer";
538 interrupts = <GIC_PPI 555 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
539 556 IRQ_TYPE_EDGE_RISING)>,
540 <GIC_PPI 557 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
541 558 IRQ_TYPE_EDGE_RISING)>,
542 <GIC_PPI 559 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
543 560 IRQ_TYPE_EDGE_RISING)>,
544 <GIC_PPI 561 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
545 562 IRQ_TYPE_EDGE_RISING)>,
546 <GIC_PPI 563 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
547 564 IRQ_TYPE_EDGE_RISING)>;
548 reg = <0x0200a000 0x10 565 reg = <0x0200a000 0x100>;
549 clock-frequency = <250 566 clock-frequency = <25000000>;
550 clocks = <&sleep_clk>; 567 clocks = <&sleep_clk>;
551 clock-names = "sleep"; 568 clock-names = "sleep";
552 cpu-offset = <0x80000> 569 cpu-offset = <0x80000>;
553 }; 570 };
554 571
555 l2cc: clock-controller@2011000 572 l2cc: clock-controller@2011000 {
556 compatible = "qcom,kps 573 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
557 reg = <0x02011000 0x10 574 reg = <0x02011000 0x1000>;
558 clocks = <&gcc PLL8_VO 575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
559 clock-names = "pll8_vo 576 clock-names = "pll8_vote", "pxo";
560 #clock-cells = <0>; 577 #clock-cells = <0>;
561 }; 578 };
562 579
563 acc0: clock-controller@2088000 580 acc0: clock-controller@2088000 {
564 compatible = "qcom,kps 581 compatible = "qcom,kpss-acc-v1";
565 reg = <0x02088000 0x10 582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
566 clocks = <&gcc PLL8_VO 583 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
567 clock-names = "pll8_vo 584 clock-names = "pll8_vote", "pxo";
568 clock-output-names = " 585 clock-output-names = "acpu0_aux";
569 #clock-cells = <0>; 586 #clock-cells = <0>;
570 }; 587 };
571 588
572 saw0: power-manager@2089000 { 589 saw0: power-manager@2089000 {
573 compatible = "qcom,ipq 590 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
574 reg = <0x02089000 0x10 591 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
575 }; 592 };
576 593
577 acc1: clock-controller@2098000 594 acc1: clock-controller@2098000 {
578 compatible = "qcom,kps 595 compatible = "qcom,kpss-acc-v1";
579 reg = <0x02098000 0x10 596 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
580 clocks = <&gcc PLL8_VO 597 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
581 clock-names = "pll8_vo 598 clock-names = "pll8_vote", "pxo";
582 clock-output-names = " 599 clock-output-names = "acpu1_aux";
583 #clock-cells = <0>; 600 #clock-cells = <0>;
584 }; 601 };
585 602
586 saw1: power-manager@2099000 { 603 saw1: power-manager@2099000 {
587 compatible = "qcom,ipq 604 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
588 reg = <0x02099000 0x10 605 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
589 }; 606 };
590 607
591 nss_common: syscon@3000000 { 608 nss_common: syscon@3000000 {
592 compatible = "syscon"; 609 compatible = "syscon";
593 reg = <0x03000000 0x00 610 reg = <0x03000000 0x0000FFFF>;
594 }; 611 };
595 612
596 usb3_0: usb@100f8800 { 613 usb3_0: usb@100f8800 {
597 compatible = "qcom,ipq 614 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
598 #address-cells = <1>; 615 #address-cells = <1>;
599 #size-cells = <1>; 616 #size-cells = <1>;
600 reg = <0x100f8800 0x80 617 reg = <0x100f8800 0x8000>;
601 clocks = <&gcc USB30_0 618 clocks = <&gcc USB30_0_MASTER_CLK>;
602 clock-names = "core"; 619 clock-names = "core";
603 620
604 ranges; 621 ranges;
605 622
606 resets = <&gcc USB30_0 623 resets = <&gcc USB30_0_MASTER_RESET>;
607 624
608 status = "disabled"; 625 status = "disabled";
609 626
610 dwc3_0: usb@10000000 { 627 dwc3_0: usb@10000000 {
611 compatible = " 628 compatible = "snps,dwc3";
612 reg = <0x10000 629 reg = <0x10000000 0xcd00>;
613 interrupts = < 630 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
614 phys = <&hs_ph 631 phys = <&hs_phy_0>, <&ss_phy_0>;
615 phy-names = "u 632 phy-names = "usb2-phy", "usb3-phy";
616 dr_mode = "hos 633 dr_mode = "host";
617 snps,dis_u3_su 634 snps,dis_u3_susphy_quirk;
618 }; 635 };
619 }; 636 };
620 637
621 hs_phy_0: phy@100f8800 { 638 hs_phy_0: phy@100f8800 {
622 compatible = "qcom,ipq 639 compatible = "qcom,ipq806x-usb-phy-hs";
623 reg = <0x100f8800 0x30 640 reg = <0x100f8800 0x30>;
624 clocks = <&gcc USB30_0 641 clocks = <&gcc USB30_0_UTMI_CLK>;
625 clock-names = "ref"; 642 clock-names = "ref";
626 #phy-cells = <0>; 643 #phy-cells = <0>;
627 644
628 status = "disabled"; 645 status = "disabled";
629 }; 646 };
630 647
631 ss_phy_0: phy@100f8830 { 648 ss_phy_0: phy@100f8830 {
632 compatible = "qcom,ipq 649 compatible = "qcom,ipq806x-usb-phy-ss";
633 reg = <0x100f8830 0x30 650 reg = <0x100f8830 0x30>;
634 clocks = <&gcc USB30_0 651 clocks = <&gcc USB30_0_MASTER_CLK>;
635 clock-names = "ref"; 652 clock-names = "ref";
636 #phy-cells = <0>; 653 #phy-cells = <0>;
637 654
638 status = "disabled"; 655 status = "disabled";
639 }; 656 };
640 657
641 usb3_1: usb@110f8800 { 658 usb3_1: usb@110f8800 {
642 compatible = "qcom,ipq 659 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
643 #address-cells = <1>; 660 #address-cells = <1>;
644 #size-cells = <1>; 661 #size-cells = <1>;
645 reg = <0x110f8800 0x80 662 reg = <0x110f8800 0x8000>;
646 clocks = <&gcc USB30_1 663 clocks = <&gcc USB30_1_MASTER_CLK>;
647 clock-names = "core"; 664 clock-names = "core";
648 665
649 ranges; 666 ranges;
650 667
651 resets = <&gcc USB30_1 668 resets = <&gcc USB30_1_MASTER_RESET>;
652 669
653 status = "disabled"; 670 status = "disabled";
654 671
655 dwc3_1: usb@11000000 { 672 dwc3_1: usb@11000000 {
656 compatible = " 673 compatible = "snps,dwc3";
657 reg = <0x11000 674 reg = <0x11000000 0xcd00>;
658 interrupts = < 675 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
659 phys = <&hs_ph 676 phys = <&hs_phy_1>, <&ss_phy_1>;
660 phy-names = "u 677 phy-names = "usb2-phy", "usb3-phy";
661 dr_mode = "hos 678 dr_mode = "host";
662 snps,dis_u3_su 679 snps,dis_u3_susphy_quirk;
663 }; 680 };
664 }; 681 };
665 682
666 hs_phy_1: phy@110f8800 { 683 hs_phy_1: phy@110f8800 {
667 compatible = "qcom,ipq 684 compatible = "qcom,ipq806x-usb-phy-hs";
668 reg = <0x110f8800 0x30 685 reg = <0x110f8800 0x30>;
669 clocks = <&gcc USB30_1 686 clocks = <&gcc USB30_1_UTMI_CLK>;
670 clock-names = "ref"; 687 clock-names = "ref";
671 #phy-cells = <0>; 688 #phy-cells = <0>;
672 689
673 status = "disabled"; 690 status = "disabled";
674 }; 691 };
675 692
676 ss_phy_1: phy@110f8830 { 693 ss_phy_1: phy@110f8830 {
677 compatible = "qcom,ipq 694 compatible = "qcom,ipq806x-usb-phy-ss";
678 reg = <0x110f8830 0x30 695 reg = <0x110f8830 0x30>;
679 clocks = <&gcc USB30_1 696 clocks = <&gcc USB30_1_MASTER_CLK>;
680 clock-names = "ref"; 697 clock-names = "ref";
681 #phy-cells = <0>; 698 #phy-cells = <0>;
682 699
683 status = "disabled"; 700 status = "disabled";
684 }; 701 };
685 702
686 sdcc3bam: dma-controller@12182 703 sdcc3bam: dma-controller@12182000 {
687 compatible = "qcom,bam 704 compatible = "qcom,bam-v1.3.0";
688 reg = <0x12182000 0x80 705 reg = <0x12182000 0x8000>;
689 interrupts = <GIC_SPI 706 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&gcc SDC3_H_ 707 clocks = <&gcc SDC3_H_CLK>;
691 clock-names = "bam_clk 708 clock-names = "bam_clk";
692 #dma-cells = <1>; 709 #dma-cells = <1>;
693 qcom,ee = <0>; 710 qcom,ee = <0>;
694 }; 711 };
695 712
696 sdcc1bam: dma-controller@12402 713 sdcc1bam: dma-controller@12402000 {
697 compatible = "qcom,bam 714 compatible = "qcom,bam-v1.3.0";
698 reg = <0x12402000 0x80 715 reg = <0x12402000 0x8000>;
699 interrupts = <GIC_SPI 716 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&gcc SDC1_H_ 717 clocks = <&gcc SDC1_H_CLK>;
701 clock-names = "bam_clk 718 clock-names = "bam_clk";
702 #dma-cells = <1>; 719 #dma-cells = <1>;
703 qcom,ee = <0>; 720 qcom,ee = <0>;
704 }; 721 };
705 722
706 amba: amba { 723 amba: amba {
707 compatible = "simple-b 724 compatible = "simple-bus";
708 #address-cells = <1>; 725 #address-cells = <1>;
709 #size-cells = <1>; 726 #size-cells = <1>;
710 ranges; 727 ranges;
711 728
712 sdcc3: mmc@12180000 { 729 sdcc3: mmc@12180000 {
713 compatible = " 730 compatible = "arm,pl18x", "arm,primecell";
714 arm,primecell- 731 arm,primecell-periphid = <0x00051180>;
715 status = "disa 732 status = "disabled";
716 reg = <0x12180 733 reg = <0x12180000 0x2000>;
717 interrupts = < 734 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&gcc 735 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
719 clock-names = 736 clock-names = "mclk", "apb_pclk";
720 bus-width = <8 737 bus-width = <8>;
721 cap-sd-highspe 738 cap-sd-highspeed;
722 cap-mmc-highsp 739 cap-mmc-highspeed;
723 max-frequency 740 max-frequency = <192000000>;
724 sd-uhs-sdr104; 741 sd-uhs-sdr104;
725 sd-uhs-ddr50; 742 sd-uhs-ddr50;
726 vqmmc-supply = 743 vqmmc-supply = <&vsdcc_fixed>;
727 dmas = <&sdcc3 744 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
728 dma-names = "t 745 dma-names = "tx", "rx";
729 }; 746 };
730 747
731 sdcc1: mmc@12400000 { 748 sdcc1: mmc@12400000 {
732 status = "disa 749 status = "disabled";
733 compatible = " 750 compatible = "arm,pl18x", "arm,primecell";
734 arm,primecell- 751 arm,primecell-periphid = <0x00051180>;
735 reg = <0x12400 752 reg = <0x12400000 0x2000>;
736 interrupts = < 753 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&gcc 754 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
738 clock-names = 755 clock-names = "mclk", "apb_pclk";
739 bus-width = <8 756 bus-width = <8>;
740 max-frequency 757 max-frequency = <96000000>;
741 non-removable; 758 non-removable;
742 cap-sd-highspe 759 cap-sd-highspeed;
743 cap-mmc-highsp 760 cap-mmc-highspeed;
744 vmmc-supply = 761 vmmc-supply = <&vsdcc_fixed>;
745 dmas = <&sdcc1 762 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
746 dma-names = "t 763 dma-names = "tx", "rx";
747 }; 764 };
748 }; 765 };
749 766
750 gsbi1: gsbi@12440000 { 767 gsbi1: gsbi@12440000 {
751 compatible = "qcom,gsb 768 compatible = "qcom,gsbi-v1.0.0";
752 reg = <0x12440000 0x10 769 reg = <0x12440000 0x100>;
753 cell-index = <1>; 770 cell-index = <1>;
754 clocks = <&gcc GSBI1_H 771 clocks = <&gcc GSBI1_H_CLK>;
755 clock-names = "iface"; 772 clock-names = "iface";
756 #address-cells = <1>; 773 #address-cells = <1>;
757 #size-cells = <1>; 774 #size-cells = <1>;
758 ranges; 775 ranges;
759 776
760 syscon-tcsr = <&tcsr>; 777 syscon-tcsr = <&tcsr>;
761 778
762 status = "disabled"; 779 status = "disabled";
763 780
764 gsbi1_serial: serial@1 781 gsbi1_serial: serial@12450000 {
765 compatible = " 782 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
766 reg = <0x12450 783 reg = <0x12450000 0x100>,
767 <0x12400 784 <0x12400000 0x03>;
768 interrupts = < 785 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&gcc 786 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
770 clock-names = 787 clock-names = "core", "iface";
771 788
772 status = "disa 789 status = "disabled";
773 }; 790 };
774 791
775 gsbi1_i2c: i2c@1246000 792 gsbi1_i2c: i2c@12460000 {
776 compatible = " 793 compatible = "qcom,i2c-qup-v1.1.1";
777 reg = <0x12460 794 reg = <0x12460000 0x1000>;
778 interrupts = < 795 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&gcc 796 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
780 clock-names = 797 clock-names = "core", "iface";
781 #address-cells 798 #address-cells = <1>;
782 #size-cells = 799 #size-cells = <0>;
783 800
784 status = "disa 801 status = "disabled";
785 }; 802 };
786 }; 803 };
787 804
788 gsbi2: gsbi@12480000 { 805 gsbi2: gsbi@12480000 {
789 compatible = "qcom,gsb 806 compatible = "qcom,gsbi-v1.0.0";
790 cell-index = <2>; 807 cell-index = <2>;
791 reg = <0x12480000 0x10 808 reg = <0x12480000 0x100>;
792 clocks = <&gcc GSBI2_H 809 clocks = <&gcc GSBI2_H_CLK>;
793 clock-names = "iface"; 810 clock-names = "iface";
794 #address-cells = <1>; 811 #address-cells = <1>;
795 #size-cells = <1>; 812 #size-cells = <1>;
796 ranges; 813 ranges;
797 status = "disabled"; 814 status = "disabled";
798 815
799 syscon-tcsr = <&tcsr>; 816 syscon-tcsr = <&tcsr>;
800 817
801 gsbi2_serial: serial@1 818 gsbi2_serial: serial@12490000 {
802 compatible = " 819 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
803 reg = <0x12490 820 reg = <0x12490000 0x1000>,
804 <0x12480 821 <0x12480000 0x1000>;
805 interrupts = < 822 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&gcc 823 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
807 clock-names = 824 clock-names = "core", "iface";
808 status = "disa 825 status = "disabled";
809 }; 826 };
810 827
811 gsbi2_i2c: i2c@124a000 828 gsbi2_i2c: i2c@124a0000 {
812 compatible = " 829 compatible = "qcom,i2c-qup-v1.1.1";
813 reg = <0x124a0 830 reg = <0x124a0000 0x1000>;
814 interrupts = < 831 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
815 832
816 clocks = <&gcc 833 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
817 clock-names = 834 clock-names = "core", "iface";
818 status = "disa 835 status = "disabled";
819 836
820 #address-cells 837 #address-cells = <1>;
821 #size-cells = 838 #size-cells = <0>;
822 }; 839 };
823 }; 840 };
824 841
825 gsbi4: gsbi@16300000 { 842 gsbi4: gsbi@16300000 {
826 compatible = "qcom,gsb 843 compatible = "qcom,gsbi-v1.0.0";
827 cell-index = <4>; 844 cell-index = <4>;
828 reg = <0x16300000 0x10 845 reg = <0x16300000 0x100>;
829 clocks = <&gcc GSBI4_H 846 clocks = <&gcc GSBI4_H_CLK>;
830 clock-names = "iface"; 847 clock-names = "iface";
831 #address-cells = <1>; 848 #address-cells = <1>;
832 #size-cells = <1>; 849 #size-cells = <1>;
833 ranges; 850 ranges;
834 status = "disabled"; 851 status = "disabled";
835 852
836 syscon-tcsr = <&tcsr>; 853 syscon-tcsr = <&tcsr>;
837 854
838 gsbi4_serial: serial@1 855 gsbi4_serial: serial@16340000 {
839 compatible = " 856 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
840 reg = <0x16340 857 reg = <0x16340000 0x1000>,
841 <0x16300 858 <0x16300000 0x1000>;
842 interrupts = < 859 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&gcc 860 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
844 clock-names = 861 clock-names = "core", "iface";
845 status = "disa 862 status = "disabled";
846 }; 863 };
847 864
848 i2c@16380000 { 865 i2c@16380000 {
849 compatible = " 866 compatible = "qcom,i2c-qup-v1.1.1";
850 reg = <0x16380 867 reg = <0x16380000 0x1000>;
851 interrupts = < 868 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
852 869
853 clocks = <&gcc 870 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
854 clock-names = 871 clock-names = "core", "iface";
855 status = "disa 872 status = "disabled";
856 873
857 #address-cells 874 #address-cells = <1>;
858 #size-cells = 875 #size-cells = <0>;
859 }; 876 };
860 }; 877 };
861 878
862 gsbi6: gsbi@16500000 { 879 gsbi6: gsbi@16500000 {
863 compatible = "qcom,gsb 880 compatible = "qcom,gsbi-v1.0.0";
864 reg = <0x16500000 0x10 881 reg = <0x16500000 0x100>;
865 cell-index = <6>; 882 cell-index = <6>;
866 clocks = <&gcc GSBI6_H 883 clocks = <&gcc GSBI6_H_CLK>;
867 clock-names = "iface"; 884 clock-names = "iface";
868 #address-cells = <1>; 885 #address-cells = <1>;
869 #size-cells = <1>; 886 #size-cells = <1>;
870 ranges; 887 ranges;
871 888
872 syscon-tcsr = <&tcsr>; 889 syscon-tcsr = <&tcsr>;
873 890
874 status = "disabled"; 891 status = "disabled";
875 892
876 gsbi6_i2c: i2c@1658000 893 gsbi6_i2c: i2c@16580000 {
877 compatible = " 894 compatible = "qcom,i2c-qup-v1.1.1";
878 reg = <0x16580 895 reg = <0x16580000 0x1000>;
879 interrupts = < 896 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
880 897
881 clocks = <&gcc 898 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
882 clock-names = 899 clock-names = "core", "iface";
883 900
884 #address-cells 901 #address-cells = <1>;
885 #size-cells = 902 #size-cells = <0>;
886 903
887 status = "disa 904 status = "disabled";
888 }; 905 };
889 906
890 gsbi6_spi: spi@1658000 907 gsbi6_spi: spi@16580000 {
891 compatible = " 908 compatible = "qcom,spi-qup-v1.1.1";
892 reg = <0x16580 909 reg = <0x16580000 0x1000>;
893 interrupts = < 910 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
894 911
895 clocks = <&gcc 912 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
896 clock-names = 913 clock-names = "core", "iface";
897 914
898 #address-cells 915 #address-cells = <1>;
899 #size-cells = 916 #size-cells = <0>;
900 917
901 status = "disa 918 status = "disabled";
902 }; 919 };
903 }; 920 };
904 921
905 gsbi7: gsbi@16600000 { 922 gsbi7: gsbi@16600000 {
906 status = "disabled"; 923 status = "disabled";
907 compatible = "qcom,gsb 924 compatible = "qcom,gsbi-v1.0.0";
908 cell-index = <7>; 925 cell-index = <7>;
909 reg = <0x16600000 0x10 926 reg = <0x16600000 0x100>;
910 clocks = <&gcc GSBI7_H 927 clocks = <&gcc GSBI7_H_CLK>;
911 clock-names = "iface"; 928 clock-names = "iface";
912 #address-cells = <1>; 929 #address-cells = <1>;
913 #size-cells = <1>; 930 #size-cells = <1>;
914 ranges; 931 ranges;
915 syscon-tcsr = <&tcsr>; 932 syscon-tcsr = <&tcsr>;
916 933
917 gsbi7_serial: serial@1 934 gsbi7_serial: serial@16640000 {
918 compatible = " 935 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
919 reg = <0x16640 936 reg = <0x16640000 0x1000>,
920 <0x16600 937 <0x16600000 0x1000>;
921 interrupts = < 938 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&gcc 939 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
923 clock-names = 940 clock-names = "core", "iface";
924 status = "disa 941 status = "disabled";
925 }; 942 };
926 943
927 gsbi7_i2c: i2c@1668000 944 gsbi7_i2c: i2c@16680000 {
928 compatible = " 945 compatible = "qcom,i2c-qup-v1.1.1";
929 reg = <0x16680 946 reg = <0x16680000 0x1000>;
930 interrupts = < 947 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
931 948
932 clocks = <&gcc 949 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
933 clock-names = 950 clock-names = "core", "iface";
934 951
935 #address-cells 952 #address-cells = <1>;
936 #size-cells = 953 #size-cells = <0>;
937 954
938 status = "disa 955 status = "disabled";
939 }; 956 };
940 }; 957 };
941 958
942 adm_dma: dma-controller@183000 959 adm_dma: dma-controller@18300000 {
943 compatible = "qcom,adm 960 compatible = "qcom,adm";
944 reg = <0x18300000 0x10 961 reg = <0x18300000 0x100000>;
945 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
946 #dma-cells = <1>; 963 #dma-cells = <1>;
947 964
948 clocks = <&gcc ADM0_CL 965 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
949 clock-names = "core", 966 clock-names = "core", "iface";
950 967
951 resets = <&gcc ADM0_RE 968 resets = <&gcc ADM0_RESET>,
952 <&gcc ADM0_PB 969 <&gcc ADM0_PBUS_RESET>,
953 <&gcc ADM0_C0 970 <&gcc ADM0_C0_RESET>,
954 <&gcc ADM0_C1 971 <&gcc ADM0_C1_RESET>,
955 <&gcc ADM0_C2 972 <&gcc ADM0_C2_RESET>;
956 reset-names = "clk", " 973 reset-names = "clk", "pbus", "c0", "c1", "c2";
957 qcom,ee = <0>; 974 qcom,ee = <0>;
958 975
959 status = "disabled"; 976 status = "disabled";
960 }; 977 };
961 978
962 gsbi5: gsbi@1a200000 { 979 gsbi5: gsbi@1a200000 {
963 compatible = "qcom,gsb 980 compatible = "qcom,gsbi-v1.0.0";
964 cell-index = <5>; 981 cell-index = <5>;
965 reg = <0x1a200000 0x10 982 reg = <0x1a200000 0x100>;
966 clocks = <&gcc GSBI5_H 983 clocks = <&gcc GSBI5_H_CLK>;
967 clock-names = "iface"; 984 clock-names = "iface";
968 #address-cells = <1>; 985 #address-cells = <1>;
969 986
970 #size-cells = <1>; 987 #size-cells = <1>;
971 ranges; 988 ranges;
972 status = "disabled"; 989 status = "disabled";
973 990
974 syscon-tcsr = <&tcsr>; 991 syscon-tcsr = <&tcsr>;
975 992
976 gsbi5_serial: serial@1 993 gsbi5_serial: serial@1a240000 {
977 compatible = " 994 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
978 reg = <0x1a240 995 reg = <0x1a240000 0x1000>,
979 <0x1a200 996 <0x1a200000 0x1000>;
980 interrupts = < 997 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&gcc 998 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
982 clock-names = 999 clock-names = "core", "iface";
983 status = "disa 1000 status = "disabled";
984 }; 1001 };
985 1002
986 i2c@1a280000 { 1003 i2c@1a280000 {
987 compatible = " 1004 compatible = "qcom,i2c-qup-v1.1.1";
988 reg = <0x1a280 1005 reg = <0x1a280000 0x1000>;
989 interrupts = < 1006 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
990 1007
991 clocks = <&gcc 1008 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
992 clock-names = 1009 clock-names = "core", "iface";
993 status = "disa 1010 status = "disabled";
994 1011
995 #address-cells 1012 #address-cells = <1>;
996 #size-cells = 1013 #size-cells = <0>;
997 }; 1014 };
998 1015
999 spi@1a280000 { 1016 spi@1a280000 {
1000 compatible = 1017 compatible = "qcom,spi-qup-v1.1.1";
1001 reg = <0x1a28 1018 reg = <0x1a280000 0x1000>;
1002 interrupts = 1019 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1003 1020
1004 clocks = <&gc 1021 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1005 clock-names = 1022 clock-names = "core", "iface";
1006 status = "dis 1023 status = "disabled";
1007 1024
1008 #address-cell 1025 #address-cells = <1>;
1009 #size-cells = 1026 #size-cells = <0>;
1010 }; 1027 };
1011 }; 1028 };
1012 1029
1013 tcsr: syscon@1a400000 { 1030 tcsr: syscon@1a400000 {
1014 compatible = "qcom,tc 1031 compatible = "qcom,tcsr-ipq8064", "syscon";
1015 reg = <0x1a400000 0x1 1032 reg = <0x1a400000 0x100>;
1016 }; 1033 };
1017 1034
1018 rng@1a500000 { 1035 rng@1a500000 {
1019 compatible = "qcom,pr 1036 compatible = "qcom,prng";
1020 reg = <0x1a500000 0x2 1037 reg = <0x1a500000 0x200>;
1021 clocks = <&gcc PRNG_C 1038 clocks = <&gcc PRNG_CLK>;
1022 clock-names = "core"; 1039 clock-names = "core";
1023 }; 1040 };
1024 1041
1025 nand: nand-controller@1ac0000 1042 nand: nand-controller@1ac00000 {
1026 compatible = "qcom,ip 1043 compatible = "qcom,ipq806x-nand";
1027 reg = <0x1ac00000 0x8 1044 reg = <0x1ac00000 0x800>;
1028 1045
1029 pinctrl-0 = <&nand_pi 1046 pinctrl-0 = <&nand_pins>;
1030 pinctrl-names = "defa 1047 pinctrl-names = "default";
1031 1048
1032 clocks = <&gcc EBI2_C 1049 clocks = <&gcc EBI2_CLK>,
1033 <&gcc EBI2_A 1050 <&gcc EBI2_AON_CLK>;
1034 clock-names = "core", 1051 clock-names = "core", "aon";
1035 1052
1036 dmas = <&adm_dma 3>; 1053 dmas = <&adm_dma 3>;
1037 dma-names = "rxtx"; 1054 dma-names = "rxtx";
1038 qcom,cmd-crci = <15>; 1055 qcom,cmd-crci = <15>;
1039 qcom,data-crci = <3>; 1056 qcom,data-crci = <3>;
1040 1057
1041 #address-cells = <1>; 1058 #address-cells = <1>;
1042 #size-cells = <0>; 1059 #size-cells = <0>;
1043 1060
1044 status = "disabled"; 1061 status = "disabled";
1045 }; 1062 };
1046 1063
1047 sata_phy: sata-phy@1b400000 { 1064 sata_phy: sata-phy@1b400000 {
1048 compatible = "qcom,ip 1065 compatible = "qcom,ipq806x-sata-phy";
1049 reg = <0x1b400000 0x2 1066 reg = <0x1b400000 0x200>;
1050 1067
1051 clocks = <&gcc SATA_P 1068 clocks = <&gcc SATA_PHY_CFG_CLK>;
1052 clock-names = "cfg"; 1069 clock-names = "cfg";
1053 1070
1054 #phy-cells = <0>; 1071 #phy-cells = <0>;
1055 status = "disabled"; 1072 status = "disabled";
1056 }; 1073 };
1057 1074
1058 pcie0: pcie@1b500000 { 1075 pcie0: pcie@1b500000 {
1059 compatible = "qcom,pc 1076 compatible = "qcom,pcie-ipq8064";
1060 reg = <0x1b500000 0x1 1077 reg = <0x1b500000 0x1000
1061 0x1b502000 0x8 1078 0x1b502000 0x80
1062 0x1b600000 0x1 1079 0x1b600000 0x100
1063 0x0ff00000 0x1 1080 0x0ff00000 0x100000>;
1064 reg-names = "dbi", "e 1081 reg-names = "dbi", "elbi", "parf", "config";
1065 device_type = "pci"; 1082 device_type = "pci";
1066 linux,pci-domain = <0 1083 linux,pci-domain = <0>;
1067 bus-range = <0x00 0xf 1084 bus-range = <0x00 0xff>;
1068 num-lanes = <1>; 1085 num-lanes = <1>;
1069 #address-cells = <3>; 1086 #address-cells = <3>;
1070 #size-cells = <2>; 1087 #size-cells = <2>;
1071 1088
1072 ranges = <0x81000000 1089 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
1073 0x82000000 1090 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
1074 1091
1075 interrupts = <GIC_SPI 1092 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1076 interrupt-names = "ms 1093 interrupt-names = "msi";
1077 #interrupt-cells = <1 1094 #interrupt-cells = <1>;
1078 interrupt-map-mask = 1095 interrupt-map-mask = <0 0 0 0x7>;
1079 interrupt-map = <0 0 1096 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1080 <0 0 1097 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1081 <0 0 1098 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1082 <0 0 1099 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1083 1100
1084 clocks = <&gcc PCIE_A 1101 clocks = <&gcc PCIE_A_CLK>,
1085 <&gcc PCIE_H 1102 <&gcc PCIE_H_CLK>,
1086 <&gcc PCIE_P 1103 <&gcc PCIE_PHY_CLK>,
1087 <&gcc PCIE_A 1104 <&gcc PCIE_AUX_CLK>,
1088 <&gcc PCIE_A 1105 <&gcc PCIE_ALT_REF_CLK>;
1089 clock-names = "core", 1106 clock-names = "core", "iface", "phy", "aux", "ref";
1090 1107
1091 assigned-clocks = <&g 1108 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1092 assigned-clock-rates 1109 assigned-clock-rates = <100000000>;
1093 1110
1094 resets = <&gcc PCIE_A 1111 resets = <&gcc PCIE_ACLK_RESET>,
1095 <&gcc PCIE_H 1112 <&gcc PCIE_HCLK_RESET>,
1096 <&gcc PCIE_P 1113 <&gcc PCIE_POR_RESET>,
1097 <&gcc PCIE_P 1114 <&gcc PCIE_PCI_RESET>,
1098 <&gcc PCIE_P 1115 <&gcc PCIE_PHY_RESET>,
1099 <&gcc PCIE_E 1116 <&gcc PCIE_EXT_RESET>;
1100 reset-names = "axi", 1117 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1101 1118
1102 pinctrl-0 = <&pcie0_p 1119 pinctrl-0 = <&pcie0_pins>;
1103 pinctrl-names = "defa 1120 pinctrl-names = "default";
1104 1121
1105 status = "disabled"; 1122 status = "disabled";
1106 perst-gpios = <&qcom_ 1123 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1107 <<
1108 pcie@0 { <<
1109 device_type = <<
1110 reg = <0x0 0x <<
1111 bus-range = < <<
1112 <<
1113 #address-cell <<
1114 #size-cells = <<
1115 ranges; <<
1116 }; <<
1117 }; 1124 };
1118 1125
1119 pcie1: pcie@1b700000 { 1126 pcie1: pcie@1b700000 {
1120 compatible = "qcom,pc 1127 compatible = "qcom,pcie-ipq8064";
1121 reg = <0x1b700000 0x1 1128 reg = <0x1b700000 0x1000
1122 0x1b702000 0x8 1129 0x1b702000 0x80
1123 0x1b800000 0x1 1130 0x1b800000 0x100
1124 0x31f00000 0x1 1131 0x31f00000 0x100000>;
1125 reg-names = "dbi", "e 1132 reg-names = "dbi", "elbi", "parf", "config";
1126 device_type = "pci"; 1133 device_type = "pci";
1127 linux,pci-domain = <1 1134 linux,pci-domain = <1>;
1128 bus-range = <0x00 0xf 1135 bus-range = <0x00 0xff>;
1129 num-lanes = <1>; 1136 num-lanes = <1>;
1130 #address-cells = <3>; 1137 #address-cells = <3>;
1131 #size-cells = <2>; 1138 #size-cells = <2>;
1132 1139
1133 ranges = <0x81000000 1140 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
1134 0x82000000 1141 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
1135 1142
1136 interrupts = <GIC_SPI 1143 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1137 interrupt-names = "ms 1144 interrupt-names = "msi";
1138 #interrupt-cells = <1 1145 #interrupt-cells = <1>;
1139 interrupt-map-mask = 1146 interrupt-map-mask = <0 0 0 0x7>;
1140 interrupt-map = <0 0 1147 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1141 <0 0 1148 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1142 <0 0 1149 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1143 <0 0 1150 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1144 1151
1145 clocks = <&gcc PCIE_1 1152 clocks = <&gcc PCIE_1_A_CLK>,
1146 <&gcc PCIE_1 1153 <&gcc PCIE_1_H_CLK>,
1147 <&gcc PCIE_1 1154 <&gcc PCIE_1_PHY_CLK>,
1148 <&gcc PCIE_1 1155 <&gcc PCIE_1_AUX_CLK>,
1149 <&gcc PCIE_1 1156 <&gcc PCIE_1_ALT_REF_CLK>;
1150 clock-names = "core", 1157 clock-names = "core", "iface", "phy", "aux", "ref";
1151 1158
1152 assigned-clocks = <&g 1159 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1153 assigned-clock-rates 1160 assigned-clock-rates = <100000000>;
1154 1161
1155 resets = <&gcc PCIE_1 1162 resets = <&gcc PCIE_1_ACLK_RESET>,
1156 <&gcc PCIE_1 1163 <&gcc PCIE_1_HCLK_RESET>,
1157 <&gcc PCIE_1 1164 <&gcc PCIE_1_POR_RESET>,
1158 <&gcc PCIE_1 1165 <&gcc PCIE_1_PCI_RESET>,
1159 <&gcc PCIE_1 1166 <&gcc PCIE_1_PHY_RESET>,
1160 <&gcc PCIE_1 1167 <&gcc PCIE_1_EXT_RESET>;
1161 reset-names = "axi", 1168 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1162 1169
1163 pinctrl-0 = <&pcie1_p 1170 pinctrl-0 = <&pcie1_pins>;
1164 pinctrl-names = "defa 1171 pinctrl-names = "default";
1165 1172
1166 status = "disabled"; 1173 status = "disabled";
1167 perst-gpios = <&qcom_ 1174 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1168 <<
1169 pcie@0 { <<
1170 device_type = <<
1171 reg = <0x0 0x <<
1172 bus-range = < <<
1173 <<
1174 #address-cell <<
1175 #size-cells = <<
1176 ranges; <<
1177 }; <<
1178 }; 1175 };
1179 1176
1180 pcie2: pcie@1b900000 { 1177 pcie2: pcie@1b900000 {
1181 compatible = "qcom,pc 1178 compatible = "qcom,pcie-ipq8064";
1182 reg = <0x1b900000 0x1 1179 reg = <0x1b900000 0x1000
1183 0x1b902000 0x8 1180 0x1b902000 0x80
1184 0x1ba00000 0x1 1181 0x1ba00000 0x100
1185 0x35f00000 0x1 1182 0x35f00000 0x100000>;
1186 reg-names = "dbi", "e 1183 reg-names = "dbi", "elbi", "parf", "config";
1187 device_type = "pci"; 1184 device_type = "pci";
1188 linux,pci-domain = <2 1185 linux,pci-domain = <2>;
1189 bus-range = <0x00 0xf 1186 bus-range = <0x00 0xff>;
1190 num-lanes = <1>; 1187 num-lanes = <1>;
1191 #address-cells = <3>; 1188 #address-cells = <3>;
1192 #size-cells = <2>; 1189 #size-cells = <2>;
1193 1190
1194 ranges = <0x81000000 1191 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
1195 0x82000000 1192 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
1196 1193
1197 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "ms 1195 interrupt-names = "msi";
1199 #interrupt-cells = <1 1196 #interrupt-cells = <1>;
1200 interrupt-map-mask = 1197 interrupt-map-mask = <0 0 0 0x7>;
1201 interrupt-map = <0 0 1198 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1202 <0 0 1199 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1203 <0 0 1200 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1204 <0 0 1201 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1205 1202
1206 clocks = <&gcc PCIE_2 1203 clocks = <&gcc PCIE_2_A_CLK>,
1207 <&gcc PCIE_2 1204 <&gcc PCIE_2_H_CLK>,
1208 <&gcc PCIE_2 1205 <&gcc PCIE_2_PHY_CLK>,
1209 <&gcc PCIE_2 1206 <&gcc PCIE_2_AUX_CLK>,
1210 <&gcc PCIE_2 1207 <&gcc PCIE_2_ALT_REF_CLK>;
1211 clock-names = "core", 1208 clock-names = "core", "iface", "phy", "aux", "ref";
1212 1209
1213 assigned-clocks = <&g 1210 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1214 assigned-clock-rates 1211 assigned-clock-rates = <100000000>;
1215 1212
1216 resets = <&gcc PCIE_2 1213 resets = <&gcc PCIE_2_ACLK_RESET>,
1217 <&gcc PCIE_2 1214 <&gcc PCIE_2_HCLK_RESET>,
1218 <&gcc PCIE_2 1215 <&gcc PCIE_2_POR_RESET>,
1219 <&gcc PCIE_2 1216 <&gcc PCIE_2_PCI_RESET>,
1220 <&gcc PCIE_2 1217 <&gcc PCIE_2_PHY_RESET>,
1221 <&gcc PCIE_2 1218 <&gcc PCIE_2_EXT_RESET>;
1222 reset-names = "axi", 1219 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1223 1220
1224 pinctrl-0 = <&pcie2_p 1221 pinctrl-0 = <&pcie2_pins>;
1225 pinctrl-names = "defa 1222 pinctrl-names = "default";
1226 1223
1227 status = "disabled"; 1224 status = "disabled";
1228 perst-gpios = <&qcom_ 1225 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1229 <<
1230 pcie@0 { <<
1231 device_type = <<
1232 reg = <0x0 0x <<
1233 bus-range = < <<
1234 <<
1235 #address-cell <<
1236 #size-cells = <<
1237 ranges; <<
1238 }; <<
1239 }; 1226 };
1240 1227
1241 qsgmii_csr: syscon@1bb00000 { 1228 qsgmii_csr: syscon@1bb00000 {
1242 compatible = "syscon" 1229 compatible = "syscon";
1243 reg = <0x1bb00000 0x0 1230 reg = <0x1bb00000 0x000001FF>;
1244 }; 1231 };
1245 1232
1246 lcc: clock-controller@2800000 1233 lcc: clock-controller@28000000 {
1247 compatible = "qcom,lc 1234 compatible = "qcom,lcc-ipq8064";
1248 reg = <0x28000000 0x1 1235 reg = <0x28000000 0x1000>;
1249 #clock-cells = <1>; 1236 #clock-cells = <1>;
1250 #reset-cells = <1>; 1237 #reset-cells = <1>;
1251 }; 1238 };
1252 1239
1253 lpass@28100000 { 1240 lpass@28100000 {
1254 compatible = "qcom,lp 1241 compatible = "qcom,lpass-cpu";
1255 status = "disabled"; 1242 status = "disabled";
1256 clocks = <&lcc AHBIX_ 1243 clocks = <&lcc AHBIX_CLK>,
1257 <&lcc 1244 <&lcc MI2S_OSR_CLK>,
1258 <&lcc 1245 <&lcc MI2S_BIT_CLK>;
1259 clock-names = "ahbix- 1246 clock-names = "ahbix-clk",
1260 "mi2s 1247 "mi2s-osr-clk",
1261 "mi2s 1248 "mi2s-bit-clk";
1262 interrupts = <GIC_SPI 1249 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1263 interrupt-names = "lp 1250 interrupt-names = "lpass-irq-lpaif";
1264 reg = <0x28100000 0x1 1251 reg = <0x28100000 0x10000>;
1265 reg-names = "lpass-lp 1252 reg-names = "lpass-lpaif";
1266 }; 1253 };
1267 1254
1268 sata: sata@29000000 { 1255 sata: sata@29000000 {
1269 compatible = "qcom,ip 1256 compatible = "qcom,ipq806x-ahci", "generic-ahci";
1270 reg = <0x29000000 0x1 1257 reg = <0x29000000 0x180>;
1271 1258
1272 interrupts = <GIC_SPI 1259 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1273 1260
1274 clocks = <&gcc SFAB_S 1261 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1275 <&gcc SATA_H 1262 <&gcc SATA_H_CLK>,
1276 <&gcc SATA_A 1263 <&gcc SATA_A_CLK>,
1277 <&gcc SATA_R 1264 <&gcc SATA_RXOOB_CLK>,
1278 <&gcc SATA_P 1265 <&gcc SATA_PMALIVE_CLK>;
1279 clock-names = "slave_ !! 1266 clock-names = "slave_face", "iface", "core",
1280 "rxoo 1267 "rxoob", "pmalive";
1281 1268
1282 assigned-clocks = <&g 1269 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1283 assigned-clock-rates 1270 assigned-clock-rates = <100000000>, <100000000>;
1284 1271
1285 phys = <&sata_phy>; 1272 phys = <&sata_phy>;
1286 phy-names = "sata-phy 1273 phy-names = "sata-phy";
1287 status = "disabled"; 1274 status = "disabled";
1288 }; 1275 };
1289 1276
1290 gmac0: ethernet@37000000 { 1277 gmac0: ethernet@37000000 {
1291 device_type = "networ 1278 device_type = "network";
1292 compatible = "qcom,ip 1279 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1293 reg = <0x37000000 0x2 1280 reg = <0x37000000 0x200000>;
1294 interrupts = <GIC_SPI 1281 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1295 interrupt-names = "ma 1282 interrupt-names = "macirq";
1296 1283
1297 snps,axi-config = <&s 1284 snps,axi-config = <&stmmac_axi_setup>;
1298 snps,pbl = <32>; 1285 snps,pbl = <32>;
1299 snps,aal; 1286 snps,aal;
1300 1287
1301 qcom,nss-common = <&n 1288 qcom,nss-common = <&nss_common>;
1302 qcom,qsgmii-csr = <&q 1289 qcom,qsgmii-csr = <&qsgmii_csr>;
1303 1290
1304 clocks = <&gcc GMAC_C 1291 clocks = <&gcc GMAC_CORE1_CLK>;
1305 clock-names = "stmmac 1292 clock-names = "stmmaceth";
1306 1293
1307 resets = <&gcc GMAC_C 1294 resets = <&gcc GMAC_CORE1_RESET>,
1308 <&gcc GMAC_A 1295 <&gcc GMAC_AHB_RESET>;
1309 reset-names = "stmmac 1296 reset-names = "stmmaceth", "ahb";
1310 1297
1311 status = "disabled"; 1298 status = "disabled";
1312 }; 1299 };
1313 1300
1314 gmac1: ethernet@37200000 { 1301 gmac1: ethernet@37200000 {
1315 device_type = "networ 1302 device_type = "network";
1316 compatible = "qcom,ip 1303 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1317 reg = <0x37200000 0x2 1304 reg = <0x37200000 0x200000>;
1318 interrupts = <GIC_SPI 1305 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1319 interrupt-names = "ma 1306 interrupt-names = "macirq";
1320 1307
1321 snps,axi-config = <&s 1308 snps,axi-config = <&stmmac_axi_setup>;
1322 snps,pbl = <32>; 1309 snps,pbl = <32>;
1323 snps,aal; 1310 snps,aal;
1324 1311
1325 qcom,nss-common = <&n 1312 qcom,nss-common = <&nss_common>;
1326 qcom,qsgmii-csr = <&q 1313 qcom,qsgmii-csr = <&qsgmii_csr>;
1327 1314
1328 clocks = <&gcc GMAC_C 1315 clocks = <&gcc GMAC_CORE2_CLK>;
1329 clock-names = "stmmac 1316 clock-names = "stmmaceth";
1330 1317
1331 resets = <&gcc GMAC_C 1318 resets = <&gcc GMAC_CORE2_RESET>,
1332 <&gcc GMAC_A 1319 <&gcc GMAC_AHB_RESET>;
1333 reset-names = "stmmac 1320 reset-names = "stmmaceth", "ahb";
1334 1321
1335 status = "disabled"; 1322 status = "disabled";
1336 }; 1323 };
1337 1324
1338 gmac2: ethernet@37400000 { 1325 gmac2: ethernet@37400000 {
1339 device_type = "networ 1326 device_type = "network";
1340 compatible = "qcom,ip 1327 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1341 reg = <0x37400000 0x2 1328 reg = <0x37400000 0x200000>;
1342 interrupts = <GIC_SPI 1329 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1343 interrupt-names = "ma 1330 interrupt-names = "macirq";
1344 1331
1345 snps,axi-config = <&s 1332 snps,axi-config = <&stmmac_axi_setup>;
1346 snps,pbl = <32>; 1333 snps,pbl = <32>;
1347 snps,aal; 1334 snps,aal;
1348 1335
1349 qcom,nss-common = <&n 1336 qcom,nss-common = <&nss_common>;
1350 qcom,qsgmii-csr = <&q 1337 qcom,qsgmii-csr = <&qsgmii_csr>;
1351 1338
1352 clocks = <&gcc GMAC_C 1339 clocks = <&gcc GMAC_CORE3_CLK>;
1353 clock-names = "stmmac 1340 clock-names = "stmmaceth";
1354 1341
1355 resets = <&gcc GMAC_C 1342 resets = <&gcc GMAC_CORE3_RESET>,
1356 <&gcc GMAC_A 1343 <&gcc GMAC_AHB_RESET>;
1357 reset-names = "stmmac 1344 reset-names = "stmmaceth", "ahb";
1358 1345
1359 status = "disabled"; 1346 status = "disabled";
1360 }; 1347 };
1361 1348
1362 gmac3: ethernet@37600000 { 1349 gmac3: ethernet@37600000 {
1363 device_type = "networ 1350 device_type = "network";
1364 compatible = "qcom,ip 1351 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1365 reg = <0x37600000 0x2 1352 reg = <0x37600000 0x200000>;
1366 interrupts = <GIC_SPI 1353 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1367 interrupt-names = "ma 1354 interrupt-names = "macirq";
1368 1355
1369 snps,axi-config = <&s 1356 snps,axi-config = <&stmmac_axi_setup>;
1370 snps,pbl = <32>; 1357 snps,pbl = <32>;
1371 snps,aal; 1358 snps,aal;
1372 1359
1373 qcom,nss-common = <&n 1360 qcom,nss-common = <&nss_common>;
1374 qcom,qsgmii-csr = <&q 1361 qcom,qsgmii-csr = <&qsgmii_csr>;
1375 1362
1376 clocks = <&gcc GMAC_C 1363 clocks = <&gcc GMAC_CORE4_CLK>;
1377 clock-names = "stmmac 1364 clock-names = "stmmaceth";
1378 1365
1379 resets = <&gcc GMAC_C 1366 resets = <&gcc GMAC_CORE4_RESET>,
1380 <&gcc GMAC_A 1367 <&gcc GMAC_AHB_RESET>;
1381 reset-names = "stmmac 1368 reset-names = "stmmaceth", "ahb";
1382 1369
1383 status = "disabled"; 1370 status = "disabled";
1384 }; 1371 };
1385 }; 1372 };
1386 }; 1373 };
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