1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /* 2 /*
3 * Device Tree Source for Qualcomm MDM9615 SoC 3 * Device Tree Source for Qualcomm MDM9615 SoC
4 * 4 *
5 * Copyright (C) 2016 BayLibre, SAS. 5 * Copyright (C) 2016 BayLibre, SAS.
6 * Author : Neil Armstrong <narmstrong@baylibre 6 * Author : Neil Armstrong <narmstrong@baylibre.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h 12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h <<
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h 13 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h> 14 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h> 15 #include <dt-bindings/soc/qcom,gsbi.h>
17 16
18 / { 17 / {
19 #address-cells = <1>; 18 #address-cells = <1>;
20 #size-cells = <1>; 19 #size-cells = <1>;
21 model = "Qualcomm MDM9615"; 20 model = "Qualcomm MDM9615";
22 compatible = "qcom,mdm9615"; 21 compatible = "qcom,mdm9615";
23 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
24 23
25 cpus { 24 cpus {
26 #address-cells = <1>; 25 #address-cells = <1>;
27 #size-cells = <0>; 26 #size-cells = <0>;
28 27
29 cpu0: cpu@0 { 28 cpu0: cpu@0 {
30 compatible = "arm,cort 29 compatible = "arm,cortex-a5";
31 reg = <0>; 30 reg = <0>;
32 device_type = "cpu"; 31 device_type = "cpu";
33 next-level-cache = <&L 32 next-level-cache = <&L2>;
34 }; 33 };
35 }; 34 };
36 35
37 cpu-pmu { 36 cpu-pmu {
38 compatible = "arm,cortex-a5-pm 37 compatible = "arm,cortex-a5-pmu";
39 interrupts = <GIC_PPI 10 (GIC_ 38 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
40 }; 39 };
41 40
42 clocks { 41 clocks {
43 cxo_board: cxo_board { !! 42 cxo_board {
44 compatible = "fixed-cl 43 compatible = "fixed-clock";
45 #clock-cells = <0>; 44 #clock-cells = <0>;
46 clock-frequency = <192 45 clock-frequency = <19200000>;
47 }; 46 };
48 }; 47 };
49 48
50 vsdcc_fixed: vsdcc-regulator { 49 vsdcc_fixed: vsdcc-regulator {
51 compatible = "regulator-fixed" 50 compatible = "regulator-fixed";
52 regulator-name = "SDCC Power"; 51 regulator-name = "SDCC Power";
53 regulator-min-microvolt = <270 52 regulator-min-microvolt = <2700000>;
54 regulator-max-microvolt = <270 53 regulator-max-microvolt = <2700000>;
55 regulator-always-on; 54 regulator-always-on;
56 }; 55 };
57 56
58 soc: soc { 57 soc: soc {
59 #address-cells = <1>; 58 #address-cells = <1>;
60 #size-cells = <1>; 59 #size-cells = <1>;
61 ranges; 60 ranges;
62 compatible = "simple-bus"; 61 compatible = "simple-bus";
63 62
64 L2: cache-controller@2040000 { 63 L2: cache-controller@2040000 {
65 compatible = "arm,pl31 64 compatible = "arm,pl310-cache";
66 reg = <0x02040000 0x10 65 reg = <0x02040000 0x1000>;
67 arm,data-latency = <2 66 arm,data-latency = <2 2 0>;
68 cache-unified; 67 cache-unified;
69 cache-level = <2>; 68 cache-level = <2>;
70 }; 69 };
71 70
72 intc: interrupt-controller@200 71 intc: interrupt-controller@2000000 {
73 compatible = "qcom,msm 72 compatible = "qcom,msm-qgic2";
74 interrupt-controller; 73 interrupt-controller;
75 #interrupt-cells = <3> 74 #interrupt-cells = <3>;
76 reg = <0x02000000 0x10 75 reg = <0x02000000 0x1000>,
77 <0x02002000 0x10 76 <0x02002000 0x1000>;
78 }; 77 };
79 78
80 timer@200a000 { 79 timer@200a000 {
81 compatible = "qcom,kps 80 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer",
82 "qcom,msm 81 "qcom,msm-timer";
83 interrupts = <GIC_PPI 82 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
84 <GIC_PPI 83 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
85 <GIC_PPI 84 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
86 reg = <0x0200a000 0x10 85 reg = <0x0200a000 0x100>;
87 clock-frequency = <270 86 clock-frequency = <27000000>;
88 cpu-offset = <0x80000> 87 cpu-offset = <0x80000>;
89 }; 88 };
90 89
91 msmgpio: pinctrl@800000 { 90 msmgpio: pinctrl@800000 {
92 compatible = "qcom,mdm 91 compatible = "qcom,mdm9615-pinctrl";
93 gpio-controller; 92 gpio-controller;
94 gpio-ranges = <&msmgpi 93 gpio-ranges = <&msmgpio 0 0 88>;
95 #gpio-cells = <2>; 94 #gpio-cells = <2>;
96 interrupts = <GIC_SPI 95 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-controller; 96 interrupt-controller;
98 #interrupt-cells = <2> 97 #interrupt-cells = <2>;
99 reg = <0x800000 0x4000 98 reg = <0x800000 0x4000>;
100 }; 99 };
101 100
102 gcc: clock-controller@900000 { 101 gcc: clock-controller@900000 {
103 compatible = "qcom,gcc 102 compatible = "qcom,gcc-mdm9615";
104 #clock-cells = <1>; 103 #clock-cells = <1>;
>> 104 #power-domain-cells = <1>;
105 #reset-cells = <1>; 105 #reset-cells = <1>;
106 reg = <0x900000 0x4000 106 reg = <0x900000 0x4000>;
107 clocks = <&cxo_board>, <<
108 <&lcc PLL4>; <<
109 }; 107 };
110 108
111 lcc: clock-controller@28000000 109 lcc: clock-controller@28000000 {
112 compatible = "qcom,lcc 110 compatible = "qcom,lcc-mdm9615";
113 reg = <0x28000000 0x10 111 reg = <0x28000000 0x1000>;
114 #clock-cells = <1>; 112 #clock-cells = <1>;
115 #reset-cells = <1>; 113 #reset-cells = <1>;
116 clocks = <&cxo_board>, <<
117 <&gcc PLL4_VO <<
118 <0>, <<
119 <0>, <0>, <<
120 <0>, <0>, <<
121 <0>; <<
122 clock-names = "cxo", <<
123 "pll4_vo <<
124 "mi2s_co <<
125 "codec_i <<
126 "spare_i <<
127 "codec_i <<
128 "spare_i <<
129 "pcm_cod <<
130 }; 114 };
131 115
132 l2cc: clock-controller@2011000 116 l2cc: clock-controller@2011000 {
133 compatible = "qcom,kps 117 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
134 reg = <0x02011000 0x10 118 reg = <0x02011000 0x1000>;
135 }; 119 };
136 120
137 rng@1a500000 { 121 rng@1a500000 {
138 compatible = "qcom,prn 122 compatible = "qcom,prng";
139 reg = <0x1a500000 0x20 123 reg = <0x1a500000 0x200>;
140 clocks = <&gcc PRNG_CL 124 clocks = <&gcc PRNG_CLK>;
141 clock-names = "core"; 125 clock-names = "core";
142 assigned-clocks = <&gc 126 assigned-clocks = <&gcc PRNG_CLK>;
143 assigned-clock-rates = 127 assigned-clock-rates = <32000000>;
144 }; 128 };
145 129
146 gsbi2: gsbi@16100000 { 130 gsbi2: gsbi@16100000 {
147 compatible = "qcom,gsb 131 compatible = "qcom,gsbi-v1.0.0";
148 cell-index = <2>; 132 cell-index = <2>;
149 reg = <0x16100000 0x10 133 reg = <0x16100000 0x100>;
150 clocks = <&gcc GSBI2_H 134 clocks = <&gcc GSBI2_H_CLK>;
151 clock-names = "iface"; 135 clock-names = "iface";
152 status = "disabled"; 136 status = "disabled";
153 #address-cells = <1>; 137 #address-cells = <1>;
154 #size-cells = <1>; 138 #size-cells = <1>;
155 ranges; 139 ranges;
156 140
157 gsbi2_i2c: i2c@1618000 141 gsbi2_i2c: i2c@16180000 {
158 compatible = " 142 compatible = "qcom,i2c-qup-v1.1.1";
159 #address-cells 143 #address-cells = <1>;
160 #size-cells = 144 #size-cells = <0>;
161 reg = <0x16180 145 reg = <0x16180000 0x1000>;
162 interrupts = < 146 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
163 147
164 clocks = <&gcc 148 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
165 clock-names = 149 clock-names = "core", "iface";
166 status = "disa 150 status = "disabled";
167 }; 151 };
168 }; 152 };
169 153
170 gsbi3: gsbi@16200000 { 154 gsbi3: gsbi@16200000 {
171 compatible = "qcom,gsb 155 compatible = "qcom,gsbi-v1.0.0";
172 cell-index = <3>; 156 cell-index = <3>;
173 reg = <0x16200000 0x10 157 reg = <0x16200000 0x100>;
174 clocks = <&gcc GSBI3_H 158 clocks = <&gcc GSBI3_H_CLK>;
175 clock-names = "iface"; 159 clock-names = "iface";
176 status = "disabled"; 160 status = "disabled";
177 #address-cells = <1>; 161 #address-cells = <1>;
178 #size-cells = <1>; 162 #size-cells = <1>;
179 ranges; 163 ranges;
180 164
181 gsbi3_spi: spi@1628000 165 gsbi3_spi: spi@16280000 {
182 compatible = " 166 compatible = "qcom,spi-qup-v1.1.1";
183 #address-cells 167 #address-cells = <1>;
184 #size-cells = 168 #size-cells = <0>;
185 reg = <0x16280 169 reg = <0x16280000 0x1000>;
186 interrupts = < 170 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
187 171
188 clocks = <&gcc 172 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
189 clock-names = 173 clock-names = "core", "iface";
190 status = "disa 174 status = "disabled";
191 }; 175 };
192 }; 176 };
193 177
194 gsbi4: gsbi@16300000 { 178 gsbi4: gsbi@16300000 {
195 compatible = "qcom,gsb 179 compatible = "qcom,gsbi-v1.0.0";
196 cell-index = <4>; 180 cell-index = <4>;
197 reg = <0x16300000 0x10 181 reg = <0x16300000 0x100>;
198 clocks = <&gcc GSBI4_H 182 clocks = <&gcc GSBI4_H_CLK>;
199 clock-names = "iface"; 183 clock-names = "iface";
200 status = "disabled"; 184 status = "disabled";
201 #address-cells = <1>; 185 #address-cells = <1>;
202 #size-cells = <1>; 186 #size-cells = <1>;
203 ranges; 187 ranges;
204 188
205 syscon-tcsr = <&tcsr>; 189 syscon-tcsr = <&tcsr>;
206 190
207 gsbi4_serial: serial@1 191 gsbi4_serial: serial@16340000 {
208 compatible = " 192 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
209 reg = <0x16340 193 reg = <0x16340000 0x1000>,
210 <0x16300 194 <0x16300000 0x1000>;
211 interrupts = < 195 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&gcc 196 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
213 clock-names = 197 clock-names = "core", "iface";
214 status = "disa 198 status = "disabled";
215 }; 199 };
216 }; 200 };
217 201
218 gsbi5: gsbi@16400000 { 202 gsbi5: gsbi@16400000 {
219 compatible = "qcom,gsb 203 compatible = "qcom,gsbi-v1.0.0";
220 cell-index = <5>; 204 cell-index = <5>;
221 reg = <0x16400000 0x10 205 reg = <0x16400000 0x100>;
222 clocks = <&gcc GSBI5_H 206 clocks = <&gcc GSBI5_H_CLK>;
223 clock-names = "iface"; 207 clock-names = "iface";
224 status = "disabled"; 208 status = "disabled";
225 #address-cells = <1>; 209 #address-cells = <1>;
226 #size-cells = <1>; 210 #size-cells = <1>;
227 ranges; 211 ranges;
228 212
229 syscon-tcsr = <&tcsr>; 213 syscon-tcsr = <&tcsr>;
230 214
231 gsbi5_i2c: i2c@1648000 215 gsbi5_i2c: i2c@16480000 {
232 compatible = " 216 compatible = "qcom,i2c-qup-v1.1.1";
233 #address-cells 217 #address-cells = <1>;
234 #size-cells = 218 #size-cells = <0>;
235 reg = <0x16480 219 reg = <0x16480000 0x1000>;
236 interrupts = < 220 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
237 221
238 /* QUP clock i 222 /* QUP clock is not initialized, set rate */
239 assigned-clock 223 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
240 assigned-clock 224 assigned-clock-rates = <24000000>;
241 225
242 clocks = <&gcc 226 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
243 clock-names = 227 clock-names = "core", "iface";
244 status = "disa 228 status = "disabled";
245 }; 229 };
246 230
247 gsbi5_serial: serial@1 231 gsbi5_serial: serial@16440000 {
248 compatible = " 232 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
249 reg = <0x16440 233 reg = <0x16440000 0x1000>,
250 <0x16400 234 <0x16400000 0x1000>;
251 interrupts = < 235 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc 236 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
253 clock-names = 237 clock-names = "core", "iface";
254 status = "disa 238 status = "disabled";
255 }; 239 };
256 }; 240 };
257 241
258 ssbi: ssbi@500000 { !! 242 qcom,ssbi@500000 {
259 compatible = "qcom,ssb 243 compatible = "qcom,ssbi";
260 reg = <0x500000 0x1000 244 reg = <0x500000 0x1000>;
261 qcom,controller-type = 245 qcom,controller-type = "pmic-arbiter";
>> 246
>> 247 pmicintc: pmic {
>> 248 compatible = "qcom,pm8018", "qcom,pm8921";
>> 249 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
>> 250 #interrupt-cells = <2>;
>> 251 interrupt-controller;
>> 252 #address-cells = <1>;
>> 253 #size-cells = <0>;
>> 254
>> 255 pwrkey@1c {
>> 256 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
>> 257 reg = <0x1c>;
>> 258 interrupt-parent = <&pmicintc>;
>> 259 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
>> 260 <51 IRQ_TYPE_EDGE_RISING>;
>> 261 debounce = <15625>;
>> 262 pull-up;
>> 263 };
>> 264
>> 265 pmicmpp: mpps@50 {
>> 266 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
>> 267 interrupt-controller;
>> 268 #interrupt-cells = <2>;
>> 269 reg = <0x50>;
>> 270 gpio-controller;
>> 271 #gpio-cells = <2>;
>> 272 gpio-ranges = <&pmicmpp 0 0 6>;
>> 273 };
>> 274
>> 275 rtc@11d {
>> 276 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
>> 277 interrupt-parent = <&pmicintc>;
>> 278 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
>> 279 reg = <0x11d>;
>> 280 allow-set-time;
>> 281 };
>> 282
>> 283 pmicgpio: gpio@150 {
>> 284 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
>> 285 reg = <0x150>;
>> 286 interrupt-controller;
>> 287 #interrupt-cells = <2>;
>> 288 gpio-controller;
>> 289 gpio-ranges = <&pmicgpio 0 0 6>;
>> 290 #gpio-cells = <2>;
>> 291 };
>> 292 };
262 }; 293 };
263 294
264 sdcc1bam: dma-controller@12182 295 sdcc1bam: dma-controller@12182000 {
265 compatible = "qcom,bam 296 compatible = "qcom,bam-v1.3.0";
266 reg = <0x12182000 0x80 297 reg = <0x12182000 0x8000>;
267 interrupts = <GIC_SPI 298 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&gcc SDC1_H_ 299 clocks = <&gcc SDC1_H_CLK>;
269 clock-names = "bam_clk 300 clock-names = "bam_clk";
270 #dma-cells = <1>; 301 #dma-cells = <1>;
271 qcom,ee = <0>; 302 qcom,ee = <0>;
272 }; 303 };
273 304
274 sdcc2bam: dma-controller@12142 305 sdcc2bam: dma-controller@12142000 {
275 compatible = "qcom,bam 306 compatible = "qcom,bam-v1.3.0";
276 reg = <0x12142000 0x80 307 reg = <0x12142000 0x8000>;
277 interrupts = <GIC_SPI 308 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&gcc SDC2_H_ 309 clocks = <&gcc SDC2_H_CLK>;
279 clock-names = "bam_clk 310 clock-names = "bam_clk";
280 #dma-cells = <1>; 311 #dma-cells = <1>;
281 qcom,ee = <0>; 312 qcom,ee = <0>;
282 }; 313 };
283 314
284 sdcc1: mmc@12180000 { 315 sdcc1: mmc@12180000 {
285 status = "disabled"; 316 status = "disabled";
286 compatible = "arm,pl18 317 compatible = "arm,pl18x", "arm,primecell";
287 arm,primecell-periphid 318 arm,primecell-periphid = <0x00051180>;
288 reg = <0x12180000 0x20 319 reg = <0x12180000 0x2000>;
289 interrupts = <GIC_SPI 320 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&gcc SDC1_CL 321 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
291 clock-names = "mclk", 322 clock-names = "mclk", "apb_pclk";
292 bus-width = <8>; 323 bus-width = <8>;
293 max-frequency = <48000 324 max-frequency = <48000000>;
294 cap-sd-highspeed; 325 cap-sd-highspeed;
295 cap-mmc-highspeed; 326 cap-mmc-highspeed;
296 vmmc-supply = <&vsdcc_ 327 vmmc-supply = <&vsdcc_fixed>;
297 dmas = <&sdcc1bam 2>, 328 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
298 dma-names = "tx", "rx" 329 dma-names = "tx", "rx";
299 assigned-clocks = <&gc 330 assigned-clocks = <&gcc SDC1_CLK>;
300 assigned-clock-rates = 331 assigned-clock-rates = <400000>;
301 }; 332 };
302 333
303 sdcc2: mmc@12140000 { 334 sdcc2: mmc@12140000 {
304 compatible = "arm,pl18 335 compatible = "arm,pl18x", "arm,primecell";
305 arm,primecell-periphid 336 arm,primecell-periphid = <0x00051180>;
306 status = "disabled"; 337 status = "disabled";
307 reg = <0x12140000 0x20 338 reg = <0x12140000 0x2000>;
308 interrupts = <GIC_SPI 339 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&gcc SDC2_CL 340 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
310 clock-names = "mclk", 341 clock-names = "mclk", "apb_pclk";
311 bus-width = <4>; 342 bus-width = <4>;
312 cap-sd-highspeed; 343 cap-sd-highspeed;
313 cap-mmc-highspeed; 344 cap-mmc-highspeed;
314 max-frequency = <48000 345 max-frequency = <48000000>;
315 no-1-8-v; 346 no-1-8-v;
316 vmmc-supply = <&vsdcc_ 347 vmmc-supply = <&vsdcc_fixed>;
317 dmas = <&sdcc2bam 2>, 348 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
318 dma-names = "tx", "rx" 349 dma-names = "tx", "rx";
319 assigned-clocks = <&gc 350 assigned-clocks = <&gcc SDC2_CLK>;
320 assigned-clock-rates = 351 assigned-clock-rates = <400000>;
321 }; 352 };
322 353
323 tcsr: syscon@1a400000 { 354 tcsr: syscon@1a400000 {
324 compatible = "qcom,tcs 355 compatible = "qcom,tcsr-mdm9615", "syscon";
325 reg = <0x1a400000 0x10 356 reg = <0x1a400000 0x100>;
326 }; 357 };
327 358
328 rpm: rpm@108000 { 359 rpm: rpm@108000 {
329 compatible = "qcom,rpm 360 compatible = "qcom,rpm-mdm9615";
330 reg = <0x108000 0x1000 361 reg = <0x108000 0x1000>;
331 362
332 qcom,ipc = <&l2cc 0x8 363 qcom,ipc = <&l2cc 0x8 2>;
333 364
334 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
335 <GIC_SPI 366 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
336 <GIC_SPI 367 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
337 interrupt-names = "ack 368 interrupt-names = "ack", "err", "wakeup";
>> 369
>> 370 regulators {
>> 371 compatible = "qcom,rpm-pm8018-regulators";
>> 372
>> 373 vin_lvs1-supply = <&pm8018_s3>;
>> 374
>> 375 vdd_l7-supply = <&pm8018_s4>;
>> 376 vdd_l8-supply = <&pm8018_s3>;
>> 377 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
>> 378
>> 379 /* Buck SMPS */
>> 380 pm8018_s1: s1 {
>> 381 regulator-min-microvolt = <500000>;
>> 382 regulator-max-microvolt = <1150000>;
>> 383 qcom,switch-mode-frequency = <1600000>;
>> 384 bias-pull-down;
>> 385 };
>> 386
>> 387 pm8018_s2: s2 {
>> 388 regulator-min-microvolt = <1225000>;
>> 389 regulator-max-microvolt = <1300000>;
>> 390 qcom,switch-mode-frequency = <1600000>;
>> 391 bias-pull-down;
>> 392 };
>> 393
>> 394 pm8018_s3: s3 {
>> 395 regulator-always-on;
>> 396 regulator-min-microvolt = <1800000>;
>> 397 regulator-max-microvolt = <1800000>;
>> 398 qcom,switch-mode-frequency = <1600000>;
>> 399 bias-pull-down;
>> 400 };
>> 401
>> 402 pm8018_s4: s4 {
>> 403 regulator-min-microvolt = <2100000>;
>> 404 regulator-max-microvolt = <2200000>;
>> 405 qcom,switch-mode-frequency = <1600000>;
>> 406 bias-pull-down;
>> 407 };
>> 408
>> 409 pm8018_s5: s5 {
>> 410 regulator-always-on;
>> 411 regulator-min-microvolt = <1350000>;
>> 412 regulator-max-microvolt = <1350000>;
>> 413 qcom,switch-mode-frequency = <1600000>;
>> 414 bias-pull-down;
>> 415 };
>> 416
>> 417 /* PMOS LDO */
>> 418 pm8018_l2: l2 {
>> 419 regulator-always-on;
>> 420 regulator-min-microvolt = <1800000>;
>> 421 regulator-max-microvolt = <1800000>;
>> 422 bias-pull-down;
>> 423 };
>> 424
>> 425 pm8018_l3: l3 {
>> 426 regulator-always-on;
>> 427 regulator-min-microvolt = <1800000>;
>> 428 regulator-max-microvolt = <1800000>;
>> 429 bias-pull-down;
>> 430 };
>> 431
>> 432 pm8018_l4: l4 {
>> 433 regulator-min-microvolt = <3300000>;
>> 434 regulator-max-microvolt = <3300000>;
>> 435 bias-pull-down;
>> 436 };
>> 437
>> 438 pm8018_l5: l5 {
>> 439 regulator-min-microvolt = <2850000>;
>> 440 regulator-max-microvolt = <2850000>;
>> 441 bias-pull-down;
>> 442 };
>> 443
>> 444 pm8018_l6: l6 {
>> 445 regulator-min-microvolt = <1800000>;
>> 446 regulator-max-microvolt = <2850000>;
>> 447 bias-pull-down;
>> 448 };
>> 449
>> 450 pm8018_l7: l7 {
>> 451 regulator-min-microvolt = <1850000>;
>> 452 regulator-max-microvolt = <1900000>;
>> 453 bias-pull-down;
>> 454 };
>> 455
>> 456 pm8018_l8: l8 {
>> 457 regulator-min-microvolt = <1200000>;
>> 458 regulator-max-microvolt = <1200000>;
>> 459 bias-pull-down;
>> 460 };
>> 461
>> 462 pm8018_l9: l9 {
>> 463 regulator-min-microvolt = <750000>;
>> 464 regulator-max-microvolt = <1150000>;
>> 465 bias-pull-down;
>> 466 };
>> 467
>> 468 pm8018_l10: l10 {
>> 469 regulator-min-microvolt = <1050000>;
>> 470 regulator-max-microvolt = <1050000>;
>> 471 bias-pull-down;
>> 472 };
>> 473
>> 474 pm8018_l11: l11 {
>> 475 regulator-min-microvolt = <1050000>;
>> 476 regulator-max-microvolt = <1050000>;
>> 477 bias-pull-down;
>> 478 };
>> 479
>> 480 pm8018_l12: l12 {
>> 481 regulator-min-microvolt = <1050000>;
>> 482 regulator-max-microvolt = <1050000>;
>> 483 bias-pull-down;
>> 484 };
>> 485
>> 486 pm8018_l13: l13 {
>> 487 regulator-min-microvolt = <1850000>;
>> 488 regulator-max-microvolt = <2950000>;
>> 489 bias-pull-down;
>> 490 };
>> 491
>> 492 pm8018_l14: l14 {
>> 493 regulator-min-microvolt = <2850000>;
>> 494 regulator-max-microvolt = <2850000>;
>> 495 bias-pull-down;
>> 496 };
>> 497
>> 498 /* Low Voltage Switch */
>> 499 pm8018_lvs1: lvs1 {
>> 500 bias-pull-down;
>> 501 };
>> 502 };
338 }; 503 };
339 }; 504 };
340 }; 505 };
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