1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /* 2 /*
3 * Device Tree Source for Qualcomm MDM9615 SoC 3 * Device Tree Source for Qualcomm MDM9615 SoC
4 * 4 *
5 * Copyright (C) 2016 BayLibre, SAS. 5 * Copyright (C) 2016 BayLibre, SAS.
6 * Author : Neil Armstrong <narmstrong@baylibre 6 * Author : Neil Armstrong <narmstrong@baylibre.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h 12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h 13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h 14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h> 15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h> 16 #include <dt-bindings/soc/qcom,gsbi.h>
17 17
18 / { 18 / {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <1>; 20 #size-cells = <1>;
21 model = "Qualcomm MDM9615"; 21 model = "Qualcomm MDM9615";
22 compatible = "qcom,mdm9615"; 22 compatible = "qcom,mdm9615";
23 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu0: cpu@0 { 29 cpu0: cpu@0 {
30 compatible = "arm,cort 30 compatible = "arm,cortex-a5";
31 reg = <0>; 31 reg = <0>;
32 device_type = "cpu"; 32 device_type = "cpu";
33 next-level-cache = <&L 33 next-level-cache = <&L2>;
34 }; 34 };
35 }; 35 };
36 36
37 cpu-pmu { 37 cpu-pmu {
38 compatible = "arm,cortex-a5-pm 38 compatible = "arm,cortex-a5-pmu";
39 interrupts = <GIC_PPI 10 (GIC_ 39 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
40 }; 40 };
41 41
42 clocks { 42 clocks {
43 cxo_board: cxo_board { 43 cxo_board: cxo_board {
44 compatible = "fixed-cl 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 clock-frequency = <192 46 clock-frequency = <19200000>;
47 }; 47 };
48 }; 48 };
49 49
50 vsdcc_fixed: vsdcc-regulator { 50 vsdcc_fixed: vsdcc-regulator {
51 compatible = "regulator-fixed" 51 compatible = "regulator-fixed";
52 regulator-name = "SDCC Power"; 52 regulator-name = "SDCC Power";
53 regulator-min-microvolt = <270 53 regulator-min-microvolt = <2700000>;
54 regulator-max-microvolt = <270 54 regulator-max-microvolt = <2700000>;
55 regulator-always-on; 55 regulator-always-on;
56 }; 56 };
57 57
58 soc: soc { 58 soc: soc {
59 #address-cells = <1>; 59 #address-cells = <1>;
60 #size-cells = <1>; 60 #size-cells = <1>;
61 ranges; 61 ranges;
62 compatible = "simple-bus"; 62 compatible = "simple-bus";
63 63
64 L2: cache-controller@2040000 { 64 L2: cache-controller@2040000 {
65 compatible = "arm,pl31 65 compatible = "arm,pl310-cache";
66 reg = <0x02040000 0x10 66 reg = <0x02040000 0x1000>;
67 arm,data-latency = <2 67 arm,data-latency = <2 2 0>;
68 cache-unified; 68 cache-unified;
69 cache-level = <2>; 69 cache-level = <2>;
70 }; 70 };
71 71
72 intc: interrupt-controller@200 72 intc: interrupt-controller@2000000 {
73 compatible = "qcom,msm 73 compatible = "qcom,msm-qgic2";
74 interrupt-controller; 74 interrupt-controller;
75 #interrupt-cells = <3> 75 #interrupt-cells = <3>;
76 reg = <0x02000000 0x10 76 reg = <0x02000000 0x1000>,
77 <0x02002000 0x10 77 <0x02002000 0x1000>;
78 }; 78 };
79 79
80 timer@200a000 { 80 timer@200a000 {
81 compatible = "qcom,kps 81 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer",
82 "qcom,msm 82 "qcom,msm-timer";
83 interrupts = <GIC_PPI 83 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
84 <GIC_PPI 84 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
85 <GIC_PPI 85 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
86 reg = <0x0200a000 0x10 86 reg = <0x0200a000 0x100>;
87 clock-frequency = <270 87 clock-frequency = <27000000>;
88 cpu-offset = <0x80000> 88 cpu-offset = <0x80000>;
89 }; 89 };
90 90
91 msmgpio: pinctrl@800000 { 91 msmgpio: pinctrl@800000 {
92 compatible = "qcom,mdm 92 compatible = "qcom,mdm9615-pinctrl";
93 gpio-controller; 93 gpio-controller;
94 gpio-ranges = <&msmgpi 94 gpio-ranges = <&msmgpio 0 0 88>;
95 #gpio-cells = <2>; 95 #gpio-cells = <2>;
96 interrupts = <GIC_SPI 96 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-controller; 97 interrupt-controller;
98 #interrupt-cells = <2> 98 #interrupt-cells = <2>;
99 reg = <0x800000 0x4000 99 reg = <0x800000 0x4000>;
100 }; 100 };
101 101
102 gcc: clock-controller@900000 { 102 gcc: clock-controller@900000 {
103 compatible = "qcom,gcc 103 compatible = "qcom,gcc-mdm9615";
104 #clock-cells = <1>; 104 #clock-cells = <1>;
>> 105 #power-domain-cells = <1>;
105 #reset-cells = <1>; 106 #reset-cells = <1>;
106 reg = <0x900000 0x4000 107 reg = <0x900000 0x4000>;
107 clocks = <&cxo_board>, 108 clocks = <&cxo_board>,
108 <&lcc PLL4>; 109 <&lcc PLL4>;
109 }; 110 };
110 111
111 lcc: clock-controller@28000000 112 lcc: clock-controller@28000000 {
112 compatible = "qcom,lcc 113 compatible = "qcom,lcc-mdm9615";
113 reg = <0x28000000 0x10 114 reg = <0x28000000 0x1000>;
114 #clock-cells = <1>; 115 #clock-cells = <1>;
115 #reset-cells = <1>; 116 #reset-cells = <1>;
116 clocks = <&cxo_board>, 117 clocks = <&cxo_board>,
117 <&gcc PLL4_VO 118 <&gcc PLL4_VOTE>,
118 <0>, 119 <0>,
119 <0>, <0>, 120 <0>, <0>,
120 <0>, <0>, 121 <0>, <0>,
121 <0>; 122 <0>;
122 clock-names = "cxo", 123 clock-names = "cxo",
123 "pll4_vo 124 "pll4_vote",
124 "mi2s_co 125 "mi2s_codec_clk",
125 "codec_i 126 "codec_i2s_mic_codec_clk",
126 "spare_i 127 "spare_i2s_mic_codec_clk",
127 "codec_i 128 "codec_i2s_spkr_codec_clk",
128 "spare_i 129 "spare_i2s_spkr_codec_clk",
129 "pcm_cod 130 "pcm_codec_clk";
130 }; 131 };
131 132
132 l2cc: clock-controller@2011000 133 l2cc: clock-controller@2011000 {
133 compatible = "qcom,kps 134 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
134 reg = <0x02011000 0x10 135 reg = <0x02011000 0x1000>;
135 }; 136 };
136 137
137 rng@1a500000 { 138 rng@1a500000 {
138 compatible = "qcom,prn 139 compatible = "qcom,prng";
139 reg = <0x1a500000 0x20 140 reg = <0x1a500000 0x200>;
140 clocks = <&gcc PRNG_CL 141 clocks = <&gcc PRNG_CLK>;
141 clock-names = "core"; 142 clock-names = "core";
142 assigned-clocks = <&gc 143 assigned-clocks = <&gcc PRNG_CLK>;
143 assigned-clock-rates = 144 assigned-clock-rates = <32000000>;
144 }; 145 };
145 146
146 gsbi2: gsbi@16100000 { 147 gsbi2: gsbi@16100000 {
147 compatible = "qcom,gsb 148 compatible = "qcom,gsbi-v1.0.0";
148 cell-index = <2>; 149 cell-index = <2>;
149 reg = <0x16100000 0x10 150 reg = <0x16100000 0x100>;
150 clocks = <&gcc GSBI2_H 151 clocks = <&gcc GSBI2_H_CLK>;
151 clock-names = "iface"; 152 clock-names = "iface";
152 status = "disabled"; 153 status = "disabled";
153 #address-cells = <1>; 154 #address-cells = <1>;
154 #size-cells = <1>; 155 #size-cells = <1>;
155 ranges; 156 ranges;
156 157
157 gsbi2_i2c: i2c@1618000 158 gsbi2_i2c: i2c@16180000 {
158 compatible = " 159 compatible = "qcom,i2c-qup-v1.1.1";
159 #address-cells 160 #address-cells = <1>;
160 #size-cells = 161 #size-cells = <0>;
161 reg = <0x16180 162 reg = <0x16180000 0x1000>;
162 interrupts = < 163 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
163 164
164 clocks = <&gcc 165 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
165 clock-names = 166 clock-names = "core", "iface";
166 status = "disa 167 status = "disabled";
167 }; 168 };
168 }; 169 };
169 170
170 gsbi3: gsbi@16200000 { 171 gsbi3: gsbi@16200000 {
171 compatible = "qcom,gsb 172 compatible = "qcom,gsbi-v1.0.0";
172 cell-index = <3>; 173 cell-index = <3>;
173 reg = <0x16200000 0x10 174 reg = <0x16200000 0x100>;
174 clocks = <&gcc GSBI3_H 175 clocks = <&gcc GSBI3_H_CLK>;
175 clock-names = "iface"; 176 clock-names = "iface";
176 status = "disabled"; 177 status = "disabled";
177 #address-cells = <1>; 178 #address-cells = <1>;
178 #size-cells = <1>; 179 #size-cells = <1>;
179 ranges; 180 ranges;
180 181
181 gsbi3_spi: spi@1628000 182 gsbi3_spi: spi@16280000 {
182 compatible = " 183 compatible = "qcom,spi-qup-v1.1.1";
183 #address-cells 184 #address-cells = <1>;
184 #size-cells = 185 #size-cells = <0>;
185 reg = <0x16280 186 reg = <0x16280000 0x1000>;
186 interrupts = < 187 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
187 188
188 clocks = <&gcc 189 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
189 clock-names = 190 clock-names = "core", "iface";
190 status = "disa 191 status = "disabled";
191 }; 192 };
192 }; 193 };
193 194
194 gsbi4: gsbi@16300000 { 195 gsbi4: gsbi@16300000 {
195 compatible = "qcom,gsb 196 compatible = "qcom,gsbi-v1.0.0";
196 cell-index = <4>; 197 cell-index = <4>;
197 reg = <0x16300000 0x10 198 reg = <0x16300000 0x100>;
198 clocks = <&gcc GSBI4_H 199 clocks = <&gcc GSBI4_H_CLK>;
199 clock-names = "iface"; 200 clock-names = "iface";
200 status = "disabled"; 201 status = "disabled";
201 #address-cells = <1>; 202 #address-cells = <1>;
202 #size-cells = <1>; 203 #size-cells = <1>;
203 ranges; 204 ranges;
204 205
205 syscon-tcsr = <&tcsr>; 206 syscon-tcsr = <&tcsr>;
206 207
207 gsbi4_serial: serial@1 208 gsbi4_serial: serial@16340000 {
208 compatible = " 209 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
209 reg = <0x16340 210 reg = <0x16340000 0x1000>,
210 <0x16300 211 <0x16300000 0x1000>;
211 interrupts = < 212 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&gcc 213 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
213 clock-names = 214 clock-names = "core", "iface";
214 status = "disa 215 status = "disabled";
215 }; 216 };
216 }; 217 };
217 218
218 gsbi5: gsbi@16400000 { 219 gsbi5: gsbi@16400000 {
219 compatible = "qcom,gsb 220 compatible = "qcom,gsbi-v1.0.0";
220 cell-index = <5>; 221 cell-index = <5>;
221 reg = <0x16400000 0x10 222 reg = <0x16400000 0x100>;
222 clocks = <&gcc GSBI5_H 223 clocks = <&gcc GSBI5_H_CLK>;
223 clock-names = "iface"; 224 clock-names = "iface";
224 status = "disabled"; 225 status = "disabled";
225 #address-cells = <1>; 226 #address-cells = <1>;
226 #size-cells = <1>; 227 #size-cells = <1>;
227 ranges; 228 ranges;
228 229
229 syscon-tcsr = <&tcsr>; 230 syscon-tcsr = <&tcsr>;
230 231
231 gsbi5_i2c: i2c@1648000 232 gsbi5_i2c: i2c@16480000 {
232 compatible = " 233 compatible = "qcom,i2c-qup-v1.1.1";
233 #address-cells 234 #address-cells = <1>;
234 #size-cells = 235 #size-cells = <0>;
235 reg = <0x16480 236 reg = <0x16480000 0x1000>;
236 interrupts = < 237 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
237 238
238 /* QUP clock i 239 /* QUP clock is not initialized, set rate */
239 assigned-clock 240 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
240 assigned-clock 241 assigned-clock-rates = <24000000>;
241 242
242 clocks = <&gcc 243 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
243 clock-names = 244 clock-names = "core", "iface";
244 status = "disa 245 status = "disabled";
245 }; 246 };
246 247
247 gsbi5_serial: serial@1 248 gsbi5_serial: serial@16440000 {
248 compatible = " 249 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
249 reg = <0x16440 250 reg = <0x16440000 0x1000>,
250 <0x16400 251 <0x16400000 0x1000>;
251 interrupts = < 252 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc 253 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
253 clock-names = 254 clock-names = "core", "iface";
254 status = "disa 255 status = "disabled";
255 }; 256 };
256 }; 257 };
257 258
258 ssbi: ssbi@500000 { 259 ssbi: ssbi@500000 {
259 compatible = "qcom,ssb 260 compatible = "qcom,ssbi";
260 reg = <0x500000 0x1000 261 reg = <0x500000 0x1000>;
261 qcom,controller-type = 262 qcom,controller-type = "pmic-arbiter";
262 }; 263 };
263 264
264 sdcc1bam: dma-controller@12182 265 sdcc1bam: dma-controller@12182000 {
265 compatible = "qcom,bam 266 compatible = "qcom,bam-v1.3.0";
266 reg = <0x12182000 0x80 267 reg = <0x12182000 0x8000>;
267 interrupts = <GIC_SPI 268 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&gcc SDC1_H_ 269 clocks = <&gcc SDC1_H_CLK>;
269 clock-names = "bam_clk 270 clock-names = "bam_clk";
270 #dma-cells = <1>; 271 #dma-cells = <1>;
271 qcom,ee = <0>; 272 qcom,ee = <0>;
272 }; 273 };
273 274
274 sdcc2bam: dma-controller@12142 275 sdcc2bam: dma-controller@12142000 {
275 compatible = "qcom,bam 276 compatible = "qcom,bam-v1.3.0";
276 reg = <0x12142000 0x80 277 reg = <0x12142000 0x8000>;
277 interrupts = <GIC_SPI 278 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&gcc SDC2_H_ 279 clocks = <&gcc SDC2_H_CLK>;
279 clock-names = "bam_clk 280 clock-names = "bam_clk";
280 #dma-cells = <1>; 281 #dma-cells = <1>;
281 qcom,ee = <0>; 282 qcom,ee = <0>;
282 }; 283 };
283 284
284 sdcc1: mmc@12180000 { 285 sdcc1: mmc@12180000 {
285 status = "disabled"; 286 status = "disabled";
286 compatible = "arm,pl18 287 compatible = "arm,pl18x", "arm,primecell";
287 arm,primecell-periphid 288 arm,primecell-periphid = <0x00051180>;
288 reg = <0x12180000 0x20 289 reg = <0x12180000 0x2000>;
289 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&gcc SDC1_CL 291 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
291 clock-names = "mclk", 292 clock-names = "mclk", "apb_pclk";
292 bus-width = <8>; 293 bus-width = <8>;
293 max-frequency = <48000 294 max-frequency = <48000000>;
294 cap-sd-highspeed; 295 cap-sd-highspeed;
295 cap-mmc-highspeed; 296 cap-mmc-highspeed;
296 vmmc-supply = <&vsdcc_ 297 vmmc-supply = <&vsdcc_fixed>;
297 dmas = <&sdcc1bam 2>, 298 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
298 dma-names = "tx", "rx" 299 dma-names = "tx", "rx";
299 assigned-clocks = <&gc 300 assigned-clocks = <&gcc SDC1_CLK>;
300 assigned-clock-rates = 301 assigned-clock-rates = <400000>;
301 }; 302 };
302 303
303 sdcc2: mmc@12140000 { 304 sdcc2: mmc@12140000 {
304 compatible = "arm,pl18 305 compatible = "arm,pl18x", "arm,primecell";
305 arm,primecell-periphid 306 arm,primecell-periphid = <0x00051180>;
306 status = "disabled"; 307 status = "disabled";
307 reg = <0x12140000 0x20 308 reg = <0x12140000 0x2000>;
308 interrupts = <GIC_SPI 309 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&gcc SDC2_CL 310 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
310 clock-names = "mclk", 311 clock-names = "mclk", "apb_pclk";
311 bus-width = <4>; 312 bus-width = <4>;
312 cap-sd-highspeed; 313 cap-sd-highspeed;
313 cap-mmc-highspeed; 314 cap-mmc-highspeed;
314 max-frequency = <48000 315 max-frequency = <48000000>;
315 no-1-8-v; 316 no-1-8-v;
316 vmmc-supply = <&vsdcc_ 317 vmmc-supply = <&vsdcc_fixed>;
317 dmas = <&sdcc2bam 2>, 318 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
318 dma-names = "tx", "rx" 319 dma-names = "tx", "rx";
319 assigned-clocks = <&gc 320 assigned-clocks = <&gcc SDC2_CLK>;
320 assigned-clock-rates = 321 assigned-clock-rates = <400000>;
321 }; 322 };
322 323
323 tcsr: syscon@1a400000 { 324 tcsr: syscon@1a400000 {
324 compatible = "qcom,tcs 325 compatible = "qcom,tcsr-mdm9615", "syscon";
325 reg = <0x1a400000 0x10 326 reg = <0x1a400000 0x100>;
326 }; 327 };
327 328
328 rpm: rpm@108000 { 329 rpm: rpm@108000 {
329 compatible = "qcom,rpm 330 compatible = "qcom,rpm-mdm9615";
330 reg = <0x108000 0x1000 331 reg = <0x108000 0x1000>;
331 332
332 qcom,ipc = <&l2cc 0x8 333 qcom,ipc = <&l2cc 0x8 2>;
333 334
334 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
335 <GIC_SPI 336 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
336 <GIC_SPI 337 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
337 interrupt-names = "ack 338 interrupt-names = "ack", "err", "wakeup";
338 }; 339 };
339 }; 340 };
340 }; 341 };
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