1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, The Linux Foundation. A
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h
15 #include <dt-bindings/thermal/thermal.h>
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&intc>;
21
22 chosen { };
23
24 clocks {
25 xo_board: xo_board {
26 compatible = "fixed-cl
27 #clock-cells = <0>;
28 clock-frequency = <192
29 };
30
31 sleep_clk: sleep_clk {
32 compatible = "fixed-cl
33 #clock-cells = <0>;
34 clock-frequency = <327
35 };
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 CPU0: cpu@0 {
43 compatible = "arm,cort
44 enable-method = "qcom,
45 device_type = "cpu";
46 reg = <0>;
47 next-level-cache = <&L
48 clocks = <&apcs>;
49 operating-points-v2 =
50 qcom,acc = <&acc0>;
51 qcom,saw = <&saw0>;
52 #cooling-cells = <2>;
53 };
54
55 CPU1: cpu@1 {
56 compatible = "arm,cort
57 enable-method = "qcom,
58 device_type = "cpu";
59 reg = <1>;
60 next-level-cache = <&L
61 clocks = <&apcs>;
62 operating-points-v2 =
63 qcom,acc = <&acc1>;
64 qcom,saw = <&saw1>;
65 #cooling-cells = <2>;
66 };
67
68 CPU2: cpu@2 {
69 compatible = "arm,cort
70 enable-method = "qcom,
71 device_type = "cpu";
72 reg = <2>;
73 next-level-cache = <&L
74 clocks = <&apcs>;
75 operating-points-v2 =
76 qcom,acc = <&acc2>;
77 qcom,saw = <&saw2>;
78 #cooling-cells = <2>;
79 };
80
81 CPU3: cpu@3 {
82 compatible = "arm,cort
83 enable-method = "qcom,
84 device_type = "cpu";
85 reg = <3>;
86 next-level-cache = <&L
87 clocks = <&apcs>;
88 operating-points-v2 =
89 qcom,acc = <&acc3>;
90 qcom,saw = <&saw3>;
91 #cooling-cells = <2>;
92 };
93
94 L2: l2-cache {
95 compatible = "cache";
96 cache-level = <2>;
97 cache-unified;
98 };
99 };
100
101 firmware {
102 scm {
103 compatible = "qcom,scm
104 clocks = <&gcc GCC_CE1
105 clock-names = "core",
106 };
107 };
108
109 memory@0 {
110 device_type = "memory";
111 reg = <0x0 0x0>;
112 };
113
114 cpu_opp_table: opp-table-cpu {
115 compatible = "operating-points
116 opp-shared;
117
118 opp-300000000 {
119 opp-hz = /bits/ 64 <30
120 };
121
122 opp-384000000 {
123 opp-hz = /bits/ 64 <38
124 };
125
126 opp-600000000 {
127 opp-hz = /bits/ 64 <60
128 };
129
130 opp-787200000 {
131 opp-hz = /bits/ 64 <78
132 };
133
134 /* Higher CPU frequencies need
135 };
136
137 pmu {
138 compatible = "arm,cortex-a7-pm
139 interrupts = <GIC_PPI 7 (GIC_C
140 IRQ_T
141 };
142
143 rpm: remoteproc {
144 compatible = "qcom,msm8226-rpm
145
146 master-stats {
147 compatible = "qcom,rpm
148 qcom,rpm-msg-ram = <&a
149 <&m
150 <&l
151 <&p
152 qcom,master-names = "A
153 "M
154 "L
155 "P
156 };
157
158 smd-edge {
159 interrupts = <GIC_SPI
160 mboxes = <&apcs 0>;
161 qcom,smd-edge = <15>;
162
163 rpm_requests: rpm-requ
164 compatible = "
165 qcom,smd-chann
166
167 rpmcc: clock-c
168 compat
169 #clock
170 clocks
171 clock-
172 };
173
174 rpmpd: power-c
175 compat
176 #power
177 operat
178
179 rpmpd_
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200 };
201 };
202 };
203 };
204 };
205
206 reserved-memory {
207 #address-cells = <1>;
208 #size-cells = <1>;
209 ranges;
210
211 smem_region: smem@3000000 {
212 reg = <0x3000000 0x100
213 no-map;
214 };
215
216 adsp_region: adsp@dc00000 {
217 reg = <0x0dc00000 0x19
218 no-map;
219 };
220 };
221
222 smem {
223 compatible = "qcom,smem";
224
225 memory-region = <&smem_region>
226 qcom,rpm-msg-ram = <&rpm_msg_r
227
228 hwlocks = <&tcsr_mutex 3>;
229 };
230
231 smp2p-adsp {
232 compatible = "qcom,smp2p";
233 qcom,smem = <443>, <429>;
234
235 interrupt-parent = <&intc>;
236 interrupts = <GIC_SPI 158 IRQ_
237
238 mboxes = <&apcs 10>;
239
240 qcom,local-pid = <0>;
241 qcom,remote-pid = <2>;
242
243 adsp_smp2p_out: master-kernel
244 qcom,entry-name = "mas
245 #qcom,smem-state-cells
246 };
247
248 adsp_smp2p_in: slave-kernel {
249 qcom,entry-name = "sla
250
251 interrupt-controller;
252 #interrupt-cells = <2>
253 };
254 };
255
256 soc: soc {
257 compatible = "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges;
261
262 intc: interrupt-controller@f90
263 compatible = "qcom,msm
264 reg = <0xf9000000 0x10
265 <0xf9002000 0x10
266 interrupt-controller;
267 #interrupt-cells = <3>
268 };
269
270 apcs: mailbox@f9011000 {
271 compatible = "qcom,msm
272 "qcom,msm
273 reg = <0xf9011000 0x10
274 #mbox-cells = <1>;
275 clocks = <&a7pll>, <&g
276 clock-names = "pll", "
277 #clock-cells = <0>;
278 };
279
280 a7pll: clock@f9016000 {
281 compatible = "qcom,msm
282 reg = <0xf9016000 0x40
283 #clock-cells = <0>;
284 clocks = <&xo_board>;
285 clock-names = "xo";
286 operating-points-v2 =
287
288 a7pll_opp_table: opp-t
289 compatible = "
290
291 opp-768000000
292 opp-hz
293 };
294
295 opp-787200000
296 opp-hz
297 };
298
299 opp-998400000
300 opp-hz
301 };
302
303 opp-1094400000
304 opp-hz
305 };
306
307 opp-1190400000
308 opp-hz
309 };
310
311 opp-1305600000
312 opp-hz
313 };
314
315 opp-1344000000
316 opp-hz
317 };
318
319 opp-1401600000
320 opp-hz
321 };
322
323 opp-1497600000
324 opp-hz
325 };
326
327 opp-1593600000
328 opp-hz
329 };
330
331 opp-1689600000
332 opp-hz
333 };
334
335 opp-1785600000
336 opp-hz
337 };
338 };
339 };
340
341 saw_l2: power-manager@f9012000
342 compatible = "qcom,msm
343 reg = <0xf9012000 0x10
344 };
345
346 watchdog@f9017000 {
347 compatible = "qcom,aps
348 reg = <0xf9017000 0x10
349 interrupts = <GIC_SPI
350 <GIC_SPI
351 clocks = <&sleep_clk>;
352 };
353
354 timer@f9020000 {
355 compatible = "arm,armv
356 reg = <0xf9020000 0x10
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges;
360
361 frame@f9021000 {
362 frame-number =
363 interrupts = <
364 <
365 reg = <0xf9021
366 <0xf9022
367 };
368
369 frame@f9023000 {
370 frame-number =
371 interrupts = <
372 reg = <0xf9023
373 status = "disa
374 };
375
376 frame@f9024000 {
377 frame-number =
378 interrupts = <
379 reg = <0xf9024
380 status = "disa
381 };
382
383 frame@f9025000 {
384 frame-number =
385 interrupts = <
386 reg = <0xf9025
387 status = "disa
388 };
389
390 frame@f9026000 {
391 frame-number =
392 interrupts = <
393 reg = <0xf9026
394 status = "disa
395 };
396
397 frame@f9027000 {
398 frame-number =
399 interrupts = <
400 reg = <0xf9027
401 status = "disa
402 };
403
404 frame@f9028000 {
405 frame-number =
406 interrupts = <
407 reg = <0xf9028
408 status = "disa
409 };
410 };
411
412 acc0: power-manager@f9088000 {
413 compatible = "qcom,kps
414 reg = <0xf9088000 0x10
415 };
416
417 saw0: power-manager@f9089000 {
418 compatible = "qcom,msm
419 reg = <0xf9089000 0x10
420 };
421
422 acc1: power-manager@f9098000 {
423 compatible = "qcom,kps
424 reg = <0xf9098000 0x10
425 };
426
427 saw1: power-manager@f9099000 {
428 compatible = "qcom,msm
429 reg = <0xf9099000 0x10
430 };
431
432 acc2: power-manager@f90a8000 {
433 compatible = "qcom,kps
434 reg = <0xf90a8000 0x10
435 };
436
437 saw2: power-manager@f90a9000 {
438 compatible = "qcom,msm
439 reg = <0xf90a9000 0x10
440 };
441
442 acc3: power-manager@f90b8000 {
443 compatible = "qcom,kps
444 reg = <0xf90b8000 0x10
445 };
446
447 saw3: power-manager@f90b9000 {
448 compatible = "qcom,msm
449 reg = <0xf90b9000 0x10
450 };
451
452 sdhc_1: mmc@f9824900 {
453 compatible = "qcom,msm
454 reg = <0xf9824900 0x11
455 reg-names = "hc", "cor
456 interrupts = <GIC_SPI
457 <GIC_SPI
458 interrupt-names = "hc_
459 clocks = <&gcc GCC_SDC
460 <&gcc GCC_SDC
461 <&rpmcc RPM_S
462 clock-names = "iface",
463 pinctrl-names = "defau
464 pinctrl-0 = <&sdhc1_de
465 status = "disabled";
466 };
467
468 sdhc_3: mmc@f9864900 {
469 compatible = "qcom,msm
470 reg = <0xf9864900 0x11
471 reg-names = "hc", "cor
472 interrupts = <GIC_SPI
473 <GIC_SPI
474 interrupt-names = "hc_
475 clocks = <&gcc GCC_SDC
476 <&gcc GCC_SDC
477 <&rpmcc RPM_S
478 clock-names = "iface",
479 pinctrl-names = "defau
480 pinctrl-0 = <&sdhc3_de
481 status = "disabled";
482 };
483
484 sdhc_2: mmc@f98a4900 {
485 compatible = "qcom,msm
486 reg = <0xf98a4900 0x11
487 reg-names = "hc", "cor
488 interrupts = <GIC_SPI
489 <GIC_SPI
490 interrupt-names = "hc_
491 clocks = <&gcc GCC_SDC
492 <&gcc GCC_SDC
493 <&rpmcc RPM_S
494 clock-names = "iface",
495 pinctrl-names = "defau
496 pinctrl-0 = <&sdhc2_de
497 status = "disabled";
498 };
499
500 blsp1_uart1: serial@f991d000 {
501 compatible = "qcom,msm
502 reg = <0xf991d000 0x10
503 interrupts = <GIC_SPI
504 clocks = <&gcc GCC_BLS
505 clock-names = "core",
506 status = "disabled";
507 };
508
509 blsp1_uart2: serial@f991e000 {
510 compatible = "qcom,msm
511 reg = <0xf991e000 0x10
512 interrupts = <GIC_SPI
513 clocks = <&gcc GCC_BLS
514 <&gcc GCC_BLS
515 clock-names = "core",
516 "iface";
517 status = "disabled";
518 };
519
520 blsp1_uart3: serial@f991f000 {
521 compatible = "qcom,msm
522 reg = <0xf991f000 0x10
523 interrupts = <GIC_SPI
524 clocks = <&gcc GCC_BLS
525 clock-names = "core",
526 status = "disabled";
527 };
528
529 blsp1_uart4: serial@f9920000 {
530 compatible = "qcom,msm
531 reg = <0xf9920000 0x10
532 interrupts = <GIC_SPI
533 clocks = <&gcc GCC_BLS
534 clock-names = "core",
535 status = "disabled";
536 };
537
538 blsp1_i2c1: i2c@f9923000 {
539 compatible = "qcom,i2c
540 reg = <0xf9923000 0x10
541 interrupts = <GIC_SPI
542 clocks = <&gcc GCC_BLS
543 clock-names = "core",
544 pinctrl-names = "defau
545 pinctrl-0 = <&blsp1_i2
546 #address-cells = <1>;
547 #size-cells = <0>;
548 status = "disabled";
549 };
550
551 blsp1_i2c2: i2c@f9924000 {
552 compatible = "qcom,i2c
553 reg = <0xf9924000 0x10
554 interrupts = <GIC_SPI
555 clocks = <&gcc GCC_BLS
556 clock-names = "core",
557 pinctrl-names = "defau
558 pinctrl-0 = <&blsp1_i2
559 #address-cells = <1>;
560 #size-cells = <0>;
561 status = "disabled";
562 };
563
564 blsp1_i2c3: i2c@f9925000 {
565 compatible = "qcom,i2c
566 reg = <0xf9925000 0x10
567 interrupts = <GIC_SPI
568 clocks = <&gcc GCC_BLS
569 clock-names = "core",
570 pinctrl-names = "defau
571 pinctrl-0 = <&blsp1_i2
572 #address-cells = <1>;
573 #size-cells = <0>;
574 status = "disabled";
575 };
576
577 blsp1_i2c4: i2c@f9926000 {
578 compatible = "qcom,i2c
579 reg = <0xf9926000 0x10
580 interrupts = <GIC_SPI
581 clocks = <&gcc GCC_BLS
582 clock-names = "core",
583 pinctrl-names = "defau
584 pinctrl-0 = <&blsp1_i2
585 #address-cells = <1>;
586 #size-cells = <0>;
587 status = "disabled";
588 };
589
590 blsp1_i2c5: i2c@f9927000 {
591 compatible = "qcom,i2c
592 reg = <0xf9927000 0x10
593 interrupts = <GIC_SPI
594 clocks = <&gcc GCC_BLS
595 clock-names = "core",
596 pinctrl-names = "defau
597 pinctrl-0 = <&blsp1_i2
598 #address-cells = <1>;
599 #size-cells = <0>;
600 status = "disabled";
601 };
602
603 blsp1_i2c6: i2c@f9928000 {
604 compatible = "qcom,i2c
605 reg = <0xf9928000 0x10
606 interrupts = <GIC_SPI
607 clocks = <&gcc GCC_BLS
608 <&gcc GCC_BLS
609 clock-names = "core",
610 "iface";
611 pinctrl-0 = <&blsp1_i2
612 pinctrl-names = "defau
613 #address-cells = <1>;
614 #size-cells = <0>;
615 status = "disabled";
616 };
617
618 usb: usb@f9a55000 {
619 compatible = "qcom,ci-
620 reg = <0xf9a55000 0x20
621 <0xf9a55200 0x20
622 interrupts = <GIC_SPI
623 clocks = <&gcc GCC_USB
624 <&gcc GCC_USB
625 clock-names = "iface",
626 assigned-clocks = <&gc
627 assigned-clock-rates =
628 resets = <&gcc GCC_USB
629 reset-names = "core";
630 phy_type = "ulpi";
631 dr_mode = "otg";
632 hnp-disable;
633 srp-disable;
634 adp-disable;
635 ahb-burst-config = <0>
636 phy-names = "usb-phy";
637 phys = <&usb_hs_phy>;
638 status = "disabled";
639 #reset-cells = <1>;
640
641 ulpi {
642 usb_hs_phy: ph
643 compat
644
645 #phy-c
646 clocks
647
648 clock-
649 resets
650 reset-
651 qcom,i
652
653 };
654 };
655 };
656
657 rng@f9bff000 {
658 compatible = "qcom,prn
659 reg = <0xf9bff000 0x20
660 clocks = <&gcc GCC_PRN
661 clock-names = "core";
662 };
663
664 sram@fc190000 {
665 compatible = "qcom,msm
666 reg = <0xfc190000 0x10
667 };
668
669 gcc: clock-controller@fc400000
670 compatible = "qcom,gcc
671 reg = <0xfc400000 0x40
672 #clock-cells = <1>;
673 #reset-cells = <1>;
674 #power-domain-cells =
675
676 clocks = <&xo_board>,
677 <&sleep_clk>;
678 clock-names = "xo",
679 "sleep_c
680 };
681
682 rpm_msg_ram: sram@fc428000 {
683 compatible = "qcom,rpm
684 reg = <0xfc428000 0x40
685
686 #address-cells = <1>;
687 #size-cells = <1>;
688 ranges = <0 0xfc428000
689
690 apss_master_stats: sra
691 reg = <0x150 0
692 };
693
694 mpss_master_stats: sra
695 reg = <0xb50 0
696 };
697
698 lpss_master_stats: sra
699 reg = <0x1550
700 };
701
702 pronto_master_stats: s
703 reg = <0x1f50
704 };
705 };
706
707 tsens: thermal-sensor@fc4a9000
708 compatible = "qcom,msm
709 reg = <0xfc4a9000 0x10
710 <0xfc4a8000 0x10
711 nvmem-cells = <&tsens_
712 <&tsens_
713 <&tsens_
714 <&tsens_
715 <&tsens_
716 <&tsens_
717 <&tsens_
718 <&tsens_
719 <&tsens_
720 nvmem-cell-names = "mo
721 "ba
722 "s0
723 "s1
724 "s2
725 "s3
726 "s4
727 "s5
728 "s6
729 #qcom,sensors = <6>;
730 interrupts = <GIC_SPI
731 interrupt-names = "upl
732 #thermal-sensor-cells
733 };
734
735 restart@fc4ab000 {
736 compatible = "qcom,psh
737 reg = <0xfc4ab000 0x4>
738 };
739
740 qfprom: efuse@fc4bc000 {
741 compatible = "qcom,msm
742 reg = <0xfc4bc000 0x10
743 #address-cells = <1>;
744 #size-cells = <1>;
745
746 tsens_base1: base1@1c1
747 reg = <0x1c1 0
748 bits = <5 8>;
749 };
750
751 tsens_s0_p1: s0-p1@1c2
752 reg = <0x1c2 0
753 bits = <5 6>;
754 };
755
756 tsens_s1_p1: s1-p1@1c4
757 reg = <0x1c4 0
758 bits = <0 6>;
759 };
760
761 tsens_s2_p1: s2-p1@1c4
762 reg = <0x1c4 0
763 bits = <6 6>;
764 };
765
766 tsens_s3_p1: s3-p1@1c5
767 reg = <0x1c5 0
768 bits = <4 6>;
769 };
770
771 tsens_s4_p1: s4-p1@1c6
772 reg = <0x1c6 0
773 bits = <2 6>;
774 };
775
776 tsens_s5_p1: s5-p1@1c7
777 reg = <0x1c7 0
778 bits = <0 6>;
779 };
780
781 tsens_s6_p1: s6-p1@1ca
782 reg = <0x1ca 0
783 bits = <4 6>;
784 };
785
786 tsens_base2: base2@1cc
787 reg = <0x1cc 0
788 bits = <0 8>;
789 };
790
791 tsens_s0_p2: s0-p2@1cd
792 reg = <0x1cd 0
793 bits = <0 6>;
794 };
795
796 tsens_s1_p2: s1-p2@1cd
797 reg = <0x1cd 0
798 bits = <6 6>;
799 };
800
801 tsens_s2_p2: s2-p2@1ce
802 reg = <0x1ce 0
803 bits = <4 6>;
804 };
805
806 tsens_s3_p2: s3-p2@1cf
807 reg = <0x1cf 0
808 bits = <2 6>;
809 };
810
811 tsens_s4_p2: s4-p2@446
812 reg = <0x446 0
813 bits = <4 6>;
814 };
815
816 tsens_s5_p2: s5-p2@447
817 reg = <0x447 0
818 bits = <2 6>;
819 };
820
821 tsens_s6_p2: s6-p2@44e
822 reg = <0x44e 0
823 bits = <1 6>;
824 };
825
826 tsens_mode: mode@44f {
827 reg = <0x44f 0
828 bits = <5 3>;
829 };
830 };
831
832 spmi_bus: spmi@fc4cf000 {
833 compatible = "qcom,spm
834 reg-names = "core", "i
835 reg = <0xfc4cf000 0x10
836 <0xfc4cb000 0x10
837 <0xfc4ca000 0x10
838 interrupt-names = "per
839 interrupts = <GIC_SPI
840 qcom,ee = <0>;
841 qcom,channel = <0>;
842 #address-cells = <2>;
843 #size-cells = <0>;
844 interrupt-controller;
845 #interrupt-cells = <4>
846 };
847
848 tcsr_mutex: hwlock@fd484000 {
849 compatible = "qcom,msm
850 reg = <0xfd484000 0x10
851 #hwlock-cells = <1>;
852 };
853
854 tlmm: pinctrl@fd510000 {
855 compatible = "qcom,msm
856 reg = <0xfd510000 0x40
857 gpio-controller;
858 #gpio-cells = <2>;
859 gpio-ranges = <&tlmm 0
860 interrupt-controller;
861 #interrupt-cells = <2>
862 interrupts = <GIC_SPI
863
864 blsp1_i2c1_pins: blsp1
865 pins = "gpio2"
866 function = "bl
867 drive-strength
868 bias-disable;
869 };
870
871 blsp1_i2c2_pins: blsp1
872 pins = "gpio6"
873 function = "bl
874 drive-strength
875 bias-disable;
876 };
877
878 blsp1_i2c3_pins: blsp1
879 pins = "gpio10
880 function = "bl
881 drive-strength
882 bias-disable;
883 };
884
885 blsp1_i2c4_pins: blsp1
886 pins = "gpio14
887 function = "bl
888 drive-strength
889 bias-disable;
890 };
891
892 blsp1_i2c5_pins: blsp1
893 pins = "gpio18
894 function = "bl
895 drive-strength
896 bias-disable;
897 };
898
899 blsp1_i2c6_pins: blsp1
900 pins = "gpio22
901 function = "bl
902 drive-strength
903 bias-disable;
904 };
905
906 cci_default: cci-defau
907 pins = "gpio29
908 function = "cc
909
910 drive-strength
911 bias-disable;
912 };
913
914 cci_sleep: cci-sleep-s
915 pins = "gpio29
916 function = "gp
917
918 drive-strength
919 bias-disable;
920 };
921
922 sdhc1_default_state: s
923 clk-pins {
924 pins =
925 drive-
926 bias-d
927 };
928
929 cmd-data-pins
930 pins =
931 drive-
932 bias-p
933 };
934 };
935
936 sdhc2_default_state: s
937 clk-pins {
938 pins =
939 drive-
940 bias-d
941 };
942
943 cmd-data-pins
944 pins =
945 drive-
946 bias-p
947 };
948 };
949
950 sdhc3_default_state: s
951 clk-pins {
952 pins =
953 functi
954 drive-
955 bias-d
956 };
957
958 cmd-pins {
959 pins =
960 functi
961 drive-
962 bias-p
963 };
964
965 data-pins {
966 pins =
967 functi
968 drive-
969 bias-p
970 };
971 };
972 };
973
974 mmcc: clock-controller@fd8c000
975 compatible = "qcom,mmc
976 reg = <0xfd8c0000 0x60
977 #clock-cells = <1>;
978 #reset-cells = <1>;
979 #power-domain-cells =
980
981 clocks = <&rpmcc RPM_S
982 <&gcc GCC_MMS
983 <&gcc GPLL0_V
984 <&gcc GPLL1_V
985 <&rpmcc RPM_S
986 <&mdss_dsi0_p
987 <&mdss_dsi0_p
988 clock-names = "xo",
989 "mmss_gp
990 "gpll0_v
991 "gpll1_v
992 "gfx3d_c
993 "dsi0pll
994 "dsi0pll
995 };
996
997 mdss: display-subsystem@fd9000
998 compatible = "qcom,mds
999 reg = <0xfd900000 0x10
1000 reg-names = "mdss_phy
1001
1002 power-domains = <&mmc
1003
1004 clocks = <&mmcc MDSS_
1005 <&mmcc MDSS_
1006 <&mmcc MDSS_
1007 clock-names = "iface"
1008 "bus",
1009 "vsync"
1010
1011 interrupts = <GIC_SPI
1012
1013 interrupt-controller;
1014 #interrupt-cells = <1
1015
1016 #address-cells = <1>;
1017 #size-cells = <1>;
1018 ranges;
1019
1020 status = "disabled";
1021
1022 mdss_mdp: display-con
1023 compatible =
1024 reg = <0xfd90
1025 reg-names = "
1026
1027 interrupt-par
1028 interrupts =
1029
1030 clocks = <&mm
1031 <&mm
1032 <&mm
1033 <&mm
1034 clock-names =
1035
1036
1037
1038
1039 ports {
1040 #addr
1041 #size
1042
1043 port@
1044
1045
1046
1047
1048 };
1049 };
1050 };
1051
1052 mdss_dsi0: dsi@fd9228
1053 compatible =
1054
1055 reg = <0xfd92
1056 reg-names = "
1057
1058 interrupt-par
1059 interrupts =
1060
1061 assigned-cloc
1062
1063 assigned-cloc
1064
1065
1066 clocks = <&mm
1067 <&mm
1068 <&mm
1069 <&mm
1070 <&mm
1071 <&mm
1072 <&mm
1073 clock-names =
1074
1075
1076
1077
1078
1079
1080
1081 phys = <&mdss
1082
1083 #address-cell
1084 #size-cells =
1085
1086 ports {
1087 #addr
1088 #size
1089
1090 port@
1091
1092
1093
1094
1095 };
1096
1097 port@
1098
1099
1100
1101 };
1102 };
1103 };
1104
1105 mdss_dsi0_phy: phy@fd
1106 compatible =
1107 reg = <0xfd92
1108 <0xfd92
1109 <0xfd92
1110 reg-names = "
1111 "
1112 "
1113
1114 #clock-cells
1115 #phy-cells =
1116
1117 clocks = <&mm
1118 <&rp
1119 clock-names =
1120
1121 };
1122 };
1123
1124 cci: cci@fda0c000 {
1125 compatible = "qcom,ms
1126 reg = <0xfda0c000 0x1
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129 interrupts = <GIC_SPI
1130 clocks = <&mmcc CAMSS
1131 <&mmcc CAMSS
1132 <&mmcc CAMSS
1133 clock-names = "camss_
1134 "cci_ah
1135 "cci";
1136
1137 pinctrl-names = "defa
1138 pinctrl-0 = <&cci_def
1139 pinctrl-1 = <&cci_sle
1140
1141 status = "disabled";
1142
1143 cci_i2c0: i2c-bus@0 {
1144 reg = <0>;
1145 clock-frequen
1146 #address-cell
1147 #size-cells =
1148 };
1149 };
1150
1151 gpu: gpu@fdb00000 {
1152 compatible = "qcom,ad
1153 reg = <0xfdb00000 0x1
1154 reg-names = "kgsl_3d0
1155
1156 interrupts = <GIC_SPI
1157 interrupt-names = "kg
1158
1159 clocks = <&mmcc OXILI
1160 <&mmcc OXILI
1161 <&mmcc OXILI
1162 clock-names = "core",
1163
1164 sram = <&gmu_sram>;
1165 power-domains = <&mmc
1166 operating-points-v2 =
1167
1168 status = "disabled";
1169
1170 gpu_opp_table: opp-ta
1171 compatible =
1172
1173 opp-450000000
1174 opp-h
1175 };
1176
1177 opp-320000000
1178 opp-h
1179 };
1180
1181 opp-200000000
1182 opp-h
1183 };
1184
1185 opp-19000000
1186 opp-h
1187 };
1188 };
1189 };
1190
1191 sram@fdd00000 {
1192 compatible = "qcom,ms
1193 reg = <0xfdd00000 0x2
1194 <0xfec00000 0x2
1195 reg-names = "ctrl", "
1196 ranges = <0 0xfec0000
1197 clocks = <&rpmcc RPM_
1198 clock-names = "core";
1199
1200 #address-cells = <1>;
1201 #size-cells = <1>;
1202
1203 gmu_sram: gmu-sram@0
1204 reg = <0x0 0x
1205 };
1206 };
1207
1208 adsp: remoteproc@fe200000 {
1209 compatible = "qcom,ms
1210 reg = <0xfe200000 0x1
1211
1212 interrupts-extended =
1213
1214
1215
1216
1217 interrupt-names = "wd
1218
1219 power-domains = <&rpm
1220 power-domain-names =
1221
1222 clocks = <&rpmcc RPM_
1223 clock-names = "xo";
1224
1225 memory-region = <&ads
1226
1227 qcom,smem-states = <&
1228 qcom,smem-state-names
1229
1230 status = "disabled";
1231
1232 smd-edge {
1233 interrupts =
1234
1235 mboxes = <&ap
1236 qcom,smd-edge
1237
1238 label = "lpas
1239 };
1240 };
1241
1242 sram@fe805000 {
1243 compatible = "qcom,ms
1244 reg = <0xfe805000 0x1
1245
1246 reboot-mode {
1247 compatible =
1248 offset = <0x6
1249
1250 mode-bootload
1251 mode-normal =
1252 mode-recovery
1253 };
1254 };
1255 };
1256
1257 thermal-zones {
1258 cpu0-thermal {
1259 polling-delay-passive
1260 polling-delay = <1000
1261
1262 thermal-sensors = <&t
1263
1264 cooling-maps {
1265 map0 {
1266 trip
1267 cooli
1268
1269
1270
1271 };
1272 };
1273
1274 trips {
1275 cpu_alert0: t
1276 tempe
1277 hyste
1278 type
1279 };
1280
1281 cpu_crit0: tr
1282 tempe
1283 hyste
1284 type
1285 };
1286 };
1287 };
1288
1289 cpu1-thermal {
1290 polling-delay-passive
1291 polling-delay = <1000
1292
1293 thermal-sensors = <&t
1294
1295 cooling-maps {
1296 map0 {
1297 trip
1298 cooli
1299
1300
1301
1302 };
1303 };
1304
1305 trips {
1306 cpu_alert1: t
1307 tempe
1308 hyste
1309 type
1310 };
1311
1312 cpu_crit1: tr
1313 tempe
1314 hyste
1315 type
1316 };
1317 };
1318 };
1319 };
1320
1321 timer {
1322 compatible = "arm,armv7-timer
1323 interrupts = <GIC_PPI 2
1324 (GIC_CPU_MASK
1325 <GIC_PPI 3
1326 (GIC_CPU_MASK
1327 <GIC_PPI 4
1328 (GIC_CPU_MASK
1329 <GIC_PPI 1
1330 (GIC_CPU_MASK
1331 };
1332 };
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