1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h 9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974. 10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h> 11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h 14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
15 #include <dt-bindings/thermal/thermal.h> <<
16 15
17 / { 16 / {
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <1>; 18 #size-cells = <1>;
20 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
21 20
22 chosen { }; 21 chosen { };
23 22
>> 23 memory@0 {
>> 24 device_type = "memory";
>> 25 reg = <0x0 0x0>;
>> 26 };
>> 27
24 clocks { 28 clocks {
25 xo_board: xo_board { 29 xo_board: xo_board {
26 compatible = "fixed-cl 30 compatible = "fixed-clock";
27 #clock-cells = <0>; 31 #clock-cells = <0>;
28 clock-frequency = <192 32 clock-frequency = <19200000>;
29 }; 33 };
30 34
31 sleep_clk: sleep_clk { 35 sleep_clk: sleep_clk {
32 compatible = "fixed-cl 36 compatible = "fixed-clock";
33 #clock-cells = <0>; 37 #clock-cells = <0>;
34 clock-frequency = <327 38 clock-frequency = <32768>;
35 }; 39 };
36 }; 40 };
37 41
38 cpus { <<
39 #address-cells = <1>; <<
40 #size-cells = <0>; <<
41 <<
42 CPU0: cpu@0 { <<
43 compatible = "arm,cort <<
44 enable-method = "qcom, <<
45 device_type = "cpu"; <<
46 reg = <0>; <<
47 next-level-cache = <&L <<
48 clocks = <&apcs>; <<
49 operating-points-v2 = <<
50 qcom,acc = <&acc0>; <<
51 qcom,saw = <&saw0>; <<
52 #cooling-cells = <2>; <<
53 }; <<
54 <<
55 CPU1: cpu@1 { <<
56 compatible = "arm,cort <<
57 enable-method = "qcom, <<
58 device_type = "cpu"; <<
59 reg = <1>; <<
60 next-level-cache = <&L <<
61 clocks = <&apcs>; <<
62 operating-points-v2 = <<
63 qcom,acc = <&acc1>; <<
64 qcom,saw = <&saw1>; <<
65 #cooling-cells = <2>; <<
66 }; <<
67 <<
68 CPU2: cpu@2 { <<
69 compatible = "arm,cort <<
70 enable-method = "qcom, <<
71 device_type = "cpu"; <<
72 reg = <2>; <<
73 next-level-cache = <&L <<
74 clocks = <&apcs>; <<
75 operating-points-v2 = <<
76 qcom,acc = <&acc2>; <<
77 qcom,saw = <&saw2>; <<
78 #cooling-cells = <2>; <<
79 }; <<
80 <<
81 CPU3: cpu@3 { <<
82 compatible = "arm,cort <<
83 enable-method = "qcom, <<
84 device_type = "cpu"; <<
85 reg = <3>; <<
86 next-level-cache = <&L <<
87 clocks = <&apcs>; <<
88 operating-points-v2 = <<
89 qcom,acc = <&acc3>; <<
90 qcom,saw = <&saw3>; <<
91 #cooling-cells = <2>; <<
92 }; <<
93 <<
94 L2: l2-cache { <<
95 compatible = "cache"; <<
96 cache-level = <2>; <<
97 cache-unified; <<
98 }; <<
99 }; <<
100 <<
101 firmware { 42 firmware {
102 scm { 43 scm {
103 compatible = "qcom,scm 44 compatible = "qcom,scm-msm8226", "qcom,scm";
104 clocks = <&gcc GCC_CE1 45 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
105 clock-names = "core", 46 clock-names = "core", "bus", "iface";
106 }; 47 };
107 }; 48 };
108 49
109 memory@0 { <<
110 device_type = "memory"; <<
111 reg = <0x0 0x0>; <<
112 }; <<
113 <<
114 cpu_opp_table: opp-table-cpu { <<
115 compatible = "operating-points <<
116 opp-shared; <<
117 <<
118 opp-300000000 { <<
119 opp-hz = /bits/ 64 <30 <<
120 }; <<
121 <<
122 opp-384000000 { <<
123 opp-hz = /bits/ 64 <38 <<
124 }; <<
125 <<
126 opp-600000000 { <<
127 opp-hz = /bits/ 64 <60 <<
128 }; <<
129 <<
130 opp-787200000 { <<
131 opp-hz = /bits/ 64 <78 <<
132 }; <<
133 <<
134 /* Higher CPU frequencies need <<
135 }; <<
136 <<
137 pmu { 50 pmu {
138 compatible = "arm,cortex-a7-pm 51 compatible = "arm,cortex-a7-pmu";
139 interrupts = <GIC_PPI 7 (GIC_C 52 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
140 IRQ_T 53 IRQ_TYPE_LEVEL_HIGH)>;
141 }; 54 };
142 55
143 rpm: remoteproc { 56 rpm: remoteproc {
144 compatible = "qcom,msm8226-rpm 57 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
145 58
146 master-stats { 59 master-stats {
147 compatible = "qcom,rpm 60 compatible = "qcom,rpm-master-stats";
148 qcom,rpm-msg-ram = <&a 61 qcom,rpm-msg-ram = <&apss_master_stats>,
149 <&m 62 <&mpss_master_stats>,
150 <&l 63 <&lpss_master_stats>,
151 <&p 64 <&pronto_master_stats>;
152 qcom,master-names = "A 65 qcom,master-names = "APSS",
153 "M 66 "MPSS",
154 "L 67 "LPSS",
155 "P 68 "PRONTO";
156 }; 69 };
157 70
158 smd-edge { 71 smd-edge {
159 interrupts = <GIC_SPI 72 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
160 mboxes = <&apcs 0>; !! 73 qcom,ipc = <&apcs 8 0>;
161 qcom,smd-edge = <15>; 74 qcom,smd-edge = <15>;
162 75
163 rpm_requests: rpm-requ 76 rpm_requests: rpm-requests {
164 compatible = " !! 77 compatible = "qcom,rpm-msm8226";
165 qcom,smd-chann 78 qcom,smd-channels = "rpm_requests";
166 79
167 rpmcc: clock-c 80 rpmcc: clock-controller {
168 compat 81 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
169 #clock 82 #clock-cells = <1>;
170 clocks 83 clocks = <&xo_board>;
171 clock- 84 clock-names = "xo";
172 }; 85 };
173 86
174 rpmpd: power-c 87 rpmpd: power-controller {
175 compat 88 compatible = "qcom,msm8226-rpmpd";
176 #power 89 #power-domain-cells = <1>;
177 operat 90 operating-points-v2 = <&rpmpd_opp_table>;
178 91
179 rpmpd_ 92 rpmpd_opp_table: opp-table {
180 93 compatible = "operating-points-v2";
181 94
182 95 rpmpd_opp_ret: opp1 {
183 96 opp-level = <1>;
184 97 };
185 98 rpmpd_opp_svs_krait: opp2 {
186 99 opp-level = <2>;
187 100 };
188 101 rpmpd_opp_svs_soc: opp3 {
189 102 opp-level = <3>;
190 103 };
191 104 rpmpd_opp_nom: opp4 {
192 105 opp-level = <4>;
193 106 };
194 107 rpmpd_opp_turbo: opp5 {
195 108 opp-level = <5>;
196 109 };
197 110 rpmpd_opp_super_turbo: opp6 {
198 111 opp-level = <6>;
199 112 };
200 }; 113 };
201 }; 114 };
202 }; 115 };
203 }; 116 };
204 }; 117 };
205 118
206 reserved-memory { 119 reserved-memory {
207 #address-cells = <1>; 120 #address-cells = <1>;
208 #size-cells = <1>; 121 #size-cells = <1>;
209 ranges; 122 ranges;
210 123
211 smem_region: smem@3000000 { 124 smem_region: smem@3000000 {
212 reg = <0x3000000 0x100 125 reg = <0x3000000 0x100000>;
213 no-map; 126 no-map;
214 }; 127 };
215 128
216 adsp_region: adsp@dc00000 { 129 adsp_region: adsp@dc00000 {
217 reg = <0x0dc00000 0x19 130 reg = <0x0dc00000 0x1900000>;
218 no-map; 131 no-map;
219 }; 132 };
220 }; 133 };
221 134
222 smem { 135 smem {
223 compatible = "qcom,smem"; 136 compatible = "qcom,smem";
224 137
225 memory-region = <&smem_region> 138 memory-region = <&smem_region>;
226 qcom,rpm-msg-ram = <&rpm_msg_r 139 qcom,rpm-msg-ram = <&rpm_msg_ram>;
227 140
228 hwlocks = <&tcsr_mutex 3>; 141 hwlocks = <&tcsr_mutex 3>;
229 }; 142 };
230 143
231 smp2p-adsp { 144 smp2p-adsp {
232 compatible = "qcom,smp2p"; 145 compatible = "qcom,smp2p";
233 qcom,smem = <443>, <429>; 146 qcom,smem = <443>, <429>;
234 147
235 interrupt-parent = <&intc>; 148 interrupt-parent = <&intc>;
236 interrupts = <GIC_SPI 158 IRQ_ 149 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
237 150
238 mboxes = <&apcs 10>; !! 151 qcom,ipc = <&apcs 8 10>;
239 152
240 qcom,local-pid = <0>; 153 qcom,local-pid = <0>;
241 qcom,remote-pid = <2>; 154 qcom,remote-pid = <2>;
242 155
243 adsp_smp2p_out: master-kernel 156 adsp_smp2p_out: master-kernel {
244 qcom,entry-name = "mas 157 qcom,entry-name = "master-kernel";
245 #qcom,smem-state-cells 158 #qcom,smem-state-cells = <1>;
246 }; 159 };
247 160
248 adsp_smp2p_in: slave-kernel { 161 adsp_smp2p_in: slave-kernel {
249 qcom,entry-name = "sla 162 qcom,entry-name = "slave-kernel";
250 163
251 interrupt-controller; 164 interrupt-controller;
252 #interrupt-cells = <2> 165 #interrupt-cells = <2>;
253 }; 166 };
254 }; 167 };
255 168
256 soc: soc { 169 soc: soc {
257 compatible = "simple-bus"; 170 compatible = "simple-bus";
258 #address-cells = <1>; 171 #address-cells = <1>;
259 #size-cells = <1>; 172 #size-cells = <1>;
260 ranges; 173 ranges;
261 174
262 intc: interrupt-controller@f90 175 intc: interrupt-controller@f9000000 {
263 compatible = "qcom,msm 176 compatible = "qcom,msm-qgic2";
264 reg = <0xf9000000 0x10 177 reg = <0xf9000000 0x1000>,
265 <0xf9002000 0x10 178 <0xf9002000 0x1000>;
266 interrupt-controller; 179 interrupt-controller;
267 #interrupt-cells = <3> 180 #interrupt-cells = <3>;
268 }; 181 };
269 182
270 apcs: mailbox@f9011000 { !! 183 apcs: syscon@f9011000 {
271 compatible = "qcom,msm !! 184 compatible = "syscon";
272 "qcom,msm <<
273 reg = <0xf9011000 0x10 185 reg = <0xf9011000 0x1000>;
274 #mbox-cells = <1>; <<
275 clocks = <&a7pll>, <&g <<
276 clock-names = "pll", " <<
277 #clock-cells = <0>; <<
278 }; <<
279 <<
280 a7pll: clock@f9016000 { <<
281 compatible = "qcom,msm <<
282 reg = <0xf9016000 0x40 <<
283 #clock-cells = <0>; <<
284 clocks = <&xo_board>; <<
285 clock-names = "xo"; <<
286 operating-points-v2 = <<
287 <<
288 a7pll_opp_table: opp-t <<
289 compatible = " <<
290 <<
291 opp-768000000 <<
292 opp-hz <<
293 }; <<
294 <<
295 opp-787200000 <<
296 opp-hz <<
297 }; <<
298 <<
299 opp-998400000 <<
300 opp-hz <<
301 }; <<
302 <<
303 opp-1094400000 <<
304 opp-hz <<
305 }; <<
306 <<
307 opp-1190400000 <<
308 opp-hz <<
309 }; <<
310 <<
311 opp-1305600000 <<
312 opp-hz <<
313 }; <<
314 <<
315 opp-1344000000 <<
316 opp-hz <<
317 }; <<
318 <<
319 opp-1401600000 <<
320 opp-hz <<
321 }; <<
322 <<
323 opp-1497600000 <<
324 opp-hz <<
325 }; <<
326 <<
327 opp-1593600000 <<
328 opp-hz <<
329 }; <<
330 <<
331 opp-1689600000 <<
332 opp-hz <<
333 }; <<
334 <<
335 opp-1785600000 <<
336 opp-hz <<
337 }; <<
338 }; <<
339 }; <<
340 <<
341 saw_l2: power-manager@f9012000 <<
342 compatible = "qcom,msm <<
343 reg = <0xf9012000 0x10 <<
344 }; <<
345 <<
346 watchdog@f9017000 { <<
347 compatible = "qcom,aps <<
348 reg = <0xf9017000 0x10 <<
349 interrupts = <GIC_SPI <<
350 <GIC_SPI <<
351 clocks = <&sleep_clk>; <<
352 }; <<
353 <<
354 timer@f9020000 { <<
355 compatible = "arm,armv <<
356 reg = <0xf9020000 0x10 <<
357 #address-cells = <1>; <<
358 #size-cells = <1>; <<
359 ranges; <<
360 <<
361 frame@f9021000 { <<
362 frame-number = <<
363 interrupts = < <<
364 < <<
365 reg = <0xf9021 <<
366 <0xf9022 <<
367 }; <<
368 <<
369 frame@f9023000 { <<
370 frame-number = <<
371 interrupts = < <<
372 reg = <0xf9023 <<
373 status = "disa <<
374 }; <<
375 <<
376 frame@f9024000 { <<
377 frame-number = <<
378 interrupts = < <<
379 reg = <0xf9024 <<
380 status = "disa <<
381 }; <<
382 <<
383 frame@f9025000 { <<
384 frame-number = <<
385 interrupts = < <<
386 reg = <0xf9025 <<
387 status = "disa <<
388 }; <<
389 <<
390 frame@f9026000 { <<
391 frame-number = <<
392 interrupts = < <<
393 reg = <0xf9026 <<
394 status = "disa <<
395 }; <<
396 <<
397 frame@f9027000 { <<
398 frame-number = <<
399 interrupts = < <<
400 reg = <0xf9027 <<
401 status = "disa <<
402 }; <<
403 <<
404 frame@f9028000 { <<
405 frame-number = <<
406 interrupts = < <<
407 reg = <0xf9028 <<
408 status = "disa <<
409 }; <<
410 }; <<
411 <<
412 acc0: power-manager@f9088000 { <<
413 compatible = "qcom,kps <<
414 reg = <0xf9088000 0x10 <<
415 }; <<
416 <<
417 saw0: power-manager@f9089000 { <<
418 compatible = "qcom,msm <<
419 reg = <0xf9089000 0x10 <<
420 }; <<
421 <<
422 acc1: power-manager@f9098000 { <<
423 compatible = "qcom,kps <<
424 reg = <0xf9098000 0x10 <<
425 }; <<
426 <<
427 saw1: power-manager@f9099000 { <<
428 compatible = "qcom,msm <<
429 reg = <0xf9099000 0x10 <<
430 }; <<
431 <<
432 acc2: power-manager@f90a8000 { <<
433 compatible = "qcom,kps <<
434 reg = <0xf90a8000 0x10 <<
435 }; <<
436 <<
437 saw2: power-manager@f90a9000 { <<
438 compatible = "qcom,msm <<
439 reg = <0xf90a9000 0x10 <<
440 }; <<
441 <<
442 acc3: power-manager@f90b8000 { <<
443 compatible = "qcom,kps <<
444 reg = <0xf90b8000 0x10 <<
445 }; <<
446 <<
447 saw3: power-manager@f90b9000 { <<
448 compatible = "qcom,msm <<
449 reg = <0xf90b9000 0x10 <<
450 }; 186 };
451 187
452 sdhc_1: mmc@f9824900 { 188 sdhc_1: mmc@f9824900 {
453 compatible = "qcom,msm 189 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
454 reg = <0xf9824900 0x11 190 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
455 reg-names = "hc", "cor 191 reg-names = "hc", "core";
456 interrupts = <GIC_SPI 192 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 193 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "hc_ 194 interrupt-names = "hc_irq", "pwr_irq";
459 clocks = <&gcc GCC_SDC 195 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
460 <&gcc GCC_SDC 196 <&gcc GCC_SDCC1_APPS_CLK>,
461 <&rpmcc RPM_S 197 <&rpmcc RPM_SMD_XO_CLK_SRC>;
462 clock-names = "iface", 198 clock-names = "iface", "core", "xo";
463 pinctrl-names = "defau 199 pinctrl-names = "default";
464 pinctrl-0 = <&sdhc1_de 200 pinctrl-0 = <&sdhc1_default_state>;
465 status = "disabled"; 201 status = "disabled";
466 }; 202 };
467 203
468 sdhc_3: mmc@f9864900 { !! 204 sdhc_2: mmc@f98a4900 {
469 compatible = "qcom,msm 205 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
470 reg = <0xf9864900 0x11 !! 206 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
471 reg-names = "hc", "cor 207 reg-names = "hc", "core";
472 interrupts = <GIC_SPI !! 208 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI !! 209 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "hc_ 210 interrupt-names = "hc_irq", "pwr_irq";
475 clocks = <&gcc GCC_SDC !! 211 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
476 <&gcc GCC_SDC !! 212 <&gcc GCC_SDCC2_APPS_CLK>,
477 <&rpmcc RPM_S 213 <&rpmcc RPM_SMD_XO_CLK_SRC>;
478 clock-names = "iface", 214 clock-names = "iface", "core", "xo";
479 pinctrl-names = "defau 215 pinctrl-names = "default";
480 pinctrl-0 = <&sdhc3_de !! 216 pinctrl-0 = <&sdhc2_default_state>;
481 status = "disabled"; 217 status = "disabled";
482 }; 218 };
483 219
484 sdhc_2: mmc@f98a4900 { !! 220 sdhc_3: mmc@f9864900 {
485 compatible = "qcom,msm 221 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
486 reg = <0xf98a4900 0x11 !! 222 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
487 reg-names = "hc", "cor 223 reg-names = "hc", "core";
488 interrupts = <GIC_SPI !! 224 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI !! 225 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
490 interrupt-names = "hc_ 226 interrupt-names = "hc_irq", "pwr_irq";
491 clocks = <&gcc GCC_SDC !! 227 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
492 <&gcc GCC_SDC !! 228 <&gcc GCC_SDCC3_APPS_CLK>,
493 <&rpmcc RPM_S 229 <&rpmcc RPM_SMD_XO_CLK_SRC>;
494 clock-names = "iface", 230 clock-names = "iface", "core", "xo";
495 pinctrl-names = "defau 231 pinctrl-names = "default";
496 pinctrl-0 = <&sdhc2_de !! 232 pinctrl-0 = <&sdhc3_default_state>;
497 status = "disabled"; 233 status = "disabled";
498 }; 234 };
499 235
500 blsp1_uart1: serial@f991d000 { 236 blsp1_uart1: serial@f991d000 {
501 compatible = "qcom,msm 237 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
502 reg = <0xf991d000 0x10 238 reg = <0xf991d000 0x1000>;
503 interrupts = <GIC_SPI 239 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&gcc GCC_BLS 240 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
505 clock-names = "core", 241 clock-names = "core", "iface";
506 status = "disabled"; 242 status = "disabled";
507 }; 243 };
508 244
509 blsp1_uart2: serial@f991e000 { 245 blsp1_uart2: serial@f991e000 {
510 compatible = "qcom,msm 246 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
511 reg = <0xf991e000 0x10 247 reg = <0xf991e000 0x1000>;
512 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&gcc GCC_BLS 249 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
514 <&gcc GCC_BLS 250 <&gcc GCC_BLSP1_AHB_CLK>;
515 clock-names = "core", 251 clock-names = "core",
516 "iface"; 252 "iface";
517 status = "disabled"; 253 status = "disabled";
518 }; 254 };
519 255
520 blsp1_uart3: serial@f991f000 { 256 blsp1_uart3: serial@f991f000 {
521 compatible = "qcom,msm 257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
522 reg = <0xf991f000 0x10 258 reg = <0xf991f000 0x1000>;
523 interrupts = <GIC_SPI 259 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&gcc GCC_BLS 260 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
525 clock-names = "core", 261 clock-names = "core", "iface";
526 status = "disabled"; 262 status = "disabled";
527 }; 263 };
528 264
529 blsp1_uart4: serial@f9920000 { 265 blsp1_uart4: serial@f9920000 {
530 compatible = "qcom,msm 266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
531 reg = <0xf9920000 0x10 267 reg = <0xf9920000 0x1000>;
532 interrupts = <GIC_SPI 268 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&gcc GCC_BLS 269 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", 270 clock-names = "core", "iface";
535 status = "disabled"; 271 status = "disabled";
536 }; 272 };
537 273
538 blsp1_i2c1: i2c@f9923000 { 274 blsp1_i2c1: i2c@f9923000 {
>> 275 status = "disabled";
539 compatible = "qcom,i2c 276 compatible = "qcom,i2c-qup-v2.1.1";
540 reg = <0xf9923000 0x10 277 reg = <0xf9923000 0x1000>;
541 interrupts = <GIC_SPI 278 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&gcc GCC_BLS 279 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
543 clock-names = "core", 280 clock-names = "core", "iface";
544 pinctrl-names = "defau 281 pinctrl-names = "default";
545 pinctrl-0 = <&blsp1_i2 282 pinctrl-0 = <&blsp1_i2c1_pins>;
546 #address-cells = <1>; 283 #address-cells = <1>;
547 #size-cells = <0>; 284 #size-cells = <0>;
548 status = "disabled"; <<
549 }; 285 };
550 286
551 blsp1_i2c2: i2c@f9924000 { 287 blsp1_i2c2: i2c@f9924000 {
>> 288 status = "disabled";
552 compatible = "qcom,i2c 289 compatible = "qcom,i2c-qup-v2.1.1";
553 reg = <0xf9924000 0x10 290 reg = <0xf9924000 0x1000>;
554 interrupts = <GIC_SPI 291 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&gcc GCC_BLS 292 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
556 clock-names = "core", 293 clock-names = "core", "iface";
557 pinctrl-names = "defau 294 pinctrl-names = "default";
558 pinctrl-0 = <&blsp1_i2 295 pinctrl-0 = <&blsp1_i2c2_pins>;
559 #address-cells = <1>; 296 #address-cells = <1>;
560 #size-cells = <0>; 297 #size-cells = <0>;
561 status = "disabled"; <<
562 }; 298 };
563 299
564 blsp1_i2c3: i2c@f9925000 { 300 blsp1_i2c3: i2c@f9925000 {
>> 301 status = "disabled";
565 compatible = "qcom,i2c 302 compatible = "qcom,i2c-qup-v2.1.1";
566 reg = <0xf9925000 0x10 303 reg = <0xf9925000 0x1000>;
567 interrupts = <GIC_SPI 304 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&gcc GCC_BLS 305 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
569 clock-names = "core", 306 clock-names = "core", "iface";
570 pinctrl-names = "defau 307 pinctrl-names = "default";
571 pinctrl-0 = <&blsp1_i2 308 pinctrl-0 = <&blsp1_i2c3_pins>;
572 #address-cells = <1>; 309 #address-cells = <1>;
573 #size-cells = <0>; 310 #size-cells = <0>;
574 status = "disabled"; <<
575 }; 311 };
576 312
577 blsp1_i2c4: i2c@f9926000 { 313 blsp1_i2c4: i2c@f9926000 {
>> 314 status = "disabled";
578 compatible = "qcom,i2c 315 compatible = "qcom,i2c-qup-v2.1.1";
579 reg = <0xf9926000 0x10 316 reg = <0xf9926000 0x1000>;
580 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&gcc GCC_BLS 318 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
582 clock-names = "core", 319 clock-names = "core", "iface";
583 pinctrl-names = "defau 320 pinctrl-names = "default";
584 pinctrl-0 = <&blsp1_i2 321 pinctrl-0 = <&blsp1_i2c4_pins>;
585 #address-cells = <1>; 322 #address-cells = <1>;
586 #size-cells = <0>; 323 #size-cells = <0>;
587 status = "disabled"; <<
588 }; 324 };
589 325
590 blsp1_i2c5: i2c@f9927000 { 326 blsp1_i2c5: i2c@f9927000 {
>> 327 status = "disabled";
591 compatible = "qcom,i2c 328 compatible = "qcom,i2c-qup-v2.1.1";
592 reg = <0xf9927000 0x10 329 reg = <0xf9927000 0x1000>;
593 interrupts = <GIC_SPI 330 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&gcc GCC_BLS 331 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
595 clock-names = "core", 332 clock-names = "core", "iface";
596 pinctrl-names = "defau 333 pinctrl-names = "default";
597 pinctrl-0 = <&blsp1_i2 334 pinctrl-0 = <&blsp1_i2c5_pins>;
598 #address-cells = <1>; 335 #address-cells = <1>;
599 #size-cells = <0>; 336 #size-cells = <0>;
600 status = "disabled"; <<
601 }; 337 };
602 338
603 blsp1_i2c6: i2c@f9928000 { 339 blsp1_i2c6: i2c@f9928000 {
604 compatible = "qcom,i2c 340 compatible = "qcom,i2c-qup-v2.1.1";
605 reg = <0xf9928000 0x10 341 reg = <0xf9928000 0x1000>;
606 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc GCC_BLS 343 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
608 <&gcc GCC_BLS 344 <&gcc GCC_BLSP1_AHB_CLK>;
609 clock-names = "core", 345 clock-names = "core",
610 "iface"; 346 "iface";
611 pinctrl-0 = <&blsp1_i2 347 pinctrl-0 = <&blsp1_i2c6_pins>;
612 pinctrl-names = "defau 348 pinctrl-names = "default";
613 #address-cells = <1>; 349 #address-cells = <1>;
614 #size-cells = <0>; 350 #size-cells = <0>;
615 status = "disabled"; 351 status = "disabled";
616 }; 352 };
617 353
>> 354 cci: cci@fda0c000 {
>> 355 compatible = "qcom,msm8226-cci";
>> 356 #address-cells = <1>;
>> 357 #size-cells = <0>;
>> 358 reg = <0xfda0c000 0x1000>;
>> 359 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
>> 360 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
>> 361 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
>> 362 <&mmcc CAMSS_CCI_CCI_CLK>;
>> 363 clock-names = "camss_top_ahb",
>> 364 "cci_ahb",
>> 365 "cci";
>> 366
>> 367 pinctrl-names = "default", "sleep";
>> 368 pinctrl-0 = <&cci_default>;
>> 369 pinctrl-1 = <&cci_sleep>;
>> 370
>> 371 status = "disabled";
>> 372
>> 373 cci_i2c0: i2c-bus@0 {
>> 374 reg = <0>;
>> 375 clock-frequency = <400000>;
>> 376 #address-cells = <1>;
>> 377 #size-cells = <0>;
>> 378 };
>> 379 };
>> 380
618 usb: usb@f9a55000 { 381 usb: usb@f9a55000 {
619 compatible = "qcom,ci- 382 compatible = "qcom,ci-hdrc";
620 reg = <0xf9a55000 0x20 383 reg = <0xf9a55000 0x200>,
621 <0xf9a55200 0x20 384 <0xf9a55200 0x200>;
622 interrupts = <GIC_SPI 385 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&gcc GCC_USB 386 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
624 <&gcc GCC_USB 387 <&gcc GCC_USB_HS_SYSTEM_CLK>;
625 clock-names = "iface", 388 clock-names = "iface", "core";
626 assigned-clocks = <&gc 389 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
627 assigned-clock-rates = 390 assigned-clock-rates = <75000000>;
628 resets = <&gcc GCC_USB 391 resets = <&gcc GCC_USB_HS_BCR>;
629 reset-names = "core"; 392 reset-names = "core";
630 phy_type = "ulpi"; 393 phy_type = "ulpi";
631 dr_mode = "otg"; 394 dr_mode = "otg";
632 hnp-disable; 395 hnp-disable;
633 srp-disable; 396 srp-disable;
634 adp-disable; 397 adp-disable;
635 ahb-burst-config = <0> 398 ahb-burst-config = <0>;
636 phy-names = "usb-phy"; 399 phy-names = "usb-phy";
637 phys = <&usb_hs_phy>; 400 phys = <&usb_hs_phy>;
638 status = "disabled"; 401 status = "disabled";
639 #reset-cells = <1>; 402 #reset-cells = <1>;
640 403
641 ulpi { 404 ulpi {
642 usb_hs_phy: ph 405 usb_hs_phy: phy {
643 compat 406 compatible = "qcom,usb-hs-phy-msm8226",
644 407 "qcom,usb-hs-phy";
645 #phy-c 408 #phy-cells = <0>;
646 clocks 409 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
647 410 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
648 clock- 411 clock-names = "ref", "sleep";
649 resets 412 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
650 reset- 413 reset-names = "phy", "por";
651 qcom,i 414 qcom,init-seq = /bits/ 8 <0x0 0x44
652 415 0x1 0x68 0x2 0x24 0x3 0x13>;
653 }; 416 };
654 }; 417 };
655 }; 418 };
656 419
657 rng@f9bff000 { <<
658 compatible = "qcom,prn <<
659 reg = <0xf9bff000 0x20 <<
660 clocks = <&gcc GCC_PRN <<
661 clock-names = "core"; <<
662 }; <<
663 <<
664 sram@fc190000 { <<
665 compatible = "qcom,msm <<
666 reg = <0xfc190000 0x10 <<
667 }; <<
668 <<
669 gcc: clock-controller@fc400000 420 gcc: clock-controller@fc400000 {
670 compatible = "qcom,gcc 421 compatible = "qcom,gcc-msm8226";
671 reg = <0xfc400000 0x40 422 reg = <0xfc400000 0x4000>;
672 #clock-cells = <1>; 423 #clock-cells = <1>;
673 #reset-cells = <1>; 424 #reset-cells = <1>;
674 #power-domain-cells = 425 #power-domain-cells = <1>;
675 426
676 clocks = <&xo_board>, !! 427 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
677 <&sleep_clk>; 428 <&sleep_clk>;
678 clock-names = "xo", 429 clock-names = "xo",
679 "sleep_c 430 "sleep_clk";
680 }; 431 };
681 432
682 rpm_msg_ram: sram@fc428000 { !! 433 mmcc: clock-controller@fd8c0000 {
683 compatible = "qcom,rpm !! 434 compatible = "qcom,mmcc-msm8226";
684 reg = <0xfc428000 0x40 !! 435 reg = <0xfd8c0000 0x6000>;
>> 436 #clock-cells = <1>;
>> 437 #reset-cells = <1>;
>> 438 #power-domain-cells = <1>;
685 439
686 #address-cells = <1>; !! 440 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
687 #size-cells = <1>; !! 441 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
688 ranges = <0 0xfc428000 !! 442 <&gcc GPLL0_VOTE>,
>> 443 <&gcc GPLL1_VOTE>,
>> 444 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
>> 445 <&mdss_dsi0_phy 1>,
>> 446 <&mdss_dsi0_phy 0>;
>> 447 clock-names = "xo",
>> 448 "mmss_gpll0_vote",
>> 449 "gpll0_vote",
>> 450 "gpll1_vote",
>> 451 "gfx3d_clk_src",
>> 452 "dsi0pll",
>> 453 "dsi0pllbyte";
>> 454 };
689 455
690 apss_master_stats: sra !! 456 tlmm: pinctrl@fd510000 {
691 reg = <0x150 0 !! 457 compatible = "qcom,msm8226-pinctrl";
>> 458 reg = <0xfd510000 0x4000>;
>> 459 gpio-controller;
>> 460 #gpio-cells = <2>;
>> 461 gpio-ranges = <&tlmm 0 0 117>;
>> 462 interrupt-controller;
>> 463 #interrupt-cells = <2>;
>> 464 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> 465
>> 466 blsp1_i2c1_pins: blsp1-i2c1-state {
>> 467 pins = "gpio2", "gpio3";
>> 468 function = "blsp_i2c1";
>> 469 drive-strength = <2>;
>> 470 bias-disable;
692 }; 471 };
693 472
694 mpss_master_stats: sra !! 473 blsp1_i2c2_pins: blsp1-i2c2-state {
695 reg = <0xb50 0 !! 474 pins = "gpio6", "gpio7";
>> 475 function = "blsp_i2c2";
>> 476 drive-strength = <2>;
>> 477 bias-disable;
696 }; 478 };
697 479
698 lpss_master_stats: sra !! 480 blsp1_i2c3_pins: blsp1-i2c3-state {
699 reg = <0x1550 !! 481 pins = "gpio10", "gpio11";
>> 482 function = "blsp_i2c3";
>> 483 drive-strength = <2>;
>> 484 bias-disable;
700 }; 485 };
701 486
702 pronto_master_stats: s !! 487 blsp1_i2c4_pins: blsp1-i2c4-state {
703 reg = <0x1f50 !! 488 pins = "gpio14", "gpio15";
>> 489 function = "blsp_i2c4";
>> 490 drive-strength = <2>;
>> 491 bias-disable;
>> 492 };
>> 493
>> 494 blsp1_i2c5_pins: blsp1-i2c5-state {
>> 495 pins = "gpio18", "gpio19";
>> 496 function = "blsp_i2c5";
>> 497 drive-strength = <2>;
>> 498 bias-disable;
>> 499 };
>> 500
>> 501 blsp1_i2c6_pins: blsp1-i2c6-state {
>> 502 pins = "gpio22", "gpio23";
>> 503 function = "blsp_i2c6";
>> 504 drive-strength = <2>;
>> 505 bias-disable;
>> 506 };
>> 507
>> 508 cci_default: cci-default-state {
>> 509 pins = "gpio29", "gpio30";
>> 510 function = "cci_i2c0";
>> 511
>> 512 drive-strength = <2>;
>> 513 bias-disable;
>> 514 };
>> 515
>> 516 cci_sleep: cci-sleep-state {
>> 517 pins = "gpio29", "gpio30";
>> 518 function = "gpio";
>> 519
>> 520 drive-strength = <2>;
>> 521 bias-disable;
>> 522 };
>> 523
>> 524 sdhc1_default_state: sdhc1-default-state {
>> 525 clk-pins {
>> 526 pins = "sdc1_clk";
>> 527 drive-strength = <10>;
>> 528 bias-disable;
>> 529 };
>> 530
>> 531 cmd-data-pins {
>> 532 pins = "sdc1_cmd", "sdc1_data";
>> 533 drive-strength = <10>;
>> 534 bias-pull-up;
>> 535 };
>> 536 };
>> 537
>> 538 sdhc2_default_state: sdhc2-default-state {
>> 539 clk-pins {
>> 540 pins = "sdc2_clk";
>> 541 drive-strength = <10>;
>> 542 bias-disable;
>> 543 };
>> 544
>> 545 cmd-data-pins {
>> 546 pins = "sdc2_cmd", "sdc2_data";
>> 547 drive-strength = <10>;
>> 548 bias-pull-up;
>> 549 };
>> 550 };
>> 551
>> 552 sdhc3_default_state: sdhc3-default-state {
>> 553 clk-pins {
>> 554 pins = "gpio44";
>> 555 function = "sdc3";
>> 556 drive-strength = <8>;
>> 557 bias-disable;
>> 558 };
>> 559
>> 560 cmd-pins {
>> 561 pins = "gpio43";
>> 562 function = "sdc3";
>> 563 drive-strength = <8>;
>> 564 bias-pull-up;
>> 565 };
>> 566
>> 567 data-pins {
>> 568 pins = "gpio39", "gpio40", "gpio41", "gpio42";
>> 569 function = "sdc3";
>> 570 drive-strength = <8>;
>> 571 bias-pull-up;
>> 572 };
704 }; 573 };
705 }; 574 };
706 575
707 tsens: thermal-sensor@fc4a9000 576 tsens: thermal-sensor@fc4a9000 {
708 compatible = "qcom,msm 577 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
709 reg = <0xfc4a9000 0x10 578 reg = <0xfc4a9000 0x1000>, /* TM */
710 <0xfc4a8000 0x10 579 <0xfc4a8000 0x1000>; /* SROT */
711 nvmem-cells = <&tsens_ 580 nvmem-cells = <&tsens_mode>,
712 <&tsens_ 581 <&tsens_base1>, <&tsens_base2>,
713 <&tsens_ 582 <&tsens_s0_p1>, <&tsens_s0_p2>,
714 <&tsens_ 583 <&tsens_s1_p1>, <&tsens_s1_p2>,
715 <&tsens_ 584 <&tsens_s2_p1>, <&tsens_s2_p2>,
716 <&tsens_ 585 <&tsens_s3_p1>, <&tsens_s3_p2>,
717 <&tsens_ 586 <&tsens_s4_p1>, <&tsens_s4_p2>,
718 <&tsens_ 587 <&tsens_s5_p1>, <&tsens_s5_p2>,
719 <&tsens_ 588 <&tsens_s6_p1>, <&tsens_s6_p2>;
720 nvmem-cell-names = "mo 589 nvmem-cell-names = "mode",
721 "ba 590 "base1", "base2",
722 "s0 591 "s0_p1", "s0_p2",
723 "s1 592 "s1_p1", "s1_p2",
724 "s2 593 "s2_p1", "s2_p2",
725 "s3 594 "s3_p1", "s3_p2",
726 "s4 595 "s4_p1", "s4_p2",
727 "s5 596 "s5_p1", "s5_p2",
728 "s6 597 "s6_p1", "s6_p2";
729 #qcom,sensors = <6>; 598 #qcom,sensors = <6>;
730 interrupts = <GIC_SPI 599 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
731 interrupt-names = "upl 600 interrupt-names = "uplow";
732 #thermal-sensor-cells 601 #thermal-sensor-cells = <1>;
733 }; 602 };
734 603
735 restart@fc4ab000 { 604 restart@fc4ab000 {
736 compatible = "qcom,psh 605 compatible = "qcom,pshold";
737 reg = <0xfc4ab000 0x4> 606 reg = <0xfc4ab000 0x4>;
738 }; 607 };
739 608
740 qfprom: efuse@fc4bc000 { !! 609 qfprom: qfprom@fc4bc000 {
741 compatible = "qcom,msm 610 compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
742 reg = <0xfc4bc000 0x10 611 reg = <0xfc4bc000 0x1000>;
743 #address-cells = <1>; 612 #address-cells = <1>;
744 #size-cells = <1>; 613 #size-cells = <1>;
745 614
746 tsens_base1: base1@1c1 615 tsens_base1: base1@1c1 {
747 reg = <0x1c1 0 616 reg = <0x1c1 0x2>;
748 bits = <5 8>; 617 bits = <5 8>;
749 }; 618 };
750 619
751 tsens_s0_p1: s0-p1@1c2 620 tsens_s0_p1: s0-p1@1c2 {
752 reg = <0x1c2 0 621 reg = <0x1c2 0x2>;
753 bits = <5 6>; 622 bits = <5 6>;
754 }; 623 };
755 624
756 tsens_s1_p1: s1-p1@1c4 625 tsens_s1_p1: s1-p1@1c4 {
757 reg = <0x1c4 0 626 reg = <0x1c4 0x1>;
758 bits = <0 6>; 627 bits = <0 6>;
759 }; 628 };
760 629
761 tsens_s2_p1: s2-p1@1c4 630 tsens_s2_p1: s2-p1@1c4 {
762 reg = <0x1c4 0 631 reg = <0x1c4 0x2>;
763 bits = <6 6>; 632 bits = <6 6>;
764 }; 633 };
765 634
766 tsens_s3_p1: s3-p1@1c5 635 tsens_s3_p1: s3-p1@1c5 {
767 reg = <0x1c5 0 636 reg = <0x1c5 0x2>;
768 bits = <4 6>; 637 bits = <4 6>;
769 }; 638 };
770 639
771 tsens_s4_p1: s4-p1@1c6 640 tsens_s4_p1: s4-p1@1c6 {
772 reg = <0x1c6 0 641 reg = <0x1c6 0x1>;
773 bits = <2 6>; 642 bits = <2 6>;
774 }; 643 };
775 644
776 tsens_s5_p1: s5-p1@1c7 645 tsens_s5_p1: s5-p1@1c7 {
777 reg = <0x1c7 0 646 reg = <0x1c7 0x1>;
778 bits = <0 6>; 647 bits = <0 6>;
779 }; 648 };
780 649
781 tsens_s6_p1: s6-p1@1ca 650 tsens_s6_p1: s6-p1@1ca {
782 reg = <0x1ca 0 651 reg = <0x1ca 0x2>;
783 bits = <4 6>; 652 bits = <4 6>;
784 }; 653 };
785 654
786 tsens_base2: base2@1cc 655 tsens_base2: base2@1cc {
787 reg = <0x1cc 0 656 reg = <0x1cc 0x1>;
788 bits = <0 8>; 657 bits = <0 8>;
789 }; 658 };
790 659
791 tsens_s0_p2: s0-p2@1cd 660 tsens_s0_p2: s0-p2@1cd {
792 reg = <0x1cd 0 661 reg = <0x1cd 0x1>;
793 bits = <0 6>; 662 bits = <0 6>;
794 }; 663 };
795 664
796 tsens_s1_p2: s1-p2@1cd 665 tsens_s1_p2: s1-p2@1cd {
797 reg = <0x1cd 0 666 reg = <0x1cd 0x2>;
798 bits = <6 6>; 667 bits = <6 6>;
799 }; 668 };
800 669
801 tsens_s2_p2: s2-p2@1ce 670 tsens_s2_p2: s2-p2@1ce {
802 reg = <0x1ce 0 671 reg = <0x1ce 0x2>;
803 bits = <4 6>; 672 bits = <4 6>;
804 }; 673 };
805 674
806 tsens_s3_p2: s3-p2@1cf 675 tsens_s3_p2: s3-p2@1cf {
807 reg = <0x1cf 0 676 reg = <0x1cf 0x1>;
808 bits = <2 6>; 677 bits = <2 6>;
809 }; 678 };
810 679
811 tsens_s4_p2: s4-p2@446 680 tsens_s4_p2: s4-p2@446 {
812 reg = <0x446 0 681 reg = <0x446 0x2>;
813 bits = <4 6>; 682 bits = <4 6>;
814 }; 683 };
815 684
816 tsens_s5_p2: s5-p2@447 685 tsens_s5_p2: s5-p2@447 {
817 reg = <0x447 0 686 reg = <0x447 0x1>;
818 bits = <2 6>; 687 bits = <2 6>;
819 }; 688 };
820 689
821 tsens_s6_p2: s6-p2@44e 690 tsens_s6_p2: s6-p2@44e {
822 reg = <0x44e 0 691 reg = <0x44e 0x1>;
823 bits = <1 6>; 692 bits = <1 6>;
824 }; 693 };
825 694
826 tsens_mode: mode@44f { 695 tsens_mode: mode@44f {
827 reg = <0x44f 0 696 reg = <0x44f 0x1>;
828 bits = <5 3>; 697 bits = <5 3>;
829 }; 698 };
830 }; 699 };
831 700
832 spmi_bus: spmi@fc4cf000 { 701 spmi_bus: spmi@fc4cf000 {
833 compatible = "qcom,spm 702 compatible = "qcom,spmi-pmic-arb";
834 reg-names = "core", "i 703 reg-names = "core", "intr", "cnfg";
835 reg = <0xfc4cf000 0x10 704 reg = <0xfc4cf000 0x1000>,
836 <0xfc4cb000 0x10 705 <0xfc4cb000 0x1000>,
837 <0xfc4ca000 0x10 706 <0xfc4ca000 0x1000>;
838 interrupt-names = "per 707 interrupt-names = "periph_irq";
839 interrupts = <GIC_SPI 708 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
840 qcom,ee = <0>; 709 qcom,ee = <0>;
841 qcom,channel = <0>; 710 qcom,channel = <0>;
842 #address-cells = <2>; 711 #address-cells = <2>;
843 #size-cells = <0>; 712 #size-cells = <0>;
844 interrupt-controller; 713 interrupt-controller;
845 #interrupt-cells = <4> 714 #interrupt-cells = <4>;
846 }; 715 };
847 716
848 tcsr_mutex: hwlock@fd484000 { !! 717 rng@f9bff000 {
849 compatible = "qcom,msm !! 718 compatible = "qcom,prng";
850 reg = <0xfd484000 0x10 !! 719 reg = <0xf9bff000 0x200>;
851 #hwlock-cells = <1>; !! 720 clocks = <&gcc GCC_PRNG_AHB_CLK>;
>> 721 clock-names = "core";
852 }; 722 };
853 723
854 tlmm: pinctrl@fd510000 { !! 724 timer@f9020000 {
855 compatible = "qcom,msm !! 725 compatible = "arm,armv7-timer-mem";
856 reg = <0xfd510000 0x40 !! 726 reg = <0xf9020000 0x1000>;
857 gpio-controller; !! 727 #address-cells = <1>;
858 #gpio-cells = <2>; !! 728 #size-cells = <1>;
859 gpio-ranges = <&tlmm 0 !! 729 ranges;
860 interrupt-controller; <<
861 #interrupt-cells = <2> <<
862 interrupts = <GIC_SPI <<
863 730
864 blsp1_i2c1_pins: blsp1 !! 731 frame@f9021000 {
865 pins = "gpio2" !! 732 frame-number = <0>;
866 function = "bl !! 733 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
867 drive-strength !! 734 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
868 bias-disable; !! 735 reg = <0xf9021000 0x1000>,
>> 736 <0xf9022000 0x1000>;
869 }; 737 };
870 738
871 blsp1_i2c2_pins: blsp1 !! 739 frame@f9023000 {
872 pins = "gpio6" !! 740 frame-number = <1>;
873 function = "bl !! 741 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
874 drive-strength !! 742 reg = <0xf9023000 0x1000>;
875 bias-disable; !! 743 status = "disabled";
876 }; 744 };
877 745
878 blsp1_i2c3_pins: blsp1 !! 746 frame@f9024000 {
879 pins = "gpio10 !! 747 frame-number = <2>;
880 function = "bl !! 748 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
881 drive-strength !! 749 reg = <0xf9024000 0x1000>;
882 bias-disable; !! 750 status = "disabled";
883 }; 751 };
884 752
885 blsp1_i2c4_pins: blsp1 !! 753 frame@f9025000 {
886 pins = "gpio14 !! 754 frame-number = <3>;
887 function = "bl !! 755 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
888 drive-strength !! 756 reg = <0xf9025000 0x1000>;
889 bias-disable; !! 757 status = "disabled";
890 }; 758 };
891 759
892 blsp1_i2c5_pins: blsp1 !! 760 frame@f9026000 {
893 pins = "gpio18 !! 761 frame-number = <4>;
894 function = "bl !! 762 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
895 drive-strength !! 763 reg = <0xf9026000 0x1000>;
896 bias-disable; !! 764 status = "disabled";
897 }; 765 };
898 766
899 blsp1_i2c6_pins: blsp1 !! 767 frame@f9027000 {
900 pins = "gpio22 !! 768 frame-number = <5>;
901 function = "bl !! 769 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
902 drive-strength !! 770 reg = <0xf9027000 0x1000>;
903 bias-disable; !! 771 status = "disabled";
904 }; 772 };
905 773
906 cci_default: cci-defau !! 774 frame@f9028000 {
907 pins = "gpio29 !! 775 frame-number = <6>;
908 function = "cc !! 776 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
909 !! 777 reg = <0xf9028000 0x1000>;
910 drive-strength !! 778 status = "disabled";
911 bias-disable; <<
912 }; 779 };
>> 780 };
913 781
914 cci_sleep: cci-sleep-s !! 782 sram@fc190000 {
915 pins = "gpio29 !! 783 compatible = "qcom,msm8226-rpm-stats";
916 function = "gp !! 784 reg = <0xfc190000 0x10000>;
>> 785 };
917 786
918 drive-strength !! 787 rpm_msg_ram: sram@fc428000 {
919 bias-disable; !! 788 compatible = "qcom,rpm-msg-ram";
>> 789 reg = <0xfc428000 0x4000>;
>> 790
>> 791 #address-cells = <1>;
>> 792 #size-cells = <1>;
>> 793 ranges = <0 0xfc428000 0x4000>;
>> 794
>> 795 apss_master_stats: sram@150 {
>> 796 reg = <0x150 0x14>;
920 }; 797 };
921 798
922 sdhc1_default_state: s !! 799 mpss_master_stats: sram@b50 {
923 clk-pins { !! 800 reg = <0xb50 0x14>;
924 pins = !! 801 };
925 drive- <<
926 bias-d <<
927 }; <<
928 802
929 cmd-data-pins !! 803 lpss_master_stats: sram@1550 {
930 pins = !! 804 reg = <0x1550 0x14>;
931 drive- <<
932 bias-p <<
933 }; <<
934 }; 805 };
935 806
936 sdhc2_default_state: s !! 807 pronto_master_stats: sram@1f50 {
937 clk-pins { !! 808 reg = <0x1f50 0x14>;
938 pins = !! 809 };
939 drive- !! 810 };
940 bias-d <<
941 }; <<
942 811
943 cmd-data-pins !! 812 tcsr_mutex: hwlock@fd484000 {
944 pins = !! 813 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
945 drive- !! 814 reg = <0xfd484000 0x1000>;
946 bias-p !! 815 #hwlock-cells = <1>;
947 }; !! 816 };
>> 817
>> 818 adsp: remoteproc@fe200000 {
>> 819 compatible = "qcom,msm8226-adsp-pil";
>> 820 reg = <0xfe200000 0x100>;
>> 821
>> 822 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
>> 823 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
>> 824 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
>> 825 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
>> 826 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
>> 827 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
>> 828
>> 829 power-domains = <&rpmpd MSM8226_VDDCX>;
>> 830 power-domain-names = "cx";
>> 831
>> 832 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
>> 833 clock-names = "xo";
>> 834
>> 835 memory-region = <&adsp_region>;
>> 836
>> 837 qcom,smem-states = <&adsp_smp2p_out 0>;
>> 838 qcom,smem-state-names = "stop";
>> 839
>> 840 status = "disabled";
>> 841
>> 842 smd-edge {
>> 843 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
>> 844
>> 845 qcom,ipc = <&apcs 8 8>;
>> 846 qcom,smd-edge = <1>;
>> 847
>> 848 label = "lpass";
948 }; 849 };
>> 850 };
949 851
950 sdhc3_default_state: s !! 852 sram@fdd00000 {
951 clk-pins { !! 853 compatible = "qcom,msm8226-ocmem";
952 pins = !! 854 reg = <0xfdd00000 0x2000>,
953 functi !! 855 <0xfec00000 0x20000>;
954 drive- !! 856 reg-names = "ctrl", "mem";
955 bias-d !! 857 ranges = <0 0xfec00000 0x20000>;
956 }; !! 858 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
>> 859 clock-names = "core";
957 860
958 cmd-pins { !! 861 #address-cells = <1>;
959 pins = !! 862 #size-cells = <1>;
960 functi <<
961 drive- <<
962 bias-p <<
963 }; <<
964 863
965 data-pins { !! 864 gmu_sram: gmu-sram@0 {
966 pins = !! 865 reg = <0x0 0x20000>;
967 functi <<
968 drive- <<
969 bias-p <<
970 }; <<
971 }; 866 };
972 }; 867 };
973 868
974 mmcc: clock-controller@fd8c000 !! 869 sram@fe805000 {
975 compatible = "qcom,mmc !! 870 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
976 reg = <0xfd8c0000 0x60 !! 871 reg = <0xfe805000 0x1000>;
977 #clock-cells = <1>; <<
978 #reset-cells = <1>; <<
979 #power-domain-cells = <<
980 872
981 clocks = <&rpmcc RPM_S !! 873 reboot-mode {
982 <&gcc GCC_MMS !! 874 compatible = "syscon-reboot-mode";
983 <&gcc GPLL0_V !! 875 offset = <0x65c>;
984 <&gcc GPLL1_V !! 876
985 <&rpmcc RPM_S !! 877 mode-bootloader = <0x77665500>;
986 <&mdss_dsi0_p !! 878 mode-normal = <0x77665501>;
987 <&mdss_dsi0_p !! 879 mode-recovery = <0x77665502>;
988 clock-names = "xo", !! 880 };
989 "mmss_gp <<
990 "gpll0_v <<
991 "gpll1_v <<
992 "gfx3d_c <<
993 "dsi0pll <<
994 "dsi0pll <<
995 }; 881 };
996 882
997 mdss: display-subsystem@fd9000 883 mdss: display-subsystem@fd900000 {
998 compatible = "qcom,mds 884 compatible = "qcom,mdss";
999 reg = <0xfd900000 0x10 885 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1000 reg-names = "mdss_phy 886 reg-names = "mdss_phys", "vbif_phys";
1001 887
1002 power-domains = <&mmc 888 power-domains = <&mmcc MDSS_GDSC>;
1003 889
1004 clocks = <&mmcc MDSS_ 890 clocks = <&mmcc MDSS_AHB_CLK>,
1005 <&mmcc MDSS_ 891 <&mmcc MDSS_AXI_CLK>,
1006 <&mmcc MDSS_ 892 <&mmcc MDSS_VSYNC_CLK>;
1007 clock-names = "iface" 893 clock-names = "iface",
1008 "bus", 894 "bus",
1009 "vsync" 895 "vsync";
1010 896
1011 interrupts = <GIC_SPI 897 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1012 898
1013 interrupt-controller; 899 interrupt-controller;
1014 #interrupt-cells = <1 900 #interrupt-cells = <1>;
1015 901
1016 #address-cells = <1>; 902 #address-cells = <1>;
1017 #size-cells = <1>; 903 #size-cells = <1>;
1018 ranges; 904 ranges;
1019 905
1020 status = "disabled"; 906 status = "disabled";
1021 907
1022 mdss_mdp: display-con 908 mdss_mdp: display-controller@fd900000 {
1023 compatible = 909 compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
1024 reg = <0xfd90 910 reg = <0xfd900100 0x22000>;
1025 reg-names = " 911 reg-names = "mdp_phys";
1026 912
1027 interrupt-par 913 interrupt-parent = <&mdss>;
1028 interrupts = 914 interrupts = <0>;
1029 915
1030 clocks = <&mm 916 clocks = <&mmcc MDSS_AHB_CLK>,
1031 <&mm 917 <&mmcc MDSS_AXI_CLK>,
1032 <&mm 918 <&mmcc MDSS_MDP_CLK>,
1033 <&mm 919 <&mmcc MDSS_VSYNC_CLK>;
1034 clock-names = 920 clock-names = "iface",
1035 921 "bus",
1036 922 "core",
1037 923 "vsync";
1038 924
1039 ports { 925 ports {
1040 #addr 926 #address-cells = <1>;
1041 #size 927 #size-cells = <0>;
1042 928
1043 port@ 929 port@0 {
1044 930 reg = <0>;
1045 931 mdss_mdp_intf1_out: endpoint {
1046 932 remote-endpoint = <&mdss_dsi0_in>;
1047 933 };
1048 }; 934 };
1049 }; 935 };
1050 }; 936 };
1051 937
1052 mdss_dsi0: dsi@fd9228 938 mdss_dsi0: dsi@fd922800 {
1053 compatible = 939 compatible = "qcom,msm8226-dsi-ctrl",
1054 940 "qcom,mdss-dsi-ctrl";
1055 reg = <0xfd92 941 reg = <0xfd922800 0x1f8>;
1056 reg-names = " 942 reg-names = "dsi_ctrl";
1057 943
1058 interrupt-par 944 interrupt-parent = <&mdss>;
1059 interrupts = 945 interrupts = <4>;
1060 946
1061 assigned-cloc 947 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1062 948 <&mmcc PCLK0_CLK_SRC>;
1063 assigned-cloc 949 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1064 950 <&mdss_dsi0_phy 1>;
1065 951
1066 clocks = <&mm 952 clocks = <&mmcc MDSS_MDP_CLK>,
1067 <&mm 953 <&mmcc MDSS_AHB_CLK>,
1068 <&mm 954 <&mmcc MDSS_AXI_CLK>,
1069 <&mm 955 <&mmcc MDSS_BYTE0_CLK>,
1070 <&mm 956 <&mmcc MDSS_PCLK0_CLK>,
1071 <&mm 957 <&mmcc MDSS_ESC0_CLK>,
1072 <&mm 958 <&mmcc MMSS_MISC_AHB_CLK>;
1073 clock-names = 959 clock-names = "mdp_core",
1074 960 "iface",
1075 961 "bus",
1076 962 "byte",
1077 963 "pixel",
1078 964 "core",
1079 965 "core_mmss";
1080 966
1081 phys = <&mdss 967 phys = <&mdss_dsi0_phy>;
1082 968
1083 #address-cell 969 #address-cells = <1>;
1084 #size-cells = 970 #size-cells = <0>;
1085 971
1086 ports { 972 ports {
1087 #addr 973 #address-cells = <1>;
1088 #size 974 #size-cells = <0>;
1089 975
1090 port@ 976 port@0 {
1091 977 reg = <0>;
1092 978 mdss_dsi0_in: endpoint {
1093 979 remote-endpoint = <&mdss_mdp_intf1_out>;
1094 980 };
1095 }; 981 };
1096 982
1097 port@ 983 port@1 {
1098 984 reg = <1>;
1099 985 mdss_dsi0_out: endpoint {
1100 986 };
1101 }; 987 };
1102 }; 988 };
1103 }; 989 };
1104 990
1105 mdss_dsi0_phy: phy@fd 991 mdss_dsi0_phy: phy@fd922a00 {
1106 compatible = 992 compatible = "qcom,dsi-phy-28nm-8226";
1107 reg = <0xfd92 993 reg = <0xfd922a00 0xd4>,
1108 <0xfd92 994 <0xfd922b00 0x280>,
1109 <0xfd92 995 <0xfd922d80 0x30>;
1110 reg-names = " 996 reg-names = "dsi_pll",
1111 " 997 "dsi_phy",
1112 " 998 "dsi_phy_regulator";
1113 999
1114 #clock-cells 1000 #clock-cells = <1>;
1115 #phy-cells = 1001 #phy-cells = <0>;
1116 1002
1117 clocks = <&mm 1003 clocks = <&mmcc MDSS_AHB_CLK>,
1118 <&rp 1004 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1119 clock-names = 1005 clock-names = "iface",
1120 1006 "ref";
1121 }; 1007 };
1122 }; 1008 };
1123 1009
1124 cci: cci@fda0c000 { !! 1010 gpu: adreno@fdb00000 {
1125 compatible = "qcom,ms <<
1126 reg = <0xfda0c000 0x1 <<
1127 #address-cells = <1>; <<
1128 #size-cells = <0>; <<
1129 interrupts = <GIC_SPI <<
1130 clocks = <&mmcc CAMSS <<
1131 <&mmcc CAMSS <<
1132 <&mmcc CAMSS <<
1133 clock-names = "camss_ <<
1134 "cci_ah <<
1135 "cci"; <<
1136 <<
1137 pinctrl-names = "defa <<
1138 pinctrl-0 = <&cci_def <<
1139 pinctrl-1 = <&cci_sle <<
1140 <<
1141 status = "disabled"; <<
1142 <<
1143 cci_i2c0: i2c-bus@0 { <<
1144 reg = <0>; <<
1145 clock-frequen <<
1146 #address-cell <<
1147 #size-cells = <<
1148 }; <<
1149 }; <<
1150 <<
1151 gpu: gpu@fdb00000 { <<
1152 compatible = "qcom,ad 1011 compatible = "qcom,adreno-305.18", "qcom,adreno";
1153 reg = <0xfdb00000 0x1 1012 reg = <0xfdb00000 0x10000>;
1154 reg-names = "kgsl_3d0 1013 reg-names = "kgsl_3d0_reg_memory";
1155 1014
1156 interrupts = <GIC_SPI 1015 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1157 interrupt-names = "kg 1016 interrupt-names = "kgsl_3d0_irq";
1158 1017
1159 clocks = <&mmcc OXILI 1018 clocks = <&mmcc OXILI_GFX3D_CLK>,
1160 <&mmcc OXILI 1019 <&mmcc OXILICX_AHB_CLK>,
1161 <&mmcc OXILI 1020 <&mmcc OXILICX_AXI_CLK>;
1162 clock-names = "core", 1021 clock-names = "core", "iface", "mem_iface";
1163 1022
1164 sram = <&gmu_sram>; 1023 sram = <&gmu_sram>;
1165 power-domains = <&mmc 1024 power-domains = <&mmcc OXILICX_GDSC>;
1166 operating-points-v2 = 1025 operating-points-v2 = <&gpu_opp_table>;
1167 1026
1168 status = "disabled"; 1027 status = "disabled";
1169 1028
1170 gpu_opp_table: opp-ta 1029 gpu_opp_table: opp-table {
1171 compatible = 1030 compatible = "operating-points-v2";
1172 1031
1173 opp-450000000 1032 opp-450000000 {
1174 opp-h 1033 opp-hz = /bits/ 64 <450000000>;
1175 }; 1034 };
1176 1035
1177 opp-320000000 1036 opp-320000000 {
1178 opp-h 1037 opp-hz = /bits/ 64 <320000000>;
1179 }; 1038 };
1180 1039
1181 opp-200000000 1040 opp-200000000 {
1182 opp-h 1041 opp-hz = /bits/ 64 <200000000>;
1183 }; 1042 };
1184 1043
1185 opp-19000000 1044 opp-19000000 {
1186 opp-h 1045 opp-hz = /bits/ 64 <19000000>;
1187 }; 1046 };
1188 }; 1047 };
1189 }; 1048 };
1190 <<
1191 sram@fdd00000 { <<
1192 compatible = "qcom,ms <<
1193 reg = <0xfdd00000 0x2 <<
1194 <0xfec00000 0x2 <<
1195 reg-names = "ctrl", " <<
1196 ranges = <0 0xfec0000 <<
1197 clocks = <&rpmcc RPM_ <<
1198 clock-names = "core"; <<
1199 <<
1200 #address-cells = <1>; <<
1201 #size-cells = <1>; <<
1202 <<
1203 gmu_sram: gmu-sram@0 <<
1204 reg = <0x0 0x <<
1205 }; <<
1206 }; <<
1207 <<
1208 adsp: remoteproc@fe200000 { <<
1209 compatible = "qcom,ms <<
1210 reg = <0xfe200000 0x1 <<
1211 <<
1212 interrupts-extended = <<
1213 <<
1214 <<
1215 <<
1216 <<
1217 interrupt-names = "wd <<
1218 <<
1219 power-domains = <&rpm <<
1220 power-domain-names = <<
1221 <<
1222 clocks = <&rpmcc RPM_ <<
1223 clock-names = "xo"; <<
1224 <<
1225 memory-region = <&ads <<
1226 <<
1227 qcom,smem-states = <& <<
1228 qcom,smem-state-names <<
1229 <<
1230 status = "disabled"; <<
1231 <<
1232 smd-edge { <<
1233 interrupts = <<
1234 <<
1235 mboxes = <&ap <<
1236 qcom,smd-edge <<
1237 <<
1238 label = "lpas <<
1239 }; <<
1240 }; <<
1241 <<
1242 sram@fe805000 { <<
1243 compatible = "qcom,ms <<
1244 reg = <0xfe805000 0x1 <<
1245 <<
1246 reboot-mode { <<
1247 compatible = <<
1248 offset = <0x6 <<
1249 <<
1250 mode-bootload <<
1251 mode-normal = <<
1252 mode-recovery <<
1253 }; <<
1254 }; <<
1255 }; 1049 };
1256 1050
1257 thermal-zones { 1051 thermal-zones {
1258 cpu0-thermal { 1052 cpu0-thermal {
1259 polling-delay-passive 1053 polling-delay-passive = <250>;
1260 polling-delay = <1000 1054 polling-delay = <1000>;
1261 1055
1262 thermal-sensors = <&t 1056 thermal-sensors = <&tsens 5>;
1263 1057
1264 cooling-maps { <<
1265 map0 { <<
1266 trip <<
1267 cooli <<
1268 <<
1269 <<
1270 <<
1271 }; <<
1272 }; <<
1273 <<
1274 trips { 1058 trips {
1275 cpu_alert0: t 1059 cpu_alert0: trip0 {
1276 tempe 1060 temperature = <75000>;
1277 hyste 1061 hysteresis = <2000>;
1278 type 1062 type = "passive";
1279 }; 1063 };
1280 1064
1281 cpu_crit0: tr 1065 cpu_crit0: trip1 {
1282 tempe 1066 temperature = <110000>;
1283 hyste 1067 hysteresis = <2000>;
1284 type 1068 type = "critical";
1285 }; 1069 };
1286 }; 1070 };
1287 }; 1071 };
1288 1072
1289 cpu1-thermal { 1073 cpu1-thermal {
1290 polling-delay-passive 1074 polling-delay-passive = <250>;
1291 polling-delay = <1000 1075 polling-delay = <1000>;
1292 1076
1293 thermal-sensors = <&t 1077 thermal-sensors = <&tsens 2>;
1294 <<
1295 cooling-maps { <<
1296 map0 { <<
1297 trip <<
1298 cooli <<
1299 <<
1300 <<
1301 <<
1302 }; <<
1303 }; <<
1304 1078
1305 trips { 1079 trips {
1306 cpu_alert1: t 1080 cpu_alert1: trip0 {
1307 tempe 1081 temperature = <75000>;
1308 hyste 1082 hysteresis = <2000>;
1309 type 1083 type = "passive";
1310 }; 1084 };
1311 1085
1312 cpu_crit1: tr 1086 cpu_crit1: trip1 {
1313 tempe 1087 temperature = <110000>;
1314 hyste 1088 hysteresis = <2000>;
1315 type 1089 type = "critical";
1316 }; 1090 };
1317 }; 1091 };
1318 }; 1092 };
1319 }; 1093 };
1320 1094
1321 timer { 1095 timer {
1322 compatible = "arm,armv7-timer 1096 compatible = "arm,armv7-timer";
1323 interrupts = <GIC_PPI 2 1097 interrupts = <GIC_PPI 2
1324 (GIC_CPU_MASK 1098 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
1325 <GIC_PPI 3 1099 <GIC_PPI 3
1326 (GIC_CPU_MASK 1100 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
1327 <GIC_PPI 4 1101 <GIC_PPI 4
1328 (GIC_CPU_MASK 1102 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
1329 <GIC_PPI 1 1103 <GIC_PPI 1
1330 (GIC_CPU_MASK 1104 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
1331 }; 1105 };
1332 }; 1106 };
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