1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/interrupt-controller/irq
5 #include <dt-bindings/interrupt-controller/arm
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h
7 #include <dt-bindings/soc/qcom,gsbi.h>
8
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Qualcomm MSM8660";
13 compatible = "qcom,msm8660";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "qcom,sco
22 enable-method = "qcom,
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L
26 };
27
28 cpu@1 {
29 compatible = "qcom,sco
30 enable-method = "qcom,
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 cache-unified;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x0 0x0>;
46 };
47
48 cpu-pmu {
49 compatible = "qcom,scorpion-mp
50 interrupts = <GIC_PPI 9 (GIC_C
51 };
52
53 clocks {
54 cxo_board: cxo-board-clk {
55 compatible = "fixed-cl
56 #clock-cells = <0>;
57 clock-frequency = <192
58 clock-output-names = "
59 };
60
61 pxo_board: pxo-board-clk {
62 compatible = "fixed-cl
63 #clock-cells = <0>;
64 clock-frequency = <270
65 clock-output-names = "
66 };
67
68 sleep-clk {
69 compatible = "fixed-cl
70 #clock-cells = <0>;
71 clock-frequency = <327
72 clock-output-names = "
73 };
74 };
75
76 soc: soc {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 compatible = "simple-bus";
81
82 intc: interrupt-controller@208
83 compatible = "qcom,msm
84 interrupt-controller;
85 #interrupt-cells = <3>
86 reg = < 0x02080000 0x1
87 < 0x02081000 0x1
88 };
89
90 timer@2000000 {
91 compatible = "qcom,scs
92 interrupts = <GIC_PPI
93 <GIC_PPI
94 <GIC_PPI
95 reg = <0x02000000 0x10
96 clock-frequency = <270
97 cpu-offset = <0x40000>
98 };
99
100 tlmm: pinctrl@800000 {
101 compatible = "qcom,msm
102 reg = <0x800000 0x4000
103
104 gpio-controller;
105 gpio-ranges = <&tlmm 0
106 #gpio-cells = <2>;
107 interrupts = <GIC_SPI
108 interrupt-controller;
109 #interrupt-cells = <2>
110
111 };
112
113 gcc: clock-controller@900000 {
114 compatible = "qcom,gcc
115 #clock-cells = <1>;
116 #reset-cells = <1>;
117 reg = <0x900000 0x4000
118 clocks = <&pxo_board>,
119 clock-names = "pxo", "
120 };
121
122 gsbi1: gsbi@16000000 {
123 compatible = "qcom,gsb
124 cell-index = <12>;
125 reg = <0x16000000 0x10
126 clocks = <&gcc GSBI1_H
127 clock-names = "iface";
128 #address-cells = <1>;
129 #size-cells = <1>;
130 ranges;
131
132 syscon-tcsr = <&tcsr>;
133
134 status = "disabled";
135
136 gsbi1_spi: spi@1608000
137 compatible = "
138 reg = <0x16080
139 interrupts = <
140 clocks = <&gcc
141 clock-names =
142 #address-cells
143 #size-cells =
144 status = "disa
145 };
146 };
147
148 gsbi3: gsbi@16200000 {
149 compatible = "qcom,gsb
150 cell-index = <12>;
151 reg = <0x16200000 0x10
152 clocks = <&gcc GSBI3_H
153 clock-names = "iface";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges;
157
158 syscon-tcsr = <&tcsr>;
159 status = "disabled";
160
161 gsbi3_i2c: i2c@1628000
162 compatible = "
163 reg = <0x16280
164 interrupts = <
165 clocks = <&gcc
166 clock-names =
167 #address-cells
168 #size-cells =
169 status = "disa
170 };
171 };
172
173 gsbi6: gsbi@16500000 {
174 compatible = "qcom,gsb
175 cell-index = <12>;
176 reg = <0x16500000 0x10
177 clocks = <&gcc GSBI6_H
178 clock-names = "iface";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
182 status = "disabled";
183
184 syscon-tcsr = <&tcsr>;
185
186 gsbi6_serial: serial@1
187 compatible = "
188 reg = <0x16540
189 <0x16500
190 interrupts = <
191 clocks = <&gcc
192 clock-names =
193 status = "disa
194 };
195
196 gsbi6_i2c: i2c@1658000
197 compatible = "
198 reg = <0x16580
199 interrupts = <
200 clocks = <&gcc
201 clock-names =
202 #address-cells
203 #size-cells =
204 status = "disa
205 };
206 };
207
208 gsbi7: gsbi@16600000 {
209 compatible = "qcom,gsb
210 cell-index = <12>;
211 reg = <0x16600000 0x10
212 clocks = <&gcc GSBI7_H
213 clock-names = "iface";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 ranges;
217 status = "disabled";
218
219 syscon-tcsr = <&tcsr>;
220
221 gsbi7_serial: serial@1
222 compatible = "
223 reg = <0x16640
224 <0x16600
225 interrupts = <
226 clocks = <&gcc
227 clock-names =
228 status = "disa
229 };
230
231 gsbi7_i2c: i2c@1668000
232 compatible = "
233 reg = <0x16680
234 interrupts = <
235 clocks = <&gcc
236 clock-names =
237 #address-cells
238 #size-cells =
239 status = "disa
240 };
241 };
242
243 gsbi8: gsbi@19800000 {
244 compatible = "qcom,gsb
245 cell-index = <12>;
246 reg = <0x19800000 0x10
247 clocks = <&gcc GSBI8_H
248 clock-names = "iface";
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges;
252
253 syscon-tcsr = <&tcsr>;
254 status = "disabled";
255
256 gsbi8_i2c: i2c@1988000
257 compatible = "
258 reg = <0x19880
259 interrupts = <
260 clocks = <&gcc
261 clock-names =
262 #address-cells
263 #size-cells =
264 status = "disa
265 };
266 };
267
268 gsbi12: gsbi@19c00000 {
269 compatible = "qcom,gsb
270 cell-index = <12>;
271 reg = <0x19c00000 0x10
272 clocks = <&gcc GSBI12_
273 clock-names = "iface";
274 #address-cells = <1>;
275 #size-cells = <1>;
276 ranges;
277
278 syscon-tcsr = <&tcsr>;
279
280 gsbi12_serial: serial@
281 compatible = "
282 reg = <0x19c40
283 <0x19c00
284 interrupts = <
285 clocks = <&gcc
286 clock-names =
287 status = "disa
288 };
289
290 gsbi12_i2c: i2c@19c800
291 compatible = "
292 reg = <0x19c80
293 interrupts = <
294 clocks = <&gcc
295 clock-names =
296 #address-cells
297 #size-cells =
298 status = "disa
299 };
300 };
301
302 ebi2: external-bus@1a100000 {
303 compatible = "qcom,msm
304 #address-cells = <2>;
305 #size-cells = <1>;
306 ranges = <0 0x0 0x1a80
307 <1 0x0 0x1b00
308 <2 0x0 0x1b80
309 <3 0x0 0x1d00
310 <4 0x0 0x1c80
311 <5 0x0 0x1c00
312 reg = <0x1a100000 0x10
313 reg-names = "ebi2", "x
314 clocks = <&gcc EBI2_2X
315 clock-names = "ebi2x",
316 status = "disabled";
317 };
318
319 ssbi: ssbi@500000 {
320 compatible = "qcom,ssb
321 reg = <0x500000 0x1000
322 qcom,controller-type =
323 };
324
325 l2cc: clock-controller@2082000
326 compatible = "qcom,kps
327 reg = <0x02082000 0x10
328 };
329
330 rpm: rpm@104000 {
331 compatible = "qcom,rpm
332 reg = <0x00104000 0x10
333 qcom,ipc = <&l2cc 0x8
334
335 interrupts = <GIC_SPI
336 <GIC_SPI
337 <GIC_SPI
338 interrupt-names = "ack
339 clocks = <&gcc RPM_MSG
340 clock-names = "ram";
341
342 rpmcc: clock-controlle
343 compatible = "
344 #clock-cells =
345 clocks = <&pxo
346 clock-names =
347 };
348 };
349
350 amba {
351 compatible = "simple-b
352 #address-cells = <1>;
353 #size-cells = <1>;
354 ranges;
355 sdcc1: mmc@12400000 {
356 status = "disa
357 compatible = "
358 arm,primecell-
359 reg = <0x12400
360 interrupts = <
361 clocks = <&gcc
362 clock-names =
363 bus-width = <8
364 max-frequency
365 non-removable;
366 cap-sd-highspe
367 cap-mmc-highsp
368 };
369
370 sdcc2: mmc@12140000 {
371 status = "disa
372 compatible = "
373 arm,primecell-
374 reg = <0x12140
375 interrupts = <
376 clocks = <&gcc
377 clock-names =
378 bus-width = <8
379 max-frequency
380 cap-sd-highspe
381 cap-mmc-highsp
382 };
383
384 sdcc3: mmc@12180000 {
385 compatible = "
386 arm,primecell-
387 status = "disa
388 reg = <0x12180
389 interrupts = <
390 clocks = <&gcc
391 clock-names =
392 bus-width = <4
393 cap-sd-highspe
394 cap-mmc-highsp
395 max-frequency
396 no-1-8-v;
397 };
398
399 sdcc4: mmc@121c0000 {
400 compatible = "
401 arm,primecell-
402 status = "disa
403 reg = <0x121c0
404 interrupts = <
405 clocks = <&gcc
406 clock-names =
407 bus-width = <4
408 max-frequency
409 cap-sd-highspe
410 cap-mmc-highsp
411 };
412
413 sdcc5: mmc@12200000 {
414 compatible = "
415 arm,primecell-
416 status = "disa
417 reg = <0x12200
418 interrupts = <
419 clocks = <&gcc
420 clock-names =
421 bus-width = <4
422 cap-sd-highspe
423 cap-mmc-highsp
424 max-frequency
425 };
426 };
427
428 tcsr: syscon@1a400000 {
429 compatible = "qcom,tcs
430 reg = <0x1a400000 0x10
431 };
432 };
433
434 };
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