1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/interrupt-controller/arm
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "Qualcomm MSM8960";
15 compatible = "qcom,msm8960";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304
22
23 cpu@0 {
24 compatible = "qcom,kra
25 enable-method = "qcom,
26 device_type = "cpu";
27 reg = <0>;
28 next-level-cache = <&L
29 qcom,acc = <&acc0>;
30 qcom,saw = <&saw0>;
31 };
32
33 cpu@1 {
34 compatible = "qcom,kra
35 enable-method = "qcom,
36 device_type = "cpu";
37 reg = <1>;
38 next-level-cache = <&L
39 qcom,acc = <&acc1>;
40 qcom,saw = <&saw1>;
41 };
42
43 L2: l2-cache {
44 compatible = "cache";
45 cache-level = <2>;
46 cache-unified;
47 };
48 };
49
50 memory@80000000 {
51 device_type = "memory";
52 reg = <0x80000000 0>;
53 };
54
55 cpu-pmu {
56 compatible = "qcom,krait-pmu";
57 interrupts = <GIC_PPI 10 0x304
58 qcom,no-pc-write;
59 };
60
61 clocks {
62 cxo_board: cxo_board {
63 compatible = "fixed-cl
64 #clock-cells = <0>;
65 clock-frequency = <192
66 clock-output-names = "
67 };
68
69 pxo_board: pxo_board {
70 compatible = "fixed-cl
71 #clock-cells = <0>;
72 clock-frequency = <270
73 clock-output-names = "
74 };
75
76 sleep_clk: sleep_clk {
77 compatible = "fixed-cl
78 #clock-cells = <0>;
79 clock-frequency = <327
80 clock-output-names = "
81 };
82 };
83
84 /* Temporary fixed regulator */
85 vsdcc_fixed: vsdcc-regulator {
86 compatible = "regulator-fixed"
87 regulator-name = "SDCC Power";
88 regulator-min-microvolt = <270
89 regulator-max-microvolt = <270
90 regulator-always-on;
91 };
92
93 soc: soc {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges;
97 compatible = "simple-bus";
98
99 intc: interrupt-controller@200
100 compatible = "qcom,msm
101 interrupt-controller;
102 #interrupt-cells = <3>
103 reg = <0x02000000 0x10
104 <0x02002000 0x10
105 };
106
107 timer@200a000 {
108 compatible = "qcom,kps
109 "qcom,msm
110 interrupts = <GIC_PPI
111 <GIC_PPI
112 <GIC_PPI
113 reg = <0x0200a000 0x10
114 clock-frequency = <270
115 cpu-offset = <0x80000>
116 };
117
118 msmgpio: pinctrl@800000 {
119 compatible = "qcom,msm
120 gpio-controller;
121 gpio-ranges = <&msmgpi
122 #gpio-cells = <2>;
123 interrupts = <GIC_SPI
124 interrupt-controller;
125 #interrupt-cells = <2>
126 reg = <0x800000 0x4000
127 };
128
129 gcc: clock-controller@900000 {
130 compatible = "qcom,gcc
131 #clock-cells = <1>;
132 #reset-cells = <1>;
133 reg = <0x900000 0x4000
134 clocks = <&cxo_board>,
135 <&pxo_board>,
136 <&lcc PLL4>;
137 clock-names = "cxo", "
138 };
139
140 lcc: clock-controller@28000000
141 compatible = "qcom,lcc
142 reg = <0x28000000 0x10
143 #clock-cells = <1>;
144 #reset-cells = <1>;
145 clocks = <&pxo_board>,
146 <&gcc PLL4_VO
147 <0>,
148 <0>, <0>,
149 <0>, <0>,
150 <0>;
151 clock-names = "pxo",
152 "pll4_vo
153 "mi2s_co
154 "codec_i
155 "spare_i
156 "codec_i
157 "spare_i
158 "pcm_cod
159 };
160
161 clock-controller@4000000 {
162 compatible = "qcom,mmc
163 reg = <0x4000000 0x100
164 #clock-cells = <1>;
165 #power-domain-cells =
166 #reset-cells = <1>;
167 clocks = <&pxo_board>,
168 <&gcc PLL3>,
169 <&gcc PLL8_VO
170 <0>,
171 <0>,
172 <0>,
173 <0>,
174 <0>;
175 clock-names = "pxo",
176 "pll3",
177 "pll8_vo
178 "dsi1pll
179 "dsi1pll
180 "dsi2pll
181 "dsi2pll
182 "hdmipll
183 };
184
185 l2cc: clock-controller@2011000
186 compatible = "qcom,kps
187 reg = <0x2011000 0x100
188 clocks = <&gcc PLL8_VO
189 clock-names = "pll8_vo
190 #clock-cells = <0>;
191 };
192
193 rpm: rpm@108000 {
194 compatible = "qcom,rpm
195 reg = <0x108000 0x1000
196 qcom,ipc = <&l2cc 0x8
197
198 interrupts = <GIC_SPI
199 <GIC_SPI
200 <GIC_SPI
201 interrupt-names = "ack
202 };
203
204 acc0: clock-controller@2088000
205 compatible = "qcom,kps
206 reg = <0x02088000 0x10
207 clocks = <&gcc PLL8_VO
208 clock-names = "pll8_vo
209 clock-output-names = "
210 #clock-cells = <0>;
211 };
212
213 acc1: clock-controller@2098000
214 compatible = "qcom,kps
215 reg = <0x02098000 0x10
216 clocks = <&gcc PLL8_VO
217 clock-names = "pll8_vo
218 clock-output-names = "
219 #clock-cells = <0>;
220 };
221
222 saw0: power-manager@2089000 {
223 compatible = "qcom,msm
224 reg = <0x02089000 0x10
225
226 saw0_vreg: regulator {
227 regulator-min-
228 regulator-max-
229 };
230 };
231
232 saw1: power-manager@2099000 {
233 compatible = "qcom,msm
234 reg = <0x02099000 0x10
235
236 saw1_vreg: regulator {
237 regulator-min-
238 regulator-max-
239 };
240 };
241
242 gsbi5: gsbi@16400000 {
243 compatible = "qcom,gsb
244 cell-index = <5>;
245 reg = <0x16400000 0x10
246 clocks = <&gcc GSBI5_H
247 clock-names = "iface";
248 #address-cells = <1>;
249 #size-cells = <1>;
250 ranges;
251
252 syscon-tcsr = <&tcsr>;
253
254 gsbi5_serial: serial@1
255 compatible = "
256 reg = <0x16440
257 <0x16400
258 interrupts = <
259 clocks = <&gcc
260 clock-names =
261 status = "disa
262 };
263 };
264
265 ssbi: ssbi@500000 {
266 compatible = "qcom,ssb
267 reg = <0x500000 0x1000
268 qcom,controller-type =
269 };
270
271 rng@1a500000 {
272 compatible = "qcom,prn
273 reg = <0x1a500000 0x20
274 clocks = <&gcc PRNG_CL
275 clock-names = "core";
276 };
277
278 sdcc3: mmc@12180000 {
279 compatible = "arm,pl18
280 arm,primecell-periphid
281 status = "disabled";
282 reg = <0x12180000 0x80
283 interrupts = <GIC_SPI
284 clocks = <&gcc SDC3_CL
285 clock-names = "mclk",
286 bus-width = <4>;
287 cap-sd-highspeed;
288 cap-mmc-highspeed;
289 max-frequency = <19200
290 no-1-8-v;
291 vmmc-supply = <&vsdcc_
292 };
293
294 sdcc1: mmc@12400000 {
295 status = "disabled";
296 compatible = "arm,pl18
297 arm,primecell-periphid
298 reg = <0x12400000 0x80
299 interrupts = <GIC_SPI
300 clocks = <&gcc SDC1_CL
301 clock-names = "mclk",
302 bus-width = <8>;
303 max-frequency = <96000
304 non-removable;
305 cap-sd-highspeed;
306 cap-mmc-highspeed;
307 vmmc-supply = <&vsdcc_
308 };
309
310 tcsr: syscon@1a400000 {
311 compatible = "qcom,tcs
312 reg = <0x1a400000 0x10
313 };
314
315 gsbi1: gsbi@16000000 {
316 compatible = "qcom,gsb
317 cell-index = <1>;
318 reg = <0x16000000 0x10
319 clocks = <&gcc GSBI1_H
320 clock-names = "iface";
321 #address-cells = <1>;
322 #size-cells = <1>;
323 ranges;
324
325 gsbi1_spi: spi@1608000
326 compatible = "
327 #address-cells
328 #size-cells =
329 reg = <0x16080
330 interrupts = <
331 cs-gpios = <&m
332
333 clocks = <&gcc
334 clock-names =
335 status = "disa
336 };
337 };
338
339 usb1: usb@12500000 {
340 compatible = "qcom,ci-
341 reg = <0x12500000 0x20
342 <0x12500200 0x20
343 interrupts = <GIC_SPI
344 clocks = <&gcc USB_HS1
345 clock-names = "core",
346 assigned-clocks = <&gc
347 assigned-clock-rates =
348 resets = <&gcc USB_HS1
349 reset-names = "core";
350 phy_type = "ulpi";
351 ahb-burst-config = <0>
352 phys = <&usb_hs1_phy>;
353 phy-names = "usb-phy";
354 #reset-cells = <1>;
355 status = "disabled";
356
357 ulpi {
358 usb_hs1_phy: p
359 compat
360
361 clocks
362 clock-
363 resets
364 reset-
365 #phy-c
366 };
367 };
368 };
369
370 gsbi3: gsbi@16200000 {
371 compatible = "qcom,gsb
372 reg = <0x16200000 0x10
373 ranges;
374 cell-index = <3>;
375 clocks = <&gcc GSBI3_H
376 clock-names = "iface";
377 #address-cells = <1>;
378 #size-cells = <1>;
379 status = "disabled";
380
381 gsbi3_i2c: i2c@1628000
382 compatible = "
383 reg = <0x16280
384 pinctrl-0 = <&
385 pinctrl-1 = <&
386 pinctrl-names
387 interrupts = <
388 clocks = <&gcc
389 <&gcc
390 clock-names =
391 #address-cells
392 #size-cells =
393 status = "disa
394 };
395 };
396 };
397 };
398 #include "qcom-msm8960-pins.dtsi"
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