1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/interrupt-controller/arm 4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h 5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h 7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h> 8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h> 9 #include <dt-bindings/soc/qcom,gsbi.h>
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 model = "Qualcomm MSM8960"; 14 model = "Qualcomm MSM8960";
15 compatible = "qcom,msm8960"; 15 compatible = "qcom,msm8960";
16 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
17 17
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304 21 interrupts = <GIC_PPI 14 0x304>;
22 22
23 cpu@0 { 23 cpu@0 {
24 compatible = "qcom,kra 24 compatible = "qcom,krait";
25 enable-method = "qcom, 25 enable-method = "qcom,kpss-acc-v1";
26 device_type = "cpu"; 26 device_type = "cpu";
27 reg = <0>; 27 reg = <0>;
28 next-level-cache = <&L 28 next-level-cache = <&L2>;
29 qcom,acc = <&acc0>; 29 qcom,acc = <&acc0>;
30 qcom,saw = <&saw0>; 30 qcom,saw = <&saw0>;
31 }; 31 };
32 32
33 cpu@1 { 33 cpu@1 {
34 compatible = "qcom,kra 34 compatible = "qcom,krait";
35 enable-method = "qcom, 35 enable-method = "qcom,kpss-acc-v1";
36 device_type = "cpu"; 36 device_type = "cpu";
37 reg = <1>; 37 reg = <1>;
38 next-level-cache = <&L 38 next-level-cache = <&L2>;
39 qcom,acc = <&acc1>; 39 qcom,acc = <&acc1>;
40 qcom,saw = <&saw1>; 40 qcom,saw = <&saw1>;
41 }; 41 };
42 42
43 L2: l2-cache { 43 L2: l2-cache {
44 compatible = "cache"; 44 compatible = "cache";
45 cache-level = <2>; 45 cache-level = <2>;
46 cache-unified; 46 cache-unified;
47 }; 47 };
48 }; 48 };
49 49
50 memory@80000000 { !! 50 memory {
51 device_type = "memory"; 51 device_type = "memory";
52 reg = <0x80000000 0>; !! 52 reg = <0x0 0x0>;
53 }; 53 };
54 54
55 cpu-pmu { 55 cpu-pmu {
56 compatible = "qcom,krait-pmu"; 56 compatible = "qcom,krait-pmu";
57 interrupts = <GIC_PPI 10 0x304 57 interrupts = <GIC_PPI 10 0x304>;
58 qcom,no-pc-write; 58 qcom,no-pc-write;
59 }; 59 };
60 60
61 clocks { 61 clocks {
62 cxo_board: cxo_board { 62 cxo_board: cxo_board {
63 compatible = "fixed-cl 63 compatible = "fixed-clock";
64 #clock-cells = <0>; 64 #clock-cells = <0>;
65 clock-frequency = <192 65 clock-frequency = <19200000>;
66 clock-output-names = " 66 clock-output-names = "cxo_board";
67 }; 67 };
68 68
69 pxo_board: pxo_board { 69 pxo_board: pxo_board {
70 compatible = "fixed-cl 70 compatible = "fixed-clock";
71 #clock-cells = <0>; 71 #clock-cells = <0>;
72 clock-frequency = <270 72 clock-frequency = <27000000>;
73 clock-output-names = " 73 clock-output-names = "pxo_board";
74 }; 74 };
75 75
76 sleep_clk: sleep_clk { 76 sleep_clk: sleep_clk {
77 compatible = "fixed-cl 77 compatible = "fixed-clock";
78 #clock-cells = <0>; 78 #clock-cells = <0>;
79 clock-frequency = <327 79 clock-frequency = <32768>;
80 clock-output-names = " 80 clock-output-names = "sleep_clk";
81 }; 81 };
82 }; 82 };
83 83
84 /* Temporary fixed regulator */ 84 /* Temporary fixed regulator */
85 vsdcc_fixed: vsdcc-regulator { 85 vsdcc_fixed: vsdcc-regulator {
86 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
87 regulator-name = "SDCC Power"; 87 regulator-name = "SDCC Power";
88 regulator-min-microvolt = <270 88 regulator-min-microvolt = <2700000>;
89 regulator-max-microvolt = <270 89 regulator-max-microvolt = <2700000>;
90 regulator-always-on; 90 regulator-always-on;
91 }; 91 };
92 92
93 soc: soc { 93 soc: soc {
94 #address-cells = <1>; 94 #address-cells = <1>;
95 #size-cells = <1>; 95 #size-cells = <1>;
96 ranges; 96 ranges;
97 compatible = "simple-bus"; 97 compatible = "simple-bus";
98 98
99 intc: interrupt-controller@200 99 intc: interrupt-controller@2000000 {
100 compatible = "qcom,msm 100 compatible = "qcom,msm-qgic2";
101 interrupt-controller; 101 interrupt-controller;
102 #interrupt-cells = <3> 102 #interrupt-cells = <3>;
103 reg = <0x02000000 0x10 103 reg = <0x02000000 0x1000>,
104 <0x02002000 0x10 104 <0x02002000 0x1000>;
105 }; 105 };
106 106
107 timer@200a000 { 107 timer@200a000 {
108 compatible = "qcom,kps 108 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
109 "qcom,msm 109 "qcom,msm-timer";
110 interrupts = <GIC_PPI 110 interrupts = <GIC_PPI 1 0x301>,
111 <GIC_PPI 111 <GIC_PPI 2 0x301>,
112 <GIC_PPI 112 <GIC_PPI 3 0x301>;
113 reg = <0x0200a000 0x10 113 reg = <0x0200a000 0x100>;
114 clock-frequency = <270 114 clock-frequency = <27000000>;
115 cpu-offset = <0x80000> 115 cpu-offset = <0x80000>;
116 }; 116 };
117 117
118 msmgpio: pinctrl@800000 { 118 msmgpio: pinctrl@800000 {
119 compatible = "qcom,msm 119 compatible = "qcom,msm8960-pinctrl";
120 gpio-controller; 120 gpio-controller;
121 gpio-ranges = <&msmgpi 121 gpio-ranges = <&msmgpio 0 0 152>;
122 #gpio-cells = <2>; 122 #gpio-cells = <2>;
123 interrupts = <GIC_SPI 123 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-controller; 124 interrupt-controller;
125 #interrupt-cells = <2> 125 #interrupt-cells = <2>;
126 reg = <0x800000 0x4000 126 reg = <0x800000 0x4000>;
127 }; 127 };
128 128
129 gcc: clock-controller@900000 { 129 gcc: clock-controller@900000 {
130 compatible = "qcom,gcc 130 compatible = "qcom,gcc-msm8960";
131 #clock-cells = <1>; 131 #clock-cells = <1>;
>> 132 #power-domain-cells = <1>;
132 #reset-cells = <1>; 133 #reset-cells = <1>;
133 reg = <0x900000 0x4000 134 reg = <0x900000 0x4000>;
134 clocks = <&cxo_board>, 135 clocks = <&cxo_board>,
135 <&pxo_board>, 136 <&pxo_board>,
136 <&lcc PLL4>; 137 <&lcc PLL4>;
137 clock-names = "cxo", " 138 clock-names = "cxo", "pxo", "pll4";
138 }; 139 };
139 140
140 lcc: clock-controller@28000000 141 lcc: clock-controller@28000000 {
141 compatible = "qcom,lcc 142 compatible = "qcom,lcc-msm8960";
142 reg = <0x28000000 0x10 143 reg = <0x28000000 0x1000>;
143 #clock-cells = <1>; 144 #clock-cells = <1>;
144 #reset-cells = <1>; 145 #reset-cells = <1>;
145 clocks = <&pxo_board>, 146 clocks = <&pxo_board>,
146 <&gcc PLL4_VO 147 <&gcc PLL4_VOTE>,
147 <0>, 148 <0>,
148 <0>, <0>, 149 <0>, <0>,
149 <0>, <0>, 150 <0>, <0>,
150 <0>; 151 <0>;
151 clock-names = "pxo", 152 clock-names = "pxo",
152 "pll4_vo 153 "pll4_vote",
153 "mi2s_co 154 "mi2s_codec_clk",
154 "codec_i 155 "codec_i2s_mic_codec_clk",
155 "spare_i 156 "spare_i2s_mic_codec_clk",
156 "codec_i 157 "codec_i2s_spkr_codec_clk",
157 "spare_i 158 "spare_i2s_spkr_codec_clk",
158 "pcm_cod 159 "pcm_codec_clk";
159 }; 160 };
160 161
161 clock-controller@4000000 { 162 clock-controller@4000000 {
162 compatible = "qcom,mmc 163 compatible = "qcom,mmcc-msm8960";
163 reg = <0x4000000 0x100 164 reg = <0x4000000 0x1000>;
164 #clock-cells = <1>; 165 #clock-cells = <1>;
165 #power-domain-cells = 166 #power-domain-cells = <1>;
166 #reset-cells = <1>; 167 #reset-cells = <1>;
167 clocks = <&pxo_board>, 168 clocks = <&pxo_board>,
168 <&gcc PLL3>, 169 <&gcc PLL3>,
169 <&gcc PLL8_VO 170 <&gcc PLL8_VOTE>,
170 <0>, 171 <0>,
171 <0>, 172 <0>,
172 <0>, 173 <0>,
173 <0>, 174 <0>,
174 <0>; 175 <0>;
175 clock-names = "pxo", 176 clock-names = "pxo",
176 "pll3", 177 "pll3",
177 "pll8_vo 178 "pll8_vote",
178 "dsi1pll 179 "dsi1pll",
179 "dsi1pll 180 "dsi1pllbyte",
180 "dsi2pll 181 "dsi2pll",
181 "dsi2pll 182 "dsi2pllbyte",
182 "hdmipll 183 "hdmipll";
183 }; 184 };
184 185
185 l2cc: clock-controller@2011000 186 l2cc: clock-controller@2011000 {
186 compatible = "qcom,kps 187 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
187 reg = <0x2011000 0x100 188 reg = <0x2011000 0x1000>;
188 clocks = <&gcc PLL8_VO 189 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
189 clock-names = "pll8_vo 190 clock-names = "pll8_vote", "pxo";
190 #clock-cells = <0>; 191 #clock-cells = <0>;
191 }; 192 };
192 193
193 rpm: rpm@108000 { 194 rpm: rpm@108000 {
194 compatible = "qcom,rpm 195 compatible = "qcom,rpm-msm8960";
195 reg = <0x108000 0x1000 196 reg = <0x108000 0x1000>;
196 qcom,ipc = <&l2cc 0x8 197 qcom,ipc = <&l2cc 0x8 2>;
197 198
198 interrupts = <GIC_SPI 199 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
199 <GIC_SPI 200 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
200 <GIC_SPI 201 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
201 interrupt-names = "ack 202 interrupt-names = "ack", "err", "wakeup";
202 }; 203 };
203 204
204 acc0: clock-controller@2088000 205 acc0: clock-controller@2088000 {
205 compatible = "qcom,kps 206 compatible = "qcom,kpss-acc-v1";
206 reg = <0x02088000 0x10 207 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
207 clocks = <&gcc PLL8_VO 208 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
208 clock-names = "pll8_vo 209 clock-names = "pll8_vote", "pxo";
209 clock-output-names = " 210 clock-output-names = "acpu0_aux";
210 #clock-cells = <0>; 211 #clock-cells = <0>;
211 }; 212 };
212 213
213 acc1: clock-controller@2098000 214 acc1: clock-controller@2098000 {
214 compatible = "qcom,kps 215 compatible = "qcom,kpss-acc-v1";
215 reg = <0x02098000 0x10 216 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
216 clocks = <&gcc PLL8_VO 217 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
217 clock-names = "pll8_vo 218 clock-names = "pll8_vote", "pxo";
218 clock-output-names = " 219 clock-output-names = "acpu1_aux";
219 #clock-cells = <0>; 220 #clock-cells = <0>;
220 }; 221 };
221 222
222 saw0: power-manager@2089000 { 223 saw0: power-manager@2089000 {
223 compatible = "qcom,msm 224 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
224 reg = <0x02089000 0x10 225 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
225 226
226 saw0_vreg: regulator { 227 saw0_vreg: regulator {
227 regulator-min- 228 regulator-min-microvolt = <850000>;
228 regulator-max- 229 regulator-max-microvolt = <1300000>;
229 }; 230 };
230 }; 231 };
231 232
232 saw1: power-manager@2099000 { 233 saw1: power-manager@2099000 {
233 compatible = "qcom,msm 234 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
234 reg = <0x02099000 0x10 235 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
235 236
236 saw1_vreg: regulator { 237 saw1_vreg: regulator {
237 regulator-min- 238 regulator-min-microvolt = <850000>;
238 regulator-max- 239 regulator-max-microvolt = <1300000>;
239 }; 240 };
240 }; 241 };
241 242
242 gsbi5: gsbi@16400000 { 243 gsbi5: gsbi@16400000 {
243 compatible = "qcom,gsb 244 compatible = "qcom,gsbi-v1.0.0";
244 cell-index = <5>; 245 cell-index = <5>;
245 reg = <0x16400000 0x10 246 reg = <0x16400000 0x100>;
246 clocks = <&gcc GSBI5_H 247 clocks = <&gcc GSBI5_H_CLK>;
247 clock-names = "iface"; 248 clock-names = "iface";
248 #address-cells = <1>; 249 #address-cells = <1>;
249 #size-cells = <1>; 250 #size-cells = <1>;
250 ranges; 251 ranges;
251 252
252 syscon-tcsr = <&tcsr>; 253 syscon-tcsr = <&tcsr>;
253 254
254 gsbi5_serial: serial@1 255 gsbi5_serial: serial@16440000 {
255 compatible = " 256 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
256 reg = <0x16440 257 reg = <0x16440000 0x1000>,
257 <0x16400 258 <0x16400000 0x1000>;
258 interrupts = < 259 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&gcc 260 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
260 clock-names = 261 clock-names = "core", "iface";
261 status = "disa 262 status = "disabled";
262 }; 263 };
263 }; 264 };
264 265
265 ssbi: ssbi@500000 { 266 ssbi: ssbi@500000 {
266 compatible = "qcom,ssb 267 compatible = "qcom,ssbi";
267 reg = <0x500000 0x1000 268 reg = <0x500000 0x1000>;
268 qcom,controller-type = 269 qcom,controller-type = "pmic-arbiter";
269 }; 270 };
270 271
271 rng@1a500000 { 272 rng@1a500000 {
272 compatible = "qcom,prn 273 compatible = "qcom,prng";
273 reg = <0x1a500000 0x20 274 reg = <0x1a500000 0x200>;
274 clocks = <&gcc PRNG_CL 275 clocks = <&gcc PRNG_CLK>;
275 clock-names = "core"; 276 clock-names = "core";
276 }; 277 };
277 278
278 sdcc3: mmc@12180000 { 279 sdcc3: mmc@12180000 {
279 compatible = "arm,pl18 280 compatible = "arm,pl18x", "arm,primecell";
280 arm,primecell-periphid 281 arm,primecell-periphid = <0x00051180>;
281 status = "disabled"; 282 status = "disabled";
282 reg = <0x12180000 0x80 283 reg = <0x12180000 0x8000>;
283 interrupts = <GIC_SPI 284 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&gcc SDC3_CL 285 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
285 clock-names = "mclk", 286 clock-names = "mclk", "apb_pclk";
286 bus-width = <4>; 287 bus-width = <4>;
287 cap-sd-highspeed; 288 cap-sd-highspeed;
288 cap-mmc-highspeed; 289 cap-mmc-highspeed;
289 max-frequency = <19200 290 max-frequency = <192000000>;
290 no-1-8-v; 291 no-1-8-v;
291 vmmc-supply = <&vsdcc_ 292 vmmc-supply = <&vsdcc_fixed>;
292 }; 293 };
293 294
294 sdcc1: mmc@12400000 { 295 sdcc1: mmc@12400000 {
295 status = "disabled"; 296 status = "disabled";
296 compatible = "arm,pl18 297 compatible = "arm,pl18x", "arm,primecell";
297 arm,primecell-periphid 298 arm,primecell-periphid = <0x00051180>;
298 reg = <0x12400000 0x80 299 reg = <0x12400000 0x8000>;
299 interrupts = <GIC_SPI 300 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&gcc SDC1_CL 301 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
301 clock-names = "mclk", 302 clock-names = "mclk", "apb_pclk";
302 bus-width = <8>; 303 bus-width = <8>;
303 max-frequency = <96000 304 max-frequency = <96000000>;
304 non-removable; 305 non-removable;
305 cap-sd-highspeed; 306 cap-sd-highspeed;
306 cap-mmc-highspeed; 307 cap-mmc-highspeed;
307 vmmc-supply = <&vsdcc_ 308 vmmc-supply = <&vsdcc_fixed>;
308 }; 309 };
309 310
310 tcsr: syscon@1a400000 { 311 tcsr: syscon@1a400000 {
311 compatible = "qcom,tcs 312 compatible = "qcom,tcsr-msm8960", "syscon";
312 reg = <0x1a400000 0x10 313 reg = <0x1a400000 0x100>;
313 }; 314 };
314 315
315 gsbi1: gsbi@16000000 { 316 gsbi1: gsbi@16000000 {
316 compatible = "qcom,gsb 317 compatible = "qcom,gsbi-v1.0.0";
317 cell-index = <1>; 318 cell-index = <1>;
318 reg = <0x16000000 0x10 319 reg = <0x16000000 0x100>;
319 clocks = <&gcc GSBI1_H 320 clocks = <&gcc GSBI1_H_CLK>;
320 clock-names = "iface"; 321 clock-names = "iface";
321 #address-cells = <1>; 322 #address-cells = <1>;
322 #size-cells = <1>; 323 #size-cells = <1>;
323 ranges; 324 ranges;
324 325
325 gsbi1_spi: spi@1608000 326 gsbi1_spi: spi@16080000 {
326 compatible = " 327 compatible = "qcom,spi-qup-v1.1.1";
327 #address-cells 328 #address-cells = <1>;
328 #size-cells = 329 #size-cells = <0>;
329 reg = <0x16080 330 reg = <0x16080000 0x1000>;
330 interrupts = < 331 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
331 cs-gpios = <&m 332 cs-gpios = <&msmgpio 8 0>;
332 333
333 clocks = <&gcc 334 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
334 clock-names = 335 clock-names = "core", "iface";
335 status = "disa 336 status = "disabled";
336 }; 337 };
337 }; 338 };
338 339
339 usb1: usb@12500000 { 340 usb1: usb@12500000 {
340 compatible = "qcom,ci- 341 compatible = "qcom,ci-hdrc";
341 reg = <0x12500000 0x20 342 reg = <0x12500000 0x200>,
342 <0x12500200 0x20 343 <0x12500200 0x200>;
343 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&gcc USB_HS1 345 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
345 clock-names = "core", 346 clock-names = "core", "iface";
346 assigned-clocks = <&gc 347 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
347 assigned-clock-rates = 348 assigned-clock-rates = <60000000>;
348 resets = <&gcc USB_HS1 349 resets = <&gcc USB_HS1_RESET>;
349 reset-names = "core"; 350 reset-names = "core";
350 phy_type = "ulpi"; 351 phy_type = "ulpi";
351 ahb-burst-config = <0> 352 ahb-burst-config = <0>;
352 phys = <&usb_hs1_phy>; 353 phys = <&usb_hs1_phy>;
353 phy-names = "usb-phy"; 354 phy-names = "usb-phy";
354 #reset-cells = <1>; 355 #reset-cells = <1>;
355 status = "disabled"; 356 status = "disabled";
356 357
357 ulpi { 358 ulpi {
358 usb_hs1_phy: p 359 usb_hs1_phy: phy {
359 compat 360 compatible = "qcom,usb-hs-phy-msm8960",
360 361 "qcom,usb-hs-phy";
361 clocks 362 clocks = <&sleep_clk>, <&cxo_board>;
362 clock- 363 clock-names = "sleep", "ref";
363 resets 364 resets = <&usb1 0>;
364 reset- 365 reset-names = "por";
365 #phy-c 366 #phy-cells = <0>;
366 }; 367 };
367 }; 368 };
368 }; 369 };
369 370
370 gsbi3: gsbi@16200000 { 371 gsbi3: gsbi@16200000 {
371 compatible = "qcom,gsb 372 compatible = "qcom,gsbi-v1.0.0";
372 reg = <0x16200000 0x10 373 reg = <0x16200000 0x100>;
373 ranges; 374 ranges;
374 cell-index = <3>; 375 cell-index = <3>;
375 clocks = <&gcc GSBI3_H 376 clocks = <&gcc GSBI3_H_CLK>;
376 clock-names = "iface"; 377 clock-names = "iface";
377 #address-cells = <1>; 378 #address-cells = <1>;
378 #size-cells = <1>; 379 #size-cells = <1>;
379 status = "disabled"; 380 status = "disabled";
380 381
381 gsbi3_i2c: i2c@1628000 382 gsbi3_i2c: i2c@16280000 {
382 compatible = " 383 compatible = "qcom,i2c-qup-v1.1.1";
383 reg = <0x16280 384 reg = <0x16280000 0x1000>;
384 pinctrl-0 = <& 385 pinctrl-0 = <&i2c3_default_state>;
385 pinctrl-1 = <& 386 pinctrl-1 = <&i2c3_sleep_state>;
386 pinctrl-names 387 pinctrl-names = "default", "sleep";
387 interrupts = < 388 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&gcc 389 clocks = <&gcc GSBI3_QUP_CLK>,
389 <&gcc 390 <&gcc GSBI3_H_CLK>;
390 clock-names = 391 clock-names = "core", "iface";
391 #address-cells 392 #address-cells = <1>;
392 #size-cells = 393 #size-cells = <0>;
393 status = "disa 394 status = "disabled";
394 }; 395 };
395 }; 396 };
396 }; 397 };
397 }; 398 };
398 #include "qcom-msm8960-pins.dtsi" 399 #include "qcom-msm8960-pins.dtsi"
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