1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/interconnect/qcom,msm897
5 #include <dt-bindings/interrupt-controller/arm
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h
10 #include <dt-bindings/gpio/gpio.h>
11
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&intc>;
16
17 chosen { };
18
19 clocks {
20 xo_board: xo_board {
21 compatible = "fixed-cl
22 #clock-cells = <0>;
23 clock-frequency = <192
24 };
25
26 sleep_clk: sleep_clk {
27 compatible = "fixed-cl
28 #clock-cells = <0>;
29 clock-frequency = <327
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 interrupts = <GIC_PPI 9 (GIC_C
37
38 CPU0: cpu@0 {
39 compatible = "qcom,kra
40 enable-method = "qcom,
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L
44 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CP
47 };
48
49 CPU1: cpu@1 {
50 compatible = "qcom,kra
51 enable-method = "qcom,
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L
55 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CP
58 };
59
60 CPU2: cpu@2 {
61 compatible = "qcom,kra
62 enable-method = "qcom,
63 device_type = "cpu";
64 reg = <2>;
65 next-level-cache = <&L
66 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CP
69 };
70
71 CPU3: cpu@3 {
72 compatible = "qcom,kra
73 enable-method = "qcom,
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CP
80 };
81
82 L2: l2-cache {
83 compatible = "cache";
84 cache-level = <2>;
85 cache-unified;
86 qcom,saw = <&saw_l2>;
87 };
88
89 idle-states {
90 CPU_SPC: cpu-spc {
91 compatible = "
92
93 entry-latency-
94 exit-latency-u
95 min-residency-
96 };
97 };
98 };
99
100 firmware {
101 scm {
102 compatible = "qcom,scm
103 clocks = <&gcc GCC_CE1
104 clock-names = "core",
105 };
106 };
107
108 memory@0 {
109 device_type = "memory";
110 reg = <0x0 0x0>;
111 };
112
113 pmu {
114 compatible = "qcom,krait-pmu";
115 interrupts = <GIC_PPI 7 (GIC_C
116 };
117
118 rpm: remoteproc {
119 compatible = "qcom,msm8974-rpm
120
121 master-stats {
122 compatible = "qcom,rpm
123 qcom,rpm-msg-ram = <&a
124 <&m
125 <&l
126 <&p
127 qcom,master-names = "A
128 "M
129 "L
130 "P
131 };
132
133 smd-edge {
134 interrupts = <GIC_SPI
135 mboxes = <&apcs 0>;
136 qcom,smd-edge = <15>;
137
138 rpm_requests: rpm-requ
139 compatible = "
140 qcom,smd-chann
141
142 rpmcc: clock-c
143 compat
144 #clock
145 clocks
146 clock-
147 };
148 };
149 };
150 };
151
152 reserved_memory: reserved-memory {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges;
156
157 mpss_region: mpss@8000000 {
158 reg = <0x08000000 0x51
159 no-map;
160 };
161
162 mba_region: mba@d100000 {
163 reg = <0x0d100000 0x10
164 no-map;
165 };
166
167 wcnss_region: wcnss@d200000 {
168 reg = <0x0d200000 0xa0
169 no-map;
170 };
171
172 adsp_region: adsp@dc00000 {
173 reg = <0x0dc00000 0x19
174 no-map;
175 };
176
177 venus_region: memory@f500000 {
178 reg = <0x0f500000 0x50
179 no-map;
180 };
181
182 smem_region: smem@fa00000 {
183 reg = <0xfa00000 0x200
184 no-map;
185 };
186
187 tz_region: memory@fc00000 {
188 reg = <0x0fc00000 0x16
189 no-map;
190 };
191
192 rfsa_mem: memory@fd60000 {
193 reg = <0x0fd60000 0x20
194 no-map;
195 };
196
197 rmtfs@fd80000 {
198 compatible = "qcom,rmt
199 reg = <0x0fd80000 0x18
200 no-map;
201
202 qcom,client-id = <1>;
203 };
204 };
205
206 smem {
207 compatible = "qcom,smem";
208
209 memory-region = <&smem_region>
210 qcom,rpm-msg-ram = <&rpm_msg_r
211
212 hwlocks = <&tcsr_mutex 3>;
213 };
214
215 smp2p-adsp {
216 compatible = "qcom,smp2p";
217 qcom,smem = <443>, <429>;
218
219 interrupt-parent = <&intc>;
220 interrupts = <GIC_SPI 158 IRQ_
221
222 mboxes = <&apcs 10>;
223
224 qcom,local-pid = <0>;
225 qcom,remote-pid = <2>;
226
227 adsp_smp2p_out: master-kernel
228 qcom,entry-name = "mas
229 #qcom,smem-state-cells
230 };
231
232 adsp_smp2p_in: slave-kernel {
233 qcom,entry-name = "sla
234
235 interrupt-controller;
236 #interrupt-cells = <2>
237 };
238 };
239
240 smp2p-modem {
241 compatible = "qcom,smp2p";
242 qcom,smem = <435>, <428>;
243
244 interrupt-parent = <&intc>;
245 interrupts = <GIC_SPI 27 IRQ_T
246
247 mboxes = <&apcs 14>;
248
249 qcom,local-pid = <0>;
250 qcom,remote-pid = <1>;
251
252 modem_smp2p_out: master-kernel
253 qcom,entry-name = "mas
254 #qcom,smem-state-cells
255 };
256
257 modem_smp2p_in: slave-kernel {
258 qcom,entry-name = "sla
259
260 interrupt-controller;
261 #interrupt-cells = <2>
262 };
263 };
264
265 smp2p-wcnss {
266 compatible = "qcom,smp2p";
267 qcom,smem = <451>, <431>;
268
269 interrupt-parent = <&intc>;
270 interrupts = <GIC_SPI 143 IRQ_
271
272 mboxes = <&apcs 18>;
273
274 qcom,local-pid = <0>;
275 qcom,remote-pid = <4>;
276
277 wcnss_smp2p_out: master-kernel
278 qcom,entry-name = "mas
279
280 #qcom,smem-state-cells
281 };
282
283 wcnss_smp2p_in: slave-kernel {
284 qcom,entry-name = "sla
285
286 interrupt-controller;
287 #interrupt-cells = <2>
288 };
289 };
290
291 smsm {
292 compatible = "qcom,smsm";
293
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 mboxes = <0>, <&apcs 13>, <&ap
298
299 apps_smsm: apps@0 {
300 reg = <0>;
301
302 #qcom,smem-state-cells
303 };
304
305 modem_smsm: modem@1 {
306 reg = <1>;
307 interrupts = <GIC_SPI
308
309 interrupt-controller;
310 #interrupt-cells = <2>
311 };
312
313 adsp_smsm: adsp@2 {
314 reg = <2>;
315 interrupts = <GIC_SPI
316
317 interrupt-controller;
318 #interrupt-cells = <2>
319 };
320
321 wcnss_smsm: wcnss@7 {
322 reg = <7>;
323 interrupts = <GIC_SPI
324
325 interrupt-controller;
326 #interrupt-cells = <2>
327 };
328 };
329
330 soc: soc {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334 compatible = "simple-bus";
335
336 intc: interrupt-controller@f90
337 compatible = "qcom,msm
338 interrupt-controller;
339 #interrupt-cells = <3>
340 reg = <0xf9000000 0x10
341 <0xf9002000 0x10
342 };
343
344 apcs: mailbox@f9011000 {
345 compatible = "qcom,msm
346 "qcom,msm
347 reg = <0xf9011000 0x10
348 #mbox-cells = <1>;
349 };
350
351 saw_l2: power-manager@f9012000
352 compatible = "qcom,msm
353 reg = <0xf9012000 0x10
354 };
355
356 watchdog@f9017000 {
357 compatible = "qcom,aps
358 reg = <0xf9017000 0x10
359 interrupts = <GIC_SPI
360 <GIC_SPI
361 clocks = <&sleep_clk>;
362 };
363
364 timer@f9020000 {
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges;
368 compatible = "arm,armv
369 reg = <0xf9020000 0x10
370 clock-frequency = <192
371
372 frame@f9021000 {
373 frame-number =
374 interrupts = <
375 <
376 reg = <0xf9021
377 <0xf9022
378 };
379
380 frame@f9023000 {
381 frame-number =
382 interrupts = <
383 reg = <0xf9023
384 status = "disa
385 };
386
387 frame@f9024000 {
388 frame-number =
389 interrupts = <
390 reg = <0xf9024
391 status = "disa
392 };
393
394 frame@f9025000 {
395 frame-number =
396 interrupts = <
397 reg = <0xf9025
398 status = "disa
399 };
400
401 frame@f9026000 {
402 frame-number =
403 interrupts = <
404 reg = <0xf9026
405 status = "disa
406 };
407
408 frame@f9027000 {
409 frame-number =
410 interrupts = <
411 reg = <0xf9027
412 status = "disa
413 };
414
415 frame@f9028000 {
416 frame-number =
417 interrupts = <
418 reg = <0xf9028
419 status = "disa
420 };
421 };
422
423 acc0: power-manager@f9088000 {
424 compatible = "qcom,kps
425 reg = <0xf9088000 0x10
426 };
427
428 saw0: power-manager@f9089000 {
429 compatible = "qcom,msm
430 reg = <0xf9089000 0x10
431 };
432
433 acc1: power-manager@f9098000 {
434 compatible = "qcom,kps
435 reg = <0xf9098000 0x10
436 };
437
438 saw1: power-manager@f9099000 {
439 compatible = "qcom,msm
440 reg = <0xf9099000 0x10
441 };
442
443 acc2: power-manager@f90a8000 {
444 compatible = "qcom,kps
445 reg = <0xf90a8000 0x10
446 };
447
448 saw2: power-manager@f90a9000 {
449 compatible = "qcom,msm
450 reg = <0xf90a9000 0x10
451 };
452
453 acc3: power-manager@f90b8000 {
454 compatible = "qcom,kps
455 reg = <0xf90b8000 0x10
456 };
457
458 saw3: power-manager@f90b9000 {
459 compatible = "qcom,msm
460 reg = <0xf90b9000 0x10
461 };
462
463 sdhc_1: mmc@f9824900 {
464 compatible = "qcom,msm
465 reg = <0xf9824900 0x11
466 reg-names = "hc", "cor
467 interrupts = <GIC_SPI
468 <GIC_SPI
469 interrupt-names = "hc_
470 clocks = <&gcc GCC_SDC
471 <&gcc GCC_SDC
472 <&xo_board>;
473 clock-names = "iface",
474 bus-width = <8>;
475 non-removable;
476
477 status = "disabled";
478 };
479
480 sdhc_3: mmc@f9864900 {
481 compatible = "qcom,msm
482 reg = <0xf9864900 0x11
483 reg-names = "hc", "cor
484 interrupts = <GIC_SPI
485 <GIC_SPI
486 interrupt-names = "hc_
487 clocks = <&gcc GCC_SDC
488 <&gcc GCC_SDC
489 <&xo_board>;
490 clock-names = "iface",
491 bus-width = <4>;
492
493 #address-cells = <1>;
494 #size-cells = <0>;
495
496 status = "disabled";
497 };
498
499 sdhc_2: mmc@f98a4900 {
500 compatible = "qcom,msm
501 reg = <0xf98a4900 0x11
502 reg-names = "hc", "cor
503 interrupts = <GIC_SPI
504 <GIC_SPI
505 interrupt-names = "hc_
506 clocks = <&gcc GCC_SDC
507 <&gcc GCC_SDC
508 <&xo_board>;
509 clock-names = "iface",
510 bus-width = <4>;
511
512 #address-cells = <1>;
513 #size-cells = <0>;
514
515 status = "disabled";
516 };
517
518 blsp1_uart1: serial@f991d000 {
519 compatible = "qcom,msm
520 reg = <0xf991d000 0x10
521 interrupts = <GIC_SPI
522 clocks = <&gcc GCC_BLS
523 clock-names = "core",
524 status = "disabled";
525 };
526
527 blsp1_uart2: serial@f991e000 {
528 compatible = "qcom,msm
529 reg = <0xf991e000 0x10
530 interrupts = <GIC_SPI
531 clocks = <&gcc GCC_BLS
532 clock-names = "core",
533 pinctrl-names = "defau
534 pinctrl-0 = <&blsp1_ua
535 status = "disabled";
536 };
537
538 blsp1_i2c1: i2c@f9923000 {
539 status = "disabled";
540 compatible = "qcom,i2c
541 reg = <0xf9923000 0x10
542 interrupts = <GIC_SPI
543 clocks = <&gcc GCC_BLS
544 clock-names = "core",
545 pinctrl-names = "defau
546 pinctrl-0 = <&blsp1_i2
547 pinctrl-1 = <&blsp1_i2
548 #address-cells = <1>;
549 #size-cells = <0>;
550 };
551
552 blsp1_i2c2: i2c@f9924000 {
553 status = "disabled";
554 compatible = "qcom,i2c
555 reg = <0xf9924000 0x10
556 interrupts = <GIC_SPI
557 clocks = <&gcc GCC_BLS
558 clock-names = "core",
559 pinctrl-names = "defau
560 pinctrl-0 = <&blsp1_i2
561 pinctrl-1 = <&blsp1_i2
562 #address-cells = <1>;
563 #size-cells = <0>;
564 };
565
566 blsp1_i2c3: i2c@f9925000 {
567 status = "disabled";
568 compatible = "qcom,i2c
569 reg = <0xf9925000 0x10
570 interrupts = <GIC_SPI
571 clocks = <&gcc GCC_BLS
572 clock-names = "core",
573 pinctrl-names = "defau
574 pinctrl-0 = <&blsp1_i2
575 pinctrl-1 = <&blsp1_i2
576 #address-cells = <1>;
577 #size-cells = <0>;
578 };
579
580 blsp1_i2c6: i2c@f9928000 {
581 status = "disabled";
582 compatible = "qcom,i2c
583 reg = <0xf9928000 0x10
584 interrupts = <GIC_SPI
585 clocks = <&gcc GCC_BLS
586 clock-names = "core",
587 pinctrl-names = "defau
588 pinctrl-0 = <&blsp1_i2
589 pinctrl-1 = <&blsp1_i2
590 #address-cells = <1>;
591 #size-cells = <0>;
592 };
593
594 blsp2_dma: dma-controller@f994
595 compatible = "qcom,bam
596 reg = <0xf9944000 0x19
597 interrupts = <GIC_SPI
598 clocks = <&gcc GCC_BLS
599 clock-names = "bam_clk
600 #dma-cells = <1>;
601 qcom,ee = <0>;
602 };
603
604 blsp2_uart1: serial@f995d000 {
605 compatible = "qcom,msm
606 reg = <0xf995d000 0x10
607 interrupts = <GIC_SPI
608 clocks = <&gcc GCC_BLS
609 clock-names = "core",
610 pinctrl-names = "defau
611 pinctrl-0 = <&blsp2_ua
612 pinctrl-1 = <&blsp2_ua
613 status = "disabled";
614 };
615
616 blsp2_uart2: serial@f995e000 {
617 compatible = "qcom,msm
618 reg = <0xf995e000 0x10
619 interrupts = <GIC_SPI
620 clocks = <&gcc GCC_BLS
621 clock-names = "core",
622 status = "disabled";
623 };
624
625 blsp2_uart4: serial@f9960000 {
626 compatible = "qcom,msm
627 reg = <0xf9960000 0x10
628 interrupts = <GIC_SPI
629 clocks = <&gcc GCC_BLS
630 clock-names = "core",
631 pinctrl-names = "defau
632 pinctrl-0 = <&blsp2_ua
633 status = "disabled";
634 };
635
636 blsp2_i2c2: i2c@f9964000 {
637 status = "disabled";
638 compatible = "qcom,i2c
639 reg = <0xf9964000 0x10
640 interrupts = <GIC_SPI
641 clocks = <&gcc GCC_BLS
642 clock-names = "core",
643 pinctrl-names = "defau
644 pinctrl-0 = <&blsp2_i2
645 pinctrl-1 = <&blsp2_i2
646 #address-cells = <1>;
647 #size-cells = <0>;
648 };
649
650 blsp2_i2c5: i2c@f9967000 {
651 status = "disabled";
652 compatible = "qcom,i2c
653 reg = <0xf9967000 0x10
654 interrupts = <GIC_SPI
655 clocks = <&gcc GCC_BLS
656 clock-names = "core",
657 dmas = <&blsp2_dma 20>
658 dma-names = "tx", "rx"
659 pinctrl-names = "defau
660 pinctrl-0 = <&blsp2_i2
661 pinctrl-1 = <&blsp2_i2
662 #address-cells = <1>;
663 #size-cells = <0>;
664 };
665
666 blsp2_i2c6: i2c@f9968000 {
667 status = "disabled";
668 compatible = "qcom,i2c
669 reg = <0xf9968000 0x10
670 interrupts = <GIC_SPI
671 clocks = <&gcc GCC_BLS
672 clock-names = "core",
673 pinctrl-names = "defau
674 pinctrl-0 = <&blsp2_i2
675 pinctrl-1 = <&blsp2_i2
676 #address-cells = <1>;
677 #size-cells = <0>;
678 };
679
680 usb: usb@f9a55000 {
681 compatible = "qcom,ci-
682 reg = <0xf9a55000 0x20
683 <0xf9a55200 0x20
684 interrupts = <GIC_SPI
685 clocks = <&gcc GCC_USB
686 <&gcc GCC_USB
687 clock-names = "iface",
688 assigned-clocks = <&gc
689 assigned-clock-rates =
690 resets = <&gcc GCC_USB
691 reset-names = "core";
692 phy_type = "ulpi";
693 dr_mode = "otg";
694 ahb-burst-config = <0>
695 phy-names = "usb-phy";
696 status = "disabled";
697 #reset-cells = <1>;
698
699 ulpi {
700 usb_hs1_phy: p
701 compat
702
703 #phy-c
704 clocks
705 clock-
706 resets
707 reset-
708 status
709 };
710
711 usb_hs2_phy: p
712 compat
713
714 #phy-c
715 clocks
716 clock-
717 resets
718 reset-
719 status
720 };
721 };
722 };
723
724 rng@f9bff000 {
725 compatible = "qcom,prn
726 reg = <0xf9bff000 0x20
727 clocks = <&gcc GCC_PRN
728 clock-names = "core";
729 };
730
731 pronto: remoteproc@fb204000 {
732 compatible = "qcom,pro
733 reg = <0xfb204000 0x20
734 reg-names = "ccu", "dx
735
736 memory-region = <&wcns
737
738 interrupts-extended =
739
740
741
742
743 interrupt-names = "wdo
744
745 qcom,smem-states = <&w
746 qcom,smem-state-names
747
748 status = "disabled";
749
750 iris {
751 compatible = "
752
753 clocks = <&rpm
754 clock-names =
755 };
756
757 smd-edge {
758 interrupts = <
759
760 mboxes = <&apc
761 qcom,smd-edge
762
763 wcnss {
764 compat
765 qcom,s
766 status
767
768 qcom,m
769
770 blueto
771
772 };
773
774 wifi {
775
776
777
778
779
780
781
782
783
784 };
785 };
786 };
787 };
788
789 sram@fc190000 {
790 compatible = "qcom,msm
791 reg = <0xfc190000 0x10
792 };
793
794 etf@fc307000 {
795 compatible = "arm,core
796 reg = <0xfc307000 0x10
797
798 clocks = <&rpmcc RPM_S
799 clock-names = "apb_pcl
800
801 out-ports {
802 port {
803 etf_ou
804
805 };
806 };
807 };
808
809 in-ports {
810 port {
811 etf_in
812
813 };
814 };
815 };
816 };
817
818 tpiu@fc318000 {
819 compatible = "arm,core
820 reg = <0xfc318000 0x10
821
822 clocks = <&rpmcc RPM_S
823 clock-names = "apb_pcl
824
825 in-ports {
826 port {
827 tpiu_i
828
829 };
830 };
831 };
832 };
833
834 funnel@fc31a000 {
835 compatible = "arm,core
836 reg = <0xfc31a000 0x10
837
838 clocks = <&rpmcc RPM_S
839 clock-names = "apb_pcl
840
841 in-ports {
842 #address-cells
843 #size-cells =
844
845 /*
846 * Not describ
847 * 0 - not-con
848 * 1 - connect
849 * 2 - connect
850 * 3 - not-con
851 * 4 - not-con
852 * 6 - not-con
853 * 7 - connect
854 */
855 port@5 {
856 reg =
857 funnel
858
859 };
860 };
861 };
862
863 out-ports {
864 port {
865 funnel
866
867 };
868 };
869 };
870 };
871
872 funnel@fc31b000 {
873 compatible = "arm,core
874 reg = <0xfc31b000 0x10
875
876 clocks = <&rpmcc RPM_S
877 clock-names = "apb_pcl
878
879 in-ports {
880 #address-cells
881 #size-cells =
882
883 /*
884 * Not describ
885 * 0 - connect
886 * Resourc
887 * 2...7 - not
888 */
889 port@1 {
890 reg =
891 merger
892
893 };
894 };
895 };
896
897 out-ports {
898 port {
899 merger
900
901 };
902 };
903 };
904 };
905
906 replicator@fc31c000 {
907 compatible = "arm,core
908 reg = <0xfc31c000 0x10
909
910 clocks = <&rpmcc RPM_S
911 clock-names = "apb_pcl
912
913 out-ports {
914 #address-cells
915 #size-cells =
916
917 port@0 {
918 reg =
919 replic
920
921 };
922 };
923 port@1 {
924 reg =
925 replic
926
927 };
928 };
929 };
930
931 in-ports {
932 port {
933 replic
934
935 };
936 };
937 };
938 };
939
940 etr@fc322000 {
941 compatible = "arm,core
942 reg = <0xfc322000 0x10
943
944 clocks = <&rpmcc RPM_S
945 clock-names = "apb_pcl
946
947 in-ports {
948 port {
949 etr_in
950
951 };
952 };
953 };
954 };
955
956 etm@fc33c000 {
957 compatible = "arm,core
958 reg = <0xfc33c000 0x10
959
960 clocks = <&rpmcc RPM_S
961 clock-names = "apb_pcl
962
963 cpu = <&CPU0>;
964
965 out-ports {
966 port {
967 etm0_o
968
969 };
970 };
971 };
972 };
973
974 etm@fc33d000 {
975 compatible = "arm,core
976 reg = <0xfc33d000 0x10
977
978 clocks = <&rpmcc RPM_S
979 clock-names = "apb_pcl
980
981 cpu = <&CPU1>;
982
983 out-ports {
984 port {
985 etm1_o
986
987 };
988 };
989 };
990 };
991
992 etm@fc33e000 {
993 compatible = "arm,core
994 reg = <0xfc33e000 0x10
995
996 clocks = <&rpmcc RPM_S
997 clock-names = "apb_pcl
998
999 cpu = <&CPU2>;
1000
1001 out-ports {
1002 port {
1003 etm2_
1004
1005 };
1006 };
1007 };
1008 };
1009
1010 etm@fc33f000 {
1011 compatible = "arm,cor
1012 reg = <0xfc33f000 0x1
1013
1014 clocks = <&rpmcc RPM_
1015 clock-names = "apb_pc
1016
1017 cpu = <&CPU3>;
1018
1019 out-ports {
1020 port {
1021 etm3_
1022
1023 };
1024 };
1025 };
1026 };
1027
1028 /* KPSS funnel, only 4 inputs
1029 funnel@fc345000 {
1030 compatible = "arm,cor
1031 reg = <0xfc345000 0x1
1032
1033 clocks = <&rpmcc RPM_
1034 clock-names = "apb_pc
1035
1036 in-ports {
1037 #address-cell
1038 #size-cells =
1039
1040 port@0 {
1041 reg =
1042 kpss_
1043
1044 };
1045 };
1046 port@1 {
1047 reg =
1048 kpss_
1049
1050 };
1051 };
1052 port@2 {
1053 reg =
1054 kpss_
1055
1056 };
1057 };
1058 port@3 {
1059 reg =
1060 kpss_
1061
1062 };
1063 };
1064 };
1065
1066 out-ports {
1067 port {
1068 kpss_
1069
1070 };
1071 };
1072 };
1073 };
1074
1075 bimc: interconnect@fc380000 {
1076 reg = <0xfc380000 0x6
1077 compatible = "qcom,ms
1078 #interconnect-cells =
1079 clock-names = "bus",
1080 clocks = <&rpmcc RPM_
1081 <&rpmcc RPM_
1082 };
1083
1084 gcc: clock-controller@fc40000
1085 compatible = "qcom,gc
1086 #clock-cells = <1>;
1087 #reset-cells = <1>;
1088 #power-domain-cells =
1089 reg = <0xfc400000 0x4
1090
1091 clocks = <&rpmcc RPM_
1092 <&sleep_clk>
1093 clock-names = "xo",
1094 "sleep_
1095 };
1096
1097 rpm_msg_ram: sram@fc428000 {
1098 compatible = "qcom,rp
1099 reg = <0xfc428000 0x4
1100
1101 #address-cells = <1>;
1102 #size-cells = <1>;
1103 ranges = <0 0xfc42800
1104
1105 apss_master_stats: sr
1106 reg = <0x150
1107 };
1108
1109 mpss_master_stats: sr
1110 reg = <0xb50
1111 };
1112
1113 lpss_master_stats: sr
1114 reg = <0x1550
1115 };
1116
1117 pronto_master_stats:
1118 reg = <0x1f50
1119 };
1120 };
1121
1122 snoc: interconnect@fc460000 {
1123 reg = <0xfc460000 0x4
1124 compatible = "qcom,ms
1125 #interconnect-cells =
1126 clock-names = "bus",
1127 clocks = <&rpmcc RPM_
1128 <&rpmcc RPM_
1129 };
1130
1131 pnoc: interconnect@fc468000 {
1132 reg = <0xfc468000 0x4
1133 compatible = "qcom,ms
1134 #interconnect-cells =
1135 clock-names = "bus",
1136 clocks = <&rpmcc RPM_
1137 <&rpmcc RPM_
1138 };
1139
1140 ocmemnoc: interconnect@fc4700
1141 reg = <0xfc470000 0x4
1142 compatible = "qcom,ms
1143 #interconnect-cells =
1144 clock-names = "bus",
1145 clocks = <&rpmcc RPM_
1146 <&rpmcc RPM_
1147 };
1148
1149 mmssnoc: interconnect@fc47800
1150 reg = <0xfc478000 0x4
1151 compatible = "qcom,ms
1152 #interconnect-cells =
1153 clock-names = "bus",
1154 clocks = <&mmcc MMSS_
1155 <&mmcc MMSS_
1156 };
1157
1158 cnoc: interconnect@fc480000 {
1159 reg = <0xfc480000 0x4
1160 compatible = "qcom,ms
1161 #interconnect-cells =
1162 clock-names = "bus",
1163 clocks = <&rpmcc RPM_
1164 <&rpmcc RPM_
1165 };
1166
1167 tsens: thermal-sensor@fc4a900
1168 compatible = "qcom,ms
1169 reg = <0xfc4a9000 0x1
1170 <0xfc4a8000 0x1
1171 nvmem-cells = <&tsens
1172 <&tsens
1173 <&tsens
1174 <&tsens
1175 <&tsens
1176 <&tsens
1177 <&tsens
1178 <&tsens
1179 <&tsens
1180 <&tsens
1181 <&tsens
1182 <&tsens
1183 <&tsens
1184 <&tsens
1185 <&tsens
1186 <&tsens
1187 <&tsens
1188 <&tsens
1189 <&tsens
1190 <&tsens
1191 <&tsens
1192 <&tsens
1193 <&tsens
1194 <&tsens
1195 <&tsens
1196 <&tsens
1197 <&tsens
1198 nvmem-cell-names = "m
1199 "b
1200 "u
1201 "m
1202 "b
1203 "s
1204 "s
1205 "s
1206 "s
1207 "s
1208 "s
1209 "s
1210 "s
1211 "s
1212 "s
1213 "s
1214 "s
1215 "s
1216 "s
1217 "s
1218 "s
1219 "s
1220 "s
1221 "s
1222 "s
1223 "s
1224 "s
1225 #qcom,sensors = <11>;
1226 interrupts = <GIC_SPI
1227 interrupt-names = "up
1228 #thermal-sensor-cells
1229 };
1230
1231 restart@fc4ab000 {
1232 compatible = "qcom,ps
1233 reg = <0xfc4ab000 0x4
1234 };
1235
1236 qfprom: efuse@fc4bc000 {
1237 compatible = "qcom,ms
1238 reg = <0xfc4bc000 0x2
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241
1242 tsens_base1: base1@d0
1243 reg = <0xd0 0
1244 bits = <0 8>;
1245 };
1246
1247 tsens_s0_p1: s0-p1@d1
1248 reg = <0xd1 0
1249 bits = <0 6>;
1250 };
1251
1252 tsens_s1_p1: s1-p1@d2
1253 reg = <0xd1 0
1254 bits = <6 6>;
1255 };
1256
1257 tsens_s2_p1: s2-p1@d2
1258 reg = <0xd2 0
1259 bits = <4 6>;
1260 };
1261
1262 tsens_s3_p1: s3-p1@d3
1263 reg = <0xd3 0
1264 bits = <2 6>;
1265 };
1266
1267 tsens_s4_p1: s4-p1@d4
1268 reg = <0xd4 0
1269 bits = <0 6>;
1270 };
1271
1272 tsens_s5_p1: s5-p1@d4
1273 reg = <0xd4 0
1274 bits = <6 6>;
1275 };
1276
1277 tsens_s6_p1: s6-p1@d5
1278 reg = <0xd5 0
1279 bits = <4 6>;
1280 };
1281
1282 tsens_s7_p1: s7-p1@d6
1283 reg = <0xd6 0
1284 bits = <2 6>;
1285 };
1286
1287 tsens_s8_p1: s8-p1@d7
1288 reg = <0xd7 0
1289 bits = <0 6>;
1290 };
1291
1292 tsens_mode: mode@d7 {
1293 reg = <0xd7 0
1294 bits = <6 2>;
1295 };
1296
1297 tsens_s9_p1: s9-p1@d8
1298 reg = <0xd8 0
1299 bits = <0 6>;
1300 };
1301
1302 tsens_s10_p1: s10_p1@
1303 reg = <0xd8 0
1304 bits = <6 6>;
1305 };
1306
1307 tsens_base2: base2@d9
1308 reg = <0xd9 0
1309 bits = <4 8>;
1310 };
1311
1312 tsens_s0_p2: s0-p2@da
1313 reg = <0xda 0
1314 bits = <4 6>;
1315 };
1316
1317 tsens_s1_p2: s1-p2@db
1318 reg = <0xdb 0
1319 bits = <2 6>;
1320 };
1321
1322 tsens_s2_p2: s2-p2@dc
1323 reg = <0xdc 0
1324 bits = <0 6>;
1325 };
1326
1327 tsens_s3_p2: s3-p2@dc
1328 reg = <0xdc 0
1329 bits = <6 6>;
1330 };
1331
1332 tsens_s4_p2: s4-p2@dd
1333 reg = <0xdd 0
1334 bits = <4 6>;
1335 };
1336
1337 tsens_s5_p2: s5-p2@de
1338 reg = <0xde 0
1339 bits = <2 6>;
1340 };
1341
1342 tsens_s6_p2: s6-p2@df
1343 reg = <0xdf 0
1344 bits = <0 6>;
1345 };
1346
1347 tsens_s7_p2: s7-p2@e0
1348 reg = <0xe0 0
1349 bits = <0 6>;
1350 };
1351
1352 tsens_s8_p2: s8-p2@e0
1353 reg = <0xe0 0
1354 bits = <6 6>;
1355 };
1356
1357 tsens_s9_p2: s9-p2@e1
1358 reg = <0xe1 0
1359 bits = <4 6>;
1360 };
1361
1362 tsens_s10_p2: s10_p2@
1363 reg = <0xe2 0
1364 bits = <2 6>;
1365 };
1366
1367 tsens_s5_p2_backup: s
1368 reg = <0xe3 0
1369 bits = <0 6>;
1370 };
1371
1372 tsens_mode_backup: mo
1373 reg = <0xe3 0
1374 bits = <6 2>;
1375 };
1376
1377 tsens_s6_p2_backup: s
1378 reg = <0xe4 0
1379 bits = <0 6>;
1380 };
1381
1382 tsens_s7_p2_backup: s
1383 reg = <0xe4 0
1384 bits = <6 6>;
1385 };
1386
1387 tsens_s8_p2_backup: s
1388 reg = <0xe5 0
1389 bits = <4 6>;
1390 };
1391
1392 tsens_s9_p2_backup: s
1393 reg = <0xe6 0
1394 bits = <2 6>;
1395 };
1396
1397 tsens_s10_p2_backup:
1398 reg = <0xe7 0
1399 bits = <0 6>;
1400 };
1401
1402 tsens_base1_backup: b
1403 reg = <0x440
1404 bits = <0 8>;
1405 };
1406
1407 tsens_s0_p1_backup: s
1408 reg = <0x441
1409 bits = <0 6>;
1410 };
1411
1412 tsens_s1_p1_backup: s
1413 reg = <0x441
1414 bits = <6 6>;
1415 };
1416
1417 tsens_s2_p1_backup: s
1418 reg = <0x442
1419 bits = <4 6>;
1420 };
1421
1422 tsens_s3_p1_backup: s
1423 reg = <0x443
1424 bits = <2 6>;
1425 };
1426
1427 tsens_s4_p1_backup: s
1428 reg = <0x444
1429 bits = <0 6>;
1430 };
1431
1432 tsens_s5_p1_backup: s
1433 reg = <0x444
1434 bits = <6 6>;
1435 };
1436
1437 tsens_s6_p1_backup: s
1438 reg = <0x445
1439 bits = <4 6>;
1440 };
1441
1442 tsens_s7_p1_backup: s
1443 reg = <0x446
1444 bits = <2 6>;
1445 };
1446
1447 tsens_use_backup: use
1448 reg = <0x447
1449 bits = <5 3>;
1450 };
1451
1452 tsens_s8_p1_backup: s
1453 reg = <0x448
1454 bits = <0 6>;
1455 };
1456
1457 tsens_s9_p1_backup: s
1458 reg = <0x448
1459 bits = <6 6>;
1460 };
1461
1462 tsens_s10_p1_backup:
1463 reg = <0x449
1464 bits = <4 6>;
1465 };
1466
1467 tsens_base2_backup: b
1468 reg = <0x44a
1469 bits = <2 8>;
1470 };
1471
1472 tsens_s0_p2_backup: s
1473 reg = <0x44b
1474 bits = <2 6>;
1475 };
1476
1477 tsens_s1_p2_backup: s
1478 reg = <0x44c
1479 bits = <0 6>;
1480 };
1481
1482 tsens_s2_p2_backup: s
1483 reg = <0x44c
1484 bits = <6 6>;
1485 };
1486
1487 tsens_s3_p2_backup: s
1488 reg = <0x44d
1489 bits = <4 6>;
1490 };
1491
1492 tsens_s4_p2_backup: s
1493 reg = <0x44e
1494 bits = <2 6>;
1495 };
1496 };
1497
1498 spmi_bus: spmi@fc4cf000 {
1499 compatible = "qcom,sp
1500 reg-names = "core", "
1501 reg = <0xfc4cf000 0x1
1502 <0xfc4cb000 0x1
1503 <0xfc4ca000 0x1
1504 interrupt-names = "pe
1505 interrupts = <GIC_SPI
1506 qcom,ee = <0>;
1507 qcom,channel = <0>;
1508 #address-cells = <2>;
1509 #size-cells = <0>;
1510 interrupt-controller;
1511 #interrupt-cells = <4
1512 };
1513
1514 bam_dmux_dma: dma-controller@
1515 compatible = "qcom,ba
1516 reg = <0xfc834000 0x7
1517 interrupts = <GIC_SPI
1518 #dma-cells = <1>;
1519 qcom,ee = <0>;
1520
1521 num-channels = <6>;
1522 qcom,num-ees = <1>;
1523 qcom,powered-remotely
1524 };
1525
1526 remoteproc_mss: remoteproc@fc
1527 compatible = "qcom,ms
1528 reg = <0xfc880000 0x1
1529 reg-names = "qdsp6",
1530
1531 interrupts-extended =
1532
1533
1534
1535
1536 interrupt-names = "wd
1537
1538 clocks = <&gcc GCC_MS
1539 <&gcc GCC_MS
1540 <&gcc GCC_BO
1541 <&xo_board>;
1542 clock-names = "iface"
1543
1544 resets = <&gcc GCC_MS
1545 reset-names = "mss_re
1546
1547 qcom,halt-regs = <&tc
1548
1549 qcom,smem-states = <&
1550 qcom,smem-state-names
1551
1552 status = "disabled";
1553
1554 mba {
1555 memory-region
1556 };
1557
1558 mpss {
1559 memory-region
1560 };
1561
1562 bam_dmux: bam-dmux {
1563 compatible =
1564
1565 interrupt-par
1566 interrupts =
1567 interrupt-nam
1568
1569 qcom,smem-sta
1570 qcom,smem-sta
1571
1572 dmas = <&bam_
1573 dma-names = "
1574 };
1575
1576 smd-edge {
1577 interrupts =
1578
1579 mboxes = <&ap
1580 qcom,smd-edge
1581
1582 label = "mode
1583 };
1584 };
1585
1586 tcsr_mutex: hwlock@fd484000 {
1587 compatible = "qcom,ms
1588 reg = <0xfd484000 0x2
1589 #hwlock-cells = <1>;
1590 };
1591
1592 tcsr: syscon@fd4a0000 {
1593 compatible = "qcom,tc
1594 reg = <0xfd4a0000 0x1
1595 };
1596
1597 tlmm: pinctrl@fd510000 {
1598 compatible = "qcom,ms
1599 reg = <0xfd510000 0x4
1600 gpio-controller;
1601 gpio-ranges = <&tlmm
1602 #gpio-cells = <2>;
1603 interrupt-controller;
1604 #interrupt-cells = <2
1605 interrupts = <GIC_SPI
1606
1607 sdc1_off: sdc1-off-st
1608 clk-pins {
1609 pins
1610 bias-
1611 drive
1612 };
1613
1614 cmd-pins {
1615 pins
1616 bias-
1617 drive
1618 };
1619
1620 data-pins {
1621 pins
1622 bias-
1623 drive
1624 };
1625 };
1626
1627 sdc2_off: sdc2-off-st
1628 clk-pins {
1629 pins
1630 bias-
1631 drive
1632 };
1633
1634 cmd-pins {
1635 pins
1636 bias-
1637 drive
1638 };
1639
1640 data-pins {
1641 pins
1642 bias-
1643 drive
1644 };
1645 };
1646
1647 blsp1_uart2_default:
1648 rx-pins {
1649 pins
1650 funct
1651 drive
1652 bias-
1653 };
1654
1655 tx-pins {
1656 pins
1657 funct
1658 drive
1659 bias-
1660 };
1661 };
1662
1663 blsp2_uart1_default:
1664 tx-rts-pins {
1665 pins
1666 funct
1667 drive
1668 bias-
1669 };
1670
1671 rx-cts-pins {
1672 pins
1673 funct
1674 drive
1675 bias-
1676 };
1677 };
1678
1679 blsp2_uart1_sleep: bl
1680 pins = "gpio4
1681 function = "g
1682 drive-strengt
1683 bias-pull-dow
1684 };
1685
1686 blsp2_uart4_default:
1687 tx-rts-pins {
1688 pins
1689 funct
1690 drive
1691 bias-
1692 };
1693
1694 rx-cts-pins {
1695 pins
1696 funct
1697 drive
1698 bias-
1699 };
1700 };
1701
1702 blsp1_i2c1_default: b
1703 pins = "gpio2
1704 function = "b
1705 drive-strengt
1706 bias-disable;
1707 };
1708
1709 blsp1_i2c1_sleep: bls
1710 pins = "gpio2
1711 function = "b
1712 drive-strengt
1713 bias-pull-up;
1714 };
1715
1716 blsp1_i2c2_default: b
1717 pins = "gpio6
1718 function = "b
1719 drive-strengt
1720 bias-disable;
1721 };
1722
1723 blsp1_i2c2_sleep: bls
1724 pins = "gpio6
1725 function = "b
1726 drive-strengt
1727 bias-pull-up;
1728 };
1729
1730 blsp1_i2c3_default: b
1731 pins = "gpio1
1732 function = "b
1733 drive-strengt
1734 bias-disable;
1735 };
1736
1737 blsp1_i2c3_sleep: bls
1738 pins = "gpio1
1739 function = "b
1740 drive-strengt
1741 bias-pull-up;
1742 };
1743
1744 /* BLSP1_I2C4 info is
1745
1746 /* BLSP1_I2C5 info is
1747
1748 blsp1_i2c6_default: b
1749 pins = "gpio2
1750 function = "b
1751 drive-strengt
1752 bias-disable;
1753 };
1754
1755 blsp1_i2c6_sleep: bls
1756 pins = "gpio2
1757 function = "b
1758 drive-strengt
1759 bias-pull-up;
1760 };
1761 /* 6 interfaces per Q
1762
1763 /* BLSP2_I2C1 info is
1764
1765 blsp2_i2c2_default: b
1766 pins = "gpio4
1767 function = "b
1768 drive-strengt
1769 bias-disable;
1770 };
1771
1772 blsp2_i2c2_sleep: bls
1773 pins = "gpio4
1774 function = "b
1775 drive-strengt
1776 bias-pull-up;
1777 };
1778
1779 /* BLSP2_I2C3 info is
1780
1781 /* BLSP2_I2C4 info is
1782
1783 blsp2_i2c5_default: b
1784 pins = "gpio8
1785 function = "b
1786 drive-strengt
1787 bias-disable;
1788 };
1789
1790 blsp2_i2c5_sleep: bls
1791 pins = "gpio8
1792 function = "b
1793 drive-strengt
1794 bias-pull-up;
1795 };
1796
1797 blsp2_i2c6_default: b
1798 pins = "gpio8
1799 function = "b
1800 drive-strengt
1801 bias-disable;
1802 };
1803
1804 blsp2_i2c6_sleep: bls
1805 pins = "gpio8
1806 function = "b
1807 drive-strengt
1808 bias-pull-up;
1809 };
1810
1811 cci_default: cci-defa
1812 cci_i2c0_defa
1813 pins
1814 funct
1815 drive
1816 bias-
1817 };
1818
1819 cci_i2c1_defa
1820 pins
1821 funct
1822 drive
1823 bias-
1824 };
1825 };
1826
1827 cci_sleep: cci-sleep-
1828 cci_i2c0_slee
1829 pins
1830 funct
1831 drive
1832 bias-
1833 };
1834
1835 cci_i2c1_slee
1836 pins
1837 funct
1838 drive
1839 bias-
1840 };
1841 };
1842
1843 spi8_default: spi8_de
1844 mosi-pins {
1845 pins
1846 funct
1847 };
1848 miso-pins {
1849 pins
1850 funct
1851 };
1852 cs-pins {
1853 pins
1854 funct
1855 };
1856 clk-pins {
1857 pins
1858 funct
1859 };
1860 };
1861 };
1862
1863 mmcc: clock-controller@fd8c00
1864 compatible = "qcom,mm
1865 #clock-cells = <1>;
1866 #reset-cells = <1>;
1867 #power-domain-cells =
1868 reg = <0xfd8c0000 0x6
1869 clocks = <&xo_board>,
1870 <&gcc GCC_MM
1871 <&gcc GPLL0_
1872 <&gcc GPLL1_
1873 <&rpmcc RPM_
1874 <&mdss_dsi0_
1875 <&mdss_dsi0_
1876 <&mdss_dsi1_
1877 <&mdss_dsi1_
1878 <0>,
1879 <0>,
1880 <0>;
1881 clock-names = "xo",
1882 "mmss_g
1883 "gpll0_
1884 "gpll1_
1885 "gfx3d_
1886 "dsi0pl
1887 "dsi0pl
1888 "dsi1pl
1889 "dsi1pl
1890 "hdmipl
1891 "edp_li
1892 "edp_vc
1893 };
1894
1895 mdss: display-subsystem@fd900
1896 compatible = "qcom,md
1897 reg = <0xfd900000 0x1
1898 reg-names = "mdss_phy
1899
1900 power-domains = <&mmc
1901
1902 clocks = <&mmcc MDSS_
1903 <&mmcc MDSS_
1904 <&mmcc MDSS_
1905 clock-names = "iface"
1906
1907 interrupts = <GIC_SPI
1908
1909 interrupt-controller;
1910 #interrupt-cells = <1
1911
1912 status = "disabled";
1913
1914 #address-cells = <1>;
1915 #size-cells = <1>;
1916 ranges;
1917
1918 mdp: display-controll
1919 compatible =
1920 reg = <0xfd90
1921 reg-names = "
1922
1923 interrupt-par
1924 interrupts =
1925
1926 clocks = <&mm
1927 <&mm
1928 <&mm
1929 <&mm
1930 clock-names =
1931
1932 interconnects
1933 interconnect-
1934
1935 ports {
1936 #addr
1937 #size
1938
1939 port@
1940
1941
1942
1943
1944 };
1945
1946 port@
1947
1948
1949
1950
1951 };
1952 };
1953 };
1954
1955 mdss_dsi0: dsi@fd9228
1956 compatible =
1957
1958 reg = <0xfd92
1959 reg-names = "
1960
1961 interrupt-par
1962 interrupts =
1963
1964 assigned-cloc
1965 assigned-cloc
1966
1967 clocks = <&mm
1968 <&mm
1969 <&mm
1970 <&mm
1971 <&mm
1972 <&mm
1973 <&mm
1974 clock-names =
1975
1976
1977
1978
1979
1980
1981
1982 phys = <&mdss
1983
1984 status = "dis
1985
1986 #address-cell
1987 #size-cells =
1988
1989 ports {
1990 #addr
1991 #size
1992
1993 port@
1994
1995
1996
1997
1998 };
1999
2000 port@
2001
2002
2003
2004 };
2005 };
2006 };
2007
2008 mdss_dsi0_phy: phy@fd
2009 compatible =
2010 reg = <0xfd92
2011 <0xfd92
2012 <0xfd92
2013 reg-names = "
2014 "
2015 "
2016
2017 #clock-cells
2018 #phy-cells =
2019
2020 clocks = <&mm
2021 clock-names =
2022
2023 status = "dis
2024 };
2025
2026 mdss_dsi1: dsi@fd922e
2027 compatible =
2028
2029 reg = <0xfd92
2030 reg-names = "
2031
2032 interrupt-par
2033 interrupts =
2034
2035 assigned-cloc
2036 assigned-cloc
2037
2038 clocks = <&mm
2039 <&mm
2040 <&mm
2041 <&mm
2042 <&mm
2043 <&mm
2044 <&mm
2045 clock-names =
2046
2047
2048
2049
2050
2051
2052
2053 phys = <&mdss
2054
2055 status = "dis
2056
2057 #address-cell
2058 #size-cells =
2059
2060 ports {
2061 #addr
2062 #size
2063
2064 port@
2065
2066
2067
2068
2069 };
2070
2071 port@
2072
2073
2074
2075 };
2076 };
2077 };
2078
2079 mdss_dsi1_phy: phy@fd
2080 compatible =
2081 reg = <0xfd92
2082 <0xfd92
2083 <0xfd92
2084 reg-names = "
2085 "
2086 "
2087
2088 #clock-cells
2089 #phy-cells =
2090
2091 clocks = <&mm
2092 clock-names =
2093
2094 status = "dis
2095 };
2096 };
2097
2098 cci: cci@fda0c000 {
2099 compatible = "qcom,ms
2100 #address-cells = <1>;
2101 #size-cells = <0>;
2102 reg = <0xfda0c000 0x1
2103 interrupts = <GIC_SPI
2104 clocks = <&mmcc CAMSS
2105 <&mmcc CAMSS
2106 <&mmcc CAMSS
2107 clock-names = "camss_
2108 "cci_ah
2109 "cci";
2110
2111 pinctrl-names = "defa
2112 pinctrl-0 = <&cci_def
2113 pinctrl-1 = <&cci_sle
2114
2115 status = "disabled";
2116
2117 cci_i2c0: i2c-bus@0 {
2118 reg = <0>;
2119 clock-frequen
2120 #address-cell
2121 #size-cells =
2122 };
2123
2124 cci_i2c1: i2c-bus@1 {
2125 reg = <1>;
2126 clock-frequen
2127 #address-cell
2128 #size-cells =
2129 };
2130 };
2131
2132 gpu: gpu@fdb00000 {
2133 compatible = "qcom,ad
2134 reg = <0xfdb00000 0x1
2135 reg-names = "kgsl_3d0
2136
2137 interrupts = <GIC_SPI
2138 interrupt-names = "kg
2139
2140 clocks = <&mmcc OXILI
2141 <&mmcc OXILI
2142 <&mmcc OXILI
2143 clock-names = "core",
2144
2145 sram = <&gmu_sram>;
2146 power-domains = <&mmc
2147 operating-points-v2 =
2148
2149 interconnects = <&mms
2150 <&ocm
2151 interconnect-names =
2152
2153 // iommus = <&gpu_iom
2154
2155 status = "disabled";
2156
2157 gpu_opp_table: opp-ta
2158 compatible =
2159
2160 opp-320000000
2161 opp-h
2162 };
2163
2164 opp-200000000
2165 opp-h
2166 };
2167
2168 opp-27000000
2169 opp-h
2170 };
2171 };
2172 };
2173
2174 sram@fdd00000 {
2175 compatible = "qcom,ms
2176 reg = <0xfdd00000 0x2
2177 <0xfec00000 0x1
2178 reg-names = "ctrl", "
2179 ranges = <0 0xfec0000
2180 clocks = <&rpmcc RPM_
2181 <&mmcc OCMEM
2182 clock-names = "core",
2183
2184 #address-cells = <1>;
2185 #size-cells = <1>;
2186
2187 gmu_sram: gmu-sram@0
2188 reg = <0x0 0x
2189 };
2190 };
2191
2192 remoteproc_adsp: remoteproc@f
2193 compatible = "qcom,ms
2194 reg = <0xfe200000 0x1
2195
2196 interrupts-extended =
2197
2198
2199
2200
2201 interrupt-names = "wd
2202
2203 clocks = <&xo_board>;
2204 clock-names = "xo";
2205
2206 memory-region = <&ads
2207
2208 qcom,smem-states = <&
2209 qcom,smem-state-names
2210
2211 status = "disabled";
2212
2213 smd-edge {
2214 interrupts =
2215
2216 mboxes = <&ap
2217 qcom,smd-edge
2218 label = "lpas
2219 };
2220 };
2221
2222 imem: sram@fe805000 {
2223 compatible = "qcom,ms
2224 reg = <0xfe805000 0x1
2225
2226 reboot-mode {
2227 compatible =
2228 offset = <0x6
2229 };
2230 };
2231 };
2232
2233 thermal-zones {
2234 cpu0-thermal {
2235 polling-delay-passive
2236 polling-delay = <1000
2237
2238 thermal-sensors = <&t
2239
2240 trips {
2241 cpu_alert0: t
2242 tempe
2243 hyste
2244 type
2245 };
2246 cpu_crit0: tr
2247 tempe
2248 hyste
2249 type
2250 };
2251 };
2252 };
2253
2254 cpu1-thermal {
2255 polling-delay-passive
2256 polling-delay = <1000
2257
2258 thermal-sensors = <&t
2259
2260 trips {
2261 cpu_alert1: t
2262 tempe
2263 hyste
2264 type
2265 };
2266 cpu_crit1: tr
2267 tempe
2268 hyste
2269 type
2270 };
2271 };
2272 };
2273
2274 cpu2-thermal {
2275 polling-delay-passive
2276 polling-delay = <1000
2277
2278 thermal-sensors = <&t
2279
2280 trips {
2281 cpu_alert2: t
2282 tempe
2283 hyste
2284 type
2285 };
2286 cpu_crit2: tr
2287 tempe
2288 hyste
2289 type
2290 };
2291 };
2292 };
2293
2294 cpu3-thermal {
2295 polling-delay-passive
2296 polling-delay = <1000
2297
2298 thermal-sensors = <&t
2299
2300 trips {
2301 cpu_alert3: t
2302 tempe
2303 hyste
2304 type
2305 };
2306 cpu_crit3: tr
2307 tempe
2308 hyste
2309 type
2310 };
2311 };
2312 };
2313
2314 q6-dsp-thermal {
2315 polling-delay-passive
2316 polling-delay = <1000
2317
2318 thermal-sensors = <&t
2319
2320 trips {
2321 q6_dsp_alert0
2322 tempe
2323 hyste
2324 type
2325 };
2326 };
2327 };
2328
2329 modemtx-thermal {
2330 polling-delay-passive
2331 polling-delay = <1000
2332
2333 thermal-sensors = <&t
2334
2335 trips {
2336 modemtx_alert
2337 tempe
2338 hyste
2339 type
2340 };
2341 };
2342 };
2343
2344 video-thermal {
2345 polling-delay-passive
2346 polling-delay = <1000
2347
2348 thermal-sensors = <&t
2349
2350 trips {
2351 video_alert0:
2352 tempe
2353 hyste
2354 type
2355 };
2356 };
2357 };
2358
2359 wlan-thermal {
2360 polling-delay-passive
2361 polling-delay = <1000
2362
2363 thermal-sensors = <&t
2364
2365 trips {
2366 wlan_alert0:
2367 tempe
2368 hyste
2369 type
2370 };
2371 };
2372 };
2373
2374 gpu-top-thermal {
2375 polling-delay-passive
2376 polling-delay = <1000
2377
2378 thermal-sensors = <&t
2379
2380 trips {
2381 gpu1_alert0:
2382 tempe
2383 hyste
2384 type
2385 };
2386 };
2387 };
2388
2389 gpu-bottom-thermal {
2390 polling-delay-passive
2391 polling-delay = <1000
2392
2393 thermal-sensors = <&t
2394
2395 trips {
2396 gpu2_alert0:
2397 tempe
2398 hyste
2399 type
2400 };
2401 };
2402 };
2403 };
2404
2405 timer {
2406 compatible = "arm,armv7-timer
2407 interrupts = <GIC_PPI 2 (GIC_
2408 <GIC_PPI 3 (GIC_
2409 <GIC_PPI 4 (GIC_
2410 <GIC_PPI 1 (GIC_
2411 clock-frequency = <19200000>;
2412 };
2413 };
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