1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/interconnect/qcom,msm897 4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h 6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974. 7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h 9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 11
12 / { 12 / {
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 16
17 chosen { }; <<
18 <<
19 clocks { 17 clocks {
20 xo_board: xo_board { 18 xo_board: xo_board {
21 compatible = "fixed-cl 19 compatible = "fixed-clock";
22 #clock-cells = <0>; 20 #clock-cells = <0>;
23 clock-frequency = <192 21 clock-frequency = <19200000>;
24 }; 22 };
25 23
26 sleep_clk: sleep_clk { 24 sleep_clk: sleep_clk {
27 compatible = "fixed-cl 25 compatible = "fixed-clock";
28 #clock-cells = <0>; 26 #clock-cells = <0>;
29 clock-frequency = <327 27 clock-frequency = <32768>;
30 }; 28 };
31 }; 29 };
32 30
33 cpus { 31 cpus {
34 #address-cells = <1>; 32 #address-cells = <1>;
35 #size-cells = <0>; 33 #size-cells = <0>;
36 interrupts = <GIC_PPI 9 (GIC_C !! 34 interrupts = <GIC_PPI 9 0xf04>;
37 35
38 CPU0: cpu@0 { 36 CPU0: cpu@0 {
39 compatible = "qcom,kra 37 compatible = "qcom,krait";
40 enable-method = "qcom, 38 enable-method = "qcom,kpss-acc-v2";
41 device_type = "cpu"; 39 device_type = "cpu";
42 reg = <0>; 40 reg = <0>;
43 next-level-cache = <&L 41 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>; 42 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>; 43 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_SPC>;
47 }; 45 };
48 46
49 CPU1: cpu@1 { 47 CPU1: cpu@1 {
50 compatible = "qcom,kra 48 compatible = "qcom,krait";
51 enable-method = "qcom, 49 enable-method = "qcom,kpss-acc-v2";
52 device_type = "cpu"; 50 device_type = "cpu";
53 reg = <1>; 51 reg = <1>;
54 next-level-cache = <&L 52 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>; 53 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>; 54 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CP 55 cpu-idle-states = <&CPU_SPC>;
58 }; 56 };
59 57
60 CPU2: cpu@2 { 58 CPU2: cpu@2 {
61 compatible = "qcom,kra 59 compatible = "qcom,krait";
62 enable-method = "qcom, 60 enable-method = "qcom,kpss-acc-v2";
63 device_type = "cpu"; 61 device_type = "cpu";
64 reg = <2>; 62 reg = <2>;
65 next-level-cache = <&L 63 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>; 64 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>; 65 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CP 66 cpu-idle-states = <&CPU_SPC>;
69 }; 67 };
70 68
71 CPU3: cpu@3 { 69 CPU3: cpu@3 {
72 compatible = "qcom,kra 70 compatible = "qcom,krait";
73 enable-method = "qcom, 71 enable-method = "qcom,kpss-acc-v2";
74 device_type = "cpu"; 72 device_type = "cpu";
75 reg = <3>; 73 reg = <3>;
76 next-level-cache = <&L 74 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>; 75 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>; 76 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CP 77 cpu-idle-states = <&CPU_SPC>;
80 }; 78 };
81 79
82 L2: l2-cache { 80 L2: l2-cache {
83 compatible = "cache"; 81 compatible = "cache";
84 cache-level = <2>; 82 cache-level = <2>;
85 cache-unified; 83 cache-unified;
86 qcom,saw = <&saw_l2>; 84 qcom,saw = <&saw_l2>;
87 }; 85 };
88 86
89 idle-states { 87 idle-states {
90 CPU_SPC: cpu-spc { !! 88 CPU_SPC: spc {
91 compatible = " 89 compatible = "qcom,idle-state-spc",
92 90 "arm,idle-state";
93 entry-latency- 91 entry-latency-us = <150>;
94 exit-latency-u 92 exit-latency-us = <200>;
95 min-residency- 93 min-residency-us = <2000>;
96 }; 94 };
97 }; 95 };
98 }; 96 };
99 97
100 firmware { 98 firmware {
101 scm { 99 scm {
102 compatible = "qcom,scm 100 compatible = "qcom,scm-msm8974", "qcom,scm";
103 clocks = <&gcc GCC_CE1 101 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
104 clock-names = "core", 102 clock-names = "core", "bus", "iface";
105 }; 103 };
106 }; 104 };
107 105
108 memory@0 { !! 106 memory {
109 device_type = "memory"; 107 device_type = "memory";
110 reg = <0x0 0x0>; 108 reg = <0x0 0x0>;
111 }; 109 };
112 110
113 pmu { 111 pmu {
114 compatible = "qcom,krait-pmu"; 112 compatible = "qcom,krait-pmu";
115 interrupts = <GIC_PPI 7 (GIC_C !! 113 interrupts = <GIC_PPI 7 0xf04>;
116 }; 114 };
117 115
118 rpm: remoteproc { 116 rpm: remoteproc {
119 compatible = "qcom,msm8974-rpm 117 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
120 118
121 master-stats { <<
122 compatible = "qcom,rpm <<
123 qcom,rpm-msg-ram = <&a <<
124 <&m <<
125 <&l <<
126 <&p <<
127 qcom,master-names = "A <<
128 "M <<
129 "L <<
130 "P <<
131 }; <<
132 <<
133 smd-edge { 119 smd-edge {
134 interrupts = <GIC_SPI 120 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
135 mboxes = <&apcs 0>; !! 121 qcom,ipc = <&apcs 8 0>;
136 qcom,smd-edge = <15>; 122 qcom,smd-edge = <15>;
137 123
138 rpm_requests: rpm-requ 124 rpm_requests: rpm-requests {
139 compatible = " !! 125 compatible = "qcom,rpm-msm8974";
140 qcom,smd-chann 126 qcom,smd-channels = "rpm_requests";
141 127
142 rpmcc: clock-c 128 rpmcc: clock-controller {
143 compat 129 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
144 #clock 130 #clock-cells = <1>;
145 clocks 131 clocks = <&xo_board>;
146 clock- 132 clock-names = "xo";
147 }; 133 };
148 }; 134 };
149 }; 135 };
150 }; 136 };
151 137
152 reserved_memory: reserved-memory { !! 138 reserved-memory {
153 #address-cells = <1>; 139 #address-cells = <1>;
154 #size-cells = <1>; 140 #size-cells = <1>;
155 ranges; 141 ranges;
156 142
157 mpss_region: mpss@8000000 { 143 mpss_region: mpss@8000000 {
158 reg = <0x08000000 0x51 144 reg = <0x08000000 0x5100000>;
159 no-map; 145 no-map;
160 }; 146 };
161 147
162 mba_region: mba@d100000 { 148 mba_region: mba@d100000 {
163 reg = <0x0d100000 0x10 149 reg = <0x0d100000 0x100000>;
164 no-map; 150 no-map;
165 }; 151 };
166 152
167 wcnss_region: wcnss@d200000 { 153 wcnss_region: wcnss@d200000 {
168 reg = <0x0d200000 0xa0 154 reg = <0x0d200000 0xa00000>;
169 no-map; 155 no-map;
170 }; 156 };
171 157
172 adsp_region: adsp@dc00000 { 158 adsp_region: adsp@dc00000 {
173 reg = <0x0dc00000 0x19 159 reg = <0x0dc00000 0x1900000>;
174 no-map; 160 no-map;
175 }; 161 };
176 162
177 venus_region: memory@f500000 { 163 venus_region: memory@f500000 {
178 reg = <0x0f500000 0x50 164 reg = <0x0f500000 0x500000>;
179 no-map; 165 no-map;
180 }; 166 };
181 167
182 smem_region: smem@fa00000 { 168 smem_region: smem@fa00000 {
183 reg = <0xfa00000 0x200 169 reg = <0xfa00000 0x200000>;
184 no-map; 170 no-map;
185 }; 171 };
186 172
187 tz_region: memory@fc00000 { 173 tz_region: memory@fc00000 {
188 reg = <0x0fc00000 0x16 174 reg = <0x0fc00000 0x160000>;
189 no-map; 175 no-map;
190 }; 176 };
191 177
192 rfsa_mem: memory@fd60000 { 178 rfsa_mem: memory@fd60000 {
193 reg = <0x0fd60000 0x20 179 reg = <0x0fd60000 0x20000>;
194 no-map; 180 no-map;
195 }; 181 };
196 182
197 rmtfs@fd80000 { 183 rmtfs@fd80000 {
198 compatible = "qcom,rmt 184 compatible = "qcom,rmtfs-mem";
199 reg = <0x0fd80000 0x18 185 reg = <0x0fd80000 0x180000>;
200 no-map; 186 no-map;
201 187
202 qcom,client-id = <1>; 188 qcom,client-id = <1>;
203 }; 189 };
204 }; 190 };
205 191
206 smem { 192 smem {
207 compatible = "qcom,smem"; 193 compatible = "qcom,smem";
208 194
209 memory-region = <&smem_region> 195 memory-region = <&smem_region>;
210 qcom,rpm-msg-ram = <&rpm_msg_r 196 qcom,rpm-msg-ram = <&rpm_msg_ram>;
211 197
212 hwlocks = <&tcsr_mutex 3>; 198 hwlocks = <&tcsr_mutex 3>;
213 }; 199 };
214 200
215 smp2p-adsp { 201 smp2p-adsp {
216 compatible = "qcom,smp2p"; 202 compatible = "qcom,smp2p";
217 qcom,smem = <443>, <429>; 203 qcom,smem = <443>, <429>;
218 204
219 interrupt-parent = <&intc>; 205 interrupt-parent = <&intc>;
220 interrupts = <GIC_SPI 158 IRQ_ 206 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
221 207
222 mboxes = <&apcs 10>; !! 208 qcom,ipc = <&apcs 8 10>;
223 209
224 qcom,local-pid = <0>; 210 qcom,local-pid = <0>;
225 qcom,remote-pid = <2>; 211 qcom,remote-pid = <2>;
226 212
227 adsp_smp2p_out: master-kernel 213 adsp_smp2p_out: master-kernel {
228 qcom,entry-name = "mas 214 qcom,entry-name = "master-kernel";
229 #qcom,smem-state-cells 215 #qcom,smem-state-cells = <1>;
230 }; 216 };
231 217
232 adsp_smp2p_in: slave-kernel { 218 adsp_smp2p_in: slave-kernel {
233 qcom,entry-name = "sla 219 qcom,entry-name = "slave-kernel";
234 220
235 interrupt-controller; 221 interrupt-controller;
236 #interrupt-cells = <2> 222 #interrupt-cells = <2>;
237 }; 223 };
238 }; 224 };
239 225
240 smp2p-modem { 226 smp2p-modem {
241 compatible = "qcom,smp2p"; 227 compatible = "qcom,smp2p";
242 qcom,smem = <435>, <428>; 228 qcom,smem = <435>, <428>;
243 229
244 interrupt-parent = <&intc>; 230 interrupt-parent = <&intc>;
245 interrupts = <GIC_SPI 27 IRQ_T 231 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
246 232
247 mboxes = <&apcs 14>; !! 233 qcom,ipc = <&apcs 8 14>;
248 234
249 qcom,local-pid = <0>; 235 qcom,local-pid = <0>;
250 qcom,remote-pid = <1>; 236 qcom,remote-pid = <1>;
251 237
252 modem_smp2p_out: master-kernel 238 modem_smp2p_out: master-kernel {
253 qcom,entry-name = "mas 239 qcom,entry-name = "master-kernel";
254 #qcom,smem-state-cells 240 #qcom,smem-state-cells = <1>;
255 }; 241 };
256 242
257 modem_smp2p_in: slave-kernel { 243 modem_smp2p_in: slave-kernel {
258 qcom,entry-name = "sla 244 qcom,entry-name = "slave-kernel";
259 245
260 interrupt-controller; 246 interrupt-controller;
261 #interrupt-cells = <2> 247 #interrupt-cells = <2>;
262 }; 248 };
263 }; 249 };
264 250
265 smp2p-wcnss { 251 smp2p-wcnss {
266 compatible = "qcom,smp2p"; 252 compatible = "qcom,smp2p";
267 qcom,smem = <451>, <431>; 253 qcom,smem = <451>, <431>;
268 254
269 interrupt-parent = <&intc>; 255 interrupt-parent = <&intc>;
270 interrupts = <GIC_SPI 143 IRQ_ 256 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
271 257
272 mboxes = <&apcs 18>; !! 258 qcom,ipc = <&apcs 8 18>;
273 259
274 qcom,local-pid = <0>; 260 qcom,local-pid = <0>;
275 qcom,remote-pid = <4>; 261 qcom,remote-pid = <4>;
276 262
277 wcnss_smp2p_out: master-kernel 263 wcnss_smp2p_out: master-kernel {
278 qcom,entry-name = "mas 264 qcom,entry-name = "master-kernel";
279 265
280 #qcom,smem-state-cells 266 #qcom,smem-state-cells = <1>;
281 }; 267 };
282 268
283 wcnss_smp2p_in: slave-kernel { 269 wcnss_smp2p_in: slave-kernel {
284 qcom,entry-name = "sla 270 qcom,entry-name = "slave-kernel";
285 271
286 interrupt-controller; 272 interrupt-controller;
287 #interrupt-cells = <2> 273 #interrupt-cells = <2>;
288 }; 274 };
289 }; 275 };
290 276
291 smsm { 277 smsm {
292 compatible = "qcom,smsm"; 278 compatible = "qcom,smsm";
293 279
294 #address-cells = <1>; 280 #address-cells = <1>;
295 #size-cells = <0>; 281 #size-cells = <0>;
296 282
297 mboxes = <0>, <&apcs 13>, <&ap !! 283 qcom,ipc-1 = <&apcs 8 13>;
>> 284 qcom,ipc-2 = <&apcs 8 9>;
>> 285 qcom,ipc-3 = <&apcs 8 19>;
298 286
299 apps_smsm: apps@0 { 287 apps_smsm: apps@0 {
300 reg = <0>; 288 reg = <0>;
301 289
302 #qcom,smem-state-cells 290 #qcom,smem-state-cells = <1>;
303 }; 291 };
304 292
305 modem_smsm: modem@1 { 293 modem_smsm: modem@1 {
306 reg = <1>; 294 reg = <1>;
307 interrupts = <GIC_SPI 295 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
308 296
309 interrupt-controller; 297 interrupt-controller;
310 #interrupt-cells = <2> 298 #interrupt-cells = <2>;
311 }; 299 };
312 300
313 adsp_smsm: adsp@2 { 301 adsp_smsm: adsp@2 {
314 reg = <2>; 302 reg = <2>;
315 interrupts = <GIC_SPI 303 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
316 304
317 interrupt-controller; 305 interrupt-controller;
318 #interrupt-cells = <2> 306 #interrupt-cells = <2>;
319 }; 307 };
320 308
321 wcnss_smsm: wcnss@7 { 309 wcnss_smsm: wcnss@7 {
322 reg = <7>; 310 reg = <7>;
323 interrupts = <GIC_SPI 311 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
324 312
325 interrupt-controller; 313 interrupt-controller;
326 #interrupt-cells = <2> 314 #interrupt-cells = <2>;
327 }; 315 };
328 }; 316 };
329 317
330 soc: soc { 318 soc: soc {
331 #address-cells = <1>; 319 #address-cells = <1>;
332 #size-cells = <1>; 320 #size-cells = <1>;
333 ranges; 321 ranges;
334 compatible = "simple-bus"; 322 compatible = "simple-bus";
335 323
336 intc: interrupt-controller@f90 324 intc: interrupt-controller@f9000000 {
337 compatible = "qcom,msm 325 compatible = "qcom,msm-qgic2";
338 interrupt-controller; 326 interrupt-controller;
339 #interrupt-cells = <3> 327 #interrupt-cells = <3>;
340 reg = <0xf9000000 0x10 328 reg = <0xf9000000 0x1000>,
341 <0xf9002000 0x10 329 <0xf9002000 0x1000>;
342 }; 330 };
343 331
344 apcs: mailbox@f9011000 { !! 332 apcs: syscon@f9011000 {
345 compatible = "qcom,msm !! 333 compatible = "syscon";
346 "qcom,msm <<
347 reg = <0xf9011000 0x10 334 reg = <0xf9011000 0x1000>;
348 #mbox-cells = <1>; <<
349 }; <<
350 <<
351 saw_l2: power-manager@f9012000 <<
352 compatible = "qcom,msm <<
353 reg = <0xf9012000 0x10 <<
354 }; <<
355 <<
356 watchdog@f9017000 { <<
357 compatible = "qcom,aps <<
358 reg = <0xf9017000 0x10 <<
359 interrupts = <GIC_SPI <<
360 <GIC_SPI <<
361 clocks = <&sleep_clk>; <<
362 }; 335 };
363 336
364 timer@f9020000 { 337 timer@f9020000 {
365 #address-cells = <1>; 338 #address-cells = <1>;
366 #size-cells = <1>; 339 #size-cells = <1>;
367 ranges; 340 ranges;
368 compatible = "arm,armv 341 compatible = "arm,armv7-timer-mem";
369 reg = <0xf9020000 0x10 342 reg = <0xf9020000 0x1000>;
370 clock-frequency = <192 343 clock-frequency = <19200000>;
371 344
372 frame@f9021000 { 345 frame@f9021000 {
373 frame-number = 346 frame-number = <0>;
374 interrupts = < 347 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
375 < 348 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
376 reg = <0xf9021 349 reg = <0xf9021000 0x1000>,
377 <0xf9022 350 <0xf9022000 0x1000>;
378 }; 351 };
379 352
380 frame@f9023000 { 353 frame@f9023000 {
381 frame-number = 354 frame-number = <1>;
382 interrupts = < 355 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
383 reg = <0xf9023 356 reg = <0xf9023000 0x1000>;
384 status = "disa 357 status = "disabled";
385 }; 358 };
386 359
387 frame@f9024000 { 360 frame@f9024000 {
388 frame-number = 361 frame-number = <2>;
389 interrupts = < 362 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
390 reg = <0xf9024 363 reg = <0xf9024000 0x1000>;
391 status = "disa 364 status = "disabled";
392 }; 365 };
393 366
394 frame@f9025000 { 367 frame@f9025000 {
395 frame-number = 368 frame-number = <3>;
396 interrupts = < 369 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
397 reg = <0xf9025 370 reg = <0xf9025000 0x1000>;
398 status = "disa 371 status = "disabled";
399 }; 372 };
400 373
401 frame@f9026000 { 374 frame@f9026000 {
402 frame-number = 375 frame-number = <4>;
403 interrupts = < 376 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
404 reg = <0xf9026 377 reg = <0xf9026000 0x1000>;
405 status = "disa 378 status = "disabled";
406 }; 379 };
407 380
408 frame@f9027000 { 381 frame@f9027000 {
409 frame-number = 382 frame-number = <5>;
410 interrupts = < 383 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
411 reg = <0xf9027 384 reg = <0xf9027000 0x1000>;
412 status = "disa 385 status = "disabled";
413 }; 386 };
414 387
415 frame@f9028000 { 388 frame@f9028000 {
416 frame-number = 389 frame-number = <6>;
417 interrupts = < 390 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
418 reg = <0xf9028 391 reg = <0xf9028000 0x1000>;
419 status = "disa 392 status = "disabled";
420 }; 393 };
421 }; 394 };
422 395
423 acc0: power-manager@f9088000 { !! 396 saw0: power-controller@f9089000 {
424 compatible = "qcom,kps !! 397 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
425 reg = <0xf9088000 0x10 !! 398 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
426 }; 399 };
427 400
428 saw0: power-manager@f9089000 { !! 401 saw1: power-controller@f9099000 {
429 compatible = "qcom,msm 402 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
430 reg = <0xf9089000 0x10 !! 403 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
431 }; 404 };
432 405
433 acc1: power-manager@f9098000 { !! 406 saw2: power-controller@f90a9000 {
434 compatible = "qcom,kps !! 407 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
435 reg = <0xf9098000 0x10 !! 408 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
436 }; 409 };
437 410
438 saw1: power-manager@f9099000 { !! 411 saw3: power-controller@f90b9000 {
439 compatible = "qcom,msm 412 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
440 reg = <0xf9099000 0x10 !! 413 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
441 }; 414 };
442 415
443 acc2: power-manager@f90a8000 { !! 416 saw_l2: power-controller@f9012000 {
>> 417 compatible = "qcom,saw2";
>> 418 reg = <0xf9012000 0x1000>;
>> 419 regulator;
>> 420 };
>> 421
>> 422 acc0: power-manager@f9088000 {
444 compatible = "qcom,kps 423 compatible = "qcom,kpss-acc-v2";
445 reg = <0xf90a8000 0x10 !! 424 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
446 }; 425 };
447 426
448 saw2: power-manager@f90a9000 { !! 427 acc1: power-manager@f9098000 {
449 compatible = "qcom,msm !! 428 compatible = "qcom,kpss-acc-v2";
450 reg = <0xf90a9000 0x10 !! 429 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
451 }; 430 };
452 431
453 acc3: power-manager@f90b8000 { !! 432 acc2: power-manager@f90a8000 {
454 compatible = "qcom,kps 433 compatible = "qcom,kpss-acc-v2";
455 reg = <0xf90b8000 0x10 !! 434 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
456 }; 435 };
457 436
458 saw3: power-manager@f90b9000 { !! 437 acc3: power-manager@f90b8000 {
459 compatible = "qcom,msm !! 438 compatible = "qcom,kpss-acc-v2";
460 reg = <0xf90b9000 0x10 !! 439 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
461 }; 440 };
462 441
463 sdhc_1: mmc@f9824900 { 442 sdhc_1: mmc@f9824900 {
464 compatible = "qcom,msm 443 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
465 reg = <0xf9824900 0x11 444 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
466 reg-names = "hc", "cor 445 reg-names = "hc", "core";
467 interrupts = <GIC_SPI 446 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 447 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "hc_ 448 interrupt-names = "hc_irq", "pwr_irq";
470 clocks = <&gcc GCC_SDC 449 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
471 <&gcc GCC_SDC 450 <&gcc GCC_SDCC1_APPS_CLK>,
472 <&xo_board>; 451 <&xo_board>;
473 clock-names = "iface", 452 clock-names = "iface", "core", "xo";
474 bus-width = <8>; 453 bus-width = <8>;
475 non-removable; 454 non-removable;
476 455
477 status = "disabled"; 456 status = "disabled";
478 }; 457 };
479 458
480 sdhc_3: mmc@f9864900 { 459 sdhc_3: mmc@f9864900 {
481 compatible = "qcom,msm 460 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
482 reg = <0xf9864900 0x11 461 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
483 reg-names = "hc", "cor 462 reg-names = "hc", "core";
484 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 464 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-names = "hc_ 465 interrupt-names = "hc_irq", "pwr_irq";
487 clocks = <&gcc GCC_SDC 466 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
488 <&gcc GCC_SDC 467 <&gcc GCC_SDCC3_APPS_CLK>,
489 <&xo_board>; 468 <&xo_board>;
490 clock-names = "iface", 469 clock-names = "iface", "core", "xo";
491 bus-width = <4>; 470 bus-width = <4>;
492 471
493 #address-cells = <1>; 472 #address-cells = <1>;
494 #size-cells = <0>; 473 #size-cells = <0>;
495 474
496 status = "disabled"; 475 status = "disabled";
497 }; 476 };
498 477
499 sdhc_2: mmc@f98a4900 { 478 sdhc_2: mmc@f98a4900 {
500 compatible = "qcom,msm 479 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
501 reg = <0xf98a4900 0x11 480 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
502 reg-names = "hc", "cor 481 reg-names = "hc", "core";
503 interrupts = <GIC_SPI 482 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 483 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "hc_ 484 interrupt-names = "hc_irq", "pwr_irq";
506 clocks = <&gcc GCC_SDC 485 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
507 <&gcc GCC_SDC 486 <&gcc GCC_SDCC2_APPS_CLK>,
508 <&xo_board>; 487 <&xo_board>;
509 clock-names = "iface", 488 clock-names = "iface", "core", "xo";
510 bus-width = <4>; 489 bus-width = <4>;
511 490
512 #address-cells = <1>; 491 #address-cells = <1>;
513 #size-cells = <0>; 492 #size-cells = <0>;
514 493
515 status = "disabled"; 494 status = "disabled";
516 }; 495 };
517 496
518 blsp1_uart1: serial@f991d000 { 497 blsp1_uart1: serial@f991d000 {
519 compatible = "qcom,msm 498 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
520 reg = <0xf991d000 0x10 499 reg = <0xf991d000 0x1000>;
521 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gcc GCC_BLS 501 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 502 clock-names = "core", "iface";
524 status = "disabled"; 503 status = "disabled";
525 }; 504 };
526 505
527 blsp1_uart2: serial@f991e000 { 506 blsp1_uart2: serial@f991e000 {
528 compatible = "qcom,msm 507 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
529 reg = <0xf991e000 0x10 508 reg = <0xf991e000 0x1000>;
530 interrupts = <GIC_SPI 509 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&gcc GCC_BLS 510 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
532 clock-names = "core", 511 clock-names = "core", "iface";
533 pinctrl-names = "defau 512 pinctrl-names = "default";
534 pinctrl-0 = <&blsp1_ua 513 pinctrl-0 = <&blsp1_uart2_default>;
535 status = "disabled"; 514 status = "disabled";
536 }; 515 };
537 516
538 blsp1_i2c1: i2c@f9923000 { 517 blsp1_i2c1: i2c@f9923000 {
539 status = "disabled"; 518 status = "disabled";
540 compatible = "qcom,i2c 519 compatible = "qcom,i2c-qup-v2.1.1";
541 reg = <0xf9923000 0x10 520 reg = <0xf9923000 0x1000>;
542 interrupts = <GIC_SPI !! 521 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS 522 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
544 clock-names = "core", 523 clock-names = "core", "iface";
545 pinctrl-names = "defau 524 pinctrl-names = "default", "sleep";
546 pinctrl-0 = <&blsp1_i2 525 pinctrl-0 = <&blsp1_i2c1_default>;
547 pinctrl-1 = <&blsp1_i2 526 pinctrl-1 = <&blsp1_i2c1_sleep>;
548 #address-cells = <1>; 527 #address-cells = <1>;
549 #size-cells = <0>; 528 #size-cells = <0>;
550 }; 529 };
551 530
552 blsp1_i2c2: i2c@f9924000 { 531 blsp1_i2c2: i2c@f9924000 {
553 status = "disabled"; 532 status = "disabled";
554 compatible = "qcom,i2c 533 compatible = "qcom,i2c-qup-v2.1.1";
555 reg = <0xf9924000 0x10 534 reg = <0xf9924000 0x1000>;
556 interrupts = <GIC_SPI 535 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&gcc GCC_BLS 536 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
558 clock-names = "core", 537 clock-names = "core", "iface";
559 pinctrl-names = "defau 538 pinctrl-names = "default", "sleep";
560 pinctrl-0 = <&blsp1_i2 539 pinctrl-0 = <&blsp1_i2c2_default>;
561 pinctrl-1 = <&blsp1_i2 540 pinctrl-1 = <&blsp1_i2c2_sleep>;
562 #address-cells = <1>; 541 #address-cells = <1>;
563 #size-cells = <0>; 542 #size-cells = <0>;
564 }; 543 };
565 544
566 blsp1_i2c3: i2c@f9925000 { 545 blsp1_i2c3: i2c@f9925000 {
567 status = "disabled"; 546 status = "disabled";
568 compatible = "qcom,i2c 547 compatible = "qcom,i2c-qup-v2.1.1";
569 reg = <0xf9925000 0x10 548 reg = <0xf9925000 0x1000>;
570 interrupts = <GIC_SPI !! 549 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc GCC_BLS 550 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
572 clock-names = "core", 551 clock-names = "core", "iface";
573 pinctrl-names = "defau 552 pinctrl-names = "default", "sleep";
574 pinctrl-0 = <&blsp1_i2 553 pinctrl-0 = <&blsp1_i2c3_default>;
575 pinctrl-1 = <&blsp1_i2 554 pinctrl-1 = <&blsp1_i2c3_sleep>;
576 #address-cells = <1>; 555 #address-cells = <1>;
577 #size-cells = <0>; 556 #size-cells = <0>;
578 }; 557 };
579 558
580 blsp1_i2c6: i2c@f9928000 { 559 blsp1_i2c6: i2c@f9928000 {
581 status = "disabled"; 560 status = "disabled";
582 compatible = "qcom,i2c 561 compatible = "qcom,i2c-qup-v2.1.1";
583 reg = <0xf9928000 0x10 562 reg = <0xf9928000 0x1000>;
584 interrupts = <GIC_SPI 563 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&gcc GCC_BLS 564 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
586 clock-names = "core", 565 clock-names = "core", "iface";
587 pinctrl-names = "defau 566 pinctrl-names = "default", "sleep";
588 pinctrl-0 = <&blsp1_i2 567 pinctrl-0 = <&blsp1_i2c6_default>;
589 pinctrl-1 = <&blsp1_i2 568 pinctrl-1 = <&blsp1_i2c6_sleep>;
590 #address-cells = <1>; 569 #address-cells = <1>;
591 #size-cells = <0>; 570 #size-cells = <0>;
592 }; 571 };
593 572
594 blsp2_dma: dma-controller@f994 573 blsp2_dma: dma-controller@f9944000 {
595 compatible = "qcom,bam 574 compatible = "qcom,bam-v1.4.0";
596 reg = <0xf9944000 0x19 575 reg = <0xf9944000 0x19000>;
597 interrupts = <GIC_SPI 576 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS 577 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
599 clock-names = "bam_clk 578 clock-names = "bam_clk";
600 #dma-cells = <1>; 579 #dma-cells = <1>;
601 qcom,ee = <0>; 580 qcom,ee = <0>;
602 }; 581 };
603 582
604 blsp2_uart1: serial@f995d000 { 583 blsp2_uart1: serial@f995d000 {
605 compatible = "qcom,msm 584 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606 reg = <0xf995d000 0x10 585 reg = <0xf995d000 0x1000>;
607 interrupts = <GIC_SPI 586 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GCC_BLS 587 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
609 clock-names = "core", 588 clock-names = "core", "iface";
610 pinctrl-names = "defau 589 pinctrl-names = "default", "sleep";
611 pinctrl-0 = <&blsp2_ua 590 pinctrl-0 = <&blsp2_uart1_default>;
612 pinctrl-1 = <&blsp2_ua 591 pinctrl-1 = <&blsp2_uart1_sleep>;
613 status = "disabled"; 592 status = "disabled";
614 }; 593 };
615 594
616 blsp2_uart2: serial@f995e000 { 595 blsp2_uart2: serial@f995e000 {
617 compatible = "qcom,msm 596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
618 reg = <0xf995e000 0x10 597 reg = <0xf995e000 0x1000>;
619 interrupts = <GIC_SPI 598 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&gcc GCC_BLS 599 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
621 clock-names = "core", 600 clock-names = "core", "iface";
622 status = "disabled"; 601 status = "disabled";
623 }; 602 };
624 603
625 blsp2_uart4: serial@f9960000 { 604 blsp2_uart4: serial@f9960000 {
626 compatible = "qcom,msm 605 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
627 reg = <0xf9960000 0x10 606 reg = <0xf9960000 0x1000>;
628 interrupts = <GIC_SPI 607 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&gcc GCC_BLS 608 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
630 clock-names = "core", 609 clock-names = "core", "iface";
631 pinctrl-names = "defau 610 pinctrl-names = "default";
632 pinctrl-0 = <&blsp2_ua 611 pinctrl-0 = <&blsp2_uart4_default>;
633 status = "disabled"; 612 status = "disabled";
634 }; 613 };
635 614
636 blsp2_i2c2: i2c@f9964000 { 615 blsp2_i2c2: i2c@f9964000 {
637 status = "disabled"; 616 status = "disabled";
638 compatible = "qcom,i2c 617 compatible = "qcom,i2c-qup-v2.1.1";
639 reg = <0xf9964000 0x10 618 reg = <0xf9964000 0x1000>;
640 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&gcc GCC_BLS 620 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
642 clock-names = "core", 621 clock-names = "core", "iface";
643 pinctrl-names = "defau 622 pinctrl-names = "default", "sleep";
644 pinctrl-0 = <&blsp2_i2 623 pinctrl-0 = <&blsp2_i2c2_default>;
645 pinctrl-1 = <&blsp2_i2 624 pinctrl-1 = <&blsp2_i2c2_sleep>;
646 #address-cells = <1>; 625 #address-cells = <1>;
647 #size-cells = <0>; 626 #size-cells = <0>;
648 }; 627 };
649 628
650 blsp2_i2c5: i2c@f9967000 { 629 blsp2_i2c5: i2c@f9967000 {
651 status = "disabled"; 630 status = "disabled";
652 compatible = "qcom,i2c 631 compatible = "qcom,i2c-qup-v2.1.1";
653 reg = <0xf9967000 0x10 632 reg = <0xf9967000 0x1000>;
654 interrupts = <GIC_SPI 633 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&gcc GCC_BLS 634 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
656 clock-names = "core", 635 clock-names = "core", "iface";
657 dmas = <&blsp2_dma 20> 636 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
658 dma-names = "tx", "rx" 637 dma-names = "tx", "rx";
659 pinctrl-names = "defau 638 pinctrl-names = "default", "sleep";
660 pinctrl-0 = <&blsp2_i2 639 pinctrl-0 = <&blsp2_i2c5_default>;
661 pinctrl-1 = <&blsp2_i2 640 pinctrl-1 = <&blsp2_i2c5_sleep>;
662 #address-cells = <1>; 641 #address-cells = <1>;
663 #size-cells = <0>; 642 #size-cells = <0>;
664 }; 643 };
665 644
666 blsp2_i2c6: i2c@f9968000 { 645 blsp2_i2c6: i2c@f9968000 {
667 status = "disabled"; 646 status = "disabled";
668 compatible = "qcom,i2c 647 compatible = "qcom,i2c-qup-v2.1.1";
669 reg = <0xf9968000 0x10 648 reg = <0xf9968000 0x1000>;
670 interrupts = <GIC_SPI !! 649 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&gcc GCC_BLS 650 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
672 clock-names = "core", 651 clock-names = "core", "iface";
673 pinctrl-names = "defau 652 pinctrl-names = "default", "sleep";
674 pinctrl-0 = <&blsp2_i2 653 pinctrl-0 = <&blsp2_i2c6_default>;
675 pinctrl-1 = <&blsp2_i2 654 pinctrl-1 = <&blsp2_i2c6_sleep>;
676 #address-cells = <1>; 655 #address-cells = <1>;
677 #size-cells = <0>; 656 #size-cells = <0>;
678 }; 657 };
679 658
680 usb: usb@f9a55000 { 659 usb: usb@f9a55000 {
681 compatible = "qcom,ci- 660 compatible = "qcom,ci-hdrc";
682 reg = <0xf9a55000 0x20 661 reg = <0xf9a55000 0x200>,
683 <0xf9a55200 0x20 662 <0xf9a55200 0x200>;
684 interrupts = <GIC_SPI 663 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&gcc GCC_USB 664 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
686 <&gcc GCC_USB 665 <&gcc GCC_USB_HS_SYSTEM_CLK>;
687 clock-names = "iface", 666 clock-names = "iface", "core";
688 assigned-clocks = <&gc 667 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
689 assigned-clock-rates = 668 assigned-clock-rates = <75000000>;
690 resets = <&gcc GCC_USB 669 resets = <&gcc GCC_USB_HS_BCR>;
691 reset-names = "core"; 670 reset-names = "core";
692 phy_type = "ulpi"; 671 phy_type = "ulpi";
693 dr_mode = "otg"; 672 dr_mode = "otg";
694 ahb-burst-config = <0> 673 ahb-burst-config = <0>;
695 phy-names = "usb-phy"; 674 phy-names = "usb-phy";
696 status = "disabled"; 675 status = "disabled";
697 #reset-cells = <1>; 676 #reset-cells = <1>;
698 677
699 ulpi { 678 ulpi {
700 usb_hs1_phy: p 679 usb_hs1_phy: phy-0 {
701 compat 680 compatible = "qcom,usb-hs-phy-msm8974",
702 681 "qcom,usb-hs-phy";
703 #phy-c 682 #phy-cells = <0>;
704 clocks 683 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
705 clock- 684 clock-names = "ref", "sleep";
706 resets 685 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
707 reset- 686 reset-names = "phy", "por";
708 status 687 status = "disabled";
709 }; 688 };
710 689
711 usb_hs2_phy: p 690 usb_hs2_phy: phy-1 {
712 compat 691 compatible = "qcom,usb-hs-phy-msm8974",
713 692 "qcom,usb-hs-phy";
714 #phy-c 693 #phy-cells = <0>;
715 clocks 694 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
716 clock- 695 clock-names = "ref", "sleep";
717 resets 696 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
718 reset- 697 reset-names = "phy", "por";
719 status 698 status = "disabled";
720 }; 699 };
721 }; 700 };
722 }; 701 };
723 702
724 rng@f9bff000 { 703 rng@f9bff000 {
725 compatible = "qcom,prn 704 compatible = "qcom,prng";
726 reg = <0xf9bff000 0x20 705 reg = <0xf9bff000 0x200>;
727 clocks = <&gcc GCC_PRN 706 clocks = <&gcc GCC_PRNG_AHB_CLK>;
728 clock-names = "core"; 707 clock-names = "core";
729 }; 708 };
730 709
731 pronto: remoteproc@fb204000 { 710 pronto: remoteproc@fb204000 {
732 compatible = "qcom,pro 711 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
733 reg = <0xfb204000 0x20 712 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
734 reg-names = "ccu", "dx 713 reg-names = "ccu", "dxe", "pmu";
735 714
736 memory-region = <&wcns 715 memory-region = <&wcnss_region>;
737 716
738 interrupts-extended = 717 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
739 718 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
740 719 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
741 720 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
742 721 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
743 interrupt-names = "wdo 722 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
744 723
745 qcom,smem-states = <&w 724 qcom,smem-states = <&wcnss_smp2p_out 0>;
746 qcom,smem-state-names 725 qcom,smem-state-names = "stop";
747 726
748 status = "disabled"; 727 status = "disabled";
749 728
750 iris { 729 iris {
751 compatible = " 730 compatible = "qcom,wcn3680";
752 731
753 clocks = <&rpm 732 clocks = <&rpmcc RPM_SMD_CXO_A2>;
754 clock-names = 733 clock-names = "xo";
755 }; 734 };
756 735
757 smd-edge { 736 smd-edge {
758 interrupts = < 737 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
759 738
760 mboxes = <&apc !! 739 qcom,ipc = <&apcs 8 17>;
761 qcom,smd-edge 740 qcom,smd-edge = <6>;
762 741
763 wcnss { 742 wcnss {
764 compat 743 compatible = "qcom,wcnss";
765 qcom,s 744 qcom,smd-channels = "WCNSS_CTRL";
766 status 745 status = "disabled";
767 746
768 qcom,m 747 qcom,mmio = <&pronto>;
769 748
770 blueto 749 bluetooth {
771 750 compatible = "qcom,wcnss-bt";
772 }; 751 };
773 752
774 wifi { 753 wifi {
775 754 compatible = "qcom,wcnss-wlan";
776 755
777 756 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
778 757 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
779 758 interrupt-names = "tx", "rx";
780 759
781 760 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
782 761 qcom,smem-state-names = "tx-enable",
783 762 "tx-rings-empty";
784 }; 763 };
785 }; 764 };
786 }; 765 };
787 }; 766 };
788 767
789 sram@fc190000 { 768 sram@fc190000 {
790 compatible = "qcom,msm 769 compatible = "qcom,msm8974-rpm-stats";
791 reg = <0xfc190000 0x10 770 reg = <0xfc190000 0x10000>;
792 }; 771 };
793 772
794 etf@fc307000 { 773 etf@fc307000 {
795 compatible = "arm,core 774 compatible = "arm,coresight-tmc", "arm,primecell";
796 reg = <0xfc307000 0x10 775 reg = <0xfc307000 0x1000>;
797 776
798 clocks = <&rpmcc RPM_S 777 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
799 clock-names = "apb_pcl 778 clock-names = "apb_pclk", "atclk";
800 779
801 out-ports { 780 out-ports {
802 port { 781 port {
803 etf_ou 782 etf_out: endpoint {
804 783 remote-endpoint = <&replicator_in>;
805 }; 784 };
806 }; 785 };
807 }; 786 };
808 787
809 in-ports { 788 in-ports {
810 port { 789 port {
811 etf_in 790 etf_in: endpoint {
812 791 remote-endpoint = <&merger_out>;
813 }; 792 };
814 }; 793 };
815 }; 794 };
816 }; 795 };
817 796
818 tpiu@fc318000 { 797 tpiu@fc318000 {
819 compatible = "arm,core 798 compatible = "arm,coresight-tpiu", "arm,primecell";
820 reg = <0xfc318000 0x10 799 reg = <0xfc318000 0x1000>;
821 800
822 clocks = <&rpmcc RPM_S 801 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
823 clock-names = "apb_pcl 802 clock-names = "apb_pclk", "atclk";
824 803
825 in-ports { 804 in-ports {
826 port { 805 port {
827 tpiu_i 806 tpiu_in: endpoint {
828 807 remote-endpoint = <&replicator_out1>;
829 }; 808 };
830 }; 809 };
831 }; 810 };
832 }; 811 };
833 812
834 funnel@fc31a000 { 813 funnel@fc31a000 {
835 compatible = "arm,core 814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
836 reg = <0xfc31a000 0x10 815 reg = <0xfc31a000 0x1000>;
837 816
838 clocks = <&rpmcc RPM_S 817 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
839 clock-names = "apb_pcl 818 clock-names = "apb_pclk", "atclk";
840 819
841 in-ports { 820 in-ports {
842 #address-cells 821 #address-cells = <1>;
843 #size-cells = 822 #size-cells = <0>;
844 823
845 /* 824 /*
846 * Not describ 825 * Not described input ports:
847 * 0 - not-con 826 * 0 - not-connected
848 * 1 - connect 827 * 1 - connected trought funnel to Multimedia CPU
849 * 2 - connect 828 * 2 - connected to Wireless CPU
850 * 3 - not-con 829 * 3 - not-connected
851 * 4 - not-con 830 * 4 - not-connected
852 * 6 - not-con 831 * 6 - not-connected
853 * 7 - connect 832 * 7 - connected to STM
854 */ 833 */
855 port@5 { 834 port@5 {
856 reg = 835 reg = <5>;
857 funnel 836 funnel1_in5: endpoint {
858 837 remote-endpoint = <&kpss_out>;
859 }; 838 };
860 }; 839 };
861 }; 840 };
862 841
863 out-ports { 842 out-ports {
864 port { 843 port {
865 funnel 844 funnel1_out: endpoint {
866 845 remote-endpoint = <&merger_in1>;
867 }; 846 };
868 }; 847 };
869 }; 848 };
870 }; 849 };
871 850
872 funnel@fc31b000 { 851 funnel@fc31b000 {
873 compatible = "arm,core 852 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
874 reg = <0xfc31b000 0x10 853 reg = <0xfc31b000 0x1000>;
875 854
876 clocks = <&rpmcc RPM_S 855 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
877 clock-names = "apb_pcl 856 clock-names = "apb_pclk", "atclk";
878 857
879 in-ports { 858 in-ports {
880 #address-cells 859 #address-cells = <1>;
881 #size-cells = 860 #size-cells = <0>;
882 861
883 /* 862 /*
884 * Not describ 863 * Not described input ports:
885 * 0 - connect 864 * 0 - connected trought funnel to Audio, Modem and
886 * Resourc 865 * Resource and Power Manager CPU's
887 * 2...7 - not 866 * 2...7 - not-connected
888 */ 867 */
889 port@1 { 868 port@1 {
890 reg = 869 reg = <1>;
891 merger 870 merger_in1: endpoint {
892 871 remote-endpoint = <&funnel1_out>;
893 }; 872 };
894 }; 873 };
895 }; 874 };
896 875
897 out-ports { 876 out-ports {
898 port { 877 port {
899 merger 878 merger_out: endpoint {
900 879 remote-endpoint = <&etf_in>;
901 }; 880 };
902 }; 881 };
903 }; 882 };
904 }; 883 };
905 884
906 replicator@fc31c000 { 885 replicator@fc31c000 {
907 compatible = "arm,core 886 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
908 reg = <0xfc31c000 0x10 887 reg = <0xfc31c000 0x1000>;
909 888
910 clocks = <&rpmcc RPM_S 889 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
911 clock-names = "apb_pcl 890 clock-names = "apb_pclk", "atclk";
912 891
913 out-ports { 892 out-ports {
914 #address-cells 893 #address-cells = <1>;
915 #size-cells = 894 #size-cells = <0>;
916 895
917 port@0 { 896 port@0 {
918 reg = 897 reg = <0>;
919 replic 898 replicator_out0: endpoint {
920 899 remote-endpoint = <&etr_in>;
921 }; 900 };
922 }; 901 };
923 port@1 { 902 port@1 {
924 reg = 903 reg = <1>;
925 replic 904 replicator_out1: endpoint {
926 905 remote-endpoint = <&tpiu_in>;
927 }; 906 };
928 }; 907 };
929 }; 908 };
930 909
931 in-ports { 910 in-ports {
932 port { 911 port {
933 replic 912 replicator_in: endpoint {
934 913 remote-endpoint = <&etf_out>;
935 }; 914 };
936 }; 915 };
937 }; 916 };
938 }; 917 };
939 918
940 etr@fc322000 { 919 etr@fc322000 {
941 compatible = "arm,core 920 compatible = "arm,coresight-tmc", "arm,primecell";
942 reg = <0xfc322000 0x10 921 reg = <0xfc322000 0x1000>;
943 922
944 clocks = <&rpmcc RPM_S 923 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
945 clock-names = "apb_pcl 924 clock-names = "apb_pclk", "atclk";
946 925
947 in-ports { 926 in-ports {
948 port { 927 port {
949 etr_in 928 etr_in: endpoint {
950 929 remote-endpoint = <&replicator_out0>;
951 }; 930 };
952 }; 931 };
953 }; 932 };
954 }; 933 };
955 934
956 etm@fc33c000 { 935 etm@fc33c000 {
957 compatible = "arm,core 936 compatible = "arm,coresight-etm4x", "arm,primecell";
958 reg = <0xfc33c000 0x10 937 reg = <0xfc33c000 0x1000>;
959 938
960 clocks = <&rpmcc RPM_S 939 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
961 clock-names = "apb_pcl 940 clock-names = "apb_pclk", "atclk";
962 941
963 cpu = <&CPU0>; 942 cpu = <&CPU0>;
964 943
965 out-ports { 944 out-ports {
966 port { 945 port {
967 etm0_o 946 etm0_out: endpoint {
968 947 remote-endpoint = <&kpss_in0>;
969 }; 948 };
970 }; 949 };
971 }; 950 };
972 }; 951 };
973 952
974 etm@fc33d000 { 953 etm@fc33d000 {
975 compatible = "arm,core 954 compatible = "arm,coresight-etm4x", "arm,primecell";
976 reg = <0xfc33d000 0x10 955 reg = <0xfc33d000 0x1000>;
977 956
978 clocks = <&rpmcc RPM_S 957 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
979 clock-names = "apb_pcl 958 clock-names = "apb_pclk", "atclk";
980 959
981 cpu = <&CPU1>; 960 cpu = <&CPU1>;
982 961
983 out-ports { 962 out-ports {
984 port { 963 port {
985 etm1_o 964 etm1_out: endpoint {
986 965 remote-endpoint = <&kpss_in1>;
987 }; 966 };
988 }; 967 };
989 }; 968 };
990 }; 969 };
991 970
992 etm@fc33e000 { 971 etm@fc33e000 {
993 compatible = "arm,core 972 compatible = "arm,coresight-etm4x", "arm,primecell";
994 reg = <0xfc33e000 0x10 973 reg = <0xfc33e000 0x1000>;
995 974
996 clocks = <&rpmcc RPM_S 975 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
997 clock-names = "apb_pcl 976 clock-names = "apb_pclk", "atclk";
998 977
999 cpu = <&CPU2>; 978 cpu = <&CPU2>;
1000 979
1001 out-ports { 980 out-ports {
1002 port { 981 port {
1003 etm2_ 982 etm2_out: endpoint {
1004 983 remote-endpoint = <&kpss_in2>;
1005 }; 984 };
1006 }; 985 };
1007 }; 986 };
1008 }; 987 };
1009 988
1010 etm@fc33f000 { 989 etm@fc33f000 {
1011 compatible = "arm,cor 990 compatible = "arm,coresight-etm4x", "arm,primecell";
1012 reg = <0xfc33f000 0x1 991 reg = <0xfc33f000 0x1000>;
1013 992
1014 clocks = <&rpmcc RPM_ 993 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1015 clock-names = "apb_pc 994 clock-names = "apb_pclk", "atclk";
1016 995
1017 cpu = <&CPU3>; 996 cpu = <&CPU3>;
1018 997
1019 out-ports { 998 out-ports {
1020 port { 999 port {
1021 etm3_ 1000 etm3_out: endpoint {
1022 1001 remote-endpoint = <&kpss_in3>;
1023 }; 1002 };
1024 }; 1003 };
1025 }; 1004 };
1026 }; 1005 };
1027 1006
1028 /* KPSS funnel, only 4 inputs 1007 /* KPSS funnel, only 4 inputs are used */
1029 funnel@fc345000 { 1008 funnel@fc345000 {
1030 compatible = "arm,cor 1009 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1031 reg = <0xfc345000 0x1 1010 reg = <0xfc345000 0x1000>;
1032 1011
1033 clocks = <&rpmcc RPM_ 1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1034 clock-names = "apb_pc 1013 clock-names = "apb_pclk", "atclk";
1035 1014
1036 in-ports { 1015 in-ports {
1037 #address-cell 1016 #address-cells = <1>;
1038 #size-cells = 1017 #size-cells = <0>;
1039 1018
1040 port@0 { 1019 port@0 {
1041 reg = 1020 reg = <0>;
1042 kpss_ 1021 kpss_in0: endpoint {
1043 1022 remote-endpoint = <&etm0_out>;
1044 }; 1023 };
1045 }; 1024 };
1046 port@1 { 1025 port@1 {
1047 reg = 1026 reg = <1>;
1048 kpss_ 1027 kpss_in1: endpoint {
1049 1028 remote-endpoint = <&etm1_out>;
1050 }; 1029 };
1051 }; 1030 };
1052 port@2 { 1031 port@2 {
1053 reg = 1032 reg = <2>;
1054 kpss_ 1033 kpss_in2: endpoint {
1055 1034 remote-endpoint = <&etm2_out>;
1056 }; 1035 };
1057 }; 1036 };
1058 port@3 { 1037 port@3 {
1059 reg = 1038 reg = <3>;
1060 kpss_ 1039 kpss_in3: endpoint {
1061 1040 remote-endpoint = <&etm3_out>;
1062 }; 1041 };
1063 }; 1042 };
1064 }; 1043 };
1065 1044
1066 out-ports { 1045 out-ports {
1067 port { 1046 port {
1068 kpss_ 1047 kpss_out: endpoint {
1069 1048 remote-endpoint = <&funnel1_in5>;
1070 }; 1049 };
1071 }; 1050 };
1072 }; 1051 };
1073 }; 1052 };
1074 1053
1075 bimc: interconnect@fc380000 { <<
1076 reg = <0xfc380000 0x6 <<
1077 compatible = "qcom,ms <<
1078 #interconnect-cells = <<
1079 clock-names = "bus", <<
1080 clocks = <&rpmcc RPM_ <<
1081 <&rpmcc RPM_ <<
1082 }; <<
1083 <<
1084 gcc: clock-controller@fc40000 1054 gcc: clock-controller@fc400000 {
1085 compatible = "qcom,gc 1055 compatible = "qcom,gcc-msm8974";
1086 #clock-cells = <1>; 1056 #clock-cells = <1>;
1087 #reset-cells = <1>; 1057 #reset-cells = <1>;
1088 #power-domain-cells = 1058 #power-domain-cells = <1>;
1089 reg = <0xfc400000 0x4 1059 reg = <0xfc400000 0x4000>;
1090 1060
1091 clocks = <&rpmcc RPM_ 1061 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1092 <&sleep_clk> 1062 <&sleep_clk>;
1093 clock-names = "xo", 1063 clock-names = "xo",
1094 "sleep_ 1064 "sleep_clk";
1095 }; 1065 };
1096 1066
1097 rpm_msg_ram: sram@fc428000 { 1067 rpm_msg_ram: sram@fc428000 {
1098 compatible = "qcom,rp 1068 compatible = "qcom,rpm-msg-ram";
1099 reg = <0xfc428000 0x4 1069 reg = <0xfc428000 0x4000>;
>> 1070 };
1100 1071
1101 #address-cells = <1>; !! 1072 bimc: interconnect@fc380000 {
1102 #size-cells = <1>; !! 1073 reg = <0xfc380000 0x6a000>;
1103 ranges = <0 0xfc42800 !! 1074 compatible = "qcom,msm8974-bimc";
1104 !! 1075 #interconnect-cells = <1>;
1105 apss_master_stats: sr !! 1076 clock-names = "bus", "bus_a";
1106 reg = <0x150 !! 1077 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1107 }; !! 1078 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1108 <<
1109 mpss_master_stats: sr <<
1110 reg = <0xb50 <<
1111 }; <<
1112 <<
1113 lpss_master_stats: sr <<
1114 reg = <0x1550 <<
1115 }; <<
1116 <<
1117 pronto_master_stats: <<
1118 reg = <0x1f50 <<
1119 }; <<
1120 }; 1079 };
1121 1080
1122 snoc: interconnect@fc460000 { 1081 snoc: interconnect@fc460000 {
1123 reg = <0xfc460000 0x4 1082 reg = <0xfc460000 0x4000>;
1124 compatible = "qcom,ms 1083 compatible = "qcom,msm8974-snoc";
1125 #interconnect-cells = 1084 #interconnect-cells = <1>;
1126 clock-names = "bus", 1085 clock-names = "bus", "bus_a";
1127 clocks = <&rpmcc RPM_ 1086 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1128 <&rpmcc RPM_ !! 1087 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1129 }; 1088 };
1130 1089
1131 pnoc: interconnect@fc468000 { 1090 pnoc: interconnect@fc468000 {
1132 reg = <0xfc468000 0x4 1091 reg = <0xfc468000 0x4000>;
1133 compatible = "qcom,ms 1092 compatible = "qcom,msm8974-pnoc";
1134 #interconnect-cells = 1093 #interconnect-cells = <1>;
1135 clock-names = "bus", 1094 clock-names = "bus", "bus_a";
1136 clocks = <&rpmcc RPM_ 1095 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1137 <&rpmcc RPM_ !! 1096 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1138 }; 1097 };
1139 1098
1140 ocmemnoc: interconnect@fc4700 1099 ocmemnoc: interconnect@fc470000 {
1141 reg = <0xfc470000 0x4 1100 reg = <0xfc470000 0x4000>;
1142 compatible = "qcom,ms 1101 compatible = "qcom,msm8974-ocmemnoc";
1143 #interconnect-cells = 1102 #interconnect-cells = <1>;
1144 clock-names = "bus", 1103 clock-names = "bus", "bus_a";
1145 clocks = <&rpmcc RPM_ 1104 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1146 <&rpmcc RPM_ !! 1105 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1147 }; 1106 };
1148 1107
1149 mmssnoc: interconnect@fc47800 1108 mmssnoc: interconnect@fc478000 {
1150 reg = <0xfc478000 0x4 1109 reg = <0xfc478000 0x4000>;
1151 compatible = "qcom,ms 1110 compatible = "qcom,msm8974-mmssnoc";
1152 #interconnect-cells = 1111 #interconnect-cells = <1>;
1153 clock-names = "bus", 1112 clock-names = "bus", "bus_a";
1154 clocks = <&mmcc MMSS_ 1113 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1155 <&mmcc MMSS_ !! 1114 <&mmcc MMSS_S0_AXI_CLK>;
1156 }; 1115 };
1157 1116
1158 cnoc: interconnect@fc480000 { 1117 cnoc: interconnect@fc480000 {
1159 reg = <0xfc480000 0x4 1118 reg = <0xfc480000 0x4000>;
1160 compatible = "qcom,ms 1119 compatible = "qcom,msm8974-cnoc";
1161 #interconnect-cells = 1120 #interconnect-cells = <1>;
1162 clock-names = "bus", 1121 clock-names = "bus", "bus_a";
1163 clocks = <&rpmcc RPM_ 1122 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1164 <&rpmcc RPM_ !! 1123 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1165 }; 1124 };
1166 1125
1167 tsens: thermal-sensor@fc4a900 1126 tsens: thermal-sensor@fc4a9000 {
1168 compatible = "qcom,ms 1127 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1169 reg = <0xfc4a9000 0x1 1128 reg = <0xfc4a9000 0x1000>, /* TM */
1170 <0xfc4a8000 0x1 1129 <0xfc4a8000 0x1000>; /* SROT */
1171 nvmem-cells = <&tsens 1130 nvmem-cells = <&tsens_mode>,
1172 <&tsens 1131 <&tsens_base1>, <&tsens_base2>,
1173 <&tsens 1132 <&tsens_use_backup>,
1174 <&tsens 1133 <&tsens_mode_backup>,
1175 <&tsens 1134 <&tsens_base1_backup>, <&tsens_base2_backup>,
1176 <&tsens 1135 <&tsens_s0_p1>, <&tsens_s0_p2>,
1177 <&tsens 1136 <&tsens_s1_p1>, <&tsens_s1_p2>,
1178 <&tsens 1137 <&tsens_s2_p1>, <&tsens_s2_p2>,
1179 <&tsens 1138 <&tsens_s3_p1>, <&tsens_s3_p2>,
1180 <&tsens 1139 <&tsens_s4_p1>, <&tsens_s4_p2>,
1181 <&tsens 1140 <&tsens_s5_p1>, <&tsens_s5_p2>,
1182 <&tsens 1141 <&tsens_s6_p1>, <&tsens_s6_p2>,
1183 <&tsens 1142 <&tsens_s7_p1>, <&tsens_s7_p2>,
1184 <&tsens 1143 <&tsens_s8_p1>, <&tsens_s8_p2>,
1185 <&tsens 1144 <&tsens_s9_p1>, <&tsens_s9_p2>,
1186 <&tsens 1145 <&tsens_s10_p1>, <&tsens_s10_p2>,
1187 <&tsens 1146 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1188 <&tsens 1147 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1189 <&tsens 1148 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1190 <&tsens 1149 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1191 <&tsens 1150 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1192 <&tsens 1151 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1193 <&tsens 1152 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1194 <&tsens 1153 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1195 <&tsens 1154 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1196 <&tsens 1155 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1197 <&tsens 1156 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1198 nvmem-cell-names = "m 1157 nvmem-cell-names = "mode",
1199 "b 1158 "base1", "base2",
1200 "u 1159 "use_backup",
1201 "m 1160 "mode_backup",
1202 "b 1161 "base1_backup", "base2_backup",
1203 "s 1162 "s0_p1", "s0_p2",
1204 "s 1163 "s1_p1", "s1_p2",
1205 "s 1164 "s2_p1", "s2_p2",
1206 "s 1165 "s3_p1", "s3_p2",
1207 "s 1166 "s4_p1", "s4_p2",
1208 "s 1167 "s5_p1", "s5_p2",
1209 "s 1168 "s6_p1", "s6_p2",
1210 "s 1169 "s7_p1", "s7_p2",
1211 "s 1170 "s8_p1", "s8_p2",
1212 "s 1171 "s9_p1", "s9_p2",
1213 "s 1172 "s10_p1", "s10_p2",
1214 "s 1173 "s0_p1_backup", "s0_p2_backup",
1215 "s 1174 "s1_p1_backup", "s1_p2_backup",
1216 "s 1175 "s2_p1_backup", "s2_p2_backup",
1217 "s 1176 "s3_p1_backup", "s3_p2_backup",
1218 "s 1177 "s4_p1_backup", "s4_p2_backup",
1219 "s 1178 "s5_p1_backup", "s5_p2_backup",
1220 "s 1179 "s6_p1_backup", "s6_p2_backup",
1221 "s 1180 "s7_p1_backup", "s7_p2_backup",
1222 "s 1181 "s8_p1_backup", "s8_p2_backup",
1223 "s 1182 "s9_p1_backup", "s9_p2_backup",
1224 "s 1183 "s10_p1_backup", "s10_p2_backup";
1225 #qcom,sensors = <11>; 1184 #qcom,sensors = <11>;
1226 interrupts = <GIC_SPI 1185 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "up 1186 interrupt-names = "uplow";
1228 #thermal-sensor-cells 1187 #thermal-sensor-cells = <1>;
1229 }; 1188 };
1230 1189
1231 restart@fc4ab000 { 1190 restart@fc4ab000 {
1232 compatible = "qcom,ps 1191 compatible = "qcom,pshold";
1233 reg = <0xfc4ab000 0x4 1192 reg = <0xfc4ab000 0x4>;
1234 }; 1193 };
1235 1194
1236 qfprom: efuse@fc4bc000 { !! 1195 qfprom: qfprom@fc4bc000 {
1237 compatible = "qcom,ms 1196 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1238 reg = <0xfc4bc000 0x2 1197 reg = <0xfc4bc000 0x2100>;
1239 #address-cells = <1>; 1198 #address-cells = <1>;
1240 #size-cells = <1>; 1199 #size-cells = <1>;
1241 1200
1242 tsens_base1: base1@d0 1201 tsens_base1: base1@d0 {
1243 reg = <0xd0 0 1202 reg = <0xd0 0x1>;
1244 bits = <0 8>; 1203 bits = <0 8>;
1245 }; 1204 };
1246 1205
1247 tsens_s0_p1: s0-p1@d1 1206 tsens_s0_p1: s0-p1@d1 {
1248 reg = <0xd1 0 1207 reg = <0xd1 0x1>;
1249 bits = <0 6>; 1208 bits = <0 6>;
1250 }; 1209 };
1251 1210
1252 tsens_s1_p1: s1-p1@d2 1211 tsens_s1_p1: s1-p1@d2 {
1253 reg = <0xd1 0 1212 reg = <0xd1 0x2>;
1254 bits = <6 6>; 1213 bits = <6 6>;
1255 }; 1214 };
1256 1215
1257 tsens_s2_p1: s2-p1@d2 1216 tsens_s2_p1: s2-p1@d2 {
1258 reg = <0xd2 0 1217 reg = <0xd2 0x2>;
1259 bits = <4 6>; 1218 bits = <4 6>;
1260 }; 1219 };
1261 1220
1262 tsens_s3_p1: s3-p1@d3 1221 tsens_s3_p1: s3-p1@d3 {
1263 reg = <0xd3 0 1222 reg = <0xd3 0x1>;
1264 bits = <2 6>; 1223 bits = <2 6>;
1265 }; 1224 };
1266 1225
1267 tsens_s4_p1: s4-p1@d4 1226 tsens_s4_p1: s4-p1@d4 {
1268 reg = <0xd4 0 1227 reg = <0xd4 0x1>;
1269 bits = <0 6>; 1228 bits = <0 6>;
1270 }; 1229 };
1271 1230
1272 tsens_s5_p1: s5-p1@d4 1231 tsens_s5_p1: s5-p1@d4 {
1273 reg = <0xd4 0 1232 reg = <0xd4 0x2>;
1274 bits = <6 6>; 1233 bits = <6 6>;
1275 }; 1234 };
1276 1235
1277 tsens_s6_p1: s6-p1@d5 1236 tsens_s6_p1: s6-p1@d5 {
1278 reg = <0xd5 0 1237 reg = <0xd5 0x2>;
1279 bits = <4 6>; 1238 bits = <4 6>;
1280 }; 1239 };
1281 1240
1282 tsens_s7_p1: s7-p1@d6 1241 tsens_s7_p1: s7-p1@d6 {
1283 reg = <0xd6 0 1242 reg = <0xd6 0x1>;
1284 bits = <2 6>; 1243 bits = <2 6>;
1285 }; 1244 };
1286 1245
1287 tsens_s8_p1: s8-p1@d7 1246 tsens_s8_p1: s8-p1@d7 {
1288 reg = <0xd7 0 1247 reg = <0xd7 0x1>;
1289 bits = <0 6>; 1248 bits = <0 6>;
1290 }; 1249 };
1291 1250
1292 tsens_mode: mode@d7 { 1251 tsens_mode: mode@d7 {
1293 reg = <0xd7 0 1252 reg = <0xd7 0x1>;
1294 bits = <6 2>; 1253 bits = <6 2>;
1295 }; 1254 };
1296 1255
1297 tsens_s9_p1: s9-p1@d8 1256 tsens_s9_p1: s9-p1@d8 {
1298 reg = <0xd8 0 1257 reg = <0xd8 0x1>;
1299 bits = <0 6>; 1258 bits = <0 6>;
1300 }; 1259 };
1301 1260
1302 tsens_s10_p1: s10_p1@ 1261 tsens_s10_p1: s10_p1@d8 {
1303 reg = <0xd8 0 1262 reg = <0xd8 0x2>;
1304 bits = <6 6>; 1263 bits = <6 6>;
1305 }; 1264 };
1306 1265
1307 tsens_base2: base2@d9 1266 tsens_base2: base2@d9 {
1308 reg = <0xd9 0 1267 reg = <0xd9 0x2>;
1309 bits = <4 8>; 1268 bits = <4 8>;
1310 }; 1269 };
1311 1270
1312 tsens_s0_p2: s0-p2@da 1271 tsens_s0_p2: s0-p2@da {
1313 reg = <0xda 0 1272 reg = <0xda 0x2>;
1314 bits = <4 6>; 1273 bits = <4 6>;
1315 }; 1274 };
1316 1275
1317 tsens_s1_p2: s1-p2@db 1276 tsens_s1_p2: s1-p2@db {
1318 reg = <0xdb 0 1277 reg = <0xdb 0x1>;
1319 bits = <2 6>; 1278 bits = <2 6>;
1320 }; 1279 };
1321 1280
1322 tsens_s2_p2: s2-p2@dc 1281 tsens_s2_p2: s2-p2@dc {
1323 reg = <0xdc 0 1282 reg = <0xdc 0x1>;
1324 bits = <0 6>; 1283 bits = <0 6>;
1325 }; 1284 };
1326 1285
1327 tsens_s3_p2: s3-p2@dc 1286 tsens_s3_p2: s3-p2@dc {
1328 reg = <0xdc 0 1287 reg = <0xdc 0x2>;
1329 bits = <6 6>; 1288 bits = <6 6>;
1330 }; 1289 };
1331 1290
1332 tsens_s4_p2: s4-p2@dd 1291 tsens_s4_p2: s4-p2@dd {
1333 reg = <0xdd 0 1292 reg = <0xdd 0x2>;
1334 bits = <4 6>; 1293 bits = <4 6>;
1335 }; 1294 };
1336 1295
1337 tsens_s5_p2: s5-p2@de 1296 tsens_s5_p2: s5-p2@de {
1338 reg = <0xde 0 1297 reg = <0xde 0x2>;
1339 bits = <2 6>; 1298 bits = <2 6>;
1340 }; 1299 };
1341 1300
1342 tsens_s6_p2: s6-p2@df 1301 tsens_s6_p2: s6-p2@df {
1343 reg = <0xdf 0 1302 reg = <0xdf 0x1>;
1344 bits = <0 6>; 1303 bits = <0 6>;
1345 }; 1304 };
1346 1305
1347 tsens_s7_p2: s7-p2@e0 1306 tsens_s7_p2: s7-p2@e0 {
1348 reg = <0xe0 0 1307 reg = <0xe0 0x1>;
1349 bits = <0 6>; 1308 bits = <0 6>;
1350 }; 1309 };
1351 1310
1352 tsens_s8_p2: s8-p2@e0 1311 tsens_s8_p2: s8-p2@e0 {
1353 reg = <0xe0 0 1312 reg = <0xe0 0x2>;
1354 bits = <6 6>; 1313 bits = <6 6>;
1355 }; 1314 };
1356 1315
1357 tsens_s9_p2: s9-p2@e1 1316 tsens_s9_p2: s9-p2@e1 {
1358 reg = <0xe1 0 1317 reg = <0xe1 0x2>;
1359 bits = <4 6>; 1318 bits = <4 6>;
1360 }; 1319 };
1361 1320
1362 tsens_s10_p2: s10_p2@ 1321 tsens_s10_p2: s10_p2@e2 {
1363 reg = <0xe2 0 1322 reg = <0xe2 0x2>;
1364 bits = <2 6>; 1323 bits = <2 6>;
1365 }; 1324 };
1366 1325
1367 tsens_s5_p2_backup: s 1326 tsens_s5_p2_backup: s5-p2_backup@e3 {
1368 reg = <0xe3 0 1327 reg = <0xe3 0x2>;
1369 bits = <0 6>; 1328 bits = <0 6>;
1370 }; 1329 };
1371 1330
1372 tsens_mode_backup: mo 1331 tsens_mode_backup: mode_backup@e3 {
1373 reg = <0xe3 0 1332 reg = <0xe3 0x1>;
1374 bits = <6 2>; 1333 bits = <6 2>;
1375 }; 1334 };
1376 1335
1377 tsens_s6_p2_backup: s 1336 tsens_s6_p2_backup: s6-p2_backup@e4 {
1378 reg = <0xe4 0 1337 reg = <0xe4 0x1>;
1379 bits = <0 6>; 1338 bits = <0 6>;
1380 }; 1339 };
1381 1340
1382 tsens_s7_p2_backup: s 1341 tsens_s7_p2_backup: s7-p2_backup@e4 {
1383 reg = <0xe4 0 1342 reg = <0xe4 0x2>;
1384 bits = <6 6>; 1343 bits = <6 6>;
1385 }; 1344 };
1386 1345
1387 tsens_s8_p2_backup: s 1346 tsens_s8_p2_backup: s8-p2_backup@e5 {
1388 reg = <0xe5 0 1347 reg = <0xe5 0x2>;
1389 bits = <4 6>; 1348 bits = <4 6>;
1390 }; 1349 };
1391 1350
1392 tsens_s9_p2_backup: s 1351 tsens_s9_p2_backup: s9-p2_backup@e6 {
1393 reg = <0xe6 0 1352 reg = <0xe6 0x2>;
1394 bits = <2 6>; 1353 bits = <2 6>;
1395 }; 1354 };
1396 1355
1397 tsens_s10_p2_backup: 1356 tsens_s10_p2_backup: s10_p2_backup@e7 {
1398 reg = <0xe7 0 1357 reg = <0xe7 0x1>;
1399 bits = <0 6>; 1358 bits = <0 6>;
1400 }; 1359 };
1401 1360
1402 tsens_base1_backup: b 1361 tsens_base1_backup: base1_backup@440 {
1403 reg = <0x440 1362 reg = <0x440 0x1>;
1404 bits = <0 8>; 1363 bits = <0 8>;
1405 }; 1364 };
1406 1365
1407 tsens_s0_p1_backup: s 1366 tsens_s0_p1_backup: s0-p1_backup@441 {
1408 reg = <0x441 1367 reg = <0x441 0x1>;
1409 bits = <0 6>; 1368 bits = <0 6>;
1410 }; 1369 };
1411 1370
1412 tsens_s1_p1_backup: s 1371 tsens_s1_p1_backup: s1-p1_backup@442 {
1413 reg = <0x441 1372 reg = <0x441 0x2>;
1414 bits = <6 6>; 1373 bits = <6 6>;
1415 }; 1374 };
1416 1375
1417 tsens_s2_p1_backup: s 1376 tsens_s2_p1_backup: s2-p1_backup@442 {
1418 reg = <0x442 1377 reg = <0x442 0x2>;
1419 bits = <4 6>; 1378 bits = <4 6>;
1420 }; 1379 };
1421 1380
1422 tsens_s3_p1_backup: s 1381 tsens_s3_p1_backup: s3-p1_backup@443 {
1423 reg = <0x443 1382 reg = <0x443 0x1>;
1424 bits = <2 6>; 1383 bits = <2 6>;
1425 }; 1384 };
1426 1385
1427 tsens_s4_p1_backup: s 1386 tsens_s4_p1_backup: s4-p1_backup@444 {
1428 reg = <0x444 1387 reg = <0x444 0x1>;
1429 bits = <0 6>; 1388 bits = <0 6>;
1430 }; 1389 };
1431 1390
1432 tsens_s5_p1_backup: s 1391 tsens_s5_p1_backup: s5-p1_backup@444 {
1433 reg = <0x444 1392 reg = <0x444 0x2>;
1434 bits = <6 6>; 1393 bits = <6 6>;
1435 }; 1394 };
1436 1395
1437 tsens_s6_p1_backup: s 1396 tsens_s6_p1_backup: s6-p1_backup@445 {
1438 reg = <0x445 1397 reg = <0x445 0x2>;
1439 bits = <4 6>; 1398 bits = <4 6>;
1440 }; 1399 };
1441 1400
1442 tsens_s7_p1_backup: s 1401 tsens_s7_p1_backup: s7-p1_backup@446 {
1443 reg = <0x446 1402 reg = <0x446 0x1>;
1444 bits = <2 6>; 1403 bits = <2 6>;
1445 }; 1404 };
1446 1405
1447 tsens_use_backup: use 1406 tsens_use_backup: use_backup@447 {
1448 reg = <0x447 1407 reg = <0x447 0x1>;
1449 bits = <5 3>; 1408 bits = <5 3>;
1450 }; 1409 };
1451 1410
1452 tsens_s8_p1_backup: s 1411 tsens_s8_p1_backup: s8-p1_backup@448 {
1453 reg = <0x448 1412 reg = <0x448 0x1>;
1454 bits = <0 6>; 1413 bits = <0 6>;
1455 }; 1414 };
1456 1415
1457 tsens_s9_p1_backup: s 1416 tsens_s9_p1_backup: s9-p1_backup@448 {
1458 reg = <0x448 1417 reg = <0x448 0x2>;
1459 bits = <6 6>; 1418 bits = <6 6>;
1460 }; 1419 };
1461 1420
1462 tsens_s10_p1_backup: 1421 tsens_s10_p1_backup: s10_p1_backup@449 {
1463 reg = <0x449 1422 reg = <0x449 0x2>;
1464 bits = <4 6>; 1423 bits = <4 6>;
1465 }; 1424 };
1466 1425
1467 tsens_base2_backup: b 1426 tsens_base2_backup: base2_backup@44a {
1468 reg = <0x44a 1427 reg = <0x44a 0x2>;
1469 bits = <2 8>; 1428 bits = <2 8>;
1470 }; 1429 };
1471 1430
1472 tsens_s0_p2_backup: s 1431 tsens_s0_p2_backup: s0-p2_backup@44b {
1473 reg = <0x44b 1432 reg = <0x44b 0x3>;
1474 bits = <2 6>; 1433 bits = <2 6>;
1475 }; 1434 };
1476 1435
1477 tsens_s1_p2_backup: s 1436 tsens_s1_p2_backup: s1-p2_backup@44c {
1478 reg = <0x44c 1437 reg = <0x44c 0x1>;
1479 bits = <0 6>; 1438 bits = <0 6>;
1480 }; 1439 };
1481 1440
1482 tsens_s2_p2_backup: s 1441 tsens_s2_p2_backup: s2-p2_backup@44c {
1483 reg = <0x44c 1442 reg = <0x44c 0x2>;
1484 bits = <6 6>; 1443 bits = <6 6>;
1485 }; 1444 };
1486 1445
1487 tsens_s3_p2_backup: s 1446 tsens_s3_p2_backup: s3-p2_backup@44d {
1488 reg = <0x44d 1447 reg = <0x44d 0x2>;
1489 bits = <4 6>; 1448 bits = <4 6>;
1490 }; 1449 };
1491 1450
1492 tsens_s4_p2_backup: s 1451 tsens_s4_p2_backup: s4-p2_backup@44e {
1493 reg = <0x44e 1452 reg = <0x44e 0x1>;
1494 bits = <2 6>; 1453 bits = <2 6>;
1495 }; 1454 };
1496 }; 1455 };
1497 1456
1498 spmi_bus: spmi@fc4cf000 { 1457 spmi_bus: spmi@fc4cf000 {
1499 compatible = "qcom,sp 1458 compatible = "qcom,spmi-pmic-arb";
1500 reg-names = "core", " 1459 reg-names = "core", "intr", "cnfg";
1501 reg = <0xfc4cf000 0x1 1460 reg = <0xfc4cf000 0x1000>,
1502 <0xfc4cb000 0x1 1461 <0xfc4cb000 0x1000>,
1503 <0xfc4ca000 0x1 1462 <0xfc4ca000 0x1000>;
1504 interrupt-names = "pe 1463 interrupt-names = "periph_irq";
1505 interrupts = <GIC_SPI 1464 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1506 qcom,ee = <0>; 1465 qcom,ee = <0>;
1507 qcom,channel = <0>; 1466 qcom,channel = <0>;
1508 #address-cells = <2>; 1467 #address-cells = <2>;
1509 #size-cells = <0>; 1468 #size-cells = <0>;
1510 interrupt-controller; 1469 interrupt-controller;
1511 #interrupt-cells = <4 1470 #interrupt-cells = <4>;
1512 }; 1471 };
1513 1472
1514 bam_dmux_dma: dma-controller@ 1473 bam_dmux_dma: dma-controller@fc834000 {
1515 compatible = "qcom,ba 1474 compatible = "qcom,bam-v1.4.0";
1516 reg = <0xfc834000 0x7 1475 reg = <0xfc834000 0x7000>;
1517 interrupts = <GIC_SPI 1476 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1518 #dma-cells = <1>; 1477 #dma-cells = <1>;
1519 qcom,ee = <0>; 1478 qcom,ee = <0>;
1520 1479
1521 num-channels = <6>; 1480 num-channels = <6>;
1522 qcom,num-ees = <1>; 1481 qcom,num-ees = <1>;
1523 qcom,powered-remotely 1482 qcom,powered-remotely;
1524 }; 1483 };
1525 1484
1526 remoteproc_mss: remoteproc@fc 1485 remoteproc_mss: remoteproc@fc880000 {
1527 compatible = "qcom,ms 1486 compatible = "qcom,msm8974-mss-pil";
1528 reg = <0xfc880000 0x1 1487 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1529 reg-names = "qdsp6", 1488 reg-names = "qdsp6", "rmb";
1530 1489
1531 interrupts-extended = 1490 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1532 1491 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1533 1492 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1534 1493 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1535 1494 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1536 interrupt-names = "wd 1495 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1537 1496
1538 clocks = <&gcc GCC_MS 1497 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1539 <&gcc GCC_MS 1498 <&gcc GCC_MSS_CFG_AHB_CLK>,
1540 <&gcc GCC_BO 1499 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1541 <&xo_board>; 1500 <&xo_board>;
1542 clock-names = "iface" 1501 clock-names = "iface", "bus", "mem", "xo";
1543 1502
1544 resets = <&gcc GCC_MS 1503 resets = <&gcc GCC_MSS_RESTART>;
1545 reset-names = "mss_re 1504 reset-names = "mss_restart";
1546 1505
1547 qcom,halt-regs = <&tc 1506 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1548 1507
1549 qcom,smem-states = <& 1508 qcom,smem-states = <&modem_smp2p_out 0>;
1550 qcom,smem-state-names 1509 qcom,smem-state-names = "stop";
1551 1510
1552 status = "disabled"; 1511 status = "disabled";
1553 1512
1554 mba { 1513 mba {
1555 memory-region 1514 memory-region = <&mba_region>;
1556 }; 1515 };
1557 1516
1558 mpss { 1517 mpss {
1559 memory-region 1518 memory-region = <&mpss_region>;
1560 }; 1519 };
1561 1520
1562 bam_dmux: bam-dmux { 1521 bam_dmux: bam-dmux {
1563 compatible = 1522 compatible = "qcom,bam-dmux";
1564 1523
1565 interrupt-par 1524 interrupt-parent = <&modem_smsm>;
1566 interrupts = 1525 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1567 interrupt-nam 1526 interrupt-names = "pc", "pc-ack";
1568 1527
1569 qcom,smem-sta 1528 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1570 qcom,smem-sta 1529 qcom,smem-state-names = "pc", "pc-ack";
1571 1530
1572 dmas = <&bam_ 1531 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1573 dma-names = " 1532 dma-names = "tx", "rx";
1574 }; 1533 };
1575 1534
1576 smd-edge { 1535 smd-edge {
1577 interrupts = 1536 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1578 1537
1579 mboxes = <&ap !! 1538 qcom,ipc = <&apcs 8 12>;
1580 qcom,smd-edge 1539 qcom,smd-edge = <0>;
1581 1540
1582 label = "mode 1541 label = "modem";
1583 }; 1542 };
1584 }; 1543 };
1585 1544
1586 tcsr_mutex: hwlock@fd484000 { 1545 tcsr_mutex: hwlock@fd484000 {
1587 compatible = "qcom,ms 1546 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1588 reg = <0xfd484000 0x2 1547 reg = <0xfd484000 0x2000>;
1589 #hwlock-cells = <1>; 1548 #hwlock-cells = <1>;
1590 }; 1549 };
1591 1550
1592 tcsr: syscon@fd4a0000 { 1551 tcsr: syscon@fd4a0000 {
1593 compatible = "qcom,tc 1552 compatible = "qcom,tcsr-msm8974", "syscon";
1594 reg = <0xfd4a0000 0x1 1553 reg = <0xfd4a0000 0x10000>;
1595 }; 1554 };
1596 1555
1597 tlmm: pinctrl@fd510000 { 1556 tlmm: pinctrl@fd510000 {
1598 compatible = "qcom,ms 1557 compatible = "qcom,msm8974-pinctrl";
1599 reg = <0xfd510000 0x4 1558 reg = <0xfd510000 0x4000>;
1600 gpio-controller; 1559 gpio-controller;
1601 gpio-ranges = <&tlmm 1560 gpio-ranges = <&tlmm 0 0 146>;
1602 #gpio-cells = <2>; 1561 #gpio-cells = <2>;
1603 interrupt-controller; 1562 interrupt-controller;
1604 #interrupt-cells = <2 1563 #interrupt-cells = <2>;
1605 interrupts = <GIC_SPI 1564 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1606 1565
1607 sdc1_off: sdc1-off-st 1566 sdc1_off: sdc1-off-state {
1608 clk-pins { 1567 clk-pins {
1609 pins 1568 pins = "sdc1_clk";
1610 bias- 1569 bias-disable;
1611 drive 1570 drive-strength = <2>;
1612 }; 1571 };
1613 1572
1614 cmd-pins { 1573 cmd-pins {
1615 pins 1574 pins = "sdc1_cmd";
1616 bias- 1575 bias-pull-up;
1617 drive 1576 drive-strength = <2>;
1618 }; 1577 };
1619 1578
1620 data-pins { 1579 data-pins {
1621 pins 1580 pins = "sdc1_data";
1622 bias- 1581 bias-pull-up;
1623 drive 1582 drive-strength = <2>;
1624 }; 1583 };
1625 }; 1584 };
1626 1585
1627 sdc2_off: sdc2-off-st 1586 sdc2_off: sdc2-off-state {
1628 clk-pins { 1587 clk-pins {
1629 pins 1588 pins = "sdc2_clk";
1630 bias- 1589 bias-disable;
1631 drive 1590 drive-strength = <2>;
1632 }; 1591 };
1633 1592
1634 cmd-pins { 1593 cmd-pins {
1635 pins 1594 pins = "sdc2_cmd";
1636 bias- 1595 bias-pull-up;
1637 drive 1596 drive-strength = <2>;
1638 }; 1597 };
1639 1598
1640 data-pins { 1599 data-pins {
1641 pins 1600 pins = "sdc2_data";
1642 bias- 1601 bias-pull-up;
1643 drive 1602 drive-strength = <2>;
1644 }; 1603 };
>> 1604
>> 1605 cd-pins {
>> 1606 pins = "gpio54";
>> 1607 function = "gpio";
>> 1608 bias-disable;
>> 1609 drive-strength = <2>;
>> 1610 };
1645 }; 1611 };
1646 1612
1647 blsp1_uart2_default: 1613 blsp1_uart2_default: blsp1-uart2-default-state {
1648 rx-pins { 1614 rx-pins {
1649 pins 1615 pins = "gpio5";
1650 funct 1616 function = "blsp_uart2";
1651 drive 1617 drive-strength = <2>;
1652 bias- 1618 bias-pull-up;
1653 }; 1619 };
1654 1620
1655 tx-pins { 1621 tx-pins {
1656 pins 1622 pins = "gpio4";
1657 funct 1623 function = "blsp_uart2";
1658 drive 1624 drive-strength = <4>;
1659 bias- 1625 bias-disable;
1660 }; 1626 };
1661 }; 1627 };
1662 1628
1663 blsp2_uart1_default: 1629 blsp2_uart1_default: blsp2-uart1-default-state {
1664 tx-rts-pins { 1630 tx-rts-pins {
1665 pins 1631 pins = "gpio41", "gpio44";
1666 funct 1632 function = "blsp_uart7";
1667 drive 1633 drive-strength = <2>;
1668 bias- 1634 bias-disable;
1669 }; 1635 };
1670 1636
1671 rx-cts-pins { 1637 rx-cts-pins {
1672 pins 1638 pins = "gpio42", "gpio43";
1673 funct 1639 function = "blsp_uart7";
1674 drive 1640 drive-strength = <2>;
1675 bias- 1641 bias-pull-up;
1676 }; 1642 };
1677 }; 1643 };
1678 1644
1679 blsp2_uart1_sleep: bl 1645 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1680 pins = "gpio4 1646 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1681 function = "g 1647 function = "gpio";
1682 drive-strengt 1648 drive-strength = <2>;
1683 bias-pull-dow 1649 bias-pull-down;
1684 }; 1650 };
1685 1651
1686 blsp2_uart4_default: 1652 blsp2_uart4_default: blsp2-uart4-default-state {
1687 tx-rts-pins { 1653 tx-rts-pins {
1688 pins 1654 pins = "gpio53", "gpio56";
1689 funct 1655 function = "blsp_uart10";
1690 drive 1656 drive-strength = <2>;
1691 bias- 1657 bias-disable;
1692 }; 1658 };
1693 1659
1694 rx-cts-pins { 1660 rx-cts-pins {
1695 pins 1661 pins = "gpio54", "gpio55";
1696 funct 1662 function = "blsp_uart10";
1697 drive 1663 drive-strength = <2>;
1698 bias- 1664 bias-pull-up;
1699 }; 1665 };
1700 }; 1666 };
1701 1667
1702 blsp1_i2c1_default: b 1668 blsp1_i2c1_default: blsp1-i2c1-default-state {
1703 pins = "gpio2 1669 pins = "gpio2", "gpio3";
1704 function = "b 1670 function = "blsp_i2c1";
1705 drive-strengt 1671 drive-strength = <2>;
1706 bias-disable; 1672 bias-disable;
1707 }; 1673 };
1708 1674
1709 blsp1_i2c1_sleep: bls 1675 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1710 pins = "gpio2 1676 pins = "gpio2", "gpio3";
1711 function = "b 1677 function = "blsp_i2c1";
1712 drive-strengt 1678 drive-strength = <2>;
1713 bias-pull-up; 1679 bias-pull-up;
1714 }; 1680 };
1715 1681
1716 blsp1_i2c2_default: b 1682 blsp1_i2c2_default: blsp1-i2c2-default-state {
1717 pins = "gpio6 1683 pins = "gpio6", "gpio7";
1718 function = "b 1684 function = "blsp_i2c2";
1719 drive-strengt 1685 drive-strength = <2>;
1720 bias-disable; 1686 bias-disable;
1721 }; 1687 };
1722 1688
1723 blsp1_i2c2_sleep: bls 1689 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1724 pins = "gpio6 1690 pins = "gpio6", "gpio7";
1725 function = "b 1691 function = "blsp_i2c2";
1726 drive-strengt 1692 drive-strength = <2>;
1727 bias-pull-up; 1693 bias-pull-up;
1728 }; 1694 };
1729 1695
1730 blsp1_i2c3_default: b 1696 blsp1_i2c3_default: blsp1-i2c3-default-state {
1731 pins = "gpio1 1697 pins = "gpio10", "gpio11";
1732 function = "b 1698 function = "blsp_i2c3";
1733 drive-strengt 1699 drive-strength = <2>;
1734 bias-disable; 1700 bias-disable;
1735 }; 1701 };
1736 1702
1737 blsp1_i2c3_sleep: bls 1703 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1738 pins = "gpio1 1704 pins = "gpio10", "gpio11";
1739 function = "b 1705 function = "blsp_i2c3";
1740 drive-strengt 1706 drive-strength = <2>;
1741 bias-pull-up; 1707 bias-pull-up;
1742 }; 1708 };
1743 1709
1744 /* BLSP1_I2C4 info is 1710 /* BLSP1_I2C4 info is missing */
1745 1711
1746 /* BLSP1_I2C5 info is 1712 /* BLSP1_I2C5 info is missing */
1747 1713
1748 blsp1_i2c6_default: b 1714 blsp1_i2c6_default: blsp1-i2c6-default-state {
1749 pins = "gpio2 1715 pins = "gpio29", "gpio30";
1750 function = "b 1716 function = "blsp_i2c6";
1751 drive-strengt 1717 drive-strength = <2>;
1752 bias-disable; 1718 bias-disable;
1753 }; 1719 };
1754 1720
1755 blsp1_i2c6_sleep: bls 1721 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1756 pins = "gpio2 1722 pins = "gpio29", "gpio30";
1757 function = "b 1723 function = "blsp_i2c6";
1758 drive-strengt 1724 drive-strength = <2>;
1759 bias-pull-up; 1725 bias-pull-up;
1760 }; 1726 };
1761 /* 6 interfaces per Q 1727 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1762 1728
1763 /* BLSP2_I2C1 info is 1729 /* BLSP2_I2C1 info is missing */
1764 1730
1765 blsp2_i2c2_default: b 1731 blsp2_i2c2_default: blsp2-i2c2-default-state {
1766 pins = "gpio4 1732 pins = "gpio47", "gpio48";
1767 function = "b 1733 function = "blsp_i2c8";
1768 drive-strengt 1734 drive-strength = <2>;
1769 bias-disable; 1735 bias-disable;
1770 }; 1736 };
1771 1737
1772 blsp2_i2c2_sleep: bls 1738 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1773 pins = "gpio4 1739 pins = "gpio47", "gpio48";
1774 function = "b 1740 function = "blsp_i2c8";
1775 drive-strengt 1741 drive-strength = <2>;
1776 bias-pull-up; 1742 bias-pull-up;
1777 }; 1743 };
1778 1744
1779 /* BLSP2_I2C3 info is 1745 /* BLSP2_I2C3 info is missing */
1780 1746
1781 /* BLSP2_I2C4 info is 1747 /* BLSP2_I2C4 info is missing */
1782 1748
1783 blsp2_i2c5_default: b 1749 blsp2_i2c5_default: blsp2-i2c5-default-state {
1784 pins = "gpio8 1750 pins = "gpio83", "gpio84";
1785 function = "b 1751 function = "blsp_i2c11";
1786 drive-strengt 1752 drive-strength = <2>;
1787 bias-disable; 1753 bias-disable;
1788 }; 1754 };
1789 1755
1790 blsp2_i2c5_sleep: bls 1756 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1791 pins = "gpio8 1757 pins = "gpio83", "gpio84";
1792 function = "b 1758 function = "blsp_i2c11";
1793 drive-strengt 1759 drive-strength = <2>;
1794 bias-pull-up; 1760 bias-pull-up;
1795 }; 1761 };
1796 1762
1797 blsp2_i2c6_default: b 1763 blsp2_i2c6_default: blsp2-i2c6-default-state {
1798 pins = "gpio8 1764 pins = "gpio87", "gpio88";
1799 function = "b 1765 function = "blsp_i2c12";
1800 drive-strengt 1766 drive-strength = <2>;
1801 bias-disable; 1767 bias-disable;
1802 }; 1768 };
1803 1769
1804 blsp2_i2c6_sleep: bls 1770 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1805 pins = "gpio8 1771 pins = "gpio87", "gpio88";
1806 function = "b 1772 function = "blsp_i2c12";
1807 drive-strengt 1773 drive-strength = <2>;
1808 bias-pull-up; 1774 bias-pull-up;
1809 }; 1775 };
1810 1776
1811 cci_default: cci-defa 1777 cci_default: cci-default-state {
1812 cci_i2c0_defa 1778 cci_i2c0_default: cci-i2c0-default-pins {
1813 pins 1779 pins = "gpio19", "gpio20";
1814 funct 1780 function = "cci_i2c0";
1815 drive 1781 drive-strength = <2>;
1816 bias- 1782 bias-disable;
1817 }; 1783 };
1818 1784
1819 cci_i2c1_defa 1785 cci_i2c1_default: cci-i2c1-default-pins {
1820 pins 1786 pins = "gpio21", "gpio22";
1821 funct 1787 function = "cci_i2c1";
1822 drive 1788 drive-strength = <2>;
1823 bias- 1789 bias-disable;
1824 }; 1790 };
1825 }; 1791 };
1826 1792
1827 cci_sleep: cci-sleep- 1793 cci_sleep: cci-sleep-state {
1828 cci_i2c0_slee 1794 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1829 pins 1795 pins = "gpio19", "gpio20";
1830 funct 1796 function = "gpio";
1831 drive 1797 drive-strength = <2>;
1832 bias- 1798 bias-disable;
1833 }; 1799 };
1834 1800
1835 cci_i2c1_slee 1801 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1836 pins 1802 pins = "gpio21", "gpio22";
1837 funct 1803 function = "gpio";
1838 drive 1804 drive-strength = <2>;
1839 bias- 1805 bias-disable;
1840 }; 1806 };
1841 }; 1807 };
1842 1808
1843 spi8_default: spi8_de 1809 spi8_default: spi8_default-state {
1844 mosi-pins { 1810 mosi-pins {
1845 pins 1811 pins = "gpio45";
1846 funct 1812 function = "blsp_spi8";
1847 }; 1813 };
1848 miso-pins { 1814 miso-pins {
1849 pins 1815 pins = "gpio46";
1850 funct 1816 function = "blsp_spi8";
1851 }; 1817 };
1852 cs-pins { 1818 cs-pins {
1853 pins 1819 pins = "gpio47";
1854 funct 1820 function = "blsp_spi8";
1855 }; 1821 };
1856 clk-pins { 1822 clk-pins {
1857 pins 1823 pins = "gpio48";
1858 funct 1824 function = "blsp_spi8";
1859 }; 1825 };
1860 }; 1826 };
1861 }; 1827 };
1862 1828
1863 mmcc: clock-controller@fd8c00 1829 mmcc: clock-controller@fd8c0000 {
1864 compatible = "qcom,mm 1830 compatible = "qcom,mmcc-msm8974";
1865 #clock-cells = <1>; 1831 #clock-cells = <1>;
1866 #reset-cells = <1>; 1832 #reset-cells = <1>;
1867 #power-domain-cells = 1833 #power-domain-cells = <1>;
1868 reg = <0xfd8c0000 0x6 1834 reg = <0xfd8c0000 0x6000>;
1869 clocks = <&xo_board>, 1835 clocks = <&xo_board>,
1870 <&gcc GCC_MM 1836 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1871 <&gcc GPLL0_ 1837 <&gcc GPLL0_VOTE>,
1872 <&gcc GPLL1_ 1838 <&gcc GPLL1_VOTE>,
1873 <&rpmcc RPM_ 1839 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1874 <&mdss_dsi0_ 1840 <&mdss_dsi0_phy 1>,
1875 <&mdss_dsi0_ 1841 <&mdss_dsi0_phy 0>,
1876 <&mdss_dsi1_ 1842 <&mdss_dsi1_phy 1>,
1877 <&mdss_dsi1_ 1843 <&mdss_dsi1_phy 0>,
1878 <0>, 1844 <0>,
1879 <0>, 1845 <0>,
1880 <0>; 1846 <0>;
1881 clock-names = "xo", 1847 clock-names = "xo",
1882 "mmss_g 1848 "mmss_gpll0_vote",
1883 "gpll0_ 1849 "gpll0_vote",
1884 "gpll1_ 1850 "gpll1_vote",
1885 "gfx3d_ 1851 "gfx3d_clk_src",
1886 "dsi0pl 1852 "dsi0pll",
1887 "dsi0pl 1853 "dsi0pllbyte",
1888 "dsi1pl 1854 "dsi1pll",
1889 "dsi1pl 1855 "dsi1pllbyte",
1890 "hdmipl 1856 "hdmipll",
1891 "edp_li 1857 "edp_link_clk",
1892 "edp_vc 1858 "edp_vco_div";
1893 }; 1859 };
1894 1860
1895 mdss: display-subsystem@fd900 1861 mdss: display-subsystem@fd900000 {
1896 compatible = "qcom,md 1862 compatible = "qcom,mdss";
1897 reg = <0xfd900000 0x1 1863 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1898 reg-names = "mdss_phy 1864 reg-names = "mdss_phys", "vbif_phys";
1899 1865
1900 power-domains = <&mmc 1866 power-domains = <&mmcc MDSS_GDSC>;
1901 1867
1902 clocks = <&mmcc MDSS_ 1868 clocks = <&mmcc MDSS_AHB_CLK>,
1903 <&mmcc MDSS_ 1869 <&mmcc MDSS_AXI_CLK>,
1904 <&mmcc MDSS_ 1870 <&mmcc MDSS_VSYNC_CLK>;
1905 clock-names = "iface" 1871 clock-names = "iface", "bus", "vsync";
1906 1872
1907 interrupts = <GIC_SPI 1873 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1908 1874
1909 interrupt-controller; 1875 interrupt-controller;
1910 #interrupt-cells = <1 1876 #interrupt-cells = <1>;
1911 1877
1912 status = "disabled"; 1878 status = "disabled";
1913 1879
1914 #address-cells = <1>; 1880 #address-cells = <1>;
1915 #size-cells = <1>; 1881 #size-cells = <1>;
1916 ranges; 1882 ranges;
1917 1883
1918 mdp: display-controll 1884 mdp: display-controller@fd900000 {
1919 compatible = 1885 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1920 reg = <0xfd90 1886 reg = <0xfd900100 0x22000>;
1921 reg-names = " 1887 reg-names = "mdp_phys";
1922 1888
1923 interrupt-par 1889 interrupt-parent = <&mdss>;
1924 interrupts = 1890 interrupts = <0>;
1925 1891
1926 clocks = <&mm 1892 clocks = <&mmcc MDSS_AHB_CLK>,
1927 <&mm 1893 <&mmcc MDSS_AXI_CLK>,
1928 <&mm 1894 <&mmcc MDSS_MDP_CLK>,
1929 <&mm 1895 <&mmcc MDSS_VSYNC_CLK>;
1930 clock-names = 1896 clock-names = "iface", "bus", "core", "vsync";
1931 1897
1932 interconnects 1898 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1933 interconnect- 1899 interconnect-names = "mdp0-mem";
1934 1900
1935 ports { 1901 ports {
1936 #addr 1902 #address-cells = <1>;
1937 #size 1903 #size-cells = <0>;
1938 1904
1939 port@ 1905 port@0 {
1940 1906 reg = <0>;
1941 1907 mdp5_intf1_out: endpoint {
1942 1908 remote-endpoint = <&mdss_dsi0_in>;
1943 1909 };
1944 }; 1910 };
1945 1911
1946 port@ 1912 port@1 {
1947 1913 reg = <1>;
1948 1914 mdp5_intf2_out: endpoint {
1949 1915 remote-endpoint = <&mdss_dsi1_in>;
1950 1916 };
1951 }; 1917 };
1952 }; 1918 };
1953 }; 1919 };
1954 1920
1955 mdss_dsi0: dsi@fd9228 1921 mdss_dsi0: dsi@fd922800 {
1956 compatible = 1922 compatible = "qcom,msm8974-dsi-ctrl",
1957 1923 "qcom,mdss-dsi-ctrl";
1958 reg = <0xfd92 1924 reg = <0xfd922800 0x1f8>;
1959 reg-names = " 1925 reg-names = "dsi_ctrl";
1960 1926
1961 interrupt-par 1927 interrupt-parent = <&mdss>;
1962 interrupts = 1928 interrupts = <4>;
1963 1929
1964 assigned-cloc 1930 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1965 assigned-cloc 1931 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1966 1932
1967 clocks = <&mm 1933 clocks = <&mmcc MDSS_MDP_CLK>,
1968 <&mm 1934 <&mmcc MDSS_AHB_CLK>,
1969 <&mm 1935 <&mmcc MDSS_AXI_CLK>,
1970 <&mm 1936 <&mmcc MDSS_BYTE0_CLK>,
1971 <&mm 1937 <&mmcc MDSS_PCLK0_CLK>,
1972 <&mm 1938 <&mmcc MDSS_ESC0_CLK>,
1973 <&mm 1939 <&mmcc MMSS_MISC_AHB_CLK>;
1974 clock-names = 1940 clock-names = "mdp_core",
1975 1941 "iface",
1976 1942 "bus",
1977 1943 "byte",
1978 1944 "pixel",
1979 1945 "core",
1980 1946 "core_mmss";
1981 1947
1982 phys = <&mdss 1948 phys = <&mdss_dsi0_phy>;
1983 1949
1984 status = "dis 1950 status = "disabled";
1985 1951
1986 #address-cell 1952 #address-cells = <1>;
1987 #size-cells = 1953 #size-cells = <0>;
1988 1954
1989 ports { 1955 ports {
1990 #addr 1956 #address-cells = <1>;
1991 #size 1957 #size-cells = <0>;
1992 1958
1993 port@ 1959 port@0 {
1994 1960 reg = <0>;
1995 1961 mdss_dsi0_in: endpoint {
1996 1962 remote-endpoint = <&mdp5_intf1_out>;
1997 1963 };
1998 }; 1964 };
1999 1965
2000 port@ 1966 port@1 {
2001 1967 reg = <1>;
2002 1968 mdss_dsi0_out: endpoint {
2003 1969 };
2004 }; 1970 };
2005 }; 1971 };
2006 }; 1972 };
2007 1973
2008 mdss_dsi0_phy: phy@fd 1974 mdss_dsi0_phy: phy@fd922a00 {
2009 compatible = 1975 compatible = "qcom,dsi-phy-28nm-hpm";
2010 reg = <0xfd92 1976 reg = <0xfd922a00 0xd4>,
2011 <0xfd92 1977 <0xfd922b00 0x280>,
2012 <0xfd92 1978 <0xfd922d80 0x30>;
2013 reg-names = " 1979 reg-names = "dsi_pll",
2014 " 1980 "dsi_phy",
2015 " 1981 "dsi_phy_regulator";
2016 1982
2017 #clock-cells 1983 #clock-cells = <1>;
2018 #phy-cells = 1984 #phy-cells = <0>;
2019 1985
2020 clocks = <&mm 1986 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2021 clock-names = 1987 clock-names = "iface", "ref";
2022 1988
2023 status = "dis 1989 status = "disabled";
2024 }; 1990 };
2025 1991
2026 mdss_dsi1: dsi@fd922e 1992 mdss_dsi1: dsi@fd922e00 {
2027 compatible = 1993 compatible = "qcom,msm8974-dsi-ctrl",
2028 1994 "qcom,mdss-dsi-ctrl";
2029 reg = <0xfd92 1995 reg = <0xfd922e00 0x1f8>;
2030 reg-names = " 1996 reg-names = "dsi_ctrl";
2031 1997
2032 interrupt-par 1998 interrupt-parent = <&mdss>;
2033 interrupts = 1999 interrupts = <4>;
2034 2000
2035 assigned-cloc 2001 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2036 assigned-cloc 2002 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2037 2003
2038 clocks = <&mm 2004 clocks = <&mmcc MDSS_MDP_CLK>,
2039 <&mm 2005 <&mmcc MDSS_AHB_CLK>,
2040 <&mm 2006 <&mmcc MDSS_AXI_CLK>,
2041 <&mm 2007 <&mmcc MDSS_BYTE1_CLK>,
2042 <&mm 2008 <&mmcc MDSS_PCLK1_CLK>,
2043 <&mm 2009 <&mmcc MDSS_ESC1_CLK>,
2044 <&mm 2010 <&mmcc MMSS_MISC_AHB_CLK>;
2045 clock-names = 2011 clock-names = "mdp_core",
2046 2012 "iface",
2047 2013 "bus",
2048 2014 "byte",
2049 2015 "pixel",
2050 2016 "core",
2051 2017 "core_mmss";
2052 2018
2053 phys = <&mdss 2019 phys = <&mdss_dsi1_phy>;
2054 2020
2055 status = "dis 2021 status = "disabled";
2056 2022
2057 #address-cell 2023 #address-cells = <1>;
2058 #size-cells = 2024 #size-cells = <0>;
2059 2025
2060 ports { 2026 ports {
2061 #addr 2027 #address-cells = <1>;
2062 #size 2028 #size-cells = <0>;
2063 2029
2064 port@ 2030 port@0 {
2065 2031 reg = <0>;
2066 2032 mdss_dsi1_in: endpoint {
2067 2033 remote-endpoint = <&mdp5_intf2_out>;
2068 2034 };
2069 }; 2035 };
2070 2036
2071 port@ 2037 port@1 {
2072 2038 reg = <1>;
2073 2039 mdss_dsi1_out: endpoint {
2074 2040 };
2075 }; 2041 };
2076 }; 2042 };
2077 }; 2043 };
2078 2044
2079 mdss_dsi1_phy: phy@fd 2045 mdss_dsi1_phy: phy@fd923000 {
2080 compatible = 2046 compatible = "qcom,dsi-phy-28nm-hpm";
2081 reg = <0xfd92 2047 reg = <0xfd923000 0xd4>,
2082 <0xfd92 2048 <0xfd923100 0x280>,
2083 <0xfd92 2049 <0xfd923380 0x30>;
2084 reg-names = " 2050 reg-names = "dsi_pll",
2085 " 2051 "dsi_phy",
2086 " 2052 "dsi_phy_regulator";
2087 2053
2088 #clock-cells 2054 #clock-cells = <1>;
2089 #phy-cells = 2055 #phy-cells = <0>;
2090 2056
2091 clocks = <&mm 2057 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2092 clock-names = 2058 clock-names = "iface", "ref";
2093 2059
2094 status = "dis 2060 status = "disabled";
2095 }; 2061 };
2096 }; 2062 };
2097 2063
2098 cci: cci@fda0c000 { 2064 cci: cci@fda0c000 {
2099 compatible = "qcom,ms 2065 compatible = "qcom,msm8974-cci";
2100 #address-cells = <1>; 2066 #address-cells = <1>;
2101 #size-cells = <0>; 2067 #size-cells = <0>;
2102 reg = <0xfda0c000 0x1 2068 reg = <0xfda0c000 0x1000>;
2103 interrupts = <GIC_SPI 2069 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2104 clocks = <&mmcc CAMSS 2070 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2105 <&mmcc CAMSS 2071 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2106 <&mmcc CAMSS 2072 <&mmcc CAMSS_CCI_CCI_CLK>;
2107 clock-names = "camss_ 2073 clock-names = "camss_top_ahb",
2108 "cci_ah 2074 "cci_ahb",
2109 "cci"; 2075 "cci";
2110 2076
2111 pinctrl-names = "defa 2077 pinctrl-names = "default", "sleep";
2112 pinctrl-0 = <&cci_def 2078 pinctrl-0 = <&cci_default>;
2113 pinctrl-1 = <&cci_sle 2079 pinctrl-1 = <&cci_sleep>;
2114 2080
2115 status = "disabled"; 2081 status = "disabled";
2116 2082
2117 cci_i2c0: i2c-bus@0 { 2083 cci_i2c0: i2c-bus@0 {
2118 reg = <0>; 2084 reg = <0>;
2119 clock-frequen 2085 clock-frequency = <100000>;
2120 #address-cell 2086 #address-cells = <1>;
2121 #size-cells = 2087 #size-cells = <0>;
2122 }; 2088 };
2123 2089
2124 cci_i2c1: i2c-bus@1 { 2090 cci_i2c1: i2c-bus@1 {
2125 reg = <1>; 2091 reg = <1>;
2126 clock-frequen 2092 clock-frequency = <100000>;
2127 #address-cell 2093 #address-cells = <1>;
2128 #size-cells = 2094 #size-cells = <0>;
2129 }; 2095 };
2130 }; 2096 };
2131 2097
2132 gpu: gpu@fdb00000 { !! 2098 gpu: adreno@fdb00000 {
2133 compatible = "qcom,ad 2099 compatible = "qcom,adreno-330.1", "qcom,adreno";
2134 reg = <0xfdb00000 0x1 2100 reg = <0xfdb00000 0x10000>;
2135 reg-names = "kgsl_3d0 2101 reg-names = "kgsl_3d0_reg_memory";
2136 2102
2137 interrupts = <GIC_SPI 2103 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2138 interrupt-names = "kg 2104 interrupt-names = "kgsl_3d0_irq";
2139 2105
2140 clocks = <&mmcc OXILI 2106 clocks = <&mmcc OXILI_GFX3D_CLK>,
2141 <&mmcc OXILI 2107 <&mmcc OXILICX_AHB_CLK>,
2142 <&mmcc OXILI 2108 <&mmcc OXILICX_AXI_CLK>;
2143 clock-names = "core", 2109 clock-names = "core", "iface", "mem_iface";
2144 2110
2145 sram = <&gmu_sram>; 2111 sram = <&gmu_sram>;
2146 power-domains = <&mmc 2112 power-domains = <&mmcc OXILICX_GDSC>;
2147 operating-points-v2 = 2113 operating-points-v2 = <&gpu_opp_table>;
2148 2114
2149 interconnects = <&mms 2115 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2150 <&ocm 2116 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2151 interconnect-names = 2117 interconnect-names = "gfx-mem", "ocmem";
2152 2118
2153 // iommus = <&gpu_iom 2119 // iommus = <&gpu_iommu 0>;
2154 2120
2155 status = "disabled"; 2121 status = "disabled";
2156 2122
2157 gpu_opp_table: opp-ta 2123 gpu_opp_table: opp-table {
2158 compatible = 2124 compatible = "operating-points-v2";
2159 2125
2160 opp-320000000 2126 opp-320000000 {
2161 opp-h 2127 opp-hz = /bits/ 64 <320000000>;
2162 }; 2128 };
2163 2129
2164 opp-200000000 2130 opp-200000000 {
2165 opp-h 2131 opp-hz = /bits/ 64 <200000000>;
2166 }; 2132 };
2167 2133
2168 opp-27000000 2134 opp-27000000 {
2169 opp-h 2135 opp-hz = /bits/ 64 <27000000>;
2170 }; 2136 };
2171 }; 2137 };
2172 }; 2138 };
2173 2139
2174 sram@fdd00000 { 2140 sram@fdd00000 {
2175 compatible = "qcom,ms 2141 compatible = "qcom,msm8974-ocmem";
2176 reg = <0xfdd00000 0x2 2142 reg = <0xfdd00000 0x2000>,
2177 <0xfec00000 0x1 2143 <0xfec00000 0x180000>;
2178 reg-names = "ctrl", " 2144 reg-names = "ctrl", "mem";
2179 ranges = <0 0xfec0000 2145 ranges = <0 0xfec00000 0x180000>;
2180 clocks = <&rpmcc RPM_ 2146 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2181 <&mmcc OCMEM 2147 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2182 clock-names = "core", 2148 clock-names = "core", "iface";
2183 2149
2184 #address-cells = <1>; 2150 #address-cells = <1>;
2185 #size-cells = <1>; 2151 #size-cells = <1>;
2186 2152
2187 gmu_sram: gmu-sram@0 2153 gmu_sram: gmu-sram@0 {
2188 reg = <0x0 0x 2154 reg = <0x0 0x100000>;
2189 }; 2155 };
2190 }; 2156 };
2191 2157
2192 remoteproc_adsp: remoteproc@f 2158 remoteproc_adsp: remoteproc@fe200000 {
2193 compatible = "qcom,ms 2159 compatible = "qcom,msm8974-adsp-pil";
2194 reg = <0xfe200000 0x1 2160 reg = <0xfe200000 0x100>;
2195 2161
2196 interrupts-extended = 2162 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2197 2163 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2198 2164 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2199 2165 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2200 2166 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2201 interrupt-names = "wd 2167 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2202 2168
2203 clocks = <&xo_board>; 2169 clocks = <&xo_board>;
2204 clock-names = "xo"; 2170 clock-names = "xo";
2205 2171
2206 memory-region = <&ads 2172 memory-region = <&adsp_region>;
2207 2173
2208 qcom,smem-states = <& 2174 qcom,smem-states = <&adsp_smp2p_out 0>;
2209 qcom,smem-state-names 2175 qcom,smem-state-names = "stop";
2210 2176
2211 status = "disabled"; 2177 status = "disabled";
2212 2178
2213 smd-edge { 2179 smd-edge {
2214 interrupts = 2180 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2215 2181
2216 mboxes = <&ap !! 2182 qcom,ipc = <&apcs 8 8>;
2217 qcom,smd-edge 2183 qcom,smd-edge = <1>;
2218 label = "lpas 2184 label = "lpass";
2219 }; 2185 };
2220 }; 2186 };
2221 2187
2222 imem: sram@fe805000 { 2188 imem: sram@fe805000 {
2223 compatible = "qcom,ms 2189 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2224 reg = <0xfe805000 0x1 2190 reg = <0xfe805000 0x1000>;
2225 2191
2226 reboot-mode { 2192 reboot-mode {
2227 compatible = 2193 compatible = "syscon-reboot-mode";
2228 offset = <0x6 2194 offset = <0x65c>;
2229 }; 2195 };
2230 }; 2196 };
2231 }; 2197 };
2232 2198
2233 thermal-zones { 2199 thermal-zones {
2234 cpu0-thermal { 2200 cpu0-thermal {
2235 polling-delay-passive 2201 polling-delay-passive = <250>;
2236 polling-delay = <1000 2202 polling-delay = <1000>;
2237 2203
2238 thermal-sensors = <&t 2204 thermal-sensors = <&tsens 5>;
2239 2205
2240 trips { 2206 trips {
2241 cpu_alert0: t 2207 cpu_alert0: trip0 {
2242 tempe 2208 temperature = <75000>;
2243 hyste 2209 hysteresis = <2000>;
2244 type 2210 type = "passive";
2245 }; 2211 };
2246 cpu_crit0: tr 2212 cpu_crit0: trip1 {
2247 tempe 2213 temperature = <110000>;
2248 hyste 2214 hysteresis = <2000>;
2249 type 2215 type = "critical";
2250 }; 2216 };
2251 }; 2217 };
2252 }; 2218 };
2253 2219
2254 cpu1-thermal { 2220 cpu1-thermal {
2255 polling-delay-passive 2221 polling-delay-passive = <250>;
2256 polling-delay = <1000 2222 polling-delay = <1000>;
2257 2223
2258 thermal-sensors = <&t 2224 thermal-sensors = <&tsens 6>;
2259 2225
2260 trips { 2226 trips {
2261 cpu_alert1: t 2227 cpu_alert1: trip0 {
2262 tempe 2228 temperature = <75000>;
2263 hyste 2229 hysteresis = <2000>;
2264 type 2230 type = "passive";
2265 }; 2231 };
2266 cpu_crit1: tr 2232 cpu_crit1: trip1 {
2267 tempe 2233 temperature = <110000>;
2268 hyste 2234 hysteresis = <2000>;
2269 type 2235 type = "critical";
2270 }; 2236 };
2271 }; 2237 };
2272 }; 2238 };
2273 2239
2274 cpu2-thermal { 2240 cpu2-thermal {
2275 polling-delay-passive 2241 polling-delay-passive = <250>;
2276 polling-delay = <1000 2242 polling-delay = <1000>;
2277 2243
2278 thermal-sensors = <&t 2244 thermal-sensors = <&tsens 7>;
2279 2245
2280 trips { 2246 trips {
2281 cpu_alert2: t 2247 cpu_alert2: trip0 {
2282 tempe 2248 temperature = <75000>;
2283 hyste 2249 hysteresis = <2000>;
2284 type 2250 type = "passive";
2285 }; 2251 };
2286 cpu_crit2: tr 2252 cpu_crit2: trip1 {
2287 tempe 2253 temperature = <110000>;
2288 hyste 2254 hysteresis = <2000>;
2289 type 2255 type = "critical";
2290 }; 2256 };
2291 }; 2257 };
2292 }; 2258 };
2293 2259
2294 cpu3-thermal { 2260 cpu3-thermal {
2295 polling-delay-passive 2261 polling-delay-passive = <250>;
2296 polling-delay = <1000 2262 polling-delay = <1000>;
2297 2263
2298 thermal-sensors = <&t 2264 thermal-sensors = <&tsens 8>;
2299 2265
2300 trips { 2266 trips {
2301 cpu_alert3: t 2267 cpu_alert3: trip0 {
2302 tempe 2268 temperature = <75000>;
2303 hyste 2269 hysteresis = <2000>;
2304 type 2270 type = "passive";
2305 }; 2271 };
2306 cpu_crit3: tr 2272 cpu_crit3: trip1 {
2307 tempe 2273 temperature = <110000>;
2308 hyste 2274 hysteresis = <2000>;
2309 type 2275 type = "critical";
2310 }; 2276 };
2311 }; 2277 };
2312 }; 2278 };
2313 2279
2314 q6-dsp-thermal { 2280 q6-dsp-thermal {
2315 polling-delay-passive 2281 polling-delay-passive = <250>;
2316 polling-delay = <1000 2282 polling-delay = <1000>;
2317 2283
2318 thermal-sensors = <&t 2284 thermal-sensors = <&tsens 1>;
2319 2285
2320 trips { 2286 trips {
2321 q6_dsp_alert0 2287 q6_dsp_alert0: trip-point0 {
2322 tempe 2288 temperature = <90000>;
2323 hyste 2289 hysteresis = <2000>;
2324 type 2290 type = "hot";
2325 }; 2291 };
2326 }; 2292 };
2327 }; 2293 };
2328 2294
2329 modemtx-thermal { 2295 modemtx-thermal {
2330 polling-delay-passive 2296 polling-delay-passive = <250>;
2331 polling-delay = <1000 2297 polling-delay = <1000>;
2332 2298
2333 thermal-sensors = <&t 2299 thermal-sensors = <&tsens 2>;
2334 2300
2335 trips { 2301 trips {
2336 modemtx_alert 2302 modemtx_alert0: trip-point0 {
2337 tempe 2303 temperature = <90000>;
2338 hyste 2304 hysteresis = <2000>;
2339 type 2305 type = "hot";
2340 }; 2306 };
2341 }; 2307 };
2342 }; 2308 };
2343 2309
2344 video-thermal { 2310 video-thermal {
2345 polling-delay-passive 2311 polling-delay-passive = <250>;
2346 polling-delay = <1000 2312 polling-delay = <1000>;
2347 2313
2348 thermal-sensors = <&t 2314 thermal-sensors = <&tsens 3>;
2349 2315
2350 trips { 2316 trips {
2351 video_alert0: 2317 video_alert0: trip-point0 {
2352 tempe 2318 temperature = <95000>;
2353 hyste 2319 hysteresis = <2000>;
2354 type 2320 type = "hot";
2355 }; 2321 };
2356 }; 2322 };
2357 }; 2323 };
2358 2324
2359 wlan-thermal { 2325 wlan-thermal {
2360 polling-delay-passive 2326 polling-delay-passive = <250>;
2361 polling-delay = <1000 2327 polling-delay = <1000>;
2362 2328
2363 thermal-sensors = <&t 2329 thermal-sensors = <&tsens 4>;
2364 2330
2365 trips { 2331 trips {
2366 wlan_alert0: 2332 wlan_alert0: trip-point0 {
2367 tempe 2333 temperature = <105000>;
2368 hyste 2334 hysteresis = <2000>;
2369 type 2335 type = "hot";
2370 }; 2336 };
2371 }; 2337 };
2372 }; 2338 };
2373 2339
2374 gpu-top-thermal { 2340 gpu-top-thermal {
2375 polling-delay-passive 2341 polling-delay-passive = <250>;
2376 polling-delay = <1000 2342 polling-delay = <1000>;
2377 2343
2378 thermal-sensors = <&t 2344 thermal-sensors = <&tsens 9>;
2379 2345
2380 trips { 2346 trips {
2381 gpu1_alert0: 2347 gpu1_alert0: trip-point0 {
2382 tempe 2348 temperature = <90000>;
2383 hyste 2349 hysteresis = <2000>;
2384 type 2350 type = "hot";
2385 }; 2351 };
2386 }; 2352 };
2387 }; 2353 };
2388 2354
2389 gpu-bottom-thermal { 2355 gpu-bottom-thermal {
2390 polling-delay-passive 2356 polling-delay-passive = <250>;
2391 polling-delay = <1000 2357 polling-delay = <1000>;
2392 2358
2393 thermal-sensors = <&t 2359 thermal-sensors = <&tsens 10>;
2394 2360
2395 trips { 2361 trips {
2396 gpu2_alert0: 2362 gpu2_alert0: trip-point0 {
2397 tempe 2363 temperature = <90000>;
2398 hyste 2364 hysteresis = <2000>;
2399 type 2365 type = "hot";
2400 }; 2366 };
2401 }; 2367 };
2402 }; 2368 };
2403 }; 2369 };
2404 2370
2405 timer { 2371 timer {
2406 compatible = "arm,armv7-timer 2372 compatible = "arm,armv7-timer";
2407 interrupts = <GIC_PPI 2 (GIC_ !! 2373 interrupts = <GIC_PPI 2 0xf08>,
2408 <GIC_PPI 3 (GIC_ !! 2374 <GIC_PPI 3 0xf08>,
2409 <GIC_PPI 4 (GIC_ !! 2375 <GIC_PPI 4 0xf08>,
2410 <GIC_PPI 1 (GIC_ !! 2376 <GIC_PPI 1 0xf08>;
2411 clock-frequency = <19200000>; 2377 clock-frequency = <19200000>;
>> 2378 };
>> 2379
>> 2380 vreg_boost: vreg-boost {
>> 2381 compatible = "regulator-fixed";
>> 2382
>> 2383 regulator-name = "vreg-boost";
>> 2384 regulator-min-microvolt = <3150000>;
>> 2385 regulator-max-microvolt = <3150000>;
>> 2386
>> 2387 regulator-always-on;
>> 2388 regulator-boot-on;
>> 2389
>> 2390 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
>> 2391 enable-active-high;
>> 2392
>> 2393 pinctrl-names = "default";
>> 2394 pinctrl-0 = <&boost_bypass_n_pin>;
>> 2395 };
>> 2396
>> 2397 vreg_vph_pwr: vreg-vph-pwr {
>> 2398 compatible = "regulator-fixed";
>> 2399 regulator-name = "vph-pwr";
>> 2400
>> 2401 regulator-min-microvolt = <3600000>;
>> 2402 regulator-max-microvolt = <3600000>;
>> 2403
>> 2404 regulator-always-on;
2412 }; 2405 };
2413 }; 2406 };
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