1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/interconnect/qcom,msm897 4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h 6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974. 7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h 9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 11
12 / { 12 / {
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 16
17 chosen { }; <<
18 <<
19 clocks { 17 clocks {
20 xo_board: xo_board { 18 xo_board: xo_board {
21 compatible = "fixed-cl 19 compatible = "fixed-clock";
22 #clock-cells = <0>; 20 #clock-cells = <0>;
23 clock-frequency = <192 21 clock-frequency = <19200000>;
24 }; 22 };
25 23
26 sleep_clk: sleep_clk { 24 sleep_clk: sleep_clk {
27 compatible = "fixed-cl 25 compatible = "fixed-clock";
28 #clock-cells = <0>; 26 #clock-cells = <0>;
29 clock-frequency = <327 27 clock-frequency = <32768>;
30 }; 28 };
31 }; 29 };
32 30
33 cpus { 31 cpus {
34 #address-cells = <1>; 32 #address-cells = <1>;
35 #size-cells = <0>; 33 #size-cells = <0>;
36 interrupts = <GIC_PPI 9 (GIC_C 34 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
37 35
38 CPU0: cpu@0 { 36 CPU0: cpu@0 {
39 compatible = "qcom,kra 37 compatible = "qcom,krait";
40 enable-method = "qcom, 38 enable-method = "qcom,kpss-acc-v2";
41 device_type = "cpu"; 39 device_type = "cpu";
42 reg = <0>; 40 reg = <0>;
43 next-level-cache = <&L 41 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>; 42 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>; 43 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_SPC>;
47 }; 45 };
48 46
49 CPU1: cpu@1 { 47 CPU1: cpu@1 {
50 compatible = "qcom,kra 48 compatible = "qcom,krait";
51 enable-method = "qcom, 49 enable-method = "qcom,kpss-acc-v2";
52 device_type = "cpu"; 50 device_type = "cpu";
53 reg = <1>; 51 reg = <1>;
54 next-level-cache = <&L 52 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>; 53 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>; 54 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CP 55 cpu-idle-states = <&CPU_SPC>;
58 }; 56 };
59 57
60 CPU2: cpu@2 { 58 CPU2: cpu@2 {
61 compatible = "qcom,kra 59 compatible = "qcom,krait";
62 enable-method = "qcom, 60 enable-method = "qcom,kpss-acc-v2";
63 device_type = "cpu"; 61 device_type = "cpu";
64 reg = <2>; 62 reg = <2>;
65 next-level-cache = <&L 63 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>; 64 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>; 65 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CP 66 cpu-idle-states = <&CPU_SPC>;
69 }; 67 };
70 68
71 CPU3: cpu@3 { 69 CPU3: cpu@3 {
72 compatible = "qcom,kra 70 compatible = "qcom,krait";
73 enable-method = "qcom, 71 enable-method = "qcom,kpss-acc-v2";
74 device_type = "cpu"; 72 device_type = "cpu";
75 reg = <3>; 73 reg = <3>;
76 next-level-cache = <&L 74 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>; 75 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>; 76 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CP 77 cpu-idle-states = <&CPU_SPC>;
80 }; 78 };
81 79
82 L2: l2-cache { 80 L2: l2-cache {
83 compatible = "cache"; 81 compatible = "cache";
84 cache-level = <2>; 82 cache-level = <2>;
85 cache-unified; 83 cache-unified;
86 qcom,saw = <&saw_l2>; 84 qcom,saw = <&saw_l2>;
87 }; 85 };
88 86
89 idle-states { 87 idle-states {
90 CPU_SPC: cpu-spc { !! 88 CPU_SPC: spc {
91 compatible = " 89 compatible = "qcom,idle-state-spc",
92 90 "arm,idle-state";
93 entry-latency- 91 entry-latency-us = <150>;
94 exit-latency-u 92 exit-latency-us = <200>;
95 min-residency- 93 min-residency-us = <2000>;
96 }; 94 };
97 }; 95 };
98 }; 96 };
99 97
100 firmware { 98 firmware {
101 scm { 99 scm {
102 compatible = "qcom,scm 100 compatible = "qcom,scm-msm8974", "qcom,scm";
103 clocks = <&gcc GCC_CE1 101 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
104 clock-names = "core", 102 clock-names = "core", "bus", "iface";
105 }; 103 };
106 }; 104 };
107 105
108 memory@0 { !! 106 memory {
109 device_type = "memory"; 107 device_type = "memory";
110 reg = <0x0 0x0>; 108 reg = <0x0 0x0>;
111 }; 109 };
112 110
113 pmu { 111 pmu {
114 compatible = "qcom,krait-pmu"; 112 compatible = "qcom,krait-pmu";
115 interrupts = <GIC_PPI 7 (GIC_C 113 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
116 }; 114 };
117 115
118 rpm: remoteproc { 116 rpm: remoteproc {
119 compatible = "qcom,msm8974-rpm 117 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
120 118
121 master-stats { 119 master-stats {
122 compatible = "qcom,rpm 120 compatible = "qcom,rpm-master-stats";
123 qcom,rpm-msg-ram = <&a 121 qcom,rpm-msg-ram = <&apss_master_stats>,
124 <&m 122 <&mpss_master_stats>,
125 <&l 123 <&lpss_master_stats>,
126 <&p 124 <&pronto_master_stats>;
127 qcom,master-names = "A 125 qcom,master-names = "APSS",
128 "M 126 "MPSS",
129 "L 127 "LPSS",
130 "P 128 "PRONTO";
131 }; 129 };
132 130
133 smd-edge { 131 smd-edge {
134 interrupts = <GIC_SPI 132 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
135 mboxes = <&apcs 0>; !! 133 qcom,ipc = <&apcs 8 0>;
136 qcom,smd-edge = <15>; 134 qcom,smd-edge = <15>;
137 135
138 rpm_requests: rpm-requ 136 rpm_requests: rpm-requests {
139 compatible = " !! 137 compatible = "qcom,rpm-msm8974";
140 qcom,smd-chann 138 qcom,smd-channels = "rpm_requests";
141 139
142 rpmcc: clock-c 140 rpmcc: clock-controller {
143 compat 141 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
144 #clock 142 #clock-cells = <1>;
145 clocks 143 clocks = <&xo_board>;
146 clock- 144 clock-names = "xo";
147 }; 145 };
148 }; 146 };
149 }; 147 };
150 }; 148 };
151 149
152 reserved_memory: reserved-memory { !! 150 reserved-memory {
153 #address-cells = <1>; 151 #address-cells = <1>;
154 #size-cells = <1>; 152 #size-cells = <1>;
155 ranges; 153 ranges;
156 154
157 mpss_region: mpss@8000000 { 155 mpss_region: mpss@8000000 {
158 reg = <0x08000000 0x51 156 reg = <0x08000000 0x5100000>;
159 no-map; 157 no-map;
160 }; 158 };
161 159
162 mba_region: mba@d100000 { 160 mba_region: mba@d100000 {
163 reg = <0x0d100000 0x10 161 reg = <0x0d100000 0x100000>;
164 no-map; 162 no-map;
165 }; 163 };
166 164
167 wcnss_region: wcnss@d200000 { 165 wcnss_region: wcnss@d200000 {
168 reg = <0x0d200000 0xa0 166 reg = <0x0d200000 0xa00000>;
169 no-map; 167 no-map;
170 }; 168 };
171 169
172 adsp_region: adsp@dc00000 { 170 adsp_region: adsp@dc00000 {
173 reg = <0x0dc00000 0x19 171 reg = <0x0dc00000 0x1900000>;
174 no-map; 172 no-map;
175 }; 173 };
176 174
177 venus_region: memory@f500000 { 175 venus_region: memory@f500000 {
178 reg = <0x0f500000 0x50 176 reg = <0x0f500000 0x500000>;
179 no-map; 177 no-map;
180 }; 178 };
181 179
182 smem_region: smem@fa00000 { 180 smem_region: smem@fa00000 {
183 reg = <0xfa00000 0x200 181 reg = <0xfa00000 0x200000>;
184 no-map; 182 no-map;
185 }; 183 };
186 184
187 tz_region: memory@fc00000 { 185 tz_region: memory@fc00000 {
188 reg = <0x0fc00000 0x16 186 reg = <0x0fc00000 0x160000>;
189 no-map; 187 no-map;
190 }; 188 };
191 189
192 rfsa_mem: memory@fd60000 { 190 rfsa_mem: memory@fd60000 {
193 reg = <0x0fd60000 0x20 191 reg = <0x0fd60000 0x20000>;
194 no-map; 192 no-map;
195 }; 193 };
196 194
197 rmtfs@fd80000 { 195 rmtfs@fd80000 {
198 compatible = "qcom,rmt 196 compatible = "qcom,rmtfs-mem";
199 reg = <0x0fd80000 0x18 197 reg = <0x0fd80000 0x180000>;
200 no-map; 198 no-map;
201 199
202 qcom,client-id = <1>; 200 qcom,client-id = <1>;
203 }; 201 };
204 }; 202 };
205 203
206 smem { 204 smem {
207 compatible = "qcom,smem"; 205 compatible = "qcom,smem";
208 206
209 memory-region = <&smem_region> 207 memory-region = <&smem_region>;
210 qcom,rpm-msg-ram = <&rpm_msg_r 208 qcom,rpm-msg-ram = <&rpm_msg_ram>;
211 209
212 hwlocks = <&tcsr_mutex 3>; 210 hwlocks = <&tcsr_mutex 3>;
213 }; 211 };
214 212
215 smp2p-adsp { 213 smp2p-adsp {
216 compatible = "qcom,smp2p"; 214 compatible = "qcom,smp2p";
217 qcom,smem = <443>, <429>; 215 qcom,smem = <443>, <429>;
218 216
219 interrupt-parent = <&intc>; 217 interrupt-parent = <&intc>;
220 interrupts = <GIC_SPI 158 IRQ_ 218 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
221 219
222 mboxes = <&apcs 10>; !! 220 qcom,ipc = <&apcs 8 10>;
223 221
224 qcom,local-pid = <0>; 222 qcom,local-pid = <0>;
225 qcom,remote-pid = <2>; 223 qcom,remote-pid = <2>;
226 224
227 adsp_smp2p_out: master-kernel 225 adsp_smp2p_out: master-kernel {
228 qcom,entry-name = "mas 226 qcom,entry-name = "master-kernel";
229 #qcom,smem-state-cells 227 #qcom,smem-state-cells = <1>;
230 }; 228 };
231 229
232 adsp_smp2p_in: slave-kernel { 230 adsp_smp2p_in: slave-kernel {
233 qcom,entry-name = "sla 231 qcom,entry-name = "slave-kernel";
234 232
235 interrupt-controller; 233 interrupt-controller;
236 #interrupt-cells = <2> 234 #interrupt-cells = <2>;
237 }; 235 };
238 }; 236 };
239 237
240 smp2p-modem { 238 smp2p-modem {
241 compatible = "qcom,smp2p"; 239 compatible = "qcom,smp2p";
242 qcom,smem = <435>, <428>; 240 qcom,smem = <435>, <428>;
243 241
244 interrupt-parent = <&intc>; 242 interrupt-parent = <&intc>;
245 interrupts = <GIC_SPI 27 IRQ_T 243 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
246 244
247 mboxes = <&apcs 14>; !! 245 qcom,ipc = <&apcs 8 14>;
248 246
249 qcom,local-pid = <0>; 247 qcom,local-pid = <0>;
250 qcom,remote-pid = <1>; 248 qcom,remote-pid = <1>;
251 249
252 modem_smp2p_out: master-kernel 250 modem_smp2p_out: master-kernel {
253 qcom,entry-name = "mas 251 qcom,entry-name = "master-kernel";
254 #qcom,smem-state-cells 252 #qcom,smem-state-cells = <1>;
255 }; 253 };
256 254
257 modem_smp2p_in: slave-kernel { 255 modem_smp2p_in: slave-kernel {
258 qcom,entry-name = "sla 256 qcom,entry-name = "slave-kernel";
259 257
260 interrupt-controller; 258 interrupt-controller;
261 #interrupt-cells = <2> 259 #interrupt-cells = <2>;
262 }; 260 };
263 }; 261 };
264 262
265 smp2p-wcnss { 263 smp2p-wcnss {
266 compatible = "qcom,smp2p"; 264 compatible = "qcom,smp2p";
267 qcom,smem = <451>, <431>; 265 qcom,smem = <451>, <431>;
268 266
269 interrupt-parent = <&intc>; 267 interrupt-parent = <&intc>;
270 interrupts = <GIC_SPI 143 IRQ_ 268 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
271 269
272 mboxes = <&apcs 18>; !! 270 qcom,ipc = <&apcs 8 18>;
273 271
274 qcom,local-pid = <0>; 272 qcom,local-pid = <0>;
275 qcom,remote-pid = <4>; 273 qcom,remote-pid = <4>;
276 274
277 wcnss_smp2p_out: master-kernel 275 wcnss_smp2p_out: master-kernel {
278 qcom,entry-name = "mas 276 qcom,entry-name = "master-kernel";
279 277
280 #qcom,smem-state-cells 278 #qcom,smem-state-cells = <1>;
281 }; 279 };
282 280
283 wcnss_smp2p_in: slave-kernel { 281 wcnss_smp2p_in: slave-kernel {
284 qcom,entry-name = "sla 282 qcom,entry-name = "slave-kernel";
285 283
286 interrupt-controller; 284 interrupt-controller;
287 #interrupt-cells = <2> 285 #interrupt-cells = <2>;
288 }; 286 };
289 }; 287 };
290 288
291 smsm { 289 smsm {
292 compatible = "qcom,smsm"; 290 compatible = "qcom,smsm";
293 291
294 #address-cells = <1>; 292 #address-cells = <1>;
295 #size-cells = <0>; 293 #size-cells = <0>;
296 294
297 mboxes = <0>, <&apcs 13>, <&ap !! 295 qcom,ipc-1 = <&apcs 8 13>;
>> 296 qcom,ipc-2 = <&apcs 8 9>;
>> 297 qcom,ipc-3 = <&apcs 8 19>;
298 298
299 apps_smsm: apps@0 { 299 apps_smsm: apps@0 {
300 reg = <0>; 300 reg = <0>;
301 301
302 #qcom,smem-state-cells 302 #qcom,smem-state-cells = <1>;
303 }; 303 };
304 304
305 modem_smsm: modem@1 { 305 modem_smsm: modem@1 {
306 reg = <1>; 306 reg = <1>;
307 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
308 308
309 interrupt-controller; 309 interrupt-controller;
310 #interrupt-cells = <2> 310 #interrupt-cells = <2>;
311 }; 311 };
312 312
313 adsp_smsm: adsp@2 { 313 adsp_smsm: adsp@2 {
314 reg = <2>; 314 reg = <2>;
315 interrupts = <GIC_SPI 315 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
316 316
317 interrupt-controller; 317 interrupt-controller;
318 #interrupt-cells = <2> 318 #interrupt-cells = <2>;
319 }; 319 };
320 320
321 wcnss_smsm: wcnss@7 { 321 wcnss_smsm: wcnss@7 {
322 reg = <7>; 322 reg = <7>;
323 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
324 324
325 interrupt-controller; 325 interrupt-controller;
326 #interrupt-cells = <2> 326 #interrupt-cells = <2>;
327 }; 327 };
328 }; 328 };
329 329
330 soc: soc { 330 soc: soc {
331 #address-cells = <1>; 331 #address-cells = <1>;
332 #size-cells = <1>; 332 #size-cells = <1>;
333 ranges; 333 ranges;
334 compatible = "simple-bus"; 334 compatible = "simple-bus";
335 335
336 intc: interrupt-controller@f90 336 intc: interrupt-controller@f9000000 {
337 compatible = "qcom,msm 337 compatible = "qcom,msm-qgic2";
338 interrupt-controller; 338 interrupt-controller;
339 #interrupt-cells = <3> 339 #interrupt-cells = <3>;
340 reg = <0xf9000000 0x10 340 reg = <0xf9000000 0x1000>,
341 <0xf9002000 0x10 341 <0xf9002000 0x1000>;
342 }; 342 };
343 343
344 apcs: mailbox@f9011000 { !! 344 apcs: syscon@f9011000 {
345 compatible = "qcom,msm !! 345 compatible = "syscon";
346 "qcom,msm <<
347 reg = <0xf9011000 0x10 346 reg = <0xf9011000 0x1000>;
348 #mbox-cells = <1>; <<
349 }; 347 };
350 348
351 saw_l2: power-manager@f9012000 349 saw_l2: power-manager@f9012000 {
352 compatible = "qcom,msm 350 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
353 reg = <0xf9012000 0x10 351 reg = <0xf9012000 0x1000>;
354 }; 352 };
355 353
356 watchdog@f9017000 { 354 watchdog@f9017000 {
357 compatible = "qcom,aps 355 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt";
358 reg = <0xf9017000 0x10 356 reg = <0xf9017000 0x1000>;
359 interrupts = <GIC_SPI 357 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
360 <GIC_SPI 358 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
361 clocks = <&sleep_clk>; 359 clocks = <&sleep_clk>;
362 }; 360 };
363 361
364 timer@f9020000 { 362 timer@f9020000 {
365 #address-cells = <1>; 363 #address-cells = <1>;
366 #size-cells = <1>; 364 #size-cells = <1>;
367 ranges; 365 ranges;
368 compatible = "arm,armv 366 compatible = "arm,armv7-timer-mem";
369 reg = <0xf9020000 0x10 367 reg = <0xf9020000 0x1000>;
370 clock-frequency = <192 368 clock-frequency = <19200000>;
371 369
372 frame@f9021000 { 370 frame@f9021000 {
373 frame-number = 371 frame-number = <0>;
374 interrupts = < 372 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
375 < 373 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
376 reg = <0xf9021 374 reg = <0xf9021000 0x1000>,
377 <0xf9022 375 <0xf9022000 0x1000>;
378 }; 376 };
379 377
380 frame@f9023000 { 378 frame@f9023000 {
381 frame-number = 379 frame-number = <1>;
382 interrupts = < 380 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
383 reg = <0xf9023 381 reg = <0xf9023000 0x1000>;
384 status = "disa 382 status = "disabled";
385 }; 383 };
386 384
387 frame@f9024000 { 385 frame@f9024000 {
388 frame-number = 386 frame-number = <2>;
389 interrupts = < 387 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
390 reg = <0xf9024 388 reg = <0xf9024000 0x1000>;
391 status = "disa 389 status = "disabled";
392 }; 390 };
393 391
394 frame@f9025000 { 392 frame@f9025000 {
395 frame-number = 393 frame-number = <3>;
396 interrupts = < 394 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
397 reg = <0xf9025 395 reg = <0xf9025000 0x1000>;
398 status = "disa 396 status = "disabled";
399 }; 397 };
400 398
401 frame@f9026000 { 399 frame@f9026000 {
402 frame-number = 400 frame-number = <4>;
403 interrupts = < 401 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
404 reg = <0xf9026 402 reg = <0xf9026000 0x1000>;
405 status = "disa 403 status = "disabled";
406 }; 404 };
407 405
408 frame@f9027000 { 406 frame@f9027000 {
409 frame-number = 407 frame-number = <5>;
410 interrupts = < 408 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
411 reg = <0xf9027 409 reg = <0xf9027000 0x1000>;
412 status = "disa 410 status = "disabled";
413 }; 411 };
414 412
415 frame@f9028000 { 413 frame@f9028000 {
416 frame-number = 414 frame-number = <6>;
417 interrupts = < 415 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
418 reg = <0xf9028 416 reg = <0xf9028000 0x1000>;
419 status = "disa 417 status = "disabled";
420 }; 418 };
421 }; 419 };
422 420
423 acc0: power-manager@f9088000 { 421 acc0: power-manager@f9088000 {
424 compatible = "qcom,kps 422 compatible = "qcom,kpss-acc-v2";
425 reg = <0xf9088000 0x10 423 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
426 }; 424 };
427 425
428 saw0: power-manager@f9089000 { 426 saw0: power-manager@f9089000 {
429 compatible = "qcom,msm 427 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
430 reg = <0xf9089000 0x10 428 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
431 }; 429 };
432 430
433 acc1: power-manager@f9098000 { 431 acc1: power-manager@f9098000 {
434 compatible = "qcom,kps 432 compatible = "qcom,kpss-acc-v2";
435 reg = <0xf9098000 0x10 433 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
436 }; 434 };
437 435
438 saw1: power-manager@f9099000 { 436 saw1: power-manager@f9099000 {
439 compatible = "qcom,msm 437 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
440 reg = <0xf9099000 0x10 438 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
441 }; 439 };
442 440
443 acc2: power-manager@f90a8000 { 441 acc2: power-manager@f90a8000 {
444 compatible = "qcom,kps 442 compatible = "qcom,kpss-acc-v2";
445 reg = <0xf90a8000 0x10 443 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
446 }; 444 };
447 445
448 saw2: power-manager@f90a9000 { 446 saw2: power-manager@f90a9000 {
449 compatible = "qcom,msm 447 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
450 reg = <0xf90a9000 0x10 448 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
451 }; 449 };
452 450
453 acc3: power-manager@f90b8000 { 451 acc3: power-manager@f90b8000 {
454 compatible = "qcom,kps 452 compatible = "qcom,kpss-acc-v2";
455 reg = <0xf90b8000 0x10 453 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
456 }; 454 };
457 455
458 saw3: power-manager@f90b9000 { 456 saw3: power-manager@f90b9000 {
459 compatible = "qcom,msm 457 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
460 reg = <0xf90b9000 0x10 458 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
461 }; 459 };
462 460
463 sdhc_1: mmc@f9824900 { 461 sdhc_1: mmc@f9824900 {
464 compatible = "qcom,msm 462 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
465 reg = <0xf9824900 0x11 463 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
466 reg-names = "hc", "cor 464 reg-names = "hc", "core";
467 interrupts = <GIC_SPI 465 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 466 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "hc_ 467 interrupt-names = "hc_irq", "pwr_irq";
470 clocks = <&gcc GCC_SDC 468 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
471 <&gcc GCC_SDC 469 <&gcc GCC_SDCC1_APPS_CLK>,
472 <&xo_board>; 470 <&xo_board>;
473 clock-names = "iface", 471 clock-names = "iface", "core", "xo";
474 bus-width = <8>; 472 bus-width = <8>;
475 non-removable; 473 non-removable;
476 474
477 status = "disabled"; 475 status = "disabled";
478 }; 476 };
479 477
480 sdhc_3: mmc@f9864900 { 478 sdhc_3: mmc@f9864900 {
481 compatible = "qcom,msm 479 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
482 reg = <0xf9864900 0x11 480 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
483 reg-names = "hc", "cor 481 reg-names = "hc", "core";
484 interrupts = <GIC_SPI 482 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 483 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-names = "hc_ 484 interrupt-names = "hc_irq", "pwr_irq";
487 clocks = <&gcc GCC_SDC 485 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
488 <&gcc GCC_SDC 486 <&gcc GCC_SDCC3_APPS_CLK>,
489 <&xo_board>; 487 <&xo_board>;
490 clock-names = "iface", 488 clock-names = "iface", "core", "xo";
491 bus-width = <4>; 489 bus-width = <4>;
492 490
493 #address-cells = <1>; 491 #address-cells = <1>;
494 #size-cells = <0>; 492 #size-cells = <0>;
495 493
496 status = "disabled"; 494 status = "disabled";
497 }; 495 };
498 496
499 sdhc_2: mmc@f98a4900 { 497 sdhc_2: mmc@f98a4900 {
500 compatible = "qcom,msm 498 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
501 reg = <0xf98a4900 0x11 499 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
502 reg-names = "hc", "cor 500 reg-names = "hc", "core";
503 interrupts = <GIC_SPI 501 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 502 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "hc_ 503 interrupt-names = "hc_irq", "pwr_irq";
506 clocks = <&gcc GCC_SDC 504 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
507 <&gcc GCC_SDC 505 <&gcc GCC_SDCC2_APPS_CLK>,
508 <&xo_board>; 506 <&xo_board>;
509 clock-names = "iface", 507 clock-names = "iface", "core", "xo";
510 bus-width = <4>; 508 bus-width = <4>;
511 509
512 #address-cells = <1>; 510 #address-cells = <1>;
513 #size-cells = <0>; 511 #size-cells = <0>;
514 512
515 status = "disabled"; 513 status = "disabled";
516 }; 514 };
517 515
518 blsp1_uart1: serial@f991d000 { 516 blsp1_uart1: serial@f991d000 {
519 compatible = "qcom,msm 517 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
520 reg = <0xf991d000 0x10 518 reg = <0xf991d000 0x1000>;
521 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gcc GCC_BLS 520 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", 521 clock-names = "core", "iface";
524 status = "disabled"; 522 status = "disabled";
525 }; 523 };
526 524
527 blsp1_uart2: serial@f991e000 { 525 blsp1_uart2: serial@f991e000 {
528 compatible = "qcom,msm 526 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
529 reg = <0xf991e000 0x10 527 reg = <0xf991e000 0x1000>;
530 interrupts = <GIC_SPI 528 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&gcc GCC_BLS 529 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
532 clock-names = "core", 530 clock-names = "core", "iface";
533 pinctrl-names = "defau 531 pinctrl-names = "default";
534 pinctrl-0 = <&blsp1_ua 532 pinctrl-0 = <&blsp1_uart2_default>;
535 status = "disabled"; 533 status = "disabled";
536 }; 534 };
537 535
538 blsp1_i2c1: i2c@f9923000 { 536 blsp1_i2c1: i2c@f9923000 {
539 status = "disabled"; 537 status = "disabled";
540 compatible = "qcom,i2c 538 compatible = "qcom,i2c-qup-v2.1.1";
541 reg = <0xf9923000 0x10 539 reg = <0xf9923000 0x1000>;
542 interrupts = <GIC_SPI 540 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLS 541 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
544 clock-names = "core", 542 clock-names = "core", "iface";
545 pinctrl-names = "defau 543 pinctrl-names = "default", "sleep";
546 pinctrl-0 = <&blsp1_i2 544 pinctrl-0 = <&blsp1_i2c1_default>;
547 pinctrl-1 = <&blsp1_i2 545 pinctrl-1 = <&blsp1_i2c1_sleep>;
548 #address-cells = <1>; 546 #address-cells = <1>;
549 #size-cells = <0>; 547 #size-cells = <0>;
550 }; 548 };
551 549
552 blsp1_i2c2: i2c@f9924000 { 550 blsp1_i2c2: i2c@f9924000 {
553 status = "disabled"; 551 status = "disabled";
554 compatible = "qcom,i2c 552 compatible = "qcom,i2c-qup-v2.1.1";
555 reg = <0xf9924000 0x10 553 reg = <0xf9924000 0x1000>;
556 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&gcc GCC_BLS 555 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
558 clock-names = "core", 556 clock-names = "core", "iface";
559 pinctrl-names = "defau 557 pinctrl-names = "default", "sleep";
560 pinctrl-0 = <&blsp1_i2 558 pinctrl-0 = <&blsp1_i2c2_default>;
561 pinctrl-1 = <&blsp1_i2 559 pinctrl-1 = <&blsp1_i2c2_sleep>;
562 #address-cells = <1>; 560 #address-cells = <1>;
563 #size-cells = <0>; 561 #size-cells = <0>;
564 }; 562 };
565 563
566 blsp1_i2c3: i2c@f9925000 { 564 blsp1_i2c3: i2c@f9925000 {
567 status = "disabled"; 565 status = "disabled";
568 compatible = "qcom,i2c 566 compatible = "qcom,i2c-qup-v2.1.1";
569 reg = <0xf9925000 0x10 567 reg = <0xf9925000 0x1000>;
570 interrupts = <GIC_SPI 568 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc GCC_BLS 569 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
572 clock-names = "core", 570 clock-names = "core", "iface";
573 pinctrl-names = "defau 571 pinctrl-names = "default", "sleep";
574 pinctrl-0 = <&blsp1_i2 572 pinctrl-0 = <&blsp1_i2c3_default>;
575 pinctrl-1 = <&blsp1_i2 573 pinctrl-1 = <&blsp1_i2c3_sleep>;
576 #address-cells = <1>; 574 #address-cells = <1>;
577 #size-cells = <0>; 575 #size-cells = <0>;
578 }; 576 };
579 577
580 blsp1_i2c6: i2c@f9928000 { 578 blsp1_i2c6: i2c@f9928000 {
581 status = "disabled"; 579 status = "disabled";
582 compatible = "qcom,i2c 580 compatible = "qcom,i2c-qup-v2.1.1";
583 reg = <0xf9928000 0x10 581 reg = <0xf9928000 0x1000>;
584 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&gcc GCC_BLS 583 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
586 clock-names = "core", 584 clock-names = "core", "iface";
587 pinctrl-names = "defau 585 pinctrl-names = "default", "sleep";
588 pinctrl-0 = <&blsp1_i2 586 pinctrl-0 = <&blsp1_i2c6_default>;
589 pinctrl-1 = <&blsp1_i2 587 pinctrl-1 = <&blsp1_i2c6_sleep>;
590 #address-cells = <1>; 588 #address-cells = <1>;
591 #size-cells = <0>; 589 #size-cells = <0>;
592 }; 590 };
593 591
594 blsp2_dma: dma-controller@f994 592 blsp2_dma: dma-controller@f9944000 {
595 compatible = "qcom,bam 593 compatible = "qcom,bam-v1.4.0";
596 reg = <0xf9944000 0x19 594 reg = <0xf9944000 0x19000>;
597 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLS 596 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
599 clock-names = "bam_clk 597 clock-names = "bam_clk";
600 #dma-cells = <1>; 598 #dma-cells = <1>;
601 qcom,ee = <0>; 599 qcom,ee = <0>;
602 }; 600 };
603 601
604 blsp2_uart1: serial@f995d000 { 602 blsp2_uart1: serial@f995d000 {
605 compatible = "qcom,msm 603 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606 reg = <0xf995d000 0x10 604 reg = <0xf995d000 0x1000>;
607 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GCC_BLS 606 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
609 clock-names = "core", 607 clock-names = "core", "iface";
610 pinctrl-names = "defau 608 pinctrl-names = "default", "sleep";
611 pinctrl-0 = <&blsp2_ua 609 pinctrl-0 = <&blsp2_uart1_default>;
612 pinctrl-1 = <&blsp2_ua 610 pinctrl-1 = <&blsp2_uart1_sleep>;
613 status = "disabled"; 611 status = "disabled";
614 }; 612 };
615 613
616 blsp2_uart2: serial@f995e000 { 614 blsp2_uart2: serial@f995e000 {
617 compatible = "qcom,msm 615 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
618 reg = <0xf995e000 0x10 616 reg = <0xf995e000 0x1000>;
619 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&gcc GCC_BLS 618 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
621 clock-names = "core", 619 clock-names = "core", "iface";
622 status = "disabled"; 620 status = "disabled";
623 }; 621 };
624 622
625 blsp2_uart4: serial@f9960000 { 623 blsp2_uart4: serial@f9960000 {
626 compatible = "qcom,msm 624 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
627 reg = <0xf9960000 0x10 625 reg = <0xf9960000 0x1000>;
628 interrupts = <GIC_SPI 626 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&gcc GCC_BLS 627 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
630 clock-names = "core", 628 clock-names = "core", "iface";
631 pinctrl-names = "defau 629 pinctrl-names = "default";
632 pinctrl-0 = <&blsp2_ua 630 pinctrl-0 = <&blsp2_uart4_default>;
633 status = "disabled"; 631 status = "disabled";
634 }; 632 };
635 633
636 blsp2_i2c2: i2c@f9964000 { 634 blsp2_i2c2: i2c@f9964000 {
637 status = "disabled"; 635 status = "disabled";
638 compatible = "qcom,i2c 636 compatible = "qcom,i2c-qup-v2.1.1";
639 reg = <0xf9964000 0x10 637 reg = <0xf9964000 0x1000>;
640 interrupts = <GIC_SPI 638 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&gcc GCC_BLS 639 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
642 clock-names = "core", 640 clock-names = "core", "iface";
643 pinctrl-names = "defau 641 pinctrl-names = "default", "sleep";
644 pinctrl-0 = <&blsp2_i2 642 pinctrl-0 = <&blsp2_i2c2_default>;
645 pinctrl-1 = <&blsp2_i2 643 pinctrl-1 = <&blsp2_i2c2_sleep>;
646 #address-cells = <1>; 644 #address-cells = <1>;
647 #size-cells = <0>; 645 #size-cells = <0>;
648 }; 646 };
649 647
650 blsp2_i2c5: i2c@f9967000 { 648 blsp2_i2c5: i2c@f9967000 {
651 status = "disabled"; 649 status = "disabled";
652 compatible = "qcom,i2c 650 compatible = "qcom,i2c-qup-v2.1.1";
653 reg = <0xf9967000 0x10 651 reg = <0xf9967000 0x1000>;
654 interrupts = <GIC_SPI 652 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&gcc GCC_BLS 653 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
656 clock-names = "core", 654 clock-names = "core", "iface";
657 dmas = <&blsp2_dma 20> 655 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
658 dma-names = "tx", "rx" 656 dma-names = "tx", "rx";
659 pinctrl-names = "defau 657 pinctrl-names = "default", "sleep";
660 pinctrl-0 = <&blsp2_i2 658 pinctrl-0 = <&blsp2_i2c5_default>;
661 pinctrl-1 = <&blsp2_i2 659 pinctrl-1 = <&blsp2_i2c5_sleep>;
662 #address-cells = <1>; 660 #address-cells = <1>;
663 #size-cells = <0>; 661 #size-cells = <0>;
664 }; 662 };
665 663
666 blsp2_i2c6: i2c@f9968000 { 664 blsp2_i2c6: i2c@f9968000 {
667 status = "disabled"; 665 status = "disabled";
668 compatible = "qcom,i2c 666 compatible = "qcom,i2c-qup-v2.1.1";
669 reg = <0xf9968000 0x10 667 reg = <0xf9968000 0x1000>;
670 interrupts = <GIC_SPI 668 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&gcc GCC_BLS 669 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
672 clock-names = "core", 670 clock-names = "core", "iface";
673 pinctrl-names = "defau 671 pinctrl-names = "default", "sleep";
674 pinctrl-0 = <&blsp2_i2 672 pinctrl-0 = <&blsp2_i2c6_default>;
675 pinctrl-1 = <&blsp2_i2 673 pinctrl-1 = <&blsp2_i2c6_sleep>;
676 #address-cells = <1>; 674 #address-cells = <1>;
677 #size-cells = <0>; 675 #size-cells = <0>;
678 }; 676 };
679 677
680 usb: usb@f9a55000 { 678 usb: usb@f9a55000 {
681 compatible = "qcom,ci- 679 compatible = "qcom,ci-hdrc";
682 reg = <0xf9a55000 0x20 680 reg = <0xf9a55000 0x200>,
683 <0xf9a55200 0x20 681 <0xf9a55200 0x200>;
684 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&gcc GCC_USB 683 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
686 <&gcc GCC_USB 684 <&gcc GCC_USB_HS_SYSTEM_CLK>;
687 clock-names = "iface", 685 clock-names = "iface", "core";
688 assigned-clocks = <&gc 686 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
689 assigned-clock-rates = 687 assigned-clock-rates = <75000000>;
690 resets = <&gcc GCC_USB 688 resets = <&gcc GCC_USB_HS_BCR>;
691 reset-names = "core"; 689 reset-names = "core";
692 phy_type = "ulpi"; 690 phy_type = "ulpi";
693 dr_mode = "otg"; 691 dr_mode = "otg";
694 ahb-burst-config = <0> 692 ahb-burst-config = <0>;
695 phy-names = "usb-phy"; 693 phy-names = "usb-phy";
696 status = "disabled"; 694 status = "disabled";
697 #reset-cells = <1>; 695 #reset-cells = <1>;
698 696
699 ulpi { 697 ulpi {
700 usb_hs1_phy: p 698 usb_hs1_phy: phy-0 {
701 compat 699 compatible = "qcom,usb-hs-phy-msm8974",
702 700 "qcom,usb-hs-phy";
703 #phy-c 701 #phy-cells = <0>;
704 clocks 702 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
705 clock- 703 clock-names = "ref", "sleep";
706 resets 704 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
707 reset- 705 reset-names = "phy", "por";
708 status 706 status = "disabled";
709 }; 707 };
710 708
711 usb_hs2_phy: p 709 usb_hs2_phy: phy-1 {
712 compat 710 compatible = "qcom,usb-hs-phy-msm8974",
713 711 "qcom,usb-hs-phy";
714 #phy-c 712 #phy-cells = <0>;
715 clocks 713 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
716 clock- 714 clock-names = "ref", "sleep";
717 resets 715 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
718 reset- 716 reset-names = "phy", "por";
719 status 717 status = "disabled";
720 }; 718 };
721 }; 719 };
722 }; 720 };
723 721
724 rng@f9bff000 { 722 rng@f9bff000 {
725 compatible = "qcom,prn 723 compatible = "qcom,prng";
726 reg = <0xf9bff000 0x20 724 reg = <0xf9bff000 0x200>;
727 clocks = <&gcc GCC_PRN 725 clocks = <&gcc GCC_PRNG_AHB_CLK>;
728 clock-names = "core"; 726 clock-names = "core";
729 }; 727 };
730 728
731 pronto: remoteproc@fb204000 { 729 pronto: remoteproc@fb204000 {
732 compatible = "qcom,pro 730 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
733 reg = <0xfb204000 0x20 731 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
734 reg-names = "ccu", "dx 732 reg-names = "ccu", "dxe", "pmu";
735 733
736 memory-region = <&wcns 734 memory-region = <&wcnss_region>;
737 735
738 interrupts-extended = 736 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
739 737 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
740 738 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
741 739 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
742 740 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
743 interrupt-names = "wdo 741 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
744 742
745 qcom,smem-states = <&w 743 qcom,smem-states = <&wcnss_smp2p_out 0>;
746 qcom,smem-state-names 744 qcom,smem-state-names = "stop";
747 745
748 status = "disabled"; 746 status = "disabled";
749 747
750 iris { 748 iris {
751 compatible = " 749 compatible = "qcom,wcn3680";
752 750
753 clocks = <&rpm 751 clocks = <&rpmcc RPM_SMD_CXO_A2>;
754 clock-names = 752 clock-names = "xo";
755 }; 753 };
756 754
757 smd-edge { 755 smd-edge {
758 interrupts = < 756 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
759 757
760 mboxes = <&apc !! 758 qcom,ipc = <&apcs 8 17>;
761 qcom,smd-edge 759 qcom,smd-edge = <6>;
762 760
763 wcnss { 761 wcnss {
764 compat 762 compatible = "qcom,wcnss";
765 qcom,s 763 qcom,smd-channels = "WCNSS_CTRL";
766 status 764 status = "disabled";
767 765
768 qcom,m 766 qcom,mmio = <&pronto>;
769 767
770 blueto 768 bluetooth {
771 769 compatible = "qcom,wcnss-bt";
772 }; 770 };
773 771
774 wifi { 772 wifi {
775 773 compatible = "qcom,wcnss-wlan";
776 774
777 775 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
778 776 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
779 777 interrupt-names = "tx", "rx";
780 778
781 779 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
782 780 qcom,smem-state-names = "tx-enable",
783 781 "tx-rings-empty";
784 }; 782 };
785 }; 783 };
786 }; 784 };
787 }; 785 };
788 786
789 sram@fc190000 { 787 sram@fc190000 {
790 compatible = "qcom,msm 788 compatible = "qcom,msm8974-rpm-stats";
791 reg = <0xfc190000 0x10 789 reg = <0xfc190000 0x10000>;
792 }; 790 };
793 791
794 etf@fc307000 { 792 etf@fc307000 {
795 compatible = "arm,core 793 compatible = "arm,coresight-tmc", "arm,primecell";
796 reg = <0xfc307000 0x10 794 reg = <0xfc307000 0x1000>;
797 795
798 clocks = <&rpmcc RPM_S 796 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
799 clock-names = "apb_pcl 797 clock-names = "apb_pclk", "atclk";
800 798
801 out-ports { 799 out-ports {
802 port { 800 port {
803 etf_ou 801 etf_out: endpoint {
804 802 remote-endpoint = <&replicator_in>;
805 }; 803 };
806 }; 804 };
807 }; 805 };
808 806
809 in-ports { 807 in-ports {
810 port { 808 port {
811 etf_in 809 etf_in: endpoint {
812 810 remote-endpoint = <&merger_out>;
813 }; 811 };
814 }; 812 };
815 }; 813 };
816 }; 814 };
817 815
818 tpiu@fc318000 { 816 tpiu@fc318000 {
819 compatible = "arm,core 817 compatible = "arm,coresight-tpiu", "arm,primecell";
820 reg = <0xfc318000 0x10 818 reg = <0xfc318000 0x1000>;
821 819
822 clocks = <&rpmcc RPM_S 820 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
823 clock-names = "apb_pcl 821 clock-names = "apb_pclk", "atclk";
824 822
825 in-ports { 823 in-ports {
826 port { 824 port {
827 tpiu_i 825 tpiu_in: endpoint {
828 826 remote-endpoint = <&replicator_out1>;
829 }; 827 };
830 }; 828 };
831 }; 829 };
832 }; 830 };
833 831
834 funnel@fc31a000 { 832 funnel@fc31a000 {
835 compatible = "arm,core 833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
836 reg = <0xfc31a000 0x10 834 reg = <0xfc31a000 0x1000>;
837 835
838 clocks = <&rpmcc RPM_S 836 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
839 clock-names = "apb_pcl 837 clock-names = "apb_pclk", "atclk";
840 838
841 in-ports { 839 in-ports {
842 #address-cells 840 #address-cells = <1>;
843 #size-cells = 841 #size-cells = <0>;
844 842
845 /* 843 /*
846 * Not describ 844 * Not described input ports:
847 * 0 - not-con 845 * 0 - not-connected
848 * 1 - connect 846 * 1 - connected trought funnel to Multimedia CPU
849 * 2 - connect 847 * 2 - connected to Wireless CPU
850 * 3 - not-con 848 * 3 - not-connected
851 * 4 - not-con 849 * 4 - not-connected
852 * 6 - not-con 850 * 6 - not-connected
853 * 7 - connect 851 * 7 - connected to STM
854 */ 852 */
855 port@5 { 853 port@5 {
856 reg = 854 reg = <5>;
857 funnel 855 funnel1_in5: endpoint {
858 856 remote-endpoint = <&kpss_out>;
859 }; 857 };
860 }; 858 };
861 }; 859 };
862 860
863 out-ports { 861 out-ports {
864 port { 862 port {
865 funnel 863 funnel1_out: endpoint {
866 864 remote-endpoint = <&merger_in1>;
867 }; 865 };
868 }; 866 };
869 }; 867 };
870 }; 868 };
871 869
872 funnel@fc31b000 { 870 funnel@fc31b000 {
873 compatible = "arm,core 871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
874 reg = <0xfc31b000 0x10 872 reg = <0xfc31b000 0x1000>;
875 873
876 clocks = <&rpmcc RPM_S 874 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
877 clock-names = "apb_pcl 875 clock-names = "apb_pclk", "atclk";
878 876
879 in-ports { 877 in-ports {
880 #address-cells 878 #address-cells = <1>;
881 #size-cells = 879 #size-cells = <0>;
882 880
883 /* 881 /*
884 * Not describ 882 * Not described input ports:
885 * 0 - connect 883 * 0 - connected trought funnel to Audio, Modem and
886 * Resourc 884 * Resource and Power Manager CPU's
887 * 2...7 - not 885 * 2...7 - not-connected
888 */ 886 */
889 port@1 { 887 port@1 {
890 reg = 888 reg = <1>;
891 merger 889 merger_in1: endpoint {
892 890 remote-endpoint = <&funnel1_out>;
893 }; 891 };
894 }; 892 };
895 }; 893 };
896 894
897 out-ports { 895 out-ports {
898 port { 896 port {
899 merger 897 merger_out: endpoint {
900 898 remote-endpoint = <&etf_in>;
901 }; 899 };
902 }; 900 };
903 }; 901 };
904 }; 902 };
905 903
906 replicator@fc31c000 { 904 replicator@fc31c000 {
907 compatible = "arm,core 905 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
908 reg = <0xfc31c000 0x10 906 reg = <0xfc31c000 0x1000>;
909 907
910 clocks = <&rpmcc RPM_S 908 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
911 clock-names = "apb_pcl 909 clock-names = "apb_pclk", "atclk";
912 910
913 out-ports { 911 out-ports {
914 #address-cells 912 #address-cells = <1>;
915 #size-cells = 913 #size-cells = <0>;
916 914
917 port@0 { 915 port@0 {
918 reg = 916 reg = <0>;
919 replic 917 replicator_out0: endpoint {
920 918 remote-endpoint = <&etr_in>;
921 }; 919 };
922 }; 920 };
923 port@1 { 921 port@1 {
924 reg = 922 reg = <1>;
925 replic 923 replicator_out1: endpoint {
926 924 remote-endpoint = <&tpiu_in>;
927 }; 925 };
928 }; 926 };
929 }; 927 };
930 928
931 in-ports { 929 in-ports {
932 port { 930 port {
933 replic 931 replicator_in: endpoint {
934 932 remote-endpoint = <&etf_out>;
935 }; 933 };
936 }; 934 };
937 }; 935 };
938 }; 936 };
939 937
940 etr@fc322000 { 938 etr@fc322000 {
941 compatible = "arm,core 939 compatible = "arm,coresight-tmc", "arm,primecell";
942 reg = <0xfc322000 0x10 940 reg = <0xfc322000 0x1000>;
943 941
944 clocks = <&rpmcc RPM_S 942 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
945 clock-names = "apb_pcl 943 clock-names = "apb_pclk", "atclk";
946 944
947 in-ports { 945 in-ports {
948 port { 946 port {
949 etr_in 947 etr_in: endpoint {
950 948 remote-endpoint = <&replicator_out0>;
951 }; 949 };
952 }; 950 };
953 }; 951 };
954 }; 952 };
955 953
956 etm@fc33c000 { 954 etm@fc33c000 {
957 compatible = "arm,core 955 compatible = "arm,coresight-etm4x", "arm,primecell";
958 reg = <0xfc33c000 0x10 956 reg = <0xfc33c000 0x1000>;
959 957
960 clocks = <&rpmcc RPM_S 958 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
961 clock-names = "apb_pcl 959 clock-names = "apb_pclk", "atclk";
962 960
963 cpu = <&CPU0>; 961 cpu = <&CPU0>;
964 962
965 out-ports { 963 out-ports {
966 port { 964 port {
967 etm0_o 965 etm0_out: endpoint {
968 966 remote-endpoint = <&kpss_in0>;
969 }; 967 };
970 }; 968 };
971 }; 969 };
972 }; 970 };
973 971
974 etm@fc33d000 { 972 etm@fc33d000 {
975 compatible = "arm,core 973 compatible = "arm,coresight-etm4x", "arm,primecell";
976 reg = <0xfc33d000 0x10 974 reg = <0xfc33d000 0x1000>;
977 975
978 clocks = <&rpmcc RPM_S 976 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
979 clock-names = "apb_pcl 977 clock-names = "apb_pclk", "atclk";
980 978
981 cpu = <&CPU1>; 979 cpu = <&CPU1>;
982 980
983 out-ports { 981 out-ports {
984 port { 982 port {
985 etm1_o 983 etm1_out: endpoint {
986 984 remote-endpoint = <&kpss_in1>;
987 }; 985 };
988 }; 986 };
989 }; 987 };
990 }; 988 };
991 989
992 etm@fc33e000 { 990 etm@fc33e000 {
993 compatible = "arm,core 991 compatible = "arm,coresight-etm4x", "arm,primecell";
994 reg = <0xfc33e000 0x10 992 reg = <0xfc33e000 0x1000>;
995 993
996 clocks = <&rpmcc RPM_S 994 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
997 clock-names = "apb_pcl 995 clock-names = "apb_pclk", "atclk";
998 996
999 cpu = <&CPU2>; 997 cpu = <&CPU2>;
1000 998
1001 out-ports { 999 out-ports {
1002 port { 1000 port {
1003 etm2_ 1001 etm2_out: endpoint {
1004 1002 remote-endpoint = <&kpss_in2>;
1005 }; 1003 };
1006 }; 1004 };
1007 }; 1005 };
1008 }; 1006 };
1009 1007
1010 etm@fc33f000 { 1008 etm@fc33f000 {
1011 compatible = "arm,cor 1009 compatible = "arm,coresight-etm4x", "arm,primecell";
1012 reg = <0xfc33f000 0x1 1010 reg = <0xfc33f000 0x1000>;
1013 1011
1014 clocks = <&rpmcc RPM_ 1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1015 clock-names = "apb_pc 1013 clock-names = "apb_pclk", "atclk";
1016 1014
1017 cpu = <&CPU3>; 1015 cpu = <&CPU3>;
1018 1016
1019 out-ports { 1017 out-ports {
1020 port { 1018 port {
1021 etm3_ 1019 etm3_out: endpoint {
1022 1020 remote-endpoint = <&kpss_in3>;
1023 }; 1021 };
1024 }; 1022 };
1025 }; 1023 };
1026 }; 1024 };
1027 1025
1028 /* KPSS funnel, only 4 inputs 1026 /* KPSS funnel, only 4 inputs are used */
1029 funnel@fc345000 { 1027 funnel@fc345000 {
1030 compatible = "arm,cor 1028 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1031 reg = <0xfc345000 0x1 1029 reg = <0xfc345000 0x1000>;
1032 1030
1033 clocks = <&rpmcc RPM_ 1031 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1034 clock-names = "apb_pc 1032 clock-names = "apb_pclk", "atclk";
1035 1033
1036 in-ports { 1034 in-ports {
1037 #address-cell 1035 #address-cells = <1>;
1038 #size-cells = 1036 #size-cells = <0>;
1039 1037
1040 port@0 { 1038 port@0 {
1041 reg = 1039 reg = <0>;
1042 kpss_ 1040 kpss_in0: endpoint {
1043 1041 remote-endpoint = <&etm0_out>;
1044 }; 1042 };
1045 }; 1043 };
1046 port@1 { 1044 port@1 {
1047 reg = 1045 reg = <1>;
1048 kpss_ 1046 kpss_in1: endpoint {
1049 1047 remote-endpoint = <&etm1_out>;
1050 }; 1048 };
1051 }; 1049 };
1052 port@2 { 1050 port@2 {
1053 reg = 1051 reg = <2>;
1054 kpss_ 1052 kpss_in2: endpoint {
1055 1053 remote-endpoint = <&etm2_out>;
1056 }; 1054 };
1057 }; 1055 };
1058 port@3 { 1056 port@3 {
1059 reg = 1057 reg = <3>;
1060 kpss_ 1058 kpss_in3: endpoint {
1061 1059 remote-endpoint = <&etm3_out>;
1062 }; 1060 };
1063 }; 1061 };
1064 }; 1062 };
1065 1063
1066 out-ports { 1064 out-ports {
1067 port { 1065 port {
1068 kpss_ 1066 kpss_out: endpoint {
1069 1067 remote-endpoint = <&funnel1_in5>;
1070 }; 1068 };
1071 }; 1069 };
1072 }; 1070 };
1073 }; 1071 };
1074 1072
1075 bimc: interconnect@fc380000 { 1073 bimc: interconnect@fc380000 {
1076 reg = <0xfc380000 0x6 1074 reg = <0xfc380000 0x6a000>;
1077 compatible = "qcom,ms 1075 compatible = "qcom,msm8974-bimc";
1078 #interconnect-cells = 1076 #interconnect-cells = <1>;
1079 clock-names = "bus", 1077 clock-names = "bus", "bus_a";
1080 clocks = <&rpmcc RPM_ 1078 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1081 <&rpmcc RPM_ 1079 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1082 }; 1080 };
1083 1081
1084 gcc: clock-controller@fc40000 1082 gcc: clock-controller@fc400000 {
1085 compatible = "qcom,gc 1083 compatible = "qcom,gcc-msm8974";
1086 #clock-cells = <1>; 1084 #clock-cells = <1>;
1087 #reset-cells = <1>; 1085 #reset-cells = <1>;
1088 #power-domain-cells = 1086 #power-domain-cells = <1>;
1089 reg = <0xfc400000 0x4 1087 reg = <0xfc400000 0x4000>;
1090 1088
1091 clocks = <&rpmcc RPM_ 1089 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1092 <&sleep_clk> 1090 <&sleep_clk>;
1093 clock-names = "xo", 1091 clock-names = "xo",
1094 "sleep_ 1092 "sleep_clk";
1095 }; 1093 };
1096 1094
1097 rpm_msg_ram: sram@fc428000 { 1095 rpm_msg_ram: sram@fc428000 {
1098 compatible = "qcom,rp 1096 compatible = "qcom,rpm-msg-ram";
1099 reg = <0xfc428000 0x4 1097 reg = <0xfc428000 0x4000>;
1100 1098
1101 #address-cells = <1>; 1099 #address-cells = <1>;
1102 #size-cells = <1>; 1100 #size-cells = <1>;
1103 ranges = <0 0xfc42800 1101 ranges = <0 0xfc428000 0x4000>;
1104 1102
1105 apss_master_stats: sr 1103 apss_master_stats: sram@150 {
1106 reg = <0x150 1104 reg = <0x150 0x14>;
1107 }; 1105 };
1108 1106
1109 mpss_master_stats: sr 1107 mpss_master_stats: sram@b50 {
1110 reg = <0xb50 1108 reg = <0xb50 0x14>;
1111 }; 1109 };
1112 1110
1113 lpss_master_stats: sr 1111 lpss_master_stats: sram@1550 {
1114 reg = <0x1550 1112 reg = <0x1550 0x14>;
1115 }; 1113 };
1116 1114
1117 pronto_master_stats: 1115 pronto_master_stats: sram@1f50 {
1118 reg = <0x1f50 1116 reg = <0x1f50 0x14>;
1119 }; 1117 };
1120 }; 1118 };
1121 1119
1122 snoc: interconnect@fc460000 { 1120 snoc: interconnect@fc460000 {
1123 reg = <0xfc460000 0x4 1121 reg = <0xfc460000 0x4000>;
1124 compatible = "qcom,ms 1122 compatible = "qcom,msm8974-snoc";
1125 #interconnect-cells = 1123 #interconnect-cells = <1>;
1126 clock-names = "bus", 1124 clock-names = "bus", "bus_a";
1127 clocks = <&rpmcc RPM_ 1125 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1128 <&rpmcc RPM_ 1126 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1129 }; 1127 };
1130 1128
1131 pnoc: interconnect@fc468000 { 1129 pnoc: interconnect@fc468000 {
1132 reg = <0xfc468000 0x4 1130 reg = <0xfc468000 0x4000>;
1133 compatible = "qcom,ms 1131 compatible = "qcom,msm8974-pnoc";
1134 #interconnect-cells = 1132 #interconnect-cells = <1>;
1135 clock-names = "bus", 1133 clock-names = "bus", "bus_a";
1136 clocks = <&rpmcc RPM_ 1134 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1137 <&rpmcc RPM_ 1135 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1138 }; 1136 };
1139 1137
1140 ocmemnoc: interconnect@fc4700 1138 ocmemnoc: interconnect@fc470000 {
1141 reg = <0xfc470000 0x4 1139 reg = <0xfc470000 0x4000>;
1142 compatible = "qcom,ms 1140 compatible = "qcom,msm8974-ocmemnoc";
1143 #interconnect-cells = 1141 #interconnect-cells = <1>;
1144 clock-names = "bus", 1142 clock-names = "bus", "bus_a";
1145 clocks = <&rpmcc RPM_ 1143 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1146 <&rpmcc RPM_ 1144 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1147 }; 1145 };
1148 1146
1149 mmssnoc: interconnect@fc47800 1147 mmssnoc: interconnect@fc478000 {
1150 reg = <0xfc478000 0x4 1148 reg = <0xfc478000 0x4000>;
1151 compatible = "qcom,ms 1149 compatible = "qcom,msm8974-mmssnoc";
1152 #interconnect-cells = 1150 #interconnect-cells = <1>;
1153 clock-names = "bus", 1151 clock-names = "bus", "bus_a";
1154 clocks = <&mmcc MMSS_ 1152 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1155 <&mmcc MMSS_ 1153 <&mmcc MMSS_S0_AXI_CLK>;
1156 }; 1154 };
1157 1155
1158 cnoc: interconnect@fc480000 { 1156 cnoc: interconnect@fc480000 {
1159 reg = <0xfc480000 0x4 1157 reg = <0xfc480000 0x4000>;
1160 compatible = "qcom,ms 1158 compatible = "qcom,msm8974-cnoc";
1161 #interconnect-cells = 1159 #interconnect-cells = <1>;
1162 clock-names = "bus", 1160 clock-names = "bus", "bus_a";
1163 clocks = <&rpmcc RPM_ 1161 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1164 <&rpmcc RPM_ 1162 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1165 }; 1163 };
1166 1164
1167 tsens: thermal-sensor@fc4a900 1165 tsens: thermal-sensor@fc4a9000 {
1168 compatible = "qcom,ms 1166 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1169 reg = <0xfc4a9000 0x1 1167 reg = <0xfc4a9000 0x1000>, /* TM */
1170 <0xfc4a8000 0x1 1168 <0xfc4a8000 0x1000>; /* SROT */
1171 nvmem-cells = <&tsens 1169 nvmem-cells = <&tsens_mode>,
1172 <&tsens 1170 <&tsens_base1>, <&tsens_base2>,
1173 <&tsens 1171 <&tsens_use_backup>,
1174 <&tsens 1172 <&tsens_mode_backup>,
1175 <&tsens 1173 <&tsens_base1_backup>, <&tsens_base2_backup>,
1176 <&tsens 1174 <&tsens_s0_p1>, <&tsens_s0_p2>,
1177 <&tsens 1175 <&tsens_s1_p1>, <&tsens_s1_p2>,
1178 <&tsens 1176 <&tsens_s2_p1>, <&tsens_s2_p2>,
1179 <&tsens 1177 <&tsens_s3_p1>, <&tsens_s3_p2>,
1180 <&tsens 1178 <&tsens_s4_p1>, <&tsens_s4_p2>,
1181 <&tsens 1179 <&tsens_s5_p1>, <&tsens_s5_p2>,
1182 <&tsens 1180 <&tsens_s6_p1>, <&tsens_s6_p2>,
1183 <&tsens 1181 <&tsens_s7_p1>, <&tsens_s7_p2>,
1184 <&tsens 1182 <&tsens_s8_p1>, <&tsens_s8_p2>,
1185 <&tsens 1183 <&tsens_s9_p1>, <&tsens_s9_p2>,
1186 <&tsens 1184 <&tsens_s10_p1>, <&tsens_s10_p2>,
1187 <&tsens 1185 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1188 <&tsens 1186 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1189 <&tsens 1187 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1190 <&tsens 1188 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1191 <&tsens 1189 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1192 <&tsens 1190 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1193 <&tsens 1191 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1194 <&tsens 1192 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1195 <&tsens 1193 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1196 <&tsens 1194 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1197 <&tsens 1195 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1198 nvmem-cell-names = "m 1196 nvmem-cell-names = "mode",
1199 "b 1197 "base1", "base2",
1200 "u 1198 "use_backup",
1201 "m 1199 "mode_backup",
1202 "b 1200 "base1_backup", "base2_backup",
1203 "s 1201 "s0_p1", "s0_p2",
1204 "s 1202 "s1_p1", "s1_p2",
1205 "s 1203 "s2_p1", "s2_p2",
1206 "s 1204 "s3_p1", "s3_p2",
1207 "s 1205 "s4_p1", "s4_p2",
1208 "s 1206 "s5_p1", "s5_p2",
1209 "s 1207 "s6_p1", "s6_p2",
1210 "s 1208 "s7_p1", "s7_p2",
1211 "s 1209 "s8_p1", "s8_p2",
1212 "s 1210 "s9_p1", "s9_p2",
1213 "s 1211 "s10_p1", "s10_p2",
1214 "s 1212 "s0_p1_backup", "s0_p2_backup",
1215 "s 1213 "s1_p1_backup", "s1_p2_backup",
1216 "s 1214 "s2_p1_backup", "s2_p2_backup",
1217 "s 1215 "s3_p1_backup", "s3_p2_backup",
1218 "s 1216 "s4_p1_backup", "s4_p2_backup",
1219 "s 1217 "s5_p1_backup", "s5_p2_backup",
1220 "s 1218 "s6_p1_backup", "s6_p2_backup",
1221 "s 1219 "s7_p1_backup", "s7_p2_backup",
1222 "s 1220 "s8_p1_backup", "s8_p2_backup",
1223 "s 1221 "s9_p1_backup", "s9_p2_backup",
1224 "s 1222 "s10_p1_backup", "s10_p2_backup";
1225 #qcom,sensors = <11>; 1223 #qcom,sensors = <11>;
1226 interrupts = <GIC_SPI 1224 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "up 1225 interrupt-names = "uplow";
1228 #thermal-sensor-cells 1226 #thermal-sensor-cells = <1>;
1229 }; 1227 };
1230 1228
1231 restart@fc4ab000 { 1229 restart@fc4ab000 {
1232 compatible = "qcom,ps 1230 compatible = "qcom,pshold";
1233 reg = <0xfc4ab000 0x4 1231 reg = <0xfc4ab000 0x4>;
1234 }; 1232 };
1235 1233
1236 qfprom: efuse@fc4bc000 { !! 1234 qfprom: qfprom@fc4bc000 {
1237 compatible = "qcom,ms 1235 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1238 reg = <0xfc4bc000 0x2 1236 reg = <0xfc4bc000 0x2100>;
1239 #address-cells = <1>; 1237 #address-cells = <1>;
1240 #size-cells = <1>; 1238 #size-cells = <1>;
1241 1239
1242 tsens_base1: base1@d0 1240 tsens_base1: base1@d0 {
1243 reg = <0xd0 0 1241 reg = <0xd0 0x1>;
1244 bits = <0 8>; 1242 bits = <0 8>;
1245 }; 1243 };
1246 1244
1247 tsens_s0_p1: s0-p1@d1 1245 tsens_s0_p1: s0-p1@d1 {
1248 reg = <0xd1 0 1246 reg = <0xd1 0x1>;
1249 bits = <0 6>; 1247 bits = <0 6>;
1250 }; 1248 };
1251 1249
1252 tsens_s1_p1: s1-p1@d2 1250 tsens_s1_p1: s1-p1@d2 {
1253 reg = <0xd1 0 1251 reg = <0xd1 0x2>;
1254 bits = <6 6>; 1252 bits = <6 6>;
1255 }; 1253 };
1256 1254
1257 tsens_s2_p1: s2-p1@d2 1255 tsens_s2_p1: s2-p1@d2 {
1258 reg = <0xd2 0 1256 reg = <0xd2 0x2>;
1259 bits = <4 6>; 1257 bits = <4 6>;
1260 }; 1258 };
1261 1259
1262 tsens_s3_p1: s3-p1@d3 1260 tsens_s3_p1: s3-p1@d3 {
1263 reg = <0xd3 0 1261 reg = <0xd3 0x1>;
1264 bits = <2 6>; 1262 bits = <2 6>;
1265 }; 1263 };
1266 1264
1267 tsens_s4_p1: s4-p1@d4 1265 tsens_s4_p1: s4-p1@d4 {
1268 reg = <0xd4 0 1266 reg = <0xd4 0x1>;
1269 bits = <0 6>; 1267 bits = <0 6>;
1270 }; 1268 };
1271 1269
1272 tsens_s5_p1: s5-p1@d4 1270 tsens_s5_p1: s5-p1@d4 {
1273 reg = <0xd4 0 1271 reg = <0xd4 0x2>;
1274 bits = <6 6>; 1272 bits = <6 6>;
1275 }; 1273 };
1276 1274
1277 tsens_s6_p1: s6-p1@d5 1275 tsens_s6_p1: s6-p1@d5 {
1278 reg = <0xd5 0 1276 reg = <0xd5 0x2>;
1279 bits = <4 6>; 1277 bits = <4 6>;
1280 }; 1278 };
1281 1279
1282 tsens_s7_p1: s7-p1@d6 1280 tsens_s7_p1: s7-p1@d6 {
1283 reg = <0xd6 0 1281 reg = <0xd6 0x1>;
1284 bits = <2 6>; 1282 bits = <2 6>;
1285 }; 1283 };
1286 1284
1287 tsens_s8_p1: s8-p1@d7 1285 tsens_s8_p1: s8-p1@d7 {
1288 reg = <0xd7 0 1286 reg = <0xd7 0x1>;
1289 bits = <0 6>; 1287 bits = <0 6>;
1290 }; 1288 };
1291 1289
1292 tsens_mode: mode@d7 { 1290 tsens_mode: mode@d7 {
1293 reg = <0xd7 0 1291 reg = <0xd7 0x1>;
1294 bits = <6 2>; 1292 bits = <6 2>;
1295 }; 1293 };
1296 1294
1297 tsens_s9_p1: s9-p1@d8 1295 tsens_s9_p1: s9-p1@d8 {
1298 reg = <0xd8 0 1296 reg = <0xd8 0x1>;
1299 bits = <0 6>; 1297 bits = <0 6>;
1300 }; 1298 };
1301 1299
1302 tsens_s10_p1: s10_p1@ 1300 tsens_s10_p1: s10_p1@d8 {
1303 reg = <0xd8 0 1301 reg = <0xd8 0x2>;
1304 bits = <6 6>; 1302 bits = <6 6>;
1305 }; 1303 };
1306 1304
1307 tsens_base2: base2@d9 1305 tsens_base2: base2@d9 {
1308 reg = <0xd9 0 1306 reg = <0xd9 0x2>;
1309 bits = <4 8>; 1307 bits = <4 8>;
1310 }; 1308 };
1311 1309
1312 tsens_s0_p2: s0-p2@da 1310 tsens_s0_p2: s0-p2@da {
1313 reg = <0xda 0 1311 reg = <0xda 0x2>;
1314 bits = <4 6>; 1312 bits = <4 6>;
1315 }; 1313 };
1316 1314
1317 tsens_s1_p2: s1-p2@db 1315 tsens_s1_p2: s1-p2@db {
1318 reg = <0xdb 0 1316 reg = <0xdb 0x1>;
1319 bits = <2 6>; 1317 bits = <2 6>;
1320 }; 1318 };
1321 1319
1322 tsens_s2_p2: s2-p2@dc 1320 tsens_s2_p2: s2-p2@dc {
1323 reg = <0xdc 0 1321 reg = <0xdc 0x1>;
1324 bits = <0 6>; 1322 bits = <0 6>;
1325 }; 1323 };
1326 1324
1327 tsens_s3_p2: s3-p2@dc 1325 tsens_s3_p2: s3-p2@dc {
1328 reg = <0xdc 0 1326 reg = <0xdc 0x2>;
1329 bits = <6 6>; 1327 bits = <6 6>;
1330 }; 1328 };
1331 1329
1332 tsens_s4_p2: s4-p2@dd 1330 tsens_s4_p2: s4-p2@dd {
1333 reg = <0xdd 0 1331 reg = <0xdd 0x2>;
1334 bits = <4 6>; 1332 bits = <4 6>;
1335 }; 1333 };
1336 1334
1337 tsens_s5_p2: s5-p2@de 1335 tsens_s5_p2: s5-p2@de {
1338 reg = <0xde 0 1336 reg = <0xde 0x2>;
1339 bits = <2 6>; 1337 bits = <2 6>;
1340 }; 1338 };
1341 1339
1342 tsens_s6_p2: s6-p2@df 1340 tsens_s6_p2: s6-p2@df {
1343 reg = <0xdf 0 1341 reg = <0xdf 0x1>;
1344 bits = <0 6>; 1342 bits = <0 6>;
1345 }; 1343 };
1346 1344
1347 tsens_s7_p2: s7-p2@e0 1345 tsens_s7_p2: s7-p2@e0 {
1348 reg = <0xe0 0 1346 reg = <0xe0 0x1>;
1349 bits = <0 6>; 1347 bits = <0 6>;
1350 }; 1348 };
1351 1349
1352 tsens_s8_p2: s8-p2@e0 1350 tsens_s8_p2: s8-p2@e0 {
1353 reg = <0xe0 0 1351 reg = <0xe0 0x2>;
1354 bits = <6 6>; 1352 bits = <6 6>;
1355 }; 1353 };
1356 1354
1357 tsens_s9_p2: s9-p2@e1 1355 tsens_s9_p2: s9-p2@e1 {
1358 reg = <0xe1 0 1356 reg = <0xe1 0x2>;
1359 bits = <4 6>; 1357 bits = <4 6>;
1360 }; 1358 };
1361 1359
1362 tsens_s10_p2: s10_p2@ 1360 tsens_s10_p2: s10_p2@e2 {
1363 reg = <0xe2 0 1361 reg = <0xe2 0x2>;
1364 bits = <2 6>; 1362 bits = <2 6>;
1365 }; 1363 };
1366 1364
1367 tsens_s5_p2_backup: s 1365 tsens_s5_p2_backup: s5-p2_backup@e3 {
1368 reg = <0xe3 0 1366 reg = <0xe3 0x2>;
1369 bits = <0 6>; 1367 bits = <0 6>;
1370 }; 1368 };
1371 1369
1372 tsens_mode_backup: mo 1370 tsens_mode_backup: mode_backup@e3 {
1373 reg = <0xe3 0 1371 reg = <0xe3 0x1>;
1374 bits = <6 2>; 1372 bits = <6 2>;
1375 }; 1373 };
1376 1374
1377 tsens_s6_p2_backup: s 1375 tsens_s6_p2_backup: s6-p2_backup@e4 {
1378 reg = <0xe4 0 1376 reg = <0xe4 0x1>;
1379 bits = <0 6>; 1377 bits = <0 6>;
1380 }; 1378 };
1381 1379
1382 tsens_s7_p2_backup: s 1380 tsens_s7_p2_backup: s7-p2_backup@e4 {
1383 reg = <0xe4 0 1381 reg = <0xe4 0x2>;
1384 bits = <6 6>; 1382 bits = <6 6>;
1385 }; 1383 };
1386 1384
1387 tsens_s8_p2_backup: s 1385 tsens_s8_p2_backup: s8-p2_backup@e5 {
1388 reg = <0xe5 0 1386 reg = <0xe5 0x2>;
1389 bits = <4 6>; 1387 bits = <4 6>;
1390 }; 1388 };
1391 1389
1392 tsens_s9_p2_backup: s 1390 tsens_s9_p2_backup: s9-p2_backup@e6 {
1393 reg = <0xe6 0 1391 reg = <0xe6 0x2>;
1394 bits = <2 6>; 1392 bits = <2 6>;
1395 }; 1393 };
1396 1394
1397 tsens_s10_p2_backup: 1395 tsens_s10_p2_backup: s10_p2_backup@e7 {
1398 reg = <0xe7 0 1396 reg = <0xe7 0x1>;
1399 bits = <0 6>; 1397 bits = <0 6>;
1400 }; 1398 };
1401 1399
1402 tsens_base1_backup: b 1400 tsens_base1_backup: base1_backup@440 {
1403 reg = <0x440 1401 reg = <0x440 0x1>;
1404 bits = <0 8>; 1402 bits = <0 8>;
1405 }; 1403 };
1406 1404
1407 tsens_s0_p1_backup: s 1405 tsens_s0_p1_backup: s0-p1_backup@441 {
1408 reg = <0x441 1406 reg = <0x441 0x1>;
1409 bits = <0 6>; 1407 bits = <0 6>;
1410 }; 1408 };
1411 1409
1412 tsens_s1_p1_backup: s 1410 tsens_s1_p1_backup: s1-p1_backup@442 {
1413 reg = <0x441 1411 reg = <0x441 0x2>;
1414 bits = <6 6>; 1412 bits = <6 6>;
1415 }; 1413 };
1416 1414
1417 tsens_s2_p1_backup: s 1415 tsens_s2_p1_backup: s2-p1_backup@442 {
1418 reg = <0x442 1416 reg = <0x442 0x2>;
1419 bits = <4 6>; 1417 bits = <4 6>;
1420 }; 1418 };
1421 1419
1422 tsens_s3_p1_backup: s 1420 tsens_s3_p1_backup: s3-p1_backup@443 {
1423 reg = <0x443 1421 reg = <0x443 0x1>;
1424 bits = <2 6>; 1422 bits = <2 6>;
1425 }; 1423 };
1426 1424
1427 tsens_s4_p1_backup: s 1425 tsens_s4_p1_backup: s4-p1_backup@444 {
1428 reg = <0x444 1426 reg = <0x444 0x1>;
1429 bits = <0 6>; 1427 bits = <0 6>;
1430 }; 1428 };
1431 1429
1432 tsens_s5_p1_backup: s 1430 tsens_s5_p1_backup: s5-p1_backup@444 {
1433 reg = <0x444 1431 reg = <0x444 0x2>;
1434 bits = <6 6>; 1432 bits = <6 6>;
1435 }; 1433 };
1436 1434
1437 tsens_s6_p1_backup: s 1435 tsens_s6_p1_backup: s6-p1_backup@445 {
1438 reg = <0x445 1436 reg = <0x445 0x2>;
1439 bits = <4 6>; 1437 bits = <4 6>;
1440 }; 1438 };
1441 1439
1442 tsens_s7_p1_backup: s 1440 tsens_s7_p1_backup: s7-p1_backup@446 {
1443 reg = <0x446 1441 reg = <0x446 0x1>;
1444 bits = <2 6>; 1442 bits = <2 6>;
1445 }; 1443 };
1446 1444
1447 tsens_use_backup: use 1445 tsens_use_backup: use_backup@447 {
1448 reg = <0x447 1446 reg = <0x447 0x1>;
1449 bits = <5 3>; 1447 bits = <5 3>;
1450 }; 1448 };
1451 1449
1452 tsens_s8_p1_backup: s 1450 tsens_s8_p1_backup: s8-p1_backup@448 {
1453 reg = <0x448 1451 reg = <0x448 0x1>;
1454 bits = <0 6>; 1452 bits = <0 6>;
1455 }; 1453 };
1456 1454
1457 tsens_s9_p1_backup: s 1455 tsens_s9_p1_backup: s9-p1_backup@448 {
1458 reg = <0x448 1456 reg = <0x448 0x2>;
1459 bits = <6 6>; 1457 bits = <6 6>;
1460 }; 1458 };
1461 1459
1462 tsens_s10_p1_backup: 1460 tsens_s10_p1_backup: s10_p1_backup@449 {
1463 reg = <0x449 1461 reg = <0x449 0x2>;
1464 bits = <4 6>; 1462 bits = <4 6>;
1465 }; 1463 };
1466 1464
1467 tsens_base2_backup: b 1465 tsens_base2_backup: base2_backup@44a {
1468 reg = <0x44a 1466 reg = <0x44a 0x2>;
1469 bits = <2 8>; 1467 bits = <2 8>;
1470 }; 1468 };
1471 1469
1472 tsens_s0_p2_backup: s 1470 tsens_s0_p2_backup: s0-p2_backup@44b {
1473 reg = <0x44b 1471 reg = <0x44b 0x3>;
1474 bits = <2 6>; 1472 bits = <2 6>;
1475 }; 1473 };
1476 1474
1477 tsens_s1_p2_backup: s 1475 tsens_s1_p2_backup: s1-p2_backup@44c {
1478 reg = <0x44c 1476 reg = <0x44c 0x1>;
1479 bits = <0 6>; 1477 bits = <0 6>;
1480 }; 1478 };
1481 1479
1482 tsens_s2_p2_backup: s 1480 tsens_s2_p2_backup: s2-p2_backup@44c {
1483 reg = <0x44c 1481 reg = <0x44c 0x2>;
1484 bits = <6 6>; 1482 bits = <6 6>;
1485 }; 1483 };
1486 1484
1487 tsens_s3_p2_backup: s 1485 tsens_s3_p2_backup: s3-p2_backup@44d {
1488 reg = <0x44d 1486 reg = <0x44d 0x2>;
1489 bits = <4 6>; 1487 bits = <4 6>;
1490 }; 1488 };
1491 1489
1492 tsens_s4_p2_backup: s 1490 tsens_s4_p2_backup: s4-p2_backup@44e {
1493 reg = <0x44e 1491 reg = <0x44e 0x1>;
1494 bits = <2 6>; 1492 bits = <2 6>;
1495 }; 1493 };
1496 }; 1494 };
1497 1495
1498 spmi_bus: spmi@fc4cf000 { 1496 spmi_bus: spmi@fc4cf000 {
1499 compatible = "qcom,sp 1497 compatible = "qcom,spmi-pmic-arb";
1500 reg-names = "core", " 1498 reg-names = "core", "intr", "cnfg";
1501 reg = <0xfc4cf000 0x1 1499 reg = <0xfc4cf000 0x1000>,
1502 <0xfc4cb000 0x1 1500 <0xfc4cb000 0x1000>,
1503 <0xfc4ca000 0x1 1501 <0xfc4ca000 0x1000>;
1504 interrupt-names = "pe 1502 interrupt-names = "periph_irq";
1505 interrupts = <GIC_SPI 1503 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1506 qcom,ee = <0>; 1504 qcom,ee = <0>;
1507 qcom,channel = <0>; 1505 qcom,channel = <0>;
1508 #address-cells = <2>; 1506 #address-cells = <2>;
1509 #size-cells = <0>; 1507 #size-cells = <0>;
1510 interrupt-controller; 1508 interrupt-controller;
1511 #interrupt-cells = <4 1509 #interrupt-cells = <4>;
1512 }; 1510 };
1513 1511
1514 bam_dmux_dma: dma-controller@ 1512 bam_dmux_dma: dma-controller@fc834000 {
1515 compatible = "qcom,ba 1513 compatible = "qcom,bam-v1.4.0";
1516 reg = <0xfc834000 0x7 1514 reg = <0xfc834000 0x7000>;
1517 interrupts = <GIC_SPI 1515 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1518 #dma-cells = <1>; 1516 #dma-cells = <1>;
1519 qcom,ee = <0>; 1517 qcom,ee = <0>;
1520 1518
1521 num-channels = <6>; 1519 num-channels = <6>;
1522 qcom,num-ees = <1>; 1520 qcom,num-ees = <1>;
1523 qcom,powered-remotely 1521 qcom,powered-remotely;
1524 }; 1522 };
1525 1523
1526 remoteproc_mss: remoteproc@fc 1524 remoteproc_mss: remoteproc@fc880000 {
1527 compatible = "qcom,ms 1525 compatible = "qcom,msm8974-mss-pil";
1528 reg = <0xfc880000 0x1 1526 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1529 reg-names = "qdsp6", 1527 reg-names = "qdsp6", "rmb";
1530 1528
1531 interrupts-extended = 1529 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1532 1530 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1533 1531 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1534 1532 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1535 1533 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1536 interrupt-names = "wd 1534 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1537 1535
1538 clocks = <&gcc GCC_MS 1536 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1539 <&gcc GCC_MS 1537 <&gcc GCC_MSS_CFG_AHB_CLK>,
1540 <&gcc GCC_BO 1538 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1541 <&xo_board>; 1539 <&xo_board>;
1542 clock-names = "iface" 1540 clock-names = "iface", "bus", "mem", "xo";
1543 1541
1544 resets = <&gcc GCC_MS 1542 resets = <&gcc GCC_MSS_RESTART>;
1545 reset-names = "mss_re 1543 reset-names = "mss_restart";
1546 1544
1547 qcom,halt-regs = <&tc 1545 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1548 1546
1549 qcom,smem-states = <& 1547 qcom,smem-states = <&modem_smp2p_out 0>;
1550 qcom,smem-state-names 1548 qcom,smem-state-names = "stop";
1551 1549
1552 status = "disabled"; 1550 status = "disabled";
1553 1551
1554 mba { 1552 mba {
1555 memory-region 1553 memory-region = <&mba_region>;
1556 }; 1554 };
1557 1555
1558 mpss { 1556 mpss {
1559 memory-region 1557 memory-region = <&mpss_region>;
1560 }; 1558 };
1561 1559
1562 bam_dmux: bam-dmux { 1560 bam_dmux: bam-dmux {
1563 compatible = 1561 compatible = "qcom,bam-dmux";
1564 1562
1565 interrupt-par 1563 interrupt-parent = <&modem_smsm>;
1566 interrupts = 1564 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1567 interrupt-nam 1565 interrupt-names = "pc", "pc-ack";
1568 1566
1569 qcom,smem-sta 1567 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1570 qcom,smem-sta 1568 qcom,smem-state-names = "pc", "pc-ack";
1571 1569
1572 dmas = <&bam_ 1570 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1573 dma-names = " 1571 dma-names = "tx", "rx";
1574 }; 1572 };
1575 1573
1576 smd-edge { 1574 smd-edge {
1577 interrupts = 1575 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1578 1576
1579 mboxes = <&ap !! 1577 qcom,ipc = <&apcs 8 12>;
1580 qcom,smd-edge 1578 qcom,smd-edge = <0>;
1581 1579
1582 label = "mode 1580 label = "modem";
1583 }; 1581 };
1584 }; 1582 };
1585 1583
1586 tcsr_mutex: hwlock@fd484000 { 1584 tcsr_mutex: hwlock@fd484000 {
1587 compatible = "qcom,ms 1585 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1588 reg = <0xfd484000 0x2 1586 reg = <0xfd484000 0x2000>;
1589 #hwlock-cells = <1>; 1587 #hwlock-cells = <1>;
1590 }; 1588 };
1591 1589
1592 tcsr: syscon@fd4a0000 { 1590 tcsr: syscon@fd4a0000 {
1593 compatible = "qcom,tc 1591 compatible = "qcom,tcsr-msm8974", "syscon";
1594 reg = <0xfd4a0000 0x1 1592 reg = <0xfd4a0000 0x10000>;
1595 }; 1593 };
1596 1594
1597 tlmm: pinctrl@fd510000 { 1595 tlmm: pinctrl@fd510000 {
1598 compatible = "qcom,ms 1596 compatible = "qcom,msm8974-pinctrl";
1599 reg = <0xfd510000 0x4 1597 reg = <0xfd510000 0x4000>;
1600 gpio-controller; 1598 gpio-controller;
1601 gpio-ranges = <&tlmm 1599 gpio-ranges = <&tlmm 0 0 146>;
1602 #gpio-cells = <2>; 1600 #gpio-cells = <2>;
1603 interrupt-controller; 1601 interrupt-controller;
1604 #interrupt-cells = <2 1602 #interrupt-cells = <2>;
1605 interrupts = <GIC_SPI 1603 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1606 1604
1607 sdc1_off: sdc1-off-st 1605 sdc1_off: sdc1-off-state {
1608 clk-pins { 1606 clk-pins {
1609 pins 1607 pins = "sdc1_clk";
1610 bias- 1608 bias-disable;
1611 drive 1609 drive-strength = <2>;
1612 }; 1610 };
1613 1611
1614 cmd-pins { 1612 cmd-pins {
1615 pins 1613 pins = "sdc1_cmd";
1616 bias- 1614 bias-pull-up;
1617 drive 1615 drive-strength = <2>;
1618 }; 1616 };
1619 1617
1620 data-pins { 1618 data-pins {
1621 pins 1619 pins = "sdc1_data";
1622 bias- 1620 bias-pull-up;
1623 drive 1621 drive-strength = <2>;
1624 }; 1622 };
1625 }; 1623 };
1626 1624
1627 sdc2_off: sdc2-off-st 1625 sdc2_off: sdc2-off-state {
1628 clk-pins { 1626 clk-pins {
1629 pins 1627 pins = "sdc2_clk";
1630 bias- 1628 bias-disable;
1631 drive 1629 drive-strength = <2>;
1632 }; 1630 };
1633 1631
1634 cmd-pins { 1632 cmd-pins {
1635 pins 1633 pins = "sdc2_cmd";
1636 bias- 1634 bias-pull-up;
1637 drive 1635 drive-strength = <2>;
1638 }; 1636 };
1639 1637
1640 data-pins { 1638 data-pins {
1641 pins 1639 pins = "sdc2_data";
1642 bias- 1640 bias-pull-up;
1643 drive 1641 drive-strength = <2>;
1644 }; 1642 };
1645 }; 1643 };
1646 1644
1647 blsp1_uart2_default: 1645 blsp1_uart2_default: blsp1-uart2-default-state {
1648 rx-pins { 1646 rx-pins {
1649 pins 1647 pins = "gpio5";
1650 funct 1648 function = "blsp_uart2";
1651 drive 1649 drive-strength = <2>;
1652 bias- 1650 bias-pull-up;
1653 }; 1651 };
1654 1652
1655 tx-pins { 1653 tx-pins {
1656 pins 1654 pins = "gpio4";
1657 funct 1655 function = "blsp_uart2";
1658 drive 1656 drive-strength = <4>;
1659 bias- 1657 bias-disable;
1660 }; 1658 };
1661 }; 1659 };
1662 1660
1663 blsp2_uart1_default: 1661 blsp2_uart1_default: blsp2-uart1-default-state {
1664 tx-rts-pins { 1662 tx-rts-pins {
1665 pins 1663 pins = "gpio41", "gpio44";
1666 funct 1664 function = "blsp_uart7";
1667 drive 1665 drive-strength = <2>;
1668 bias- 1666 bias-disable;
1669 }; 1667 };
1670 1668
1671 rx-cts-pins { 1669 rx-cts-pins {
1672 pins 1670 pins = "gpio42", "gpio43";
1673 funct 1671 function = "blsp_uart7";
1674 drive 1672 drive-strength = <2>;
1675 bias- 1673 bias-pull-up;
1676 }; 1674 };
1677 }; 1675 };
1678 1676
1679 blsp2_uart1_sleep: bl 1677 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1680 pins = "gpio4 1678 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1681 function = "g 1679 function = "gpio";
1682 drive-strengt 1680 drive-strength = <2>;
1683 bias-pull-dow 1681 bias-pull-down;
1684 }; 1682 };
1685 1683
1686 blsp2_uart4_default: 1684 blsp2_uart4_default: blsp2-uart4-default-state {
1687 tx-rts-pins { 1685 tx-rts-pins {
1688 pins 1686 pins = "gpio53", "gpio56";
1689 funct 1687 function = "blsp_uart10";
1690 drive 1688 drive-strength = <2>;
1691 bias- 1689 bias-disable;
1692 }; 1690 };
1693 1691
1694 rx-cts-pins { 1692 rx-cts-pins {
1695 pins 1693 pins = "gpio54", "gpio55";
1696 funct 1694 function = "blsp_uart10";
1697 drive 1695 drive-strength = <2>;
1698 bias- 1696 bias-pull-up;
1699 }; 1697 };
1700 }; 1698 };
1701 1699
1702 blsp1_i2c1_default: b 1700 blsp1_i2c1_default: blsp1-i2c1-default-state {
1703 pins = "gpio2 1701 pins = "gpio2", "gpio3";
1704 function = "b 1702 function = "blsp_i2c1";
1705 drive-strengt 1703 drive-strength = <2>;
1706 bias-disable; 1704 bias-disable;
1707 }; 1705 };
1708 1706
1709 blsp1_i2c1_sleep: bls 1707 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1710 pins = "gpio2 1708 pins = "gpio2", "gpio3";
1711 function = "b 1709 function = "blsp_i2c1";
1712 drive-strengt 1710 drive-strength = <2>;
1713 bias-pull-up; 1711 bias-pull-up;
1714 }; 1712 };
1715 1713
1716 blsp1_i2c2_default: b 1714 blsp1_i2c2_default: blsp1-i2c2-default-state {
1717 pins = "gpio6 1715 pins = "gpio6", "gpio7";
1718 function = "b 1716 function = "blsp_i2c2";
1719 drive-strengt 1717 drive-strength = <2>;
1720 bias-disable; 1718 bias-disable;
1721 }; 1719 };
1722 1720
1723 blsp1_i2c2_sleep: bls 1721 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1724 pins = "gpio6 1722 pins = "gpio6", "gpio7";
1725 function = "b 1723 function = "blsp_i2c2";
1726 drive-strengt 1724 drive-strength = <2>;
1727 bias-pull-up; 1725 bias-pull-up;
1728 }; 1726 };
1729 1727
1730 blsp1_i2c3_default: b 1728 blsp1_i2c3_default: blsp1-i2c3-default-state {
1731 pins = "gpio1 1729 pins = "gpio10", "gpio11";
1732 function = "b 1730 function = "blsp_i2c3";
1733 drive-strengt 1731 drive-strength = <2>;
1734 bias-disable; 1732 bias-disable;
1735 }; 1733 };
1736 1734
1737 blsp1_i2c3_sleep: bls 1735 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1738 pins = "gpio1 1736 pins = "gpio10", "gpio11";
1739 function = "b 1737 function = "blsp_i2c3";
1740 drive-strengt 1738 drive-strength = <2>;
1741 bias-pull-up; 1739 bias-pull-up;
1742 }; 1740 };
1743 1741
1744 /* BLSP1_I2C4 info is 1742 /* BLSP1_I2C4 info is missing */
1745 1743
1746 /* BLSP1_I2C5 info is 1744 /* BLSP1_I2C5 info is missing */
1747 1745
1748 blsp1_i2c6_default: b 1746 blsp1_i2c6_default: blsp1-i2c6-default-state {
1749 pins = "gpio2 1747 pins = "gpio29", "gpio30";
1750 function = "b 1748 function = "blsp_i2c6";
1751 drive-strengt 1749 drive-strength = <2>;
1752 bias-disable; 1750 bias-disable;
1753 }; 1751 };
1754 1752
1755 blsp1_i2c6_sleep: bls 1753 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1756 pins = "gpio2 1754 pins = "gpio29", "gpio30";
1757 function = "b 1755 function = "blsp_i2c6";
1758 drive-strengt 1756 drive-strength = <2>;
1759 bias-pull-up; 1757 bias-pull-up;
1760 }; 1758 };
1761 /* 6 interfaces per Q 1759 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1762 1760
1763 /* BLSP2_I2C1 info is 1761 /* BLSP2_I2C1 info is missing */
1764 1762
1765 blsp2_i2c2_default: b 1763 blsp2_i2c2_default: blsp2-i2c2-default-state {
1766 pins = "gpio4 1764 pins = "gpio47", "gpio48";
1767 function = "b 1765 function = "blsp_i2c8";
1768 drive-strengt 1766 drive-strength = <2>;
1769 bias-disable; 1767 bias-disable;
1770 }; 1768 };
1771 1769
1772 blsp2_i2c2_sleep: bls 1770 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1773 pins = "gpio4 1771 pins = "gpio47", "gpio48";
1774 function = "b 1772 function = "blsp_i2c8";
1775 drive-strengt 1773 drive-strength = <2>;
1776 bias-pull-up; 1774 bias-pull-up;
1777 }; 1775 };
1778 1776
1779 /* BLSP2_I2C3 info is 1777 /* BLSP2_I2C3 info is missing */
1780 1778
1781 /* BLSP2_I2C4 info is 1779 /* BLSP2_I2C4 info is missing */
1782 1780
1783 blsp2_i2c5_default: b 1781 blsp2_i2c5_default: blsp2-i2c5-default-state {
1784 pins = "gpio8 1782 pins = "gpio83", "gpio84";
1785 function = "b 1783 function = "blsp_i2c11";
1786 drive-strengt 1784 drive-strength = <2>;
1787 bias-disable; 1785 bias-disable;
1788 }; 1786 };
1789 1787
1790 blsp2_i2c5_sleep: bls 1788 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1791 pins = "gpio8 1789 pins = "gpio83", "gpio84";
1792 function = "b 1790 function = "blsp_i2c11";
1793 drive-strengt 1791 drive-strength = <2>;
1794 bias-pull-up; 1792 bias-pull-up;
1795 }; 1793 };
1796 1794
1797 blsp2_i2c6_default: b 1795 blsp2_i2c6_default: blsp2-i2c6-default-state {
1798 pins = "gpio8 1796 pins = "gpio87", "gpio88";
1799 function = "b 1797 function = "blsp_i2c12";
1800 drive-strengt 1798 drive-strength = <2>;
1801 bias-disable; 1799 bias-disable;
1802 }; 1800 };
1803 1801
1804 blsp2_i2c6_sleep: bls 1802 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1805 pins = "gpio8 1803 pins = "gpio87", "gpio88";
1806 function = "b 1804 function = "blsp_i2c12";
1807 drive-strengt 1805 drive-strength = <2>;
1808 bias-pull-up; 1806 bias-pull-up;
1809 }; 1807 };
1810 1808
1811 cci_default: cci-defa 1809 cci_default: cci-default-state {
1812 cci_i2c0_defa 1810 cci_i2c0_default: cci-i2c0-default-pins {
1813 pins 1811 pins = "gpio19", "gpio20";
1814 funct 1812 function = "cci_i2c0";
1815 drive 1813 drive-strength = <2>;
1816 bias- 1814 bias-disable;
1817 }; 1815 };
1818 1816
1819 cci_i2c1_defa 1817 cci_i2c1_default: cci-i2c1-default-pins {
1820 pins 1818 pins = "gpio21", "gpio22";
1821 funct 1819 function = "cci_i2c1";
1822 drive 1820 drive-strength = <2>;
1823 bias- 1821 bias-disable;
1824 }; 1822 };
1825 }; 1823 };
1826 1824
1827 cci_sleep: cci-sleep- 1825 cci_sleep: cci-sleep-state {
1828 cci_i2c0_slee 1826 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1829 pins 1827 pins = "gpio19", "gpio20";
1830 funct 1828 function = "gpio";
1831 drive 1829 drive-strength = <2>;
1832 bias- 1830 bias-disable;
1833 }; 1831 };
1834 1832
1835 cci_i2c1_slee 1833 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1836 pins 1834 pins = "gpio21", "gpio22";
1837 funct 1835 function = "gpio";
1838 drive 1836 drive-strength = <2>;
1839 bias- 1837 bias-disable;
1840 }; 1838 };
1841 }; 1839 };
1842 1840
1843 spi8_default: spi8_de 1841 spi8_default: spi8_default-state {
1844 mosi-pins { 1842 mosi-pins {
1845 pins 1843 pins = "gpio45";
1846 funct 1844 function = "blsp_spi8";
1847 }; 1845 };
1848 miso-pins { 1846 miso-pins {
1849 pins 1847 pins = "gpio46";
1850 funct 1848 function = "blsp_spi8";
1851 }; 1849 };
1852 cs-pins { 1850 cs-pins {
1853 pins 1851 pins = "gpio47";
1854 funct 1852 function = "blsp_spi8";
1855 }; 1853 };
1856 clk-pins { 1854 clk-pins {
1857 pins 1855 pins = "gpio48";
1858 funct 1856 function = "blsp_spi8";
1859 }; 1857 };
1860 }; 1858 };
1861 }; 1859 };
1862 1860
1863 mmcc: clock-controller@fd8c00 1861 mmcc: clock-controller@fd8c0000 {
1864 compatible = "qcom,mm 1862 compatible = "qcom,mmcc-msm8974";
1865 #clock-cells = <1>; 1863 #clock-cells = <1>;
1866 #reset-cells = <1>; 1864 #reset-cells = <1>;
1867 #power-domain-cells = 1865 #power-domain-cells = <1>;
1868 reg = <0xfd8c0000 0x6 1866 reg = <0xfd8c0000 0x6000>;
1869 clocks = <&xo_board>, 1867 clocks = <&xo_board>,
1870 <&gcc GCC_MM 1868 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1871 <&gcc GPLL0_ 1869 <&gcc GPLL0_VOTE>,
1872 <&gcc GPLL1_ 1870 <&gcc GPLL1_VOTE>,
1873 <&rpmcc RPM_ 1871 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1874 <&mdss_dsi0_ 1872 <&mdss_dsi0_phy 1>,
1875 <&mdss_dsi0_ 1873 <&mdss_dsi0_phy 0>,
1876 <&mdss_dsi1_ 1874 <&mdss_dsi1_phy 1>,
1877 <&mdss_dsi1_ 1875 <&mdss_dsi1_phy 0>,
1878 <0>, 1876 <0>,
1879 <0>, 1877 <0>,
1880 <0>; 1878 <0>;
1881 clock-names = "xo", 1879 clock-names = "xo",
1882 "mmss_g 1880 "mmss_gpll0_vote",
1883 "gpll0_ 1881 "gpll0_vote",
1884 "gpll1_ 1882 "gpll1_vote",
1885 "gfx3d_ 1883 "gfx3d_clk_src",
1886 "dsi0pl 1884 "dsi0pll",
1887 "dsi0pl 1885 "dsi0pllbyte",
1888 "dsi1pl 1886 "dsi1pll",
1889 "dsi1pl 1887 "dsi1pllbyte",
1890 "hdmipl 1888 "hdmipll",
1891 "edp_li 1889 "edp_link_clk",
1892 "edp_vc 1890 "edp_vco_div";
1893 }; 1891 };
1894 1892
1895 mdss: display-subsystem@fd900 1893 mdss: display-subsystem@fd900000 {
1896 compatible = "qcom,md 1894 compatible = "qcom,mdss";
1897 reg = <0xfd900000 0x1 1895 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1898 reg-names = "mdss_phy 1896 reg-names = "mdss_phys", "vbif_phys";
1899 1897
1900 power-domains = <&mmc 1898 power-domains = <&mmcc MDSS_GDSC>;
1901 1899
1902 clocks = <&mmcc MDSS_ 1900 clocks = <&mmcc MDSS_AHB_CLK>,
1903 <&mmcc MDSS_ 1901 <&mmcc MDSS_AXI_CLK>,
1904 <&mmcc MDSS_ 1902 <&mmcc MDSS_VSYNC_CLK>;
1905 clock-names = "iface" 1903 clock-names = "iface", "bus", "vsync";
1906 1904
1907 interrupts = <GIC_SPI 1905 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1908 1906
1909 interrupt-controller; 1907 interrupt-controller;
1910 #interrupt-cells = <1 1908 #interrupt-cells = <1>;
1911 1909
1912 status = "disabled"; 1910 status = "disabled";
1913 1911
1914 #address-cells = <1>; 1912 #address-cells = <1>;
1915 #size-cells = <1>; 1913 #size-cells = <1>;
1916 ranges; 1914 ranges;
1917 1915
1918 mdp: display-controll 1916 mdp: display-controller@fd900000 {
1919 compatible = 1917 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1920 reg = <0xfd90 1918 reg = <0xfd900100 0x22000>;
1921 reg-names = " 1919 reg-names = "mdp_phys";
1922 1920
1923 interrupt-par 1921 interrupt-parent = <&mdss>;
1924 interrupts = 1922 interrupts = <0>;
1925 1923
1926 clocks = <&mm 1924 clocks = <&mmcc MDSS_AHB_CLK>,
1927 <&mm 1925 <&mmcc MDSS_AXI_CLK>,
1928 <&mm 1926 <&mmcc MDSS_MDP_CLK>,
1929 <&mm 1927 <&mmcc MDSS_VSYNC_CLK>;
1930 clock-names = 1928 clock-names = "iface", "bus", "core", "vsync";
1931 1929
1932 interconnects 1930 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1933 interconnect- 1931 interconnect-names = "mdp0-mem";
1934 1932
1935 ports { 1933 ports {
1936 #addr 1934 #address-cells = <1>;
1937 #size 1935 #size-cells = <0>;
1938 1936
1939 port@ 1937 port@0 {
1940 1938 reg = <0>;
1941 1939 mdp5_intf1_out: endpoint {
1942 1940 remote-endpoint = <&mdss_dsi0_in>;
1943 1941 };
1944 }; 1942 };
1945 1943
1946 port@ 1944 port@1 {
1947 1945 reg = <1>;
1948 1946 mdp5_intf2_out: endpoint {
1949 1947 remote-endpoint = <&mdss_dsi1_in>;
1950 1948 };
1951 }; 1949 };
1952 }; 1950 };
1953 }; 1951 };
1954 1952
1955 mdss_dsi0: dsi@fd9228 1953 mdss_dsi0: dsi@fd922800 {
1956 compatible = 1954 compatible = "qcom,msm8974-dsi-ctrl",
1957 1955 "qcom,mdss-dsi-ctrl";
1958 reg = <0xfd92 1956 reg = <0xfd922800 0x1f8>;
1959 reg-names = " 1957 reg-names = "dsi_ctrl";
1960 1958
1961 interrupt-par 1959 interrupt-parent = <&mdss>;
1962 interrupts = 1960 interrupts = <4>;
1963 1961
1964 assigned-cloc 1962 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1965 assigned-cloc 1963 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1966 1964
1967 clocks = <&mm 1965 clocks = <&mmcc MDSS_MDP_CLK>,
1968 <&mm 1966 <&mmcc MDSS_AHB_CLK>,
1969 <&mm 1967 <&mmcc MDSS_AXI_CLK>,
1970 <&mm 1968 <&mmcc MDSS_BYTE0_CLK>,
1971 <&mm 1969 <&mmcc MDSS_PCLK0_CLK>,
1972 <&mm 1970 <&mmcc MDSS_ESC0_CLK>,
1973 <&mm 1971 <&mmcc MMSS_MISC_AHB_CLK>;
1974 clock-names = 1972 clock-names = "mdp_core",
1975 1973 "iface",
1976 1974 "bus",
1977 1975 "byte",
1978 1976 "pixel",
1979 1977 "core",
1980 1978 "core_mmss";
1981 1979
1982 phys = <&mdss 1980 phys = <&mdss_dsi0_phy>;
1983 1981
1984 status = "dis 1982 status = "disabled";
1985 1983
1986 #address-cell 1984 #address-cells = <1>;
1987 #size-cells = 1985 #size-cells = <0>;
1988 1986
1989 ports { 1987 ports {
1990 #addr 1988 #address-cells = <1>;
1991 #size 1989 #size-cells = <0>;
1992 1990
1993 port@ 1991 port@0 {
1994 1992 reg = <0>;
1995 1993 mdss_dsi0_in: endpoint {
1996 1994 remote-endpoint = <&mdp5_intf1_out>;
1997 1995 };
1998 }; 1996 };
1999 1997
2000 port@ 1998 port@1 {
2001 1999 reg = <1>;
2002 2000 mdss_dsi0_out: endpoint {
2003 2001 };
2004 }; 2002 };
2005 }; 2003 };
2006 }; 2004 };
2007 2005
2008 mdss_dsi0_phy: phy@fd 2006 mdss_dsi0_phy: phy@fd922a00 {
2009 compatible = 2007 compatible = "qcom,dsi-phy-28nm-hpm";
2010 reg = <0xfd92 2008 reg = <0xfd922a00 0xd4>,
2011 <0xfd92 2009 <0xfd922b00 0x280>,
2012 <0xfd92 2010 <0xfd922d80 0x30>;
2013 reg-names = " 2011 reg-names = "dsi_pll",
2014 " 2012 "dsi_phy",
2015 " 2013 "dsi_phy_regulator";
2016 2014
2017 #clock-cells 2015 #clock-cells = <1>;
2018 #phy-cells = 2016 #phy-cells = <0>;
2019 2017
2020 clocks = <&mm 2018 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2021 clock-names = 2019 clock-names = "iface", "ref";
2022 2020
2023 status = "dis 2021 status = "disabled";
2024 }; 2022 };
2025 2023
2026 mdss_dsi1: dsi@fd922e 2024 mdss_dsi1: dsi@fd922e00 {
2027 compatible = 2025 compatible = "qcom,msm8974-dsi-ctrl",
2028 2026 "qcom,mdss-dsi-ctrl";
2029 reg = <0xfd92 2027 reg = <0xfd922e00 0x1f8>;
2030 reg-names = " 2028 reg-names = "dsi_ctrl";
2031 2029
2032 interrupt-par 2030 interrupt-parent = <&mdss>;
2033 interrupts = 2031 interrupts = <4>;
2034 2032
2035 assigned-cloc 2033 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2036 assigned-cloc 2034 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2037 2035
2038 clocks = <&mm 2036 clocks = <&mmcc MDSS_MDP_CLK>,
2039 <&mm 2037 <&mmcc MDSS_AHB_CLK>,
2040 <&mm 2038 <&mmcc MDSS_AXI_CLK>,
2041 <&mm 2039 <&mmcc MDSS_BYTE1_CLK>,
2042 <&mm 2040 <&mmcc MDSS_PCLK1_CLK>,
2043 <&mm 2041 <&mmcc MDSS_ESC1_CLK>,
2044 <&mm 2042 <&mmcc MMSS_MISC_AHB_CLK>;
2045 clock-names = 2043 clock-names = "mdp_core",
2046 2044 "iface",
2047 2045 "bus",
2048 2046 "byte",
2049 2047 "pixel",
2050 2048 "core",
2051 2049 "core_mmss";
2052 2050
2053 phys = <&mdss 2051 phys = <&mdss_dsi1_phy>;
2054 2052
2055 status = "dis 2053 status = "disabled";
2056 2054
2057 #address-cell 2055 #address-cells = <1>;
2058 #size-cells = 2056 #size-cells = <0>;
2059 2057
2060 ports { 2058 ports {
2061 #addr 2059 #address-cells = <1>;
2062 #size 2060 #size-cells = <0>;
2063 2061
2064 port@ 2062 port@0 {
2065 2063 reg = <0>;
2066 2064 mdss_dsi1_in: endpoint {
2067 2065 remote-endpoint = <&mdp5_intf2_out>;
2068 2066 };
2069 }; 2067 };
2070 2068
2071 port@ 2069 port@1 {
2072 2070 reg = <1>;
2073 2071 mdss_dsi1_out: endpoint {
2074 2072 };
2075 }; 2073 };
2076 }; 2074 };
2077 }; 2075 };
2078 2076
2079 mdss_dsi1_phy: phy@fd 2077 mdss_dsi1_phy: phy@fd923000 {
2080 compatible = 2078 compatible = "qcom,dsi-phy-28nm-hpm";
2081 reg = <0xfd92 2079 reg = <0xfd923000 0xd4>,
2082 <0xfd92 2080 <0xfd923100 0x280>,
2083 <0xfd92 2081 <0xfd923380 0x30>;
2084 reg-names = " 2082 reg-names = "dsi_pll",
2085 " 2083 "dsi_phy",
2086 " 2084 "dsi_phy_regulator";
2087 2085
2088 #clock-cells 2086 #clock-cells = <1>;
2089 #phy-cells = 2087 #phy-cells = <0>;
2090 2088
2091 clocks = <&mm 2089 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2092 clock-names = 2090 clock-names = "iface", "ref";
2093 2091
2094 status = "dis 2092 status = "disabled";
2095 }; 2093 };
2096 }; 2094 };
2097 2095
2098 cci: cci@fda0c000 { 2096 cci: cci@fda0c000 {
2099 compatible = "qcom,ms 2097 compatible = "qcom,msm8974-cci";
2100 #address-cells = <1>; 2098 #address-cells = <1>;
2101 #size-cells = <0>; 2099 #size-cells = <0>;
2102 reg = <0xfda0c000 0x1 2100 reg = <0xfda0c000 0x1000>;
2103 interrupts = <GIC_SPI 2101 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2104 clocks = <&mmcc CAMSS 2102 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2105 <&mmcc CAMSS 2103 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2106 <&mmcc CAMSS 2104 <&mmcc CAMSS_CCI_CCI_CLK>;
2107 clock-names = "camss_ 2105 clock-names = "camss_top_ahb",
2108 "cci_ah 2106 "cci_ahb",
2109 "cci"; 2107 "cci";
2110 2108
2111 pinctrl-names = "defa 2109 pinctrl-names = "default", "sleep";
2112 pinctrl-0 = <&cci_def 2110 pinctrl-0 = <&cci_default>;
2113 pinctrl-1 = <&cci_sle 2111 pinctrl-1 = <&cci_sleep>;
2114 2112
2115 status = "disabled"; 2113 status = "disabled";
2116 2114
2117 cci_i2c0: i2c-bus@0 { 2115 cci_i2c0: i2c-bus@0 {
2118 reg = <0>; 2116 reg = <0>;
2119 clock-frequen 2117 clock-frequency = <100000>;
2120 #address-cell 2118 #address-cells = <1>;
2121 #size-cells = 2119 #size-cells = <0>;
2122 }; 2120 };
2123 2121
2124 cci_i2c1: i2c-bus@1 { 2122 cci_i2c1: i2c-bus@1 {
2125 reg = <1>; 2123 reg = <1>;
2126 clock-frequen 2124 clock-frequency = <100000>;
2127 #address-cell 2125 #address-cells = <1>;
2128 #size-cells = 2126 #size-cells = <0>;
2129 }; 2127 };
2130 }; 2128 };
2131 2129
2132 gpu: gpu@fdb00000 { !! 2130 gpu: adreno@fdb00000 {
2133 compatible = "qcom,ad 2131 compatible = "qcom,adreno-330.1", "qcom,adreno";
2134 reg = <0xfdb00000 0x1 2132 reg = <0xfdb00000 0x10000>;
2135 reg-names = "kgsl_3d0 2133 reg-names = "kgsl_3d0_reg_memory";
2136 2134
2137 interrupts = <GIC_SPI 2135 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2138 interrupt-names = "kg 2136 interrupt-names = "kgsl_3d0_irq";
2139 2137
2140 clocks = <&mmcc OXILI 2138 clocks = <&mmcc OXILI_GFX3D_CLK>,
2141 <&mmcc OXILI 2139 <&mmcc OXILICX_AHB_CLK>,
2142 <&mmcc OXILI 2140 <&mmcc OXILICX_AXI_CLK>;
2143 clock-names = "core", 2141 clock-names = "core", "iface", "mem_iface";
2144 2142
2145 sram = <&gmu_sram>; 2143 sram = <&gmu_sram>;
2146 power-domains = <&mmc 2144 power-domains = <&mmcc OXILICX_GDSC>;
2147 operating-points-v2 = 2145 operating-points-v2 = <&gpu_opp_table>;
2148 2146
2149 interconnects = <&mms 2147 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2150 <&ocm 2148 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2151 interconnect-names = 2149 interconnect-names = "gfx-mem", "ocmem";
2152 2150
2153 // iommus = <&gpu_iom 2151 // iommus = <&gpu_iommu 0>;
2154 2152
2155 status = "disabled"; 2153 status = "disabled";
2156 2154
2157 gpu_opp_table: opp-ta 2155 gpu_opp_table: opp-table {
2158 compatible = 2156 compatible = "operating-points-v2";
2159 2157
2160 opp-320000000 2158 opp-320000000 {
2161 opp-h 2159 opp-hz = /bits/ 64 <320000000>;
2162 }; 2160 };
2163 2161
2164 opp-200000000 2162 opp-200000000 {
2165 opp-h 2163 opp-hz = /bits/ 64 <200000000>;
2166 }; 2164 };
2167 2165
2168 opp-27000000 2166 opp-27000000 {
2169 opp-h 2167 opp-hz = /bits/ 64 <27000000>;
2170 }; 2168 };
2171 }; 2169 };
2172 }; 2170 };
2173 2171
2174 sram@fdd00000 { 2172 sram@fdd00000 {
2175 compatible = "qcom,ms 2173 compatible = "qcom,msm8974-ocmem";
2176 reg = <0xfdd00000 0x2 2174 reg = <0xfdd00000 0x2000>,
2177 <0xfec00000 0x1 2175 <0xfec00000 0x180000>;
2178 reg-names = "ctrl", " 2176 reg-names = "ctrl", "mem";
2179 ranges = <0 0xfec0000 2177 ranges = <0 0xfec00000 0x180000>;
2180 clocks = <&rpmcc RPM_ 2178 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2181 <&mmcc OCMEM 2179 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2182 clock-names = "core", 2180 clock-names = "core", "iface";
2183 2181
2184 #address-cells = <1>; 2182 #address-cells = <1>;
2185 #size-cells = <1>; 2183 #size-cells = <1>;
2186 2184
2187 gmu_sram: gmu-sram@0 2185 gmu_sram: gmu-sram@0 {
2188 reg = <0x0 0x 2186 reg = <0x0 0x100000>;
2189 }; 2187 };
2190 }; 2188 };
2191 2189
2192 remoteproc_adsp: remoteproc@f 2190 remoteproc_adsp: remoteproc@fe200000 {
2193 compatible = "qcom,ms 2191 compatible = "qcom,msm8974-adsp-pil";
2194 reg = <0xfe200000 0x1 2192 reg = <0xfe200000 0x100>;
2195 2193
2196 interrupts-extended = 2194 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2197 2195 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2198 2196 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2199 2197 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2200 2198 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2201 interrupt-names = "wd 2199 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2202 2200
2203 clocks = <&xo_board>; 2201 clocks = <&xo_board>;
2204 clock-names = "xo"; 2202 clock-names = "xo";
2205 2203
2206 memory-region = <&ads 2204 memory-region = <&adsp_region>;
2207 2205
2208 qcom,smem-states = <& 2206 qcom,smem-states = <&adsp_smp2p_out 0>;
2209 qcom,smem-state-names 2207 qcom,smem-state-names = "stop";
2210 2208
2211 status = "disabled"; 2209 status = "disabled";
2212 2210
2213 smd-edge { 2211 smd-edge {
2214 interrupts = 2212 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2215 2213
2216 mboxes = <&ap !! 2214 qcom,ipc = <&apcs 8 8>;
2217 qcom,smd-edge 2215 qcom,smd-edge = <1>;
2218 label = "lpas 2216 label = "lpass";
2219 }; 2217 };
2220 }; 2218 };
2221 2219
2222 imem: sram@fe805000 { 2220 imem: sram@fe805000 {
2223 compatible = "qcom,ms 2221 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2224 reg = <0xfe805000 0x1 2222 reg = <0xfe805000 0x1000>;
2225 2223
2226 reboot-mode { 2224 reboot-mode {
2227 compatible = 2225 compatible = "syscon-reboot-mode";
2228 offset = <0x6 2226 offset = <0x65c>;
2229 }; 2227 };
2230 }; 2228 };
2231 }; 2229 };
2232 2230
2233 thermal-zones { 2231 thermal-zones {
2234 cpu0-thermal { 2232 cpu0-thermal {
2235 polling-delay-passive 2233 polling-delay-passive = <250>;
2236 polling-delay = <1000 2234 polling-delay = <1000>;
2237 2235
2238 thermal-sensors = <&t 2236 thermal-sensors = <&tsens 5>;
2239 2237
2240 trips { 2238 trips {
2241 cpu_alert0: t 2239 cpu_alert0: trip0 {
2242 tempe 2240 temperature = <75000>;
2243 hyste 2241 hysteresis = <2000>;
2244 type 2242 type = "passive";
2245 }; 2243 };
2246 cpu_crit0: tr 2244 cpu_crit0: trip1 {
2247 tempe 2245 temperature = <110000>;
2248 hyste 2246 hysteresis = <2000>;
2249 type 2247 type = "critical";
2250 }; 2248 };
2251 }; 2249 };
2252 }; 2250 };
2253 2251
2254 cpu1-thermal { 2252 cpu1-thermal {
2255 polling-delay-passive 2253 polling-delay-passive = <250>;
2256 polling-delay = <1000 2254 polling-delay = <1000>;
2257 2255
2258 thermal-sensors = <&t 2256 thermal-sensors = <&tsens 6>;
2259 2257
2260 trips { 2258 trips {
2261 cpu_alert1: t 2259 cpu_alert1: trip0 {
2262 tempe 2260 temperature = <75000>;
2263 hyste 2261 hysteresis = <2000>;
2264 type 2262 type = "passive";
2265 }; 2263 };
2266 cpu_crit1: tr 2264 cpu_crit1: trip1 {
2267 tempe 2265 temperature = <110000>;
2268 hyste 2266 hysteresis = <2000>;
2269 type 2267 type = "critical";
2270 }; 2268 };
2271 }; 2269 };
2272 }; 2270 };
2273 2271
2274 cpu2-thermal { 2272 cpu2-thermal {
2275 polling-delay-passive 2273 polling-delay-passive = <250>;
2276 polling-delay = <1000 2274 polling-delay = <1000>;
2277 2275
2278 thermal-sensors = <&t 2276 thermal-sensors = <&tsens 7>;
2279 2277
2280 trips { 2278 trips {
2281 cpu_alert2: t 2279 cpu_alert2: trip0 {
2282 tempe 2280 temperature = <75000>;
2283 hyste 2281 hysteresis = <2000>;
2284 type 2282 type = "passive";
2285 }; 2283 };
2286 cpu_crit2: tr 2284 cpu_crit2: trip1 {
2287 tempe 2285 temperature = <110000>;
2288 hyste 2286 hysteresis = <2000>;
2289 type 2287 type = "critical";
2290 }; 2288 };
2291 }; 2289 };
2292 }; 2290 };
2293 2291
2294 cpu3-thermal { 2292 cpu3-thermal {
2295 polling-delay-passive 2293 polling-delay-passive = <250>;
2296 polling-delay = <1000 2294 polling-delay = <1000>;
2297 2295
2298 thermal-sensors = <&t 2296 thermal-sensors = <&tsens 8>;
2299 2297
2300 trips { 2298 trips {
2301 cpu_alert3: t 2299 cpu_alert3: trip0 {
2302 tempe 2300 temperature = <75000>;
2303 hyste 2301 hysteresis = <2000>;
2304 type 2302 type = "passive";
2305 }; 2303 };
2306 cpu_crit3: tr 2304 cpu_crit3: trip1 {
2307 tempe 2305 temperature = <110000>;
2308 hyste 2306 hysteresis = <2000>;
2309 type 2307 type = "critical";
2310 }; 2308 };
2311 }; 2309 };
2312 }; 2310 };
2313 2311
2314 q6-dsp-thermal { 2312 q6-dsp-thermal {
2315 polling-delay-passive 2313 polling-delay-passive = <250>;
2316 polling-delay = <1000 2314 polling-delay = <1000>;
2317 2315
2318 thermal-sensors = <&t 2316 thermal-sensors = <&tsens 1>;
2319 2317
2320 trips { 2318 trips {
2321 q6_dsp_alert0 2319 q6_dsp_alert0: trip-point0 {
2322 tempe 2320 temperature = <90000>;
2323 hyste 2321 hysteresis = <2000>;
2324 type 2322 type = "hot";
2325 }; 2323 };
2326 }; 2324 };
2327 }; 2325 };
2328 2326
2329 modemtx-thermal { 2327 modemtx-thermal {
2330 polling-delay-passive 2328 polling-delay-passive = <250>;
2331 polling-delay = <1000 2329 polling-delay = <1000>;
2332 2330
2333 thermal-sensors = <&t 2331 thermal-sensors = <&tsens 2>;
2334 2332
2335 trips { 2333 trips {
2336 modemtx_alert 2334 modemtx_alert0: trip-point0 {
2337 tempe 2335 temperature = <90000>;
2338 hyste 2336 hysteresis = <2000>;
2339 type 2337 type = "hot";
2340 }; 2338 };
2341 }; 2339 };
2342 }; 2340 };
2343 2341
2344 video-thermal { 2342 video-thermal {
2345 polling-delay-passive 2343 polling-delay-passive = <250>;
2346 polling-delay = <1000 2344 polling-delay = <1000>;
2347 2345
2348 thermal-sensors = <&t 2346 thermal-sensors = <&tsens 3>;
2349 2347
2350 trips { 2348 trips {
2351 video_alert0: 2349 video_alert0: trip-point0 {
2352 tempe 2350 temperature = <95000>;
2353 hyste 2351 hysteresis = <2000>;
2354 type 2352 type = "hot";
2355 }; 2353 };
2356 }; 2354 };
2357 }; 2355 };
2358 2356
2359 wlan-thermal { 2357 wlan-thermal {
2360 polling-delay-passive 2358 polling-delay-passive = <250>;
2361 polling-delay = <1000 2359 polling-delay = <1000>;
2362 2360
2363 thermal-sensors = <&t 2361 thermal-sensors = <&tsens 4>;
2364 2362
2365 trips { 2363 trips {
2366 wlan_alert0: 2364 wlan_alert0: trip-point0 {
2367 tempe 2365 temperature = <105000>;
2368 hyste 2366 hysteresis = <2000>;
2369 type 2367 type = "hot";
2370 }; 2368 };
2371 }; 2369 };
2372 }; 2370 };
2373 2371
2374 gpu-top-thermal { 2372 gpu-top-thermal {
2375 polling-delay-passive 2373 polling-delay-passive = <250>;
2376 polling-delay = <1000 2374 polling-delay = <1000>;
2377 2375
2378 thermal-sensors = <&t 2376 thermal-sensors = <&tsens 9>;
2379 2377
2380 trips { 2378 trips {
2381 gpu1_alert0: 2379 gpu1_alert0: trip-point0 {
2382 tempe 2380 temperature = <90000>;
2383 hyste 2381 hysteresis = <2000>;
2384 type 2382 type = "hot";
2385 }; 2383 };
2386 }; 2384 };
2387 }; 2385 };
2388 2386
2389 gpu-bottom-thermal { 2387 gpu-bottom-thermal {
2390 polling-delay-passive 2388 polling-delay-passive = <250>;
2391 polling-delay = <1000 2389 polling-delay = <1000>;
2392 2390
2393 thermal-sensors = <&t 2391 thermal-sensors = <&tsens 10>;
2394 2392
2395 trips { 2393 trips {
2396 gpu2_alert0: 2394 gpu2_alert0: trip-point0 {
2397 tempe 2395 temperature = <90000>;
2398 hyste 2396 hysteresis = <2000>;
2399 type 2397 type = "hot";
2400 }; 2398 };
2401 }; 2399 };
2402 }; 2400 };
2403 }; 2401 };
2404 2402
2405 timer { 2403 timer {
2406 compatible = "arm,armv7-timer 2404 compatible = "arm,armv7-timer";
2407 interrupts = <GIC_PPI 2 (GIC_ 2405 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2408 <GIC_PPI 3 (GIC_ 2406 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2409 <GIC_PPI 4 (GIC_ 2407 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2410 <GIC_PPI 1 (GIC_ 2408 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2411 clock-frequency = <19200000>; 2409 clock-frequency = <19200000>;
2412 }; 2410 };
2413 }; 2411 };
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