1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SDX65 SoC device tree source
4 *
5 * Copyright (c) 2021 Qualcomm Innovation Cent
6 *
7 */
8
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <458 0x10000>, <483 0x10
21 interrupt-parent = <&intc>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-cl
31 clock-frequency = <768
32 clock-output-names = "
33 #clock-cells = <0>;
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-cl
38 clock-frequency = <327
39 clock-output-names = "
40 #clock-cells = <0>;
41 };
42
43 nand_clk_dummy: nand-clk-dummy
44 compatible = "fixed-cl
45 clock-frequency = <327
46 #clock-cells = <0>;
47 };
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cort
57 reg = <0x0>;
58 enable-method = "psci"
59 clocks = <&apcs>;
60 power-domains = <&rpmh
61 power-domain-names = "
62 operating-points-v2 =
63 };
64 };
65
66 firmware {
67 scm {
68 compatible = "qcom,scm
69 };
70 };
71
72 mc_virt: interconnect-mc-virt {
73 compatible = "qcom,sdx65-mc-vi
74 #interconnect-cells = <1>;
75 qcom,bcm-voters = <&apps_bcm_v
76 };
77
78 cpu_opp_table: opp-table-cpu {
79 compatible = "operating-points
80 opp-shared;
81
82 opp-345600000 {
83 opp-hz = /bits/ 64 <34
84 required-opps = <&rpmh
85 };
86
87 opp-576000000 {
88 opp-hz = /bits/ 64 <57
89 required-opps = <&rpmh
90 };
91
92 opp-1094400000 {
93 opp-hz = /bits/ 64 <10
94 required-opps = <&rpmh
95 };
96
97 opp-1497600000 {
98 opp-hz = /bits/ 64 <14
99 required-opps = <&rpmh
100 };
101 };
102
103 psci {
104 compatible = "arm,psci-1.0";
105 method = "smc";
106 };
107
108 reserved_memory: reserved-memory {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112
113 tz_heap_mem: memory@8fcad000 {
114 no-map;
115 reg = <0x8fcad000 0x40
116 };
117
118 secdata_mem: memory@8fcfd000 {
119 no-map;
120 reg = <0x8fcfd000 0x10
121 };
122
123 hyp_mem: memory@8fd00000 {
124 no-map;
125 reg = <0x8fd00000 0x80
126 };
127
128 access_control_mem: memory@8fd
129 no-map;
130 reg = <0x8fd80000 0x80
131 };
132
133 aop_mem: memory@8fe00000 {
134 no-map;
135 reg = <0x8fe00000 0x20
136 };
137
138 smem_mem: memory@8fe20000 {
139 compatible = "qcom,sme
140 reg = <0x8fe20000 0xc0
141 hwlocks = <&tcsr_mutex
142 no-map;
143 };
144
145 cmd_db: reserved-memory@8fee00
146 compatible = "qcom,cmd
147 reg = <0x8fee0000 0x20
148 no-map;
149 };
150
151 tz_mem: memory@8ff00000 {
152 no-map;
153 reg = <0x8ff00000 0x10
154 };
155
156 tz_apps_mem: memory@90000000 {
157 no-map;
158 reg = <0x90000000 0x50
159 };
160
161 llcc_tcm_mem: memory@15800000
162 no-map;
163 reg = <0x15800000 0x80
164 };
165 };
166
167 smp2p-mpss {
168 compatible = "qcom,smp2p";
169 qcom,smem = <435>, <428>;
170 interrupts = <GIC_SPI 113 IRQ_
171 mboxes = <&apcs 14>;
172 qcom,local-pid = <0>;
173 qcom,remote-pid = <1>;
174
175 modem_smp2p_out: master-kernel
176 qcom,entry-name = "mas
177 #qcom,smem-state-cells
178 };
179
180 modem_smp2p_in: slave-kernel {
181 qcom,entry-name = "sla
182 interrupt-controller;
183 #interrupt-cells = <2>
184 };
185
186 ipa_smp2p_out: ipa-ap-to-modem
187 qcom,entry-name = "ipa
188 #qcom,smem-state-cells
189 };
190
191 ipa_smp2p_in: ipa-modem-to-ap
192 qcom,entry-name = "ipa
193 interrupt-controller;
194 #interrupt-cells = <2>
195 };
196 };
197
198 soc: soc {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 ranges;
202 compatible = "simple-bus";
203
204 gcc: clock-controller@100000 {
205 compatible = "qcom,gcc
206 reg = <0x00100000 0x00
207 clocks = <&rpmhcc RPMH
208 <&rpmhcc RPMH
209 <&sleep_clk>,
210 <&pcie_phy>,
211 <0>;
212 clock-names = "bi_tcxo
213 "bi_tcxo
214 "sleep_c
215 "pcie_pi
216 "usb3_ph
217 #power-domain-cells =
218 #clock-cells = <1>;
219 #reset-cells = <1>;
220 };
221
222 blsp1_uart3: serial@831000 {
223 compatible = "qcom,msm
224 reg = <0x00831000 0x20
225 interrupts = <GIC_SPI
226 clocks = <&gcc GCC_BLS
227 clock-names = "core",
228 status = "disabled";
229 };
230
231 usb_hsphy: phy@ff4000 {
232 compatible = "qcom,sdx
233 "qcom,usb
234 reg = <0xff4000 0x120>
235 #phy-cells = <0>;
236 clocks = <&rpmhcc RPMH
237 clock-names = "ref";
238 resets = <&gcc GCC_QUS
239 status = "disabled";
240 };
241
242 usb_qmpphy: phy@ff6000 {
243 compatible = "qcom,sdx
244 reg = <0x00ff6000 0x20
245
246 clocks = <&gcc GCC_USB
247 <&gcc GCC_USB
248 <&gcc GCC_USB
249 <&gcc GCC_USB
250 clock-names = "aux",
251 "ref",
252 "cfg_ahb
253 "pipe";
254 clock-output-names = "
255 #clock-cells = <0>;
256 #phy-cells = <0>;
257
258 resets = <&gcc GCC_USB
259 <&gcc GCC_USB
260 reset-names = "phy",
261 "phy_phy
262
263 status = "disabled";
264
265 };
266
267 system_noc: interconnect@16200
268 compatible = "qcom,sdx
269 reg = <0x01620000 0x31
270 #interconnect-cells =
271 qcom,bcm-voters = <&ap
272 };
273
274 qpic_bam: dma-controller@1b040
275 compatible = "qcom,bam
276 reg = <0x01b04000 0x1c
277 interrupts = <GIC_SPI
278 clocks = <&rpmhcc RPMH
279 clock-names = "bam_clk
280 #dma-cells = <1>;
281 qcom,ee = <0>;
282 qcom,controlled-remote
283 status = "disabled";
284 };
285
286 qpic_nand: nand-controller@1b3
287 compatible = "qcom,sdx
288 reg = <0x01b30000 0x10
289 #address-cells = <1>;
290 #size-cells = <0>;
291 clocks = <&rpmhcc RPMH
292 <&nand_clk_du
293 clock-names = "core",
294
295 dmas = <&qpic_bam 0>,
296 <&qpic_bam 1>,
297 <&qpic_bam 2>;
298 dma-names = "tx", "rx"
299 status = "disabled";
300 };
301
302 pcie_ep: pcie-ep@1c00000 {
303 compatible = "qcom,sdx
304 reg = <0x01c00000 0x30
305 <0x40000000 0xf1
306 <0x40000f20 0xa8
307 <0x40001000 0x10
308 <0x40200000 0x10
309 <0x01c03000 0x30
310 reg-names = "parf",
311 "dbi",
312 "elbi",
313 "atu",
314 "addr_spac
315 "mmio";
316
317 qcom,perst-regs = <&tc
318
319 clocks = <&gcc GCC_PCI
320 <&gcc GCC_PCI
321 <&gcc GCC_PCI
322 <&gcc GCC_PCI
323 <&gcc GCC_PCI
324 <&gcc GCC_PCI
325 <&gcc GCC_PCI
326 clock-names = "aux",
327 "cfg",
328 "bus_mas
329 "bus_sla
330 "slave_q
331 "sleep",
332 "ref";
333
334 interrupts = <GIC_SPI
335 <GIC_SPI
336 interrupt-names = "glo
337
338 resets = <&gcc GCC_PCI
339 reset-names = "core";
340
341 power-domains = <&gcc
342
343 phys = <&pcie_phy>;
344 phy-names = "pciephy";
345
346 max-link-speed = <3>;
347 num-lanes = <2>;
348
349 status = "disabled";
350 };
351
352 pcie_phy: phy@1c06000 {
353 compatible = "qcom,sdx
354 reg = <0x01c06000 0x20
355
356 clocks = <&gcc GCC_PCI
357 <&gcc GCC_PCI
358 <&gcc GCC_PCI
359 <&gcc GCC_PCI
360 <&gcc GCC_PCI
361 clock-names = "aux",
362 "cfg_ahb
363 "ref",
364 "rchng",
365 "pipe";
366
367 resets = <&gcc GCC_PCI
368 reset-names = "phy";
369
370 assigned-clocks = <&gc
371 assigned-clock-rates =
372
373 power-domains = <&gcc
374
375 #clock-cells = <0>;
376 clock-output-names = "
377
378 #phy-cells = <0>;
379
380 status = "disabled";
381 };
382
383 tcsr_mutex: hwlock@1f40000 {
384 compatible = "qcom,tcs
385 reg = <0x01f40000 0x40
386 #hwlock-cells = <1>;
387 };
388
389 tcsr: syscon@1fcb000 {
390 compatible = "qcom,sdx
391 reg = <0x01fc0000 0x10
392 };
393
394 ipa: ipa@3f40000 {
395 compatible = "qcom,sdx
396
397 reg = <0x03f40000 0x10
398 <0x03f50000 0x50
399 <0x03e04000 0xfc
400 reg-names = "ipa-reg",
401 "ipa-share
402 "gsi";
403
404 interrupts-extended =
405
406
407
408 interrupt-names = "ipa
409 "gsi
410 "ipa
411 "ipa
412
413 iommus = <&apps_smmu 0
414 <&apps_smmu 0
415
416 clocks = <&rpmhcc RPMH
417 clock-names = "core";
418
419 interconnects = <&syst
420 <&mem_
421 interconnect-names = "
422 "
423
424 qcom,smem-states = <&i
425 <&i
426 qcom,smem-state-names
427
428
429 status = "disabled";
430 };
431
432 remoteproc_mpss: remoteproc@40
433 compatible = "qcom,sdx
434 reg = <0x04080000 0x40
435
436 interrupts-extended =
437
438
439
440
441
442 interrupt-names = "wdo
443 "sto
444
445 clocks = <&rpmhcc RPMH
446 clock-names = "xo";
447
448 power-domains = <&rpmh
449 <&rpmh
450 power-domain-names = "
451
452 qcom,smem-states = <&m
453 qcom,smem-state-names
454
455 status = "disabled";
456
457 glink-edge {
458 interrupts = <
459 label = "mpss"
460 qcom,remote-pi
461 mboxes = <&apc
462 };
463 };
464
465 sdhc_1: mmc@8804000 {
466 compatible = "qcom,sdx
467 reg = <0x08804000 0x10
468 reg-names = "hc";
469 interrupts = <GIC_SPI
470 <GIC_SPI
471 interrupt-names = "hc_
472 clocks = <&gcc GCC_SDC
473 <&gcc GCC_SDC
474 clock-names = "iface",
475 status = "disabled";
476 };
477
478 mem_noc: interconnect@9680000
479 compatible = "qcom,sdx
480 reg = <0x09680000 0x27
481 #interconnect-cells =
482 qcom,bcm-voters = <&ap
483 };
484
485 usb: usb@a6f8800 {
486 compatible = "qcom,sdx
487 reg = <0x0a6f8800 0x40
488 #address-cells = <1>;
489 #size-cells = <1>;
490 ranges;
491
492 clocks = <&gcc GCC_USB
493 <&gcc GCC_USB
494 <&gcc GCC_USB
495 <&gcc GCC_USB
496 <&gcc GCC_USB
497 clock-names = "cfg_noc
498 "mock_ut
499
500 assigned-clocks = <&gc
501 <&gc
502 assigned-clock-rates =
503
504 interrupts-extended =
505
506
507
508
509 interrupt-names = "pwr
510 "hs_
511 "dp_
512 "dm_
513 "ss_
514
515 power-domains = <&gcc
516
517 resets = <&gcc GCC_USB
518
519 status = "disabled";
520
521 usb_dwc3: usb@a600000
522 compatible = "
523 reg = <0x0a600
524 interrupts = <
525 iommus = <&app
526 snps,dis_u2_su
527 snps,dis_enbls
528 phys = <&usb_h
529 phy-names = "u
530 };
531 };
532
533 restart@c264000 {
534 compatible = "qcom,psh
535 reg = <0x0c264000 0x10
536 };
537
538 spmi_bus: spmi@c440000 {
539 compatible = "qcom,spm
540 reg = <0xc440000 0xd00
541 <0xc600000 0x2
542 <0xe600000 0x1
543 <0xe700000 0xa
544 <0xc40a000 0x2
545 reg-names = "core", "c
546 interrupts-extended =
547 interrupt-names = "per
548 interrupt-controller;
549 #interrupt-cells = <4>
550 #address-cells = <2>;
551 #size-cells = <0>;
552 qcom,channel = <0>;
553 qcom,ee = <0>;
554 };
555
556 tlmm: pinctrl@f100000 {
557 compatible = "qcom,sdx
558 reg = <0xf100000 0x300
559 interrupts = <GIC_SPI
560 gpio-controller;
561 #gpio-cells = <2>;
562 gpio-ranges = <&tlmm 0
563 interrupt-controller;
564 interrupt-parent = <&i
565 #interrupt-cells = <2>
566 };
567
568 pdc: interrupt-controller@b210
569 compatible = "qcom,sdx
570 reg = <0xb210000 0x100
571 qcom,pdc-ranges = <0 1
572 #interrupt-cells = <2>
573 interrupt-parent = <&i
574 interrupt-controller;
575 };
576
577 sram@1468f000 {
578 compatible = "qcom,sdx
579 reg = <0x1468f000 0x10
580 ranges = <0x0 0x1468f0
581 #address-cells = <1>;
582 #size-cells = <1>;
583
584 pil-reloc@94c {
585 compatible = "
586 reg = <0x94c 0
587 };
588 };
589
590 apps_smmu: iommu@15000000 {
591 compatible = "qcom,sdx
592 reg = <0x15000000 0x40
593 #iommu-cells = <2>;
594 #global-interrupts = <
595 interrupts = <GIC_S
596 <GIC_S
597 <GIC_S
598 <GIC_S
599 <GIC_S
600 <GIC_S
601 <GIC_S
602 <GIC_S
603 <GIC_S
604 <GIC_S
605 <GIC_S
606 <GIC_S
607 <GIC_S
608 <GIC_S
609 <GIC_S
610 <GIC_S
611 <GIC_S
612 <GIC_S
613 <GIC_S
614 <GIC_S
615 <GIC_S
616 <GIC_S
617 <GIC_S
618 <GIC_S
619 <GIC_S
620 <GIC_S
621 <GIC_S
622 <GIC_S
623 <GIC_S
624 <GIC_S
625 <GIC_S
626 <GIC_S
627 <GIC_S
628 };
629
630 intc: interrupt-controller@178
631 compatible = "qcom,msm
632 interrupt-controller;
633 interrupt-parent = <&i
634 #interrupt-cells = <3>
635 reg = <0x17800000 0x10
636 <0x17802000 0x10
637 };
638
639 a7pll: clock@17808000 {
640 compatible = "qcom,sdx
641 reg = <0x17808000 0x10
642 clocks = <&rpmhcc RPMH
643 clock-names = "bi_tcxo
644 #clock-cells = <0>;
645 };
646
647 apcs: mailbox@17810000 {
648 compatible = "qcom,sdx
649 reg = <0x17810000 0x20
650 #mbox-cells = <1>;
651 clocks = <&rpmhcc RPMH
652 clock-names = "ref", "
653 #clock-cells = <0>;
654 };
655
656 watchdog@17817000 {
657 compatible = "qcom,aps
658 reg = <0x17817000 0x10
659 clocks = <&sleep_clk>;
660 };
661
662 timer@17820000 {
663 #address-cells = <1>;
664 #size-cells = <1>;
665 ranges;
666 compatible = "arm,armv
667 reg = <0x17820000 0x10
668 clock-frequency = <192
669
670 frame@17821000 {
671 frame-number =
672 interrupts = <
673 <
674 reg = <0x17821
675 <0x17822
676 };
677
678 frame@17823000 {
679 frame-number =
680 interrupts = <
681 reg = <0x17823
682 status = "disa
683 };
684
685 frame@17824000 {
686 frame-number =
687 interrupts = <
688 reg = <0x17824
689 status = "disa
690 };
691
692 frame@17825000 {
693 frame-number =
694 interrupts = <
695 reg = <0x17825
696 status = "disa
697 };
698
699 frame@17826000 {
700 frame-number =
701 interrupts = <
702 reg = <0x17826
703 status = "disa
704 };
705
706 frame@17827000 {
707 frame-number =
708 interrupts = <
709 reg = <0x17827
710 status = "disa
711 };
712
713 frame@17828000 {
714 frame-number =
715 interrupts = <
716 reg = <0x17828
717 status = "disa
718 };
719
720 frame@17829000 {
721 frame-number =
722 interrupts = <
723 reg = <0x17829
724 status = "disa
725 };
726 };
727
728 apps_rsc: rsc@17830000 {
729 label = "apps_rsc";
730 compatible = "qcom,rpm
731 reg = <0x17830000 0x10
732 <0x17840000 0x1000
733 reg-names = "drv-0", "
734 interrupts = <GIC_SPI
735 <GIC_SPI 17
736 qcom,tcs-offset = <0xd
737 qcom,drv-id = <1>;
738 qcom,tcs-config = <ACT
739 <SLEEP_TCS 2
740 <WAKE_TCS 2
741 <CONTROL_TCS 1
742
743 rpmhcc: clock-controll
744 compatible = "
745 #clock-cells =
746 clock-names =
747 clocks = <&xo_
748 };
749
750 rpmhpd: power-controll
751 compatible = "
752 #power-domain-
753 operating-poin
754
755 rpmhpd_opp_tab
756 compat
757
758 rpmhpd
759
760 };
761
762 rpmhpd
763
764 };
765
766 rpmhpd
767
768 };
769
770 rpmhpd
771
772 };
773
774 rpmhpd
775
776 };
777
778 rpmhpd
779
780 };
781
782 rpmhpd
783
784 };
785
786 rpmhpd
787
788 };
789
790 rpmhpd
791
792 };
793
794 rpmhpd
795
796 };
797 };
798 };
799
800 apps_bcm_voter: bcm-vo
801 compatible = "
802 };
803
804 };
805 };
806
807 timer {
808 compatible = "arm,armv7-timer"
809 interrupts = <GIC_PPI 13 (GIC_
810 <GIC_PPI 12 (GIC_
811 <GIC_PPI 10 (GIC_
812 <GIC_PPI 11 (GIC_
813 clock-frequency = <19200000>;
814 };
815 };
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