1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SDX65 SoC device tree source 3 * SDX65 SoC device tree source
4 * 4 *
5 * Copyright (c) 2021 Qualcomm Innovation Cent 5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h> 9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65. 15 #include <dt-bindings/interconnect/qcom,sdx65.h>
16 16
17 / { 17 / {
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 qcom,msm-id = <458 0x10000>, <483 0x10 20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
21 interrupt-parent = <&intc>; 21 interrupt-parent = <&intc>;
22 22
23 memory { 23 memory {
24 device_type = "memory"; 24 device_type = "memory";
25 reg = <0 0>; 25 reg = <0 0>;
26 }; 26 };
27 27
28 clocks { 28 clocks {
29 xo_board: xo-board { 29 xo_board: xo-board {
30 compatible = "fixed-cl 30 compatible = "fixed-clock";
31 clock-frequency = <768 31 clock-frequency = <76800000>;
32 clock-output-names = " 32 clock-output-names = "xo_board";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 }; 34 };
35 35
36 sleep_clk: sleep-clk { 36 sleep_clk: sleep-clk {
37 compatible = "fixed-cl 37 compatible = "fixed-clock";
38 clock-frequency = <327 38 clock-frequency = <32764>;
39 clock-output-names = " 39 clock-output-names = "sleep_clk";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 }; 41 };
42 42
43 nand_clk_dummy: nand-clk-dummy 43 nand_clk_dummy: nand-clk-dummy {
44 compatible = "fixed-cl 44 compatible = "fixed-clock";
45 clock-frequency = <327 45 clock-frequency = <32764>;
46 #clock-cells = <0>; 46 #clock-cells = <0>;
47 }; 47 };
48 }; 48 };
49 49
50 cpus { 50 cpus {
51 #address-cells = <1>; 51 #address-cells = <1>;
52 #size-cells = <0>; 52 #size-cells = <0>;
53 53
54 cpu0: cpu@0 { 54 cpu0: cpu@0 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "arm,cort 56 compatible = "arm,cortex-a7";
57 reg = <0x0>; 57 reg = <0x0>;
58 enable-method = "psci" 58 enable-method = "psci";
59 clocks = <&apcs>; 59 clocks = <&apcs>;
60 power-domains = <&rpmh 60 power-domains = <&rpmhpd SDX65_CX_AO>;
61 power-domain-names = " 61 power-domain-names = "rpmhpd";
62 operating-points-v2 = 62 operating-points-v2 = <&cpu_opp_table>;
63 }; 63 };
64 }; 64 };
65 65
66 firmware { 66 firmware {
67 scm { 67 scm {
68 compatible = "qcom,scm 68 compatible = "qcom,scm-sdx65", "qcom,scm";
69 }; 69 };
70 }; 70 };
71 71
72 mc_virt: interconnect-mc-virt { 72 mc_virt: interconnect-mc-virt {
73 compatible = "qcom,sdx65-mc-vi 73 compatible = "qcom,sdx65-mc-virt";
74 #interconnect-cells = <1>; 74 #interconnect-cells = <1>;
75 qcom,bcm-voters = <&apps_bcm_v 75 qcom,bcm-voters = <&apps_bcm_voter>;
76 }; 76 };
77 77
78 cpu_opp_table: opp-table-cpu { 78 cpu_opp_table: opp-table-cpu {
79 compatible = "operating-points 79 compatible = "operating-points-v2";
80 opp-shared; 80 opp-shared;
81 81
82 opp-345600000 { 82 opp-345600000 {
83 opp-hz = /bits/ 64 <34 83 opp-hz = /bits/ 64 <345600000>;
84 required-opps = <&rpmh 84 required-opps = <&rpmhpd_opp_low_svs>;
85 }; 85 };
86 86
87 opp-576000000 { 87 opp-576000000 {
88 opp-hz = /bits/ 64 <57 88 opp-hz = /bits/ 64 <576000000>;
89 required-opps = <&rpmh 89 required-opps = <&rpmhpd_opp_svs>;
90 }; 90 };
91 91
92 opp-1094400000 { 92 opp-1094400000 {
93 opp-hz = /bits/ 64 <10 93 opp-hz = /bits/ 64 <1094400000>;
94 required-opps = <&rpmh 94 required-opps = <&rpmhpd_opp_nom>;
95 }; 95 };
96 96
97 opp-1497600000 { 97 opp-1497600000 {
98 opp-hz = /bits/ 64 <14 98 opp-hz = /bits/ 64 <1497600000>;
99 required-opps = <&rpmh 99 required-opps = <&rpmhpd_opp_turbo>;
100 }; 100 };
101 }; 101 };
102 102
103 psci { 103 psci {
104 compatible = "arm,psci-1.0"; 104 compatible = "arm,psci-1.0";
105 method = "smc"; 105 method = "smc";
106 }; 106 };
107 107
108 reserved_memory: reserved-memory { 108 reserved_memory: reserved-memory {
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <1>; 110 #size-cells = <1>;
111 ranges; 111 ranges;
112 112
113 tz_heap_mem: memory@8fcad000 { 113 tz_heap_mem: memory@8fcad000 {
114 no-map; 114 no-map;
115 reg = <0x8fcad000 0x40 115 reg = <0x8fcad000 0x40000>;
116 }; 116 };
117 117
118 secdata_mem: memory@8fcfd000 { 118 secdata_mem: memory@8fcfd000 {
119 no-map; 119 no-map;
120 reg = <0x8fcfd000 0x10 120 reg = <0x8fcfd000 0x1000>;
121 }; 121 };
122 122
123 hyp_mem: memory@8fd00000 { 123 hyp_mem: memory@8fd00000 {
124 no-map; 124 no-map;
125 reg = <0x8fd00000 0x80 125 reg = <0x8fd00000 0x80000>;
126 }; 126 };
127 127
128 access_control_mem: memory@8fd 128 access_control_mem: memory@8fd80000 {
129 no-map; 129 no-map;
130 reg = <0x8fd80000 0x80 130 reg = <0x8fd80000 0x80000>;
131 }; 131 };
132 132
133 aop_mem: memory@8fe00000 { 133 aop_mem: memory@8fe00000 {
134 no-map; 134 no-map;
135 reg = <0x8fe00000 0x20 135 reg = <0x8fe00000 0x20000>;
136 }; 136 };
137 137
138 smem_mem: memory@8fe20000 { 138 smem_mem: memory@8fe20000 {
139 compatible = "qcom,sme 139 compatible = "qcom,smem";
140 reg = <0x8fe20000 0xc0 140 reg = <0x8fe20000 0xc0000>;
141 hwlocks = <&tcsr_mutex 141 hwlocks = <&tcsr_mutex 3>;
142 no-map; 142 no-map;
143 }; 143 };
144 144
145 cmd_db: reserved-memory@8fee00 145 cmd_db: reserved-memory@8fee0000 {
146 compatible = "qcom,cmd 146 compatible = "qcom,cmd-db";
147 reg = <0x8fee0000 0x20 147 reg = <0x8fee0000 0x20000>;
148 no-map; 148 no-map;
149 }; 149 };
150 150
151 tz_mem: memory@8ff00000 { 151 tz_mem: memory@8ff00000 {
152 no-map; 152 no-map;
153 reg = <0x8ff00000 0x10 153 reg = <0x8ff00000 0x100000>;
154 }; 154 };
155 155
156 tz_apps_mem: memory@90000000 { 156 tz_apps_mem: memory@90000000 {
157 no-map; 157 no-map;
158 reg = <0x90000000 0x50 158 reg = <0x90000000 0x500000>;
159 }; 159 };
160 160
161 llcc_tcm_mem: memory@15800000 161 llcc_tcm_mem: memory@15800000 {
162 no-map; 162 no-map;
163 reg = <0x15800000 0x80 163 reg = <0x15800000 0x800000>;
164 }; 164 };
165 }; 165 };
166 166
167 smp2p-mpss { 167 smp2p-mpss {
168 compatible = "qcom,smp2p"; 168 compatible = "qcom,smp2p";
169 qcom,smem = <435>, <428>; 169 qcom,smem = <435>, <428>;
170 interrupts = <GIC_SPI 113 IRQ_ 170 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
171 mboxes = <&apcs 14>; 171 mboxes = <&apcs 14>;
172 qcom,local-pid = <0>; 172 qcom,local-pid = <0>;
173 qcom,remote-pid = <1>; 173 qcom,remote-pid = <1>;
174 174
175 modem_smp2p_out: master-kernel 175 modem_smp2p_out: master-kernel {
176 qcom,entry-name = "mas 176 qcom,entry-name = "master-kernel";
177 #qcom,smem-state-cells 177 #qcom,smem-state-cells = <1>;
178 }; 178 };
179 179
180 modem_smp2p_in: slave-kernel { 180 modem_smp2p_in: slave-kernel {
181 qcom,entry-name = "sla 181 qcom,entry-name = "slave-kernel";
182 interrupt-controller; 182 interrupt-controller;
183 #interrupt-cells = <2> 183 #interrupt-cells = <2>;
184 }; 184 };
185 185
186 ipa_smp2p_out: ipa-ap-to-modem 186 ipa_smp2p_out: ipa-ap-to-modem {
187 qcom,entry-name = "ipa 187 qcom,entry-name = "ipa";
188 #qcom,smem-state-cells 188 #qcom,smem-state-cells = <1>;
189 }; 189 };
190 190
191 ipa_smp2p_in: ipa-modem-to-ap 191 ipa_smp2p_in: ipa-modem-to-ap {
192 qcom,entry-name = "ipa 192 qcom,entry-name = "ipa";
193 interrupt-controller; 193 interrupt-controller;
194 #interrupt-cells = <2> 194 #interrupt-cells = <2>;
195 }; 195 };
196 }; 196 };
197 197
198 soc: soc { 198 soc: soc {
199 #address-cells = <1>; 199 #address-cells = <1>;
200 #size-cells = <1>; 200 #size-cells = <1>;
201 ranges; 201 ranges;
202 compatible = "simple-bus"; 202 compatible = "simple-bus";
203 203
204 gcc: clock-controller@100000 { 204 gcc: clock-controller@100000 {
205 compatible = "qcom,gcc 205 compatible = "qcom,gcc-sdx65";
206 reg = <0x00100000 0x00 206 reg = <0x00100000 0x001f7400>;
207 clocks = <&rpmhcc RPMH !! 207 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
208 <&rpmhcc RPMH !! 208 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
209 <&sleep_clk>, <<
210 <&pcie_phy>, <<
211 <0>; <<
212 clock-names = "bi_tcxo <<
213 "bi_tcxo <<
214 "sleep_c <<
215 "pcie_pi <<
216 "usb3_ph <<
217 #power-domain-cells = 209 #power-domain-cells = <1>;
218 #clock-cells = <1>; 210 #clock-cells = <1>;
219 #reset-cells = <1>; 211 #reset-cells = <1>;
220 }; 212 };
221 213
222 blsp1_uart3: serial@831000 { 214 blsp1_uart3: serial@831000 {
223 compatible = "qcom,msm 215 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
224 reg = <0x00831000 0x20 216 reg = <0x00831000 0x200>;
225 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&gcc GCC_BLS 218 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
227 clock-names = "core", 219 clock-names = "core", "iface";
228 status = "disabled"; 220 status = "disabled";
229 }; 221 };
230 222
231 usb_hsphy: phy@ff4000 { 223 usb_hsphy: phy@ff4000 {
232 compatible = "qcom,sdx 224 compatible = "qcom,sdx65-usb-hs-phy",
233 "qcom,usb 225 "qcom,usb-snps-hs-7nm-phy";
234 reg = <0xff4000 0x120> 226 reg = <0xff4000 0x120>;
235 #phy-cells = <0>; 227 #phy-cells = <0>;
236 clocks = <&rpmhcc RPMH 228 clocks = <&rpmhcc RPMH_CXO_CLK>;
237 clock-names = "ref"; 229 clock-names = "ref";
238 resets = <&gcc GCC_QUS 230 resets = <&gcc GCC_QUSB2PHY_BCR>;
239 status = "disabled"; 231 status = "disabled";
240 }; 232 };
241 233
242 usb_qmpphy: phy@ff6000 { 234 usb_qmpphy: phy@ff6000 {
243 compatible = "qcom,sdx 235 compatible = "qcom,sdx65-qmp-usb3-uni-phy";
244 reg = <0x00ff6000 0x20 !! 236 reg = <0x00ff6000 0x1c8>;
>> 237 #address-cells = <1>;
>> 238 #size-cells = <1>;
>> 239 ranges;
245 240
246 clocks = <&gcc GCC_USB 241 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
247 <&gcc GCC_USB <<
248 <&gcc GCC_USB 242 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
249 <&gcc GCC_USB !! 243 <&gcc GCC_USB3_PRIM_CLKREF_EN>;
250 clock-names = "aux", !! 244 clock-names = "aux", "cfg_ahb", "ref";
251 "ref", <<
252 "cfg_ahb <<
253 "pipe"; <<
254 clock-output-names = " <<
255 #clock-cells = <0>; <<
256 #phy-cells = <0>; <<
257 245
258 resets = <&gcc GCC_USB !! 246 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
259 <&gcc GCC_USB !! 247 <&gcc GCC_USB3_PHY_BCR>;
260 reset-names = "phy", !! 248 reset-names = "phy", "common";
261 "phy_phy <<
262 249
263 status = "disabled"; 250 status = "disabled";
264 251
>> 252 usb_ssphy: phy@ff6200 {
>> 253 reg = <0x00ff6e00 0x160>,
>> 254 <0x00ff7000 0x1ec>,
>> 255 <0x00ff6200 0x1e00>;
>> 256 #phy-cells = <0>;
>> 257 #clock-cells = <0>;
>> 258 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
>> 259 clock-names = "pipe0";
>> 260 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 261 };
265 }; 262 };
266 263
267 system_noc: interconnect@16200 264 system_noc: interconnect@1620000 {
268 compatible = "qcom,sdx 265 compatible = "qcom,sdx65-system-noc";
269 reg = <0x01620000 0x31 266 reg = <0x01620000 0x31200>;
270 #interconnect-cells = 267 #interconnect-cells = <1>;
271 qcom,bcm-voters = <&ap 268 qcom,bcm-voters = <&apps_bcm_voter>;
272 }; 269 };
273 270
274 qpic_bam: dma-controller@1b040 271 qpic_bam: dma-controller@1b04000 {
275 compatible = "qcom,bam 272 compatible = "qcom,bam-v1.7.0";
276 reg = <0x01b04000 0x1c 273 reg = <0x01b04000 0x1c000>;
277 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&rpmhcc RPMH 275 clocks = <&rpmhcc RPMH_QPIC_CLK>;
279 clock-names = "bam_clk 276 clock-names = "bam_clk";
280 #dma-cells = <1>; 277 #dma-cells = <1>;
281 qcom,ee = <0>; 278 qcom,ee = <0>;
282 qcom,controlled-remote 279 qcom,controlled-remotely;
283 status = "disabled"; 280 status = "disabled";
284 }; 281 };
285 282
286 qpic_nand: nand-controller@1b3 283 qpic_nand: nand-controller@1b30000 {
287 compatible = "qcom,sdx 284 compatible = "qcom,sdx55-nand";
288 reg = <0x01b30000 0x10 285 reg = <0x01b30000 0x10000>;
289 #address-cells = <1>; 286 #address-cells = <1>;
290 #size-cells = <0>; 287 #size-cells = <0>;
291 clocks = <&rpmhcc RPMH 288 clocks = <&rpmhcc RPMH_QPIC_CLK>,
292 <&nand_clk_du 289 <&nand_clk_dummy>;
293 clock-names = "core", 290 clock-names = "core", "aon";
294 291
295 dmas = <&qpic_bam 0>, 292 dmas = <&qpic_bam 0>,
296 <&qpic_bam 1>, 293 <&qpic_bam 1>,
297 <&qpic_bam 2>; 294 <&qpic_bam 2>;
298 dma-names = "tx", "rx" 295 dma-names = "tx", "rx", "cmd";
299 status = "disabled"; 296 status = "disabled";
300 }; 297 };
301 298
302 pcie_ep: pcie-ep@1c00000 { 299 pcie_ep: pcie-ep@1c00000 {
303 compatible = "qcom,sdx 300 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
304 reg = <0x01c00000 0x30 301 reg = <0x01c00000 0x3000>,
305 <0x40000000 0xf1 302 <0x40000000 0xf1d>,
306 <0x40000f20 0xa8 303 <0x40000f20 0xa8>,
307 <0x40001000 0x10 304 <0x40001000 0x1000>,
308 <0x40200000 0x10 305 <0x40200000 0x100000>,
309 <0x01c03000 0x30 306 <0x01c03000 0x3000>;
310 reg-names = "parf", 307 reg-names = "parf",
311 "dbi", 308 "dbi",
312 "elbi", 309 "elbi",
313 "atu", 310 "atu",
314 "addr_spac 311 "addr_space",
315 "mmio"; 312 "mmio";
316 313
317 qcom,perst-regs = <&tc 314 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
318 315
319 clocks = <&gcc GCC_PCI 316 clocks = <&gcc GCC_PCIE_AUX_CLK>,
320 <&gcc GCC_PCI 317 <&gcc GCC_PCIE_CFG_AHB_CLK>,
321 <&gcc GCC_PCI 318 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
322 <&gcc GCC_PCI 319 <&gcc GCC_PCIE_SLV_AXI_CLK>,
323 <&gcc GCC_PCI 320 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
324 <&gcc GCC_PCI 321 <&gcc GCC_PCIE_SLEEP_CLK>,
325 <&gcc GCC_PCI 322 <&gcc GCC_PCIE_0_CLKREF_EN>;
326 clock-names = "aux", 323 clock-names = "aux",
327 "cfg", 324 "cfg",
328 "bus_mas 325 "bus_master",
329 "bus_sla 326 "bus_slave",
330 "slave_q 327 "slave_q2a",
331 "sleep", 328 "sleep",
332 "ref"; 329 "ref";
333 330
334 interrupts = <GIC_SPI 331 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 332 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "glo 333 interrupt-names = "global", "doorbell";
337 334
338 resets = <&gcc GCC_PCI 335 resets = <&gcc GCC_PCIE_BCR>;
339 reset-names = "core"; 336 reset-names = "core";
340 337
341 power-domains = <&gcc 338 power-domains = <&gcc PCIE_GDSC>;
342 339
343 phys = <&pcie_phy>; 340 phys = <&pcie_phy>;
344 phy-names = "pciephy"; 341 phy-names = "pciephy";
345 342
346 max-link-speed = <3>; 343 max-link-speed = <3>;
347 num-lanes = <2>; 344 num-lanes = <2>;
348 345
349 status = "disabled"; 346 status = "disabled";
350 }; 347 };
351 348
352 pcie_phy: phy@1c06000 { 349 pcie_phy: phy@1c06000 {
353 compatible = "qcom,sdx 350 compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
354 reg = <0x01c06000 0x20 351 reg = <0x01c06000 0x2000>;
355 352
356 clocks = <&gcc GCC_PCI 353 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
357 <&gcc GCC_PCI 354 <&gcc GCC_PCIE_CFG_AHB_CLK>,
358 <&gcc GCC_PCI 355 <&gcc GCC_PCIE_0_CLKREF_EN>,
359 <&gcc GCC_PCI 356 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
360 <&gcc GCC_PCI 357 <&gcc GCC_PCIE_PIPE_CLK>;
361 clock-names = "aux", 358 clock-names = "aux",
362 "cfg_ahb 359 "cfg_ahb",
363 "ref", 360 "ref",
364 "rchng", 361 "rchng",
365 "pipe"; 362 "pipe";
366 363
367 resets = <&gcc GCC_PCI 364 resets = <&gcc GCC_PCIE_PHY_BCR>;
368 reset-names = "phy"; 365 reset-names = "phy";
369 366
370 assigned-clocks = <&gc 367 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
371 assigned-clock-rates = 368 assigned-clock-rates = <100000000>;
372 369
373 power-domains = <&gcc 370 power-domains = <&gcc PCIE_GDSC>;
374 371
375 #clock-cells = <0>; 372 #clock-cells = <0>;
376 clock-output-names = " 373 clock-output-names = "pcie_pipe_clk";
377 374
378 #phy-cells = <0>; 375 #phy-cells = <0>;
379 376
380 status = "disabled"; 377 status = "disabled";
381 }; 378 };
382 379
383 tcsr_mutex: hwlock@1f40000 { 380 tcsr_mutex: hwlock@1f40000 {
384 compatible = "qcom,tcs 381 compatible = "qcom,tcsr-mutex";
385 reg = <0x01f40000 0x40 382 reg = <0x01f40000 0x40000>;
386 #hwlock-cells = <1>; 383 #hwlock-cells = <1>;
387 }; 384 };
388 385
389 tcsr: syscon@1fcb000 { 386 tcsr: syscon@1fcb000 {
390 compatible = "qcom,sdx 387 compatible = "qcom,sdx65-tcsr", "syscon";
391 reg = <0x01fc0000 0x10 388 reg = <0x01fc0000 0x1000>;
392 }; 389 };
393 390
394 ipa: ipa@3f40000 { 391 ipa: ipa@3f40000 {
395 compatible = "qcom,sdx 392 compatible = "qcom,sdx65-ipa";
396 393
397 reg = <0x03f40000 0x10 394 reg = <0x03f40000 0x10000>,
398 <0x03f50000 0x50 395 <0x03f50000 0x5000>,
399 <0x03e04000 0xfc 396 <0x03e04000 0xfc000>;
400 reg-names = "ipa-reg", 397 reg-names = "ipa-reg",
401 "ipa-share 398 "ipa-shared",
402 "gsi"; 399 "gsi";
403 400
404 interrupts-extended = 401 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
405 402 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
406 403 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
407 404 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
408 interrupt-names = "ipa 405 interrupt-names = "ipa",
409 "gsi 406 "gsi",
410 "ipa 407 "ipa-clock-query",
411 "ipa 408 "ipa-setup-ready";
412 409
413 iommus = <&apps_smmu 0 410 iommus = <&apps_smmu 0x5e0 0x0>,
414 <&apps_smmu 0 411 <&apps_smmu 0x5e2 0x0>;
415 412
416 clocks = <&rpmhcc RPMH 413 clocks = <&rpmhcc RPMH_IPA_CLK>;
417 clock-names = "core"; 414 clock-names = "core";
418 415
419 interconnects = <&syst 416 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
420 <&mem_ 417 <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
421 interconnect-names = " 418 interconnect-names = "memory",
422 " 419 "config";
423 420
424 qcom,smem-states = <&i 421 qcom,smem-states = <&ipa_smp2p_out 0>,
425 <&i 422 <&ipa_smp2p_out 1>;
426 qcom,smem-state-names 423 qcom,smem-state-names = "ipa-clock-enabled-valid",
427 424 "ipa-clock-enabled";
428 425
429 status = "disabled"; 426 status = "disabled";
430 }; 427 };
431 428
432 remoteproc_mpss: remoteproc@40 429 remoteproc_mpss: remoteproc@4080000 {
433 compatible = "qcom,sdx 430 compatible = "qcom,sdx55-mpss-pas";
434 reg = <0x04080000 0x40 431 reg = <0x04080000 0x4040>;
435 432
436 interrupts-extended = 433 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
437 434 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
438 435 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
439 436 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
440 437 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
441 438 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
442 interrupt-names = "wdo 439 interrupt-names = "wdog", "fatal", "ready", "handover",
443 "sto 440 "stop-ack", "shutdown-ack";
444 441
445 clocks = <&rpmhcc RPMH 442 clocks = <&rpmhcc RPMH_CXO_CLK>;
446 clock-names = "xo"; 443 clock-names = "xo";
447 444
448 power-domains = <&rpmh 445 power-domains = <&rpmhpd SDX65_CX>,
449 <&rpmh 446 <&rpmhpd SDX65_MSS>;
450 power-domain-names = " 447 power-domain-names = "cx", "mss";
451 448
452 qcom,smem-states = <&m 449 qcom,smem-states = <&modem_smp2p_out 0>;
453 qcom,smem-state-names 450 qcom,smem-state-names = "stop";
454 451
455 status = "disabled"; 452 status = "disabled";
456 453
457 glink-edge { 454 glink-edge {
458 interrupts = < 455 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
459 label = "mpss" 456 label = "mpss";
460 qcom,remote-pi 457 qcom,remote-pid = <1>;
461 mboxes = <&apc 458 mboxes = <&apcs 15>;
462 }; 459 };
463 }; 460 };
464 461
465 sdhc_1: mmc@8804000 { 462 sdhc_1: mmc@8804000 {
466 compatible = "qcom,sdx 463 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
467 reg = <0x08804000 0x10 464 reg = <0x08804000 0x1000>;
468 reg-names = "hc"; 465 reg-names = "hc";
469 interrupts = <GIC_SPI 466 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 467 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-names = "hc_ 468 interrupt-names = "hc_irq", "pwr_irq";
472 clocks = <&gcc GCC_SDC 469 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
473 <&gcc GCC_SDC 470 <&gcc GCC_SDCC1_APPS_CLK>;
474 clock-names = "iface", 471 clock-names = "iface", "core";
475 status = "disabled"; 472 status = "disabled";
476 }; 473 };
477 474
478 mem_noc: interconnect@9680000 475 mem_noc: interconnect@9680000 {
479 compatible = "qcom,sdx 476 compatible = "qcom,sdx65-mem-noc";
480 reg = <0x09680000 0x27 477 reg = <0x09680000 0x27200>;
481 #interconnect-cells = 478 #interconnect-cells = <1>;
482 qcom,bcm-voters = <&ap 479 qcom,bcm-voters = <&apps_bcm_voter>;
483 }; 480 };
484 481
485 usb: usb@a6f8800 { 482 usb: usb@a6f8800 {
486 compatible = "qcom,sdx 483 compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
487 reg = <0x0a6f8800 0x40 484 reg = <0x0a6f8800 0x400>;
488 #address-cells = <1>; 485 #address-cells = <1>;
489 #size-cells = <1>; 486 #size-cells = <1>;
490 ranges; 487 ranges;
491 488
492 clocks = <&gcc GCC_USB 489 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
493 <&gcc GCC_USB 490 <&gcc GCC_USB30_MASTER_CLK>,
494 <&gcc GCC_USB 491 <&gcc GCC_USB30_MSTR_AXI_CLK>,
495 <&gcc GCC_USB !! 492 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
496 <&gcc GCC_USB !! 493 <&gcc GCC_USB30_SLEEP_CLK>;
497 clock-names = "cfg_noc !! 494 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
498 "mock_ut !! 495 "sleep";
499 496
500 assigned-clocks = <&gc 497 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
501 <&gc 498 <&gcc GCC_USB30_MASTER_CLK>;
502 assigned-clock-rates = 499 assigned-clock-rates = <19200000>, <200000000>;
503 500
504 interrupts-extended = !! 501 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
505 !! 502 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
506 <<
507 503 <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
508 !! 504 <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
509 interrupt-names = "pwr !! 505 interrupt-names = "hs_phy_irq",
510 "hs_ !! 506 "ss_phy_irq",
511 "dp_ <<
512 "dm_ 507 "dm_hs_phy_irq",
513 "ss_ !! 508 "dp_hs_phy_irq";
514 509
515 power-domains = <&gcc 510 power-domains = <&gcc USB30_GDSC>;
516 511
517 resets = <&gcc GCC_USB 512 resets = <&gcc GCC_USB30_BCR>;
518 513
519 status = "disabled"; 514 status = "disabled";
520 515
521 usb_dwc3: usb@a600000 516 usb_dwc3: usb@a600000 {
522 compatible = " 517 compatible = "snps,dwc3";
523 reg = <0x0a600 518 reg = <0x0a600000 0xcd00>;
524 interrupts = < 519 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
525 iommus = <&app 520 iommus = <&apps_smmu 0x1a0 0x0>;
526 snps,dis_u2_su 521 snps,dis_u2_susphy_quirk;
527 snps,dis_enbls 522 snps,dis_enblslpm_quirk;
528 phys = <&usb_h !! 523 phys = <&usb_hsphy>, <&usb_ssphy>;
529 phy-names = "u 524 phy-names = "usb2-phy", "usb3-phy";
530 }; 525 };
531 }; 526 };
532 527
533 restart@c264000 { 528 restart@c264000 {
534 compatible = "qcom,psh 529 compatible = "qcom,pshold";
535 reg = <0x0c264000 0x10 530 reg = <0x0c264000 0x1000>;
536 }; 531 };
537 532
538 spmi_bus: spmi@c440000 { 533 spmi_bus: spmi@c440000 {
539 compatible = "qcom,spm 534 compatible = "qcom,spmi-pmic-arb";
540 reg = <0xc440000 0xd00 535 reg = <0xc440000 0xd00>,
541 <0xc600000 0x2 536 <0xc600000 0x2000000>,
542 <0xe600000 0x1 537 <0xe600000 0x100000>,
543 <0xe700000 0xa 538 <0xe700000 0xa0000>,
544 <0xc40a000 0x2 539 <0xc40a000 0x26000>;
545 reg-names = "core", "c 540 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
546 interrupts-extended = 541 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "per 542 interrupt-names = "periph_irq";
548 interrupt-controller; 543 interrupt-controller;
549 #interrupt-cells = <4> 544 #interrupt-cells = <4>;
550 #address-cells = <2>; 545 #address-cells = <2>;
551 #size-cells = <0>; 546 #size-cells = <0>;
552 qcom,channel = <0>; 547 qcom,channel = <0>;
553 qcom,ee = <0>; 548 qcom,ee = <0>;
554 }; 549 };
555 550
556 tlmm: pinctrl@f100000 { 551 tlmm: pinctrl@f100000 {
557 compatible = "qcom,sdx 552 compatible = "qcom,sdx65-tlmm";
558 reg = <0xf100000 0x300 553 reg = <0xf100000 0x300000>;
559 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
560 gpio-controller; 555 gpio-controller;
561 #gpio-cells = <2>; 556 #gpio-cells = <2>;
562 gpio-ranges = <&tlmm 0 557 gpio-ranges = <&tlmm 0 0 109>;
563 interrupt-controller; 558 interrupt-controller;
564 interrupt-parent = <&i 559 interrupt-parent = <&intc>;
565 #interrupt-cells = <2> 560 #interrupt-cells = <2>;
566 }; 561 };
567 562
568 pdc: interrupt-controller@b210 563 pdc: interrupt-controller@b210000 {
569 compatible = "qcom,sdx 564 compatible = "qcom,sdx65-pdc", "qcom,pdc";
570 reg = <0xb210000 0x100 565 reg = <0xb210000 0x10000>;
571 qcom,pdc-ranges = <0 1 566 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
572 #interrupt-cells = <2> 567 #interrupt-cells = <2>;
573 interrupt-parent = <&i 568 interrupt-parent = <&intc>;
574 interrupt-controller; 569 interrupt-controller;
575 }; 570 };
576 571
577 sram@1468f000 { 572 sram@1468f000 {
578 compatible = "qcom,sdx 573 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
579 reg = <0x1468f000 0x10 574 reg = <0x1468f000 0x1000>;
580 ranges = <0x0 0x1468f0 575 ranges = <0x0 0x1468f000 0x1000>;
581 #address-cells = <1>; 576 #address-cells = <1>;
582 #size-cells = <1>; 577 #size-cells = <1>;
583 578
584 pil-reloc@94c { 579 pil-reloc@94c {
585 compatible = " 580 compatible = "qcom,pil-reloc-info";
586 reg = <0x94c 0 581 reg = <0x94c 0xc8>;
587 }; 582 };
588 }; 583 };
589 584
590 apps_smmu: iommu@15000000 { 585 apps_smmu: iommu@15000000 {
591 compatible = "qcom,sdx 586 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
592 reg = <0x15000000 0x40 587 reg = <0x15000000 0x40000>;
593 #iommu-cells = <2>; 588 #iommu-cells = <2>;
594 #global-interrupts = < 589 #global-interrupts = <1>;
595 interrupts = <GIC_S 590 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_S 591 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_S 592 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_S 593 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_S 594 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_S 595 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_S 596 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_S 597 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_S 598 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_S 599 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_S 600 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_S 601 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_S 602 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_S 603 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_S 604 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_S 605 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_S 606 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_S 607 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_S 608 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_S 609 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_S 610 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_S 611 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_S 612 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_S 613 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_S 614 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_S 615 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_S 616 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_S 617 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_S 618 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_S 619 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_S 620 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_S 621 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_S 622 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
628 }; 623 };
629 624
630 intc: interrupt-controller@178 625 intc: interrupt-controller@17800000 {
631 compatible = "qcom,msm 626 compatible = "qcom,msm-qgic2";
632 interrupt-controller; 627 interrupt-controller;
633 interrupt-parent = <&i 628 interrupt-parent = <&intc>;
634 #interrupt-cells = <3> 629 #interrupt-cells = <3>;
635 reg = <0x17800000 0x10 630 reg = <0x17800000 0x1000>,
636 <0x17802000 0x10 631 <0x17802000 0x1000>;
637 }; 632 };
638 633
639 a7pll: clock@17808000 { 634 a7pll: clock@17808000 {
640 compatible = "qcom,sdx 635 compatible = "qcom,sdx55-a7pll";
641 reg = <0x17808000 0x10 636 reg = <0x17808000 0x1000>;
642 clocks = <&rpmhcc RPMH 637 clocks = <&rpmhcc RPMH_CXO_CLK>;
643 clock-names = "bi_tcxo 638 clock-names = "bi_tcxo";
644 #clock-cells = <0>; 639 #clock-cells = <0>;
645 }; 640 };
646 641
647 apcs: mailbox@17810000 { 642 apcs: mailbox@17810000 {
648 compatible = "qcom,sdx 643 compatible = "qcom,sdx55-apcs-gcc", "syscon";
649 reg = <0x17810000 0x20 644 reg = <0x17810000 0x2000>;
650 #mbox-cells = <1>; 645 #mbox-cells = <1>;
651 clocks = <&rpmhcc RPMH 646 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
652 clock-names = "ref", " 647 clock-names = "ref", "pll", "aux";
653 #clock-cells = <0>; 648 #clock-cells = <0>;
654 }; 649 };
655 650
656 watchdog@17817000 { 651 watchdog@17817000 {
657 compatible = "qcom,aps 652 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
658 reg = <0x17817000 0x10 653 reg = <0x17817000 0x1000>;
659 clocks = <&sleep_clk>; 654 clocks = <&sleep_clk>;
660 }; 655 };
661 656
662 timer@17820000 { 657 timer@17820000 {
663 #address-cells = <1>; 658 #address-cells = <1>;
664 #size-cells = <1>; 659 #size-cells = <1>;
665 ranges; 660 ranges;
666 compatible = "arm,armv 661 compatible = "arm,armv7-timer-mem";
667 reg = <0x17820000 0x10 662 reg = <0x17820000 0x1000>;
668 clock-frequency = <192 663 clock-frequency = <19200000>;
669 664
670 frame@17821000 { 665 frame@17821000 {
671 frame-number = 666 frame-number = <0>;
672 interrupts = < !! 667 interrupts = <GIC_SPI 7 0x4>,
673 < !! 668 <GIC_SPI 6 0x4>;
674 reg = <0x17821 669 reg = <0x17821000 0x1000>,
675 <0x17822 670 <0x17822000 0x1000>;
676 }; 671 };
677 672
678 frame@17823000 { 673 frame@17823000 {
679 frame-number = 674 frame-number = <1>;
680 interrupts = < !! 675 interrupts = <GIC_SPI 8 0x4>;
681 reg = <0x17823 676 reg = <0x17823000 0x1000>;
682 status = "disa 677 status = "disabled";
683 }; 678 };
684 679
685 frame@17824000 { 680 frame@17824000 {
686 frame-number = 681 frame-number = <2>;
687 interrupts = < !! 682 interrupts = <GIC_SPI 9 0x4>;
688 reg = <0x17824 683 reg = <0x17824000 0x1000>;
689 status = "disa 684 status = "disabled";
690 }; 685 };
691 686
692 frame@17825000 { 687 frame@17825000 {
693 frame-number = 688 frame-number = <3>;
694 interrupts = < !! 689 interrupts = <GIC_SPI 10 0x4>;
695 reg = <0x17825 690 reg = <0x17825000 0x1000>;
696 status = "disa 691 status = "disabled";
697 }; 692 };
698 693
699 frame@17826000 { 694 frame@17826000 {
700 frame-number = 695 frame-number = <4>;
701 interrupts = < !! 696 interrupts = <GIC_SPI 11 0x4>;
702 reg = <0x17826 697 reg = <0x17826000 0x1000>;
703 status = "disa 698 status = "disabled";
704 }; 699 };
705 700
706 frame@17827000 { 701 frame@17827000 {
707 frame-number = 702 frame-number = <5>;
708 interrupts = < !! 703 interrupts = <GIC_SPI 12 0x4>;
709 reg = <0x17827 704 reg = <0x17827000 0x1000>;
710 status = "disa 705 status = "disabled";
711 }; 706 };
712 707
713 frame@17828000 { 708 frame@17828000 {
714 frame-number = 709 frame-number = <6>;
715 interrupts = < !! 710 interrupts = <GIC_SPI 13 0x4>;
716 reg = <0x17828 711 reg = <0x17828000 0x1000>;
717 status = "disa 712 status = "disabled";
718 }; 713 };
719 714
720 frame@17829000 { 715 frame@17829000 {
721 frame-number = 716 frame-number = <7>;
722 interrupts = < !! 717 interrupts = <GIC_SPI 14 0x4>;
723 reg = <0x17829 718 reg = <0x17829000 0x1000>;
724 status = "disa 719 status = "disabled";
725 }; 720 };
726 }; 721 };
727 722
728 apps_rsc: rsc@17830000 { 723 apps_rsc: rsc@17830000 {
729 label = "apps_rsc"; 724 label = "apps_rsc";
730 compatible = "qcom,rpm 725 compatible = "qcom,rpmh-rsc";
731 reg = <0x17830000 0x10 726 reg = <0x17830000 0x10000>,
732 <0x17840000 0x1000 727 <0x17840000 0x10000>;
733 reg-names = "drv-0", " 728 reg-names = "drv-0", "drv-1";
734 interrupts = <GIC_SPI 729 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 17 730 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
736 qcom,tcs-offset = <0xd 731 qcom,tcs-offset = <0xd00>;
737 qcom,drv-id = <1>; 732 qcom,drv-id = <1>;
738 qcom,tcs-config = <ACT 733 qcom,tcs-config = <ACTIVE_TCS 2>,
739 <SLEEP_TCS 2 734 <SLEEP_TCS 2>,
740 <WAKE_TCS 2 735 <WAKE_TCS 2>,
741 <CONTROL_TCS 1 736 <CONTROL_TCS 1>;
742 737
743 rpmhcc: clock-controll 738 rpmhcc: clock-controller {
744 compatible = " 739 compatible = "qcom,sdx65-rpmh-clk";
745 #clock-cells = 740 #clock-cells = <1>;
746 clock-names = 741 clock-names = "xo";
747 clocks = <&xo_ 742 clocks = <&xo_board>;
748 }; 743 };
749 744
750 rpmhpd: power-controll 745 rpmhpd: power-controller {
751 compatible = " 746 compatible = "qcom,sdx65-rpmhpd";
752 #power-domain- 747 #power-domain-cells = <1>;
753 operating-poin 748 operating-points-v2 = <&rpmhpd_opp_table>;
754 749
755 rpmhpd_opp_tab 750 rpmhpd_opp_table: opp-table {
756 compat 751 compatible = "operating-points-v2";
757 752
758 rpmhpd 753 rpmhpd_opp_ret: opp1 {
759 754 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
760 }; 755 };
761 756
762 rpmhpd 757 rpmhpd_opp_min_svs: opp2 {
763 758 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
764 }; 759 };
765 760
766 rpmhpd 761 rpmhpd_opp_low_svs: opp3 {
767 762 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
768 }; 763 };
769 764
770 rpmhpd 765 rpmhpd_opp_svs: opp4 {
771 766 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
772 }; 767 };
773 768
774 rpmhpd 769 rpmhpd_opp_svs_l1: opp5 {
775 770 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
776 }; 771 };
777 772
778 rpmhpd 773 rpmhpd_opp_nom: opp6 {
779 774 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
780 }; 775 };
781 776
782 rpmhpd 777 rpmhpd_opp_nom_l1: opp7 {
783 778 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
784 }; 779 };
785 780
786 rpmhpd 781 rpmhpd_opp_nom_l2: opp8 {
787 782 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
788 }; 783 };
789 784
790 rpmhpd 785 rpmhpd_opp_turbo: opp9 {
791 786 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
792 }; 787 };
793 788
794 rpmhpd 789 rpmhpd_opp_turbo_l1: opp10 {
795 790 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
796 }; 791 };
797 }; 792 };
798 }; 793 };
799 794
800 apps_bcm_voter: bcm-vo 795 apps_bcm_voter: bcm-voter {
801 compatible = " 796 compatible = "qcom,bcm-voter";
802 }; 797 };
803 798
804 }; 799 };
805 }; 800 };
806 801
807 timer { 802 timer {
808 compatible = "arm,armv7-timer" 803 compatible = "arm,armv7-timer";
809 interrupts = <GIC_PPI 13 (GIC_ !! 804 interrupts = <1 13 0xf08>,
810 <GIC_PPI 12 (GIC_ !! 805 <1 12 0xf08>,
811 <GIC_PPI 10 (GIC_ !! 806 <1 10 0xf08>,
812 <GIC_PPI 11 (GIC_ !! 807 <1 11 0xf08>;
813 clock-frequency = <19200000>; 808 clock-frequency = <19200000>;
814 }; 809 };
815 }; 810 };
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