1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2 /* 2 /*
3 * Copyright (c) 2017-2019 Andreas Färber 3 * Copyright (c) 2017-2019 Andreas Färber
4 */ 4 */
5 5
6 /memreserve/ 0x00000000 0x0000a800; /* boot co 6 /memreserve/ 0x00000000 0x0000a800; /* boot code */
7 /memreserve/ 0x0000a800 0x000f5800; 7 /memreserve/ 0x0000a800 0x000f5800;
8 /memreserve/ 0x17fff000 0x00001000; 8 /memreserve/ 0x17fff000 0x00001000;
9 9
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h> 11 #include <dt-bindings/reset/realtek,rtd1195.h>
12 12
13 / { 13 / {
14 compatible = "realtek,rtd1195"; 14 compatible = "realtek,rtd1195";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 18
19 cpus { 19 cpus {
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <0>; 21 #size-cells = <0>;
22 22
23 cpu0: cpu@0 { 23 cpu0: cpu@0 {
24 device_type = "cpu"; 24 device_type = "cpu";
25 compatible = "arm,cort 25 compatible = "arm,cortex-a7";
26 reg = <0x0>; 26 reg = <0x0>;
27 clock-frequency = <100 27 clock-frequency = <1000000000>;
28 }; 28 };
29 29
30 cpu1: cpu@1 { 30 cpu1: cpu@1 {
31 device_type = "cpu"; 31 device_type = "cpu";
32 compatible = "arm,cort 32 compatible = "arm,cortex-a7";
33 reg = <0x1>; 33 reg = <0x1>;
34 clock-frequency = <100 34 clock-frequency = <1000000000>;
35 }; 35 };
36 }; 36 };
37 37
38 reserved-memory { 38 reserved-memory {
39 #address-cells = <1>; 39 #address-cells = <1>;
40 #size-cells = <1>; 40 #size-cells = <1>;
41 ranges; 41 ranges;
42 42
43 rpc_comm: rpc@b000 { 43 rpc_comm: rpc@b000 {
44 reg = <0x0000b000 0x10 44 reg = <0x0000b000 0x1000>;
45 }; 45 };
46 46
47 audio@1b00000 { 47 audio@1b00000 {
48 reg = <0x01b00000 0x40 48 reg = <0x01b00000 0x400000>;
49 }; 49 };
50 50
51 rpc_ringbuf: rpc@1ffe000 { 51 rpc_ringbuf: rpc@1ffe000 {
52 reg = <0x01ffe000 0x40 52 reg = <0x01ffe000 0x4000>;
53 }; 53 };
54 54
55 secure@10000000 { 55 secure@10000000 {
56 reg = <0x10000000 0x10 56 reg = <0x10000000 0x100000>;
57 no-map; 57 no-map;
58 }; 58 };
59 }; 59 };
60 60
61 arm-pmu { 61 arm-pmu {
62 compatible = "arm,cortex-a7-pm 62 compatible = "arm,cortex-a7-pmu";
63 interrupts = <GIC_SPI 48 IRQ_T 63 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 49 IRQ_T 64 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&cpu0>, 65 interrupt-affinity = <&cpu0>, <&cpu1>;
66 }; 66 };
67 67
68 timer { 68 timer {
69 compatible = "arm,armv7-timer" 69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 70 interrupts = <GIC_PPI 13
71 (GIC_CPU_MASK_SIMPLE(2 71 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 14 72 <GIC_PPI 14
73 (GIC_CPU_MASK_SIMPLE(2 73 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 74 <GIC_PPI 11
75 (GIC_CPU_MASK_SIMPLE(2 75 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 10 76 <GIC_PPI 10
77 (GIC_CPU_MASK_SIMPLE(2 77 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <27000000>; 78 clock-frequency = <27000000>;
79 }; 79 };
80 80
81 osc27M: osc { 81 osc27M: osc {
82 compatible = "fixed-clock"; 82 compatible = "fixed-clock";
83 clock-frequency = <27000000>; 83 clock-frequency = <27000000>;
84 #clock-cells = <0>; 84 #clock-cells = <0>;
85 clock-output-names = "osc27M"; 85 clock-output-names = "osc27M";
86 }; 86 };
87 87
88 soc { 88 soc {
89 compatible = "simple-bus"; 89 compatible = "simple-bus";
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <1>; 91 #size-cells = <1>;
92 ranges = <0x00000000 0x0000000 92 ranges = <0x00000000 0x00000000 0x0000a800>,
93 <0x18000000 0x1800000 93 <0x18000000 0x18000000 0x00070000>,
94 <0x18100000 0x1810000 94 <0x18100000 0x18100000 0x01000000>,
95 <0x80000000 0x8000000 95 <0x80000000 0x80000000 0x80000000>;
96 96
97 rbus: bus@18000000 { 97 rbus: bus@18000000 {
98 compatible = "simple-b 98 compatible = "simple-bus";
99 reg = <0x18000000 0x70 99 reg = <0x18000000 0x70000>;
100 #address-cells = <1>; 100 #address-cells = <1>;
101 #size-cells = <1>; 101 #size-cells = <1>;
102 ranges = <0x0 0x180000 102 ranges = <0x0 0x18000000 0x70000>;
103 103
104 crt: syscon@0 { 104 crt: syscon@0 {
105 compatible = " 105 compatible = "syscon", "simple-mfd";
106 reg = <0x0 0x1 106 reg = <0x0 0x1000>;
107 reg-io-width = 107 reg-io-width = <4>;
108 #address-cells 108 #address-cells = <1>;
109 #size-cells = 109 #size-cells = <1>;
110 ranges = <0x0 110 ranges = <0x0 0x0 0x1000>;
111 }; 111 };
112 112
113 iso: syscon@7000 { 113 iso: syscon@7000 {
114 compatible = " 114 compatible = "syscon", "simple-mfd";
115 reg = <0x7000 115 reg = <0x7000 0x1000>;
116 reg-io-width = 116 reg-io-width = <4>;
117 #address-cells 117 #address-cells = <1>;
118 #size-cells = 118 #size-cells = <1>;
119 ranges = <0x0 119 ranges = <0x0 0x7000 0x1000>;
120 }; 120 };
121 121
122 sb2: syscon@1a000 { 122 sb2: syscon@1a000 {
123 compatible = " 123 compatible = "syscon", "simple-mfd";
124 reg = <0x1a000 124 reg = <0x1a000 0x1000>;
125 reg-io-width = 125 reg-io-width = <4>;
126 #address-cells 126 #address-cells = <1>;
127 #size-cells = 127 #size-cells = <1>;
128 ranges = <0x0 128 ranges = <0x0 0x1a000 0x1000>;
129 }; 129 };
130 130
131 misc: syscon@1b000 { 131 misc: syscon@1b000 {
132 compatible = " 132 compatible = "syscon", "simple-mfd";
133 reg = <0x1b000 133 reg = <0x1b000 0x1000>;
134 reg-io-width = 134 reg-io-width = <4>;
135 #address-cells 135 #address-cells = <1>;
136 #size-cells = 136 #size-cells = <1>;
137 ranges = <0x0 137 ranges = <0x0 0x1b000 0x1000>;
138 }; 138 };
139 139
140 scpu_wrapper: syscon@1 140 scpu_wrapper: syscon@1d000 {
141 compatible = " 141 compatible = "syscon", "simple-mfd";
142 reg = <0x1d000 142 reg = <0x1d000 0x1000>;
143 reg-io-width = 143 reg-io-width = <4>;
144 #address-cells 144 #address-cells = <1>;
145 #size-cells = 145 #size-cells = <1>;
146 ranges = <0x0 146 ranges = <0x0 0x1d000 0x1000>;
147 }; 147 };
148 }; 148 };
149 149
150 gic: interrupt-controller@ff01 150 gic: interrupt-controller@ff011000 {
151 compatible = "arm,cort 151 compatible = "arm,cortex-a7-gic";
152 reg = <0xff011000 0x10 152 reg = <0xff011000 0x1000>,
153 <0xff012000 0x20 153 <0xff012000 0x2000>,
154 <0xff014000 0x20 154 <0xff014000 0x2000>,
155 <0xff016000 0x20 155 <0xff016000 0x2000>;
156 interrupts = <GIC_PPI 156 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
157 interrupt-controller; 157 interrupt-controller;
158 #interrupt-cells = <3> 158 #interrupt-cells = <3>;
159 }; 159 };
160 }; 160 };
161 }; 161 };
162 162
163 &crt { 163 &crt {
164 reset1: reset-controller@0 { 164 reset1: reset-controller@0 {
165 compatible = "snps,dw-low-rese 165 compatible = "snps,dw-low-reset";
166 reg = <0x0 0x4>; 166 reg = <0x0 0x4>;
167 #reset-cells = <1>; 167 #reset-cells = <1>;
168 }; 168 };
169 169
170 reset2: reset-controller@4 { 170 reset2: reset-controller@4 {
171 compatible = "snps,dw-low-rese 171 compatible = "snps,dw-low-reset";
172 reg = <0x4 0x4>; 172 reg = <0x4 0x4>;
173 #reset-cells = <1>; 173 #reset-cells = <1>;
174 }; 174 };
175 175
176 reset3: reset-controller@8 { 176 reset3: reset-controller@8 {
177 compatible = "snps,dw-low-rese 177 compatible = "snps,dw-low-reset";
178 reg = <0x8 0x4>; 178 reg = <0x8 0x4>;
179 #reset-cells = <1>; 179 #reset-cells = <1>;
180 }; 180 };
181 }; 181 };
182 182
183 &iso { 183 &iso {
184 iso_reset: reset-controller@88 { 184 iso_reset: reset-controller@88 {
185 compatible = "snps,dw-low-rese 185 compatible = "snps,dw-low-reset";
186 reg = <0x88 0x4>; 186 reg = <0x88 0x4>;
187 #reset-cells = <1>; 187 #reset-cells = <1>;
188 }; 188 };
189 189
190 wdt: watchdog@680 { 190 wdt: watchdog@680 {
191 compatible = "realtek,rtd1295- 191 compatible = "realtek,rtd1295-watchdog";
192 reg = <0x680 0x100>; 192 reg = <0x680 0x100>;
193 clocks = <&osc27M>; 193 clocks = <&osc27M>;
194 }; 194 };
195 195
196 uart0: serial@800 { 196 uart0: serial@800 {
197 compatible = "snps,dw-apb-uart 197 compatible = "snps,dw-apb-uart";
198 reg = <0x800 0x400>; 198 reg = <0x800 0x400>;
199 reg-shift = <2>; 199 reg-shift = <2>;
200 reg-io-width = <4>; 200 reg-io-width = <4>;
201 resets = <&iso_reset RTD1195_I 201 resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
202 clock-frequency = <27000000>; 202 clock-frequency = <27000000>;
203 status = "disabled"; 203 status = "disabled";
204 }; 204 };
205 }; 205 };
206 206
207 &misc { 207 &misc {
208 uart1: serial@200 { 208 uart1: serial@200 {
209 compatible = "snps,dw-apb-uart 209 compatible = "snps,dw-apb-uart";
210 reg = <0x200 0x100>; 210 reg = <0x200 0x100>;
211 reg-shift = <2>; 211 reg-shift = <2>;
212 reg-io-width = <4>; 212 reg-io-width = <4>;
213 resets = <&reset2 RTD1195_RSTN 213 resets = <&reset2 RTD1195_RSTN_UR1>;
214 clock-frequency = <27000000>; 214 clock-frequency = <27000000>;
215 status = "disabled"; 215 status = "disabled";
216 }; 216 };
217 }; 217 };
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