1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0 2 /* 2 /* 3 * Device Tree Source for the GR-Peach board 3 * Device Tree Source for the GR-Peach board 4 * 4 * 5 * Copyright (C) 2017 Jacopo Mondi <jacopo+rene 5 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * Copyright (C) 2016 Renesas Electronics 6 * Copyright (C) 2016 Renesas Electronics 7 */ 7 */ 8 8 9 /dts-v1/; 9 /dts-v1/; 10 #include "r7s72100.dtsi" 10 #include "r7s72100.dtsi" 11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/pinctrl/r7s72100-pinctrl 12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 13 13 14 / { 14 / { 15 model = "GR-Peach"; 15 model = "GR-Peach"; 16 compatible = "renesas,gr-peach", "rene 16 compatible = "renesas,gr-peach", "renesas,r7s72100"; 17 17 18 aliases { 18 aliases { 19 serial0 = &scif2; 19 serial0 = &scif2; 20 }; 20 }; 21 21 22 chosen { 22 chosen { 23 bootargs = "ignore_loglevel rw 23 bootargs = "ignore_loglevel rw root=/dev/mtdblock0"; 24 stdout-path = "serial0:115200n 24 stdout-path = "serial0:115200n8"; 25 }; 25 }; 26 26 27 memory@20000000 { 27 memory@20000000 { 28 device_type = "memory"; 28 device_type = "memory"; 29 reg = <0x20000000 0x00a00000>; 29 reg = <0x20000000 0x00a00000>; 30 }; 30 }; 31 31 32 flash@18000000 { 32 flash@18000000 { 33 compatible = "mtd-rom"; 33 compatible = "mtd-rom"; 34 reg = <0x18000000 0x00800000>; 34 reg = <0x18000000 0x00800000>; 35 bank-width = <4>; 35 bank-width = <4>; 36 device-width = <1>; 36 device-width = <1>; 37 37 38 clocks = <&mstp9_clks R7S72100 38 clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; 39 power-domains = <&cpg_clocks>; 39 power-domains = <&cpg_clocks>; 40 40 41 #address-cells = <1>; 41 #address-cells = <1>; 42 #size-cells = <1>; 42 #size-cells = <1>; 43 43 44 rootfs@600000 { 44 rootfs@600000 { 45 label = "rootfs"; 45 label = "rootfs"; 46 reg = <0x00600000 0x00 46 reg = <0x00600000 0x00200000>; 47 }; 47 }; 48 }; 48 }; 49 49 50 leds { 50 leds { 51 status = "okay"; 51 status = "okay"; 52 compatible = "gpio-leds"; 52 compatible = "gpio-leds"; 53 53 54 led1 { 54 led1 { 55 gpios = <&port6 12 GPI 55 gpios = <&port6 12 GPIO_ACTIVE_HIGH>; 56 }; 56 }; 57 }; 57 }; 58 }; 58 }; 59 59 60 &pinctrl { 60 &pinctrl { 61 scif2_pins: serial2 { 61 scif2_pins: serial2 { 62 /* P6_2 as RxD2; P6_3 as TxD2 62 /* P6_2 as RxD2; P6_3 as TxD2 */ 63 pinmux = <RZA1_PINMUX(6, 2, 7) 63 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>; 64 }; 64 }; 65 65 66 ether_pins: ether { 66 ether_pins: ether { 67 /* Ethernet on Ports 1,3,5,10 67 /* Ethernet on Ports 1,3,5,10 */ 68 pinmux = <RZA1_PINMUX(1, 14, 4 68 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */ 69 <RZA1_PINMUX(3, 0, 2) 69 <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */ 70 <RZA1_PINMUX(3, 3, 2) 70 <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */ 71 <RZA1_PINMUX(3, 4, 2) 71 <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */ 72 <RZA1_PINMUX(3, 5, 2) 72 <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */ 73 <RZA1_PINMUX(3, 6, 2) 73 <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */ 74 <RZA1_PINMUX(5, 9, 2) 74 <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */ 75 <RZA1_PINMUX(10, 1, 4 75 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */ 76 <RZA1_PINMUX(10, 2, 4 76 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */ 77 <RZA1_PINMUX(10, 3, 4 77 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */ 78 <RZA1_PINMUX(10, 4, 4 78 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */ 79 <RZA1_PINMUX(10, 5, 4 79 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */ 80 <RZA1_PINMUX(10, 6, 4 80 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */ 81 <RZA1_PINMUX(10, 7, 4 81 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */ 82 <RZA1_PINMUX(10, 8, 4 82 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */ 83 <RZA1_PINMUX(10, 9, 4 83 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */ 84 <RZA1_PINMUX(10, 10, 84 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */ 85 <RZA1_PINMUX(10, 11, 85 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */ 86 }; 86 }; 87 }; 87 }; 88 88 89 &extal_clk { 89 &extal_clk { 90 clock-frequency = <13333000>; 90 clock-frequency = <13333000>; 91 }; 91 }; 92 92 93 &usb_x1_clk { 93 &usb_x1_clk { 94 clock-frequency = <48000000>; 94 clock-frequency = <48000000>; 95 }; 95 }; 96 96 97 &mtu2 { 97 &mtu2 { 98 status = "okay"; 98 status = "okay"; 99 }; 99 }; 100 100 101 &ostm0 { 101 &ostm0 { 102 status = "okay"; 102 status = "okay"; 103 }; 103 }; 104 104 105 &ostm1 { 105 &ostm1 { 106 status = "okay"; 106 status = "okay"; 107 }; 107 }; 108 108 109 &scif2 { 109 &scif2 { 110 pinctrl-names = "default"; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&scif2_pins>; 111 pinctrl-0 = <&scif2_pins>; 112 112 113 status = "okay"; 113 status = "okay"; 114 }; 114 }; 115 115 116 ðer { 116 ðer { 117 pinctrl-names = "default"; 117 pinctrl-names = "default"; 118 pinctrl-0 = <ðer_pins>; 118 pinctrl-0 = <ðer_pins>; 119 119 120 status = "okay"; 120 status = "okay"; 121 121 122 renesas,no-ether-link; 122 renesas,no-ether-link; 123 phy-handle = <&phy0>; 123 phy-handle = <&phy0>; 124 124 125 phy0: ethernet-phy@0 { 125 phy0: ethernet-phy@0 { 126 compatible = "ethernet-phy-id0 126 compatible = "ethernet-phy-id0007.c0f0", 127 "ethernet-phy-iee 127 "ethernet-phy-ieee802.3-c22"; 128 reg = <0>; 128 reg = <0>; 129 129 130 reset-gpios = <&port4 2 GPIO_A 130 reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; 131 reset-delay-us = <5>; 131 reset-delay-us = <5>; 132 }; 132 }; 133 }; 133 };
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