1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the GR-Peach board 3 * Device Tree Source for the GR-Peach board
4 * 4 *
5 * Copyright (C) 2017 Jacopo Mondi <jacopo+rene 5 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics 6 * Copyright (C) 2016 Renesas Electronics
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 #include "r7s72100.dtsi" 10 #include "r7s72100.dtsi"
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/r7s72100-pinctrl 12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
13 13
14 / { 14 / {
15 model = "GR-Peach"; 15 model = "GR-Peach";
16 compatible = "renesas,gr-peach", "rene 16 compatible = "renesas,gr-peach", "renesas,r7s72100";
17 17
18 aliases { 18 aliases {
19 serial0 = &scif2; 19 serial0 = &scif2;
20 }; 20 };
21 21
22 chosen { 22 chosen {
23 bootargs = "ignore_loglevel rw 23 bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
24 stdout-path = "serial0:115200n 24 stdout-path = "serial0:115200n8";
25 }; 25 };
26 26
27 memory@20000000 { 27 memory@20000000 {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x20000000 0x00a00000>; 29 reg = <0x20000000 0x00a00000>;
30 }; 30 };
31 31
>> 32 lbsc {
>> 33 #address-cells = <1>;
>> 34 #size-cells = <1>;
>> 35 };
>> 36
32 flash@18000000 { 37 flash@18000000 {
33 compatible = "mtd-rom"; 38 compatible = "mtd-rom";
>> 39 probe-type = "map_rom";
34 reg = <0x18000000 0x00800000>; 40 reg = <0x18000000 0x00800000>;
35 bank-width = <4>; 41 bank-width = <4>;
36 device-width = <1>; 42 device-width = <1>;
37 43
38 clocks = <&mstp9_clks R7S72100 44 clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
39 power-domains = <&cpg_clocks>; 45 power-domains = <&cpg_clocks>;
40 46
41 #address-cells = <1>; 47 #address-cells = <1>;
42 #size-cells = <1>; 48 #size-cells = <1>;
43 49
44 rootfs@600000 { 50 rootfs@600000 {
45 label = "rootfs"; 51 label = "rootfs";
46 reg = <0x00600000 0x00 52 reg = <0x00600000 0x00200000>;
47 }; 53 };
48 }; 54 };
49 55
50 leds { 56 leds {
51 status = "okay"; 57 status = "okay";
52 compatible = "gpio-leds"; 58 compatible = "gpio-leds";
53 59
54 led1 { 60 led1 {
55 gpios = <&port6 12 GPI 61 gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
56 }; 62 };
57 }; 63 };
58 }; 64 };
59 65
60 &pinctrl { 66 &pinctrl {
61 scif2_pins: serial2 { 67 scif2_pins: serial2 {
62 /* P6_2 as RxD2; P6_3 as TxD2 68 /* P6_2 as RxD2; P6_3 as TxD2 */
63 pinmux = <RZA1_PINMUX(6, 2, 7) 69 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
64 }; 70 };
65 71
66 ether_pins: ether { 72 ether_pins: ether {
67 /* Ethernet on Ports 1,3,5,10 73 /* Ethernet on Ports 1,3,5,10 */
68 pinmux = <RZA1_PINMUX(1, 14, 4 74 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
69 <RZA1_PINMUX(3, 0, 2) 75 <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
70 <RZA1_PINMUX(3, 3, 2) 76 <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
71 <RZA1_PINMUX(3, 4, 2) 77 <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
72 <RZA1_PINMUX(3, 5, 2) 78 <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
73 <RZA1_PINMUX(3, 6, 2) 79 <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
74 <RZA1_PINMUX(5, 9, 2) 80 <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
75 <RZA1_PINMUX(10, 1, 4 81 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
76 <RZA1_PINMUX(10, 2, 4 82 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
77 <RZA1_PINMUX(10, 3, 4 83 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
78 <RZA1_PINMUX(10, 4, 4 84 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
79 <RZA1_PINMUX(10, 5, 4 85 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
80 <RZA1_PINMUX(10, 6, 4 86 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
81 <RZA1_PINMUX(10, 7, 4 87 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
82 <RZA1_PINMUX(10, 8, 4 88 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
83 <RZA1_PINMUX(10, 9, 4 89 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
84 <RZA1_PINMUX(10, 10, 90 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
85 <RZA1_PINMUX(10, 11, 91 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
86 }; 92 };
87 }; 93 };
88 94
89 &extal_clk { 95 &extal_clk {
90 clock-frequency = <13333000>; 96 clock-frequency = <13333000>;
91 }; 97 };
92 98
93 &usb_x1_clk { 99 &usb_x1_clk {
94 clock-frequency = <48000000>; 100 clock-frequency = <48000000>;
95 }; 101 };
96 102
97 &mtu2 { 103 &mtu2 {
98 status = "okay"; 104 status = "okay";
99 }; 105 };
100 106
101 &ostm0 { 107 &ostm0 {
102 status = "okay"; 108 status = "okay";
103 }; 109 };
104 110
105 &ostm1 { 111 &ostm1 {
106 status = "okay"; 112 status = "okay";
107 }; 113 };
108 114
109 &scif2 { 115 &scif2 {
110 pinctrl-names = "default"; 116 pinctrl-names = "default";
111 pinctrl-0 = <&scif2_pins>; 117 pinctrl-0 = <&scif2_pins>;
112 118
113 status = "okay"; 119 status = "okay";
114 }; 120 };
115 121
116 ðer { 122 ðer {
117 pinctrl-names = "default"; 123 pinctrl-names = "default";
118 pinctrl-0 = <ðer_pins>; 124 pinctrl-0 = <ðer_pins>;
119 125
120 status = "okay"; 126 status = "okay";
121 127
122 renesas,no-ether-link; 128 renesas,no-ether-link;
123 phy-handle = <&phy0>; 129 phy-handle = <&phy0>;
124 130
125 phy0: ethernet-phy@0 { 131 phy0: ethernet-phy@0 {
126 compatible = "ethernet-phy-id0 132 compatible = "ethernet-phy-id0007.c0f0",
127 "ethernet-phy-iee 133 "ethernet-phy-ieee802.3-c22";
128 reg = <0>; 134 reg = <0>;
129 135
130 reset-gpios = <&port4 2 GPIO_A 136 reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
131 reset-delay-us = <5>; 137 reset-delay-us = <5>;
132 }; 138 };
133 }; 139 };
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