1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the r7s72100 SoC
4 *
5 * Copyright (C) 2013-14 Renesas Solutions Cor
6 * Copyright (C) 2014 Wolfram Sang, Sang Engin<
7 */
8
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/interrupt-controller/irq
12
13 / {
14 compatible = "renesas,r7s72100";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 spi0 = &spi0;
24 spi1 = &spi1;
25 spi2 = &spi2;
26 spi3 = &spi3;
27 spi4 = &spi4;
28 };
29
30 /* Fixed factor clocks */
31 b_clk: b {
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clo
34 clocks = <&cpg_clocks R7S72100
35 clock-mult = <1>;
36 clock-div = <3>;
37 };
38
39 bsc: bsc {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges = <0 0 0x18000000>;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cort
53 reg = <0>;
54 clock-frequency = <400
55 clocks = <&cpg_clocks
56 next-level-cache = <&L
57 };
58 };
59
60 /* External clocks */
61 extal_clk: extal {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 /* If clk present, value must
65 clock-frequency = <0>;
66 };
67
68 p0_clk: p0 {
69 #clock-cells = <0>;
70 compatible = "fixed-factor-clo
71 clocks = <&cpg_clocks R7S72100
72 clock-mult = <1>;
73 clock-div = <12>;
74 };
75
76 p1_clk: p1 {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clo
79 clocks = <&cpg_clocks R7S72100
80 clock-mult = <1>;
81 clock-div = <6>;
82 };
83
84 pmu {
85 compatible = "arm,cortex-a9-pm
86 interrupts-extended = <&gic GI
87 };
88
89 rtc_x1_clk: rtc_x1 {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 /* If clk present, value must
93 clock-frequency = <0>;
94 };
95
96 rtc_x3_clk: rtc_x3 {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 /* If clk present, value must
100 clock-frequency = <0>;
101 };
102
103 soc {
104 compatible = "simple-bus";
105 interrupt-parent = <&gic>;
106
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 L2: cache-controller@3ffff000
112 compatible = "arm,pl31
113 reg = <0x3ffff000 0x10
114 interrupts = <GIC_SPI
115 arm,early-bresp-disabl
116 arm,full-line-zero-dis
117 cache-unified;
118 cache-level = <2>;
119 };
120
121 scif0: serial@e8007000 {
122 compatible = "renesas,
123 reg = <0xe8007000 64>;
124 interrupts = <GIC_SPI
125 <GIC_SPI
126 <GIC_SPI
127 <GIC_SPI
128 interrupt-names = "eri
129 clocks = <&mstp4_clks
130 clock-names = "fck";
131 power-domains = <&cpg_
132 status = "disabled";
133 };
134
135 scif1: serial@e8007800 {
136 compatible = "renesas,
137 reg = <0xe8007800 64>;
138 interrupts = <GIC_SPI
139 <GIC_SPI
140 <GIC_SPI
141 <GIC_SPI
142 interrupt-names = "eri
143 clocks = <&mstp4_clks
144 clock-names = "fck";
145 power-domains = <&cpg_
146 status = "disabled";
147 };
148
149 scif2: serial@e8008000 {
150 compatible = "renesas,
151 reg = <0xe8008000 64>;
152 interrupts = <GIC_SPI
153 <GIC_SPI
154 <GIC_SPI
155 <GIC_SPI
156 interrupt-names = "eri
157 clocks = <&mstp4_clks
158 clock-names = "fck";
159 power-domains = <&cpg_
160 status = "disabled";
161 };
162
163 scif3: serial@e8008800 {
164 compatible = "renesas,
165 reg = <0xe8008800 64>;
166 interrupts = <GIC_SPI
167 <GIC_SPI
168 <GIC_SPI
169 <GIC_SPI
170 interrupt-names = "eri
171 clocks = <&mstp4_clks
172 clock-names = "fck";
173 power-domains = <&cpg_
174 status = "disabled";
175 };
176
177 scif4: serial@e8009000 {
178 compatible = "renesas,
179 reg = <0xe8009000 64>;
180 interrupts = <GIC_SPI
181 <GIC_SPI
182 <GIC_SPI
183 <GIC_SPI
184 interrupt-names = "eri
185 clocks = <&mstp4_clks
186 clock-names = "fck";
187 power-domains = <&cpg_
188 status = "disabled";
189 };
190
191 scif5: serial@e8009800 {
192 compatible = "renesas,
193 reg = <0xe8009800 64>;
194 interrupts = <GIC_SPI
195 <GIC_SPI
196 <GIC_SPI
197 <GIC_SPI
198 interrupt-names = "eri
199 clocks = <&mstp4_clks
200 clock-names = "fck";
201 power-domains = <&cpg_
202 status = "disabled";
203 };
204
205 scif6: serial@e800a000 {
206 compatible = "renesas,
207 reg = <0xe800a000 64>;
208 interrupts = <GIC_SPI
209 <GIC_SPI
210 <GIC_SPI
211 <GIC_SPI
212 interrupt-names = "eri
213 clocks = <&mstp4_clks
214 clock-names = "fck";
215 power-domains = <&cpg_
216 status = "disabled";
217 };
218
219 scif7: serial@e800a800 {
220 compatible = "renesas,
221 reg = <0xe800a800 64>;
222 interrupts = <GIC_SPI
223 <GIC_SPI
224 <GIC_SPI
225 <GIC_SPI
226 interrupt-names = "eri
227 clocks = <&mstp4_clks
228 clock-names = "fck";
229 power-domains = <&cpg_
230 status = "disabled";
231 };
232
233 spi0: spi@e800c800 {
234 compatible = "renesas,
235 reg = <0xe800c800 0x24
236 interrupts = <GIC_SPI
237 <GIC_SPI
238 <GIC_SPI
239 interrupt-names = "err
240 clocks = <&mstp10_clks
241 power-domains = <&cpg_
242 num-cs = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 status = "disabled";
246 };
247
248 spi1: spi@e800d000 {
249 compatible = "renesas,
250 reg = <0xe800d000 0x24
251 interrupts = <GIC_SPI
252 <GIC_SPI
253 <GIC_SPI
254 interrupt-names = "err
255 clocks = <&mstp10_clks
256 power-domains = <&cpg_
257 num-cs = <1>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
263 spi2: spi@e800d800 {
264 compatible = "renesas,
265 reg = <0xe800d800 0x24
266 interrupts = <GIC_SPI
267 <GIC_SPI
268 <GIC_SPI
269 interrupt-names = "err
270 clocks = <&mstp10_clks
271 power-domains = <&cpg_
272 num-cs = <1>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 status = "disabled";
276 };
277
278 spi3: spi@e800e000 {
279 compatible = "renesas,
280 reg = <0xe800e000 0x24
281 interrupts = <GIC_SPI
282 <GIC_SPI
283 <GIC_SPI
284 interrupt-names = "err
285 clocks = <&mstp10_clks
286 power-domains = <&cpg_
287 num-cs = <1>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 status = "disabled";
291 };
292
293 spi4: spi@e800e800 {
294 compatible = "renesas,
295 reg = <0xe800e800 0x24
296 interrupts = <GIC_SPI
297 <GIC_SPI
298 <GIC_SPI
299 interrupt-names = "err
300 clocks = <&mstp10_clks
301 power-domains = <&cpg_
302 num-cs = <1>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 status = "disabled";
306 };
307
308 usbhs0: usb@e8010000 {
309 compatible = "renesas,
310 reg = <0xe8010000 0x1a
311 interrupts = <GIC_SPI
312 clocks = <&mstp7_clks
313 renesas,buswait = <4>;
314 power-domains = <&cpg_
315 status = "disabled";
316 };
317
318 usbhs1: usb@e8207000 {
319 compatible = "renesas,
320 reg = <0xe8207000 0x1a
321 interrupts = <GIC_SPI
322 clocks = <&mstp7_clks
323 renesas,buswait = <4>;
324 power-domains = <&cpg_
325 status = "disabled";
326 };
327
328 mmcif: mmc@e804c800 {
329 compatible = "renesas,
330 reg = <0xe804c800 0x80
331 interrupts = <GIC_SPI
332 <GIC_SPI
333 <GIC_SPI
334 clocks = <&mstp8_clks
335 power-domains = <&cpg_
336 reg-io-width = <4>;
337 bus-width = <8>;
338 status = "disabled";
339 };
340
341 sdhi0: mmc@e804e000 {
342 compatible = "renesas,
343 reg = <0xe804e000 0x10
344 interrupts = <GIC_SPI
345 <GIC_SPI
346 <GIC_SPI
347
348 clocks = <&mstp12_clks
349 <&mstp12_clks
350 clock-names = "core",
351 power-domains = <&cpg_
352 cap-sd-highspeed;
353 cap-sdio-irq;
354 status = "disabled";
355 };
356
357 sdhi1: mmc@e804e800 {
358 compatible = "renesas,
359 reg = <0xe804e800 0x10
360 interrupts = <GIC_SPI
361 <GIC_SPI
362 <GIC_SPI
363
364 clocks = <&mstp12_clks
365 <&mstp12_clks
366 clock-names = "core",
367 power-domains = <&cpg_
368 cap-sd-highspeed;
369 cap-sdio-irq;
370 status = "disabled";
371 };
372
373 gic: interrupt-controller@e820
374 compatible = "arm,pl39
375 #interrupt-cells = <3>
376 #address-cells = <0>;
377 interrupt-controller;
378 reg = <0xe8201000 0x10
379 <0xe8202000 0x
380 };
381
382 ether: ethernet@e8203000 {
383 compatible = "renesas,
384 reg = <0xe8203000 0x80
385 <0xe8204800 0x20
386 interrupts = <GIC_SPI
387 clocks = <&mstp7_clks
388 power-domains = <&cpg_
389 phy-mode = "mii";
390 #address-cells = <1>;
391 #size-cells = <0>;
392 status = "disabled";
393 };
394
395 ceu: camera@e8210000 {
396 reg = <0xe8210000 0x30
397 compatible = "renesas,
398 interrupts = <GIC_SPI
399 clocks = <&mstp6_clks
400 power-domains = <&cpg_
401 status = "disabled";
402 };
403
404 wdt: watchdog@fcfe0000 {
405 compatible = "renesas,
406 reg = <0xfcfe0000 0x6>
407 interrupts = <GIC_SPI
408 clocks = <&p0_clk>;
409 };
410
411 /* Special CPG clocks */
412 cpg_clocks: cpg_clocks@fcfe000
413 #clock-cells = <1>;
414 compatible = "renesas,
415 "renesas,
416 reg = <0xfcfe0000 0x18
417 clocks = <&extal_clk>,
418 clock-output-names = "
419 #power-domain-cells =
420 };
421
422 /* MSTP clocks */
423 mstp3_clks: mstp3_clks@fcfe042
424 #clock-cells = <1>;
425 compatible = "renesas,
426 reg = <0xfcfe0420 4>;
427 clocks = <&p0_clk>;
428 clock-indices = <R7S72
429 clock-output-names = "
430 };
431
432 mstp4_clks: mstp4_clks@fcfe042
433 #clock-cells = <1>;
434 compatible = "renesas,
435 reg = <0xfcfe0424 4>;
436 clocks = <&p1_clk>, <&
437 <&p1_clk>, <&
438 clock-indices = <
439 R7S72100_CLK_S
440 R7S72100_CLK_S
441 >;
442 clock-output-names = "
443 };
444
445 mstp5_clks: mstp5_clks@fcfe042
446 #clock-cells = <1>;
447 compatible = "renesas,
448 reg = <0xfcfe0428 4>;
449 clocks = <&p0_clk>, <&
450 clock-indices = <R7S72
451 clock-output-names = "
452 };
453
454 mstp6_clks: mstp6_clks@fcfe042
455 #clock-cells = <1>;
456 compatible = "renesas,
457 reg = <0xfcfe042c 4>;
458 clocks = <&b_clk>, <&p
459 clock-indices = <R7S72
460 clock-output-names = "
461 };
462
463 mstp7_clks: mstp7_clks@fcfe043
464 #clock-cells = <1>;
465 compatible = "renesas,
466 reg = <0xfcfe0430 4>;
467 clocks = <&b_clk>, <&p
468 clock-indices = <R7S72
469 clock-output-names = "
470 };
471
472 mstp8_clks: mstp8_clks@fcfe043
473 #clock-cells = <1>;
474 compatible = "renesas,
475 reg = <0xfcfe0434 4>;
476 clocks = <&p1_clk>;
477 clock-indices = <R7S72
478 clock-output-names = "
479 };
480
481 mstp9_clks: mstp9_clks@fcfe043
482 #clock-cells = <1>;
483 compatible = "renesas,
484 reg = <0xfcfe0438 4>;
485 clocks = <&p0_clk>, <&
486 clock-indices = <
487 R7S72100_CLK_I
488 R7S72100_CLK_S
489 >;
490 clock-output-names = "
491 };
492
493 mstp10_clks: mstp10_clks@fcfe0
494 #clock-cells = <1>;
495 compatible = "renesas,
496 reg = <0xfcfe043c 4>;
497 clocks = <&p1_clk>, <&
498 <&p1_clk>;
499 clock-indices = <
500 R7S72100_CLK_S
501 R7S72100_CLK_S
502 >;
503 clock-output-names = "
504 };
505 mstp12_clks: mstp12_clks@fcfe0
506 #clock-cells = <1>;
507 compatible = "renesas,
508 reg = <0xfcfe0444 4>;
509 clocks = <&p1_clk>, <&
510 clock-indices = <
511 R7S72100_CLK_S
512 R7S72100_CLK_S
513 >;
514 clock-output-names = "
515 };
516
517 pinctrl: pinctrl@fcfe3000 {
518 compatible = "renesas,
519
520 reg = <0xfcfe3000 0x42
521
522 port0: gpio-0 {
523 gpio-controlle
524 #gpio-cells =
525 gpio-ranges =
526 };
527
528 port1: gpio-1 {
529 gpio-controlle
530 #gpio-cells =
531 gpio-ranges =
532 };
533
534 port2: gpio-2 {
535 gpio-controlle
536 #gpio-cells =
537 gpio-ranges =
538 };
539
540 port3: gpio-3 {
541 gpio-controlle
542 #gpio-cells =
543 gpio-ranges =
544 };
545
546 port4: gpio-4 {
547 gpio-controlle
548 #gpio-cells =
549 gpio-ranges =
550 };
551
552 port5: gpio-5 {
553 gpio-controlle
554 #gpio-cells =
555 gpio-ranges =
556 };
557
558 port6: gpio-6 {
559 gpio-controlle
560 #gpio-cells =
561 gpio-ranges =
562 };
563
564 port7: gpio-7 {
565 gpio-controlle
566 #gpio-cells =
567 gpio-ranges =
568 };
569
570 port8: gpio-8 {
571 gpio-controlle
572 #gpio-cells =
573 gpio-ranges =
574 };
575
576 port9: gpio-9 {
577 gpio-controlle
578 #gpio-cells =
579 gpio-ranges =
580 };
581
582 port10: gpio-10 {
583 gpio-controlle
584 #gpio-cells =
585 gpio-ranges =
586 };
587
588 port11: gpio-11 {
589 gpio-controlle
590 #gpio-cells =
591 gpio-ranges =
592 };
593 };
594
595 ostm0: timer@fcfec000 {
596 compatible = "renesas,
597 reg = <0xfcfec000 0x30
598 interrupts = <GIC_SPI
599 clocks = <&mstp5_clks
600 power-domains = <&cpg_
601 status = "disabled";
602 };
603
604 ostm1: timer@fcfec400 {
605 compatible = "renesas,
606 reg = <0xfcfec400 0x30
607 interrupts = <GIC_SPI
608 clocks = <&mstp5_clks
609 power-domains = <&cpg_
610 status = "disabled";
611 };
612
613 i2c0: i2c@fcfee000 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "renesas,
617 reg = <0xfcfee000 0x44
618 interrupts = <GIC_SPI
619 <GIC_SPI
620 <GIC_SPI
621 <GIC_SPI
622 <GIC_SPI
623 <GIC_SPI
624 <GIC_SPI
625 <GIC_SPI
626 interrupt-names = "tei
627 "nak
628 clocks = <&mstp9_clks
629 clock-frequency = <100
630 power-domains = <&cpg_
631 status = "disabled";
632 };
633
634 i2c1: i2c@fcfee400 {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "renesas,
638 reg = <0xfcfee400 0x44
639 interrupts = <GIC_SPI
640 <GIC_SPI
641 <GIC_SPI
642 <GIC_SPI
643 <GIC_SPI
644 <GIC_SPI
645 <GIC_SPI
646 <GIC_SPI
647 interrupt-names = "tei
648 "nak
649 clocks = <&mstp9_clks
650 clock-frequency = <100
651 power-domains = <&cpg_
652 status = "disabled";
653 };
654
655 i2c2: i2c@fcfee800 {
656 #address-cells = <1>;
657 #size-cells = <0>;
658 compatible = "renesas,
659 reg = <0xfcfee800 0x44
660 interrupts = <GIC_SPI
661 <GIC_SPI
662 <GIC_SPI
663 <GIC_SPI
664 <GIC_SPI
665 <GIC_SPI
666 <GIC_SPI
667 <GIC_SPI
668 interrupt-names = "tei
669 "nak
670 clocks = <&mstp9_clks
671 clock-frequency = <100
672 power-domains = <&cpg_
673 status = "disabled";
674 };
675
676 i2c3: i2c@fcfeec00 {
677 #address-cells = <1>;
678 #size-cells = <0>;
679 compatible = "renesas,
680 reg = <0xfcfeec00 0x44
681 interrupts = <GIC_SPI
682 <GIC_SPI
683 <GIC_SPI
684 <GIC_SPI
685 <GIC_SPI
686 <GIC_SPI
687 <GIC_SPI
688 <GIC_SPI
689 interrupt-names = "tei
690 "nak
691 clocks = <&mstp9_clks
692 clock-frequency = <100
693 power-domains = <&cpg_
694 status = "disabled";
695 };
696
697 irqc: interrupt-controller@fcf
698 compatible = "renesas,
699 "renesas,
700 #interrupt-cells = <2>
701 #address-cells = <0>;
702 interrupt-controller;
703 reg = <0xfcfef800 0x6>
704 interrupt-map =
705 <0 0 &gic GIC_
706 <1 0 &gic GIC_
707 <2 0 &gic GIC_
708 <3 0 &gic GIC_
709 <4 0 &gic GIC_
710 <5 0 &gic GIC_
711 <6 0 &gic GIC_
712 <7 0 &gic GIC_
713 interrupt-map-mask = <
714 };
715
716 mtu2: timer@fcff0000 {
717 compatible = "renesas,
718 reg = <0xfcff0000 0x40
719 interrupts = <GIC_SPI
720 interrupt-names = "tgi
721 clocks = <&mstp3_clks
722 clock-names = "fck";
723 power-domains = <&cpg_
724 status = "disabled";
725 };
726
727 rtc: rtc@fcff1000 {
728 compatible = "renesas,
729 reg = <0xfcff1000 0x2e
730 interrupts = <GIC_SPI
731 <GIC_SPI
732 <GIC_SPI
733 interrupt-names = "ala
734 clocks = <&mstp6_clks
735 <&rtc_x3_clk>
736 clock-names = "fck", "
737 power-domains = <&cpg_
738 status = "disabled";
739 };
740 };
741
742 usb_x1_clk: usb_x1 {
743 #clock-cells = <0>;
744 compatible = "fixed-clock";
745 /* If clk present, value must
746 clock-frequency = <0>;
747 };
748 };
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