1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the r8a73a4 SoC 3 * Device Tree Source for the r8a73a4 SoC
4 * 4 *
5 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm 6 * Copyright (C) 2013 Magnus Damm
7 */ 7 */
8 8
9 #include <dt-bindings/clock/r8a73a4-clock.h> 9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq 11 #include <dt-bindings/interrupt-controller/irq.h>
12 12
13 / { 13 / {
14 compatible = "renesas,r8a73a4"; 14 compatible = "renesas,r8a73a4";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 cpus { 19 cpus {
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <0>; 21 #size-cells = <0>;
22 22
23 cpu0: cpu@0 { 23 cpu0: cpu@0 {
24 device_type = "cpu"; 24 device_type = "cpu";
25 compatible = "arm,cort 25 compatible = "arm,cortex-a15";
26 reg = <0>; 26 reg = <0>;
27 clocks = <&cpg_clocks 27 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
28 clock-frequency = <150 28 clock-frequency = <1500000000>;
29 power-domains = <&pd_a 29 power-domains = <&pd_a2sl>;
30 next-level-cache = <&L 30 next-level-cache = <&L2_CA15>;
31 }; 31 };
32 32
33 L2_CA15: cache-controller-0 { 33 L2_CA15: cache-controller-0 {
34 compatible = "cache"; 34 compatible = "cache";
35 clocks = <&cpg_clocks 35 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
36 power-domains = <&pd_a 36 power-domains = <&pd_a3sm>;
37 cache-unified; 37 cache-unified;
38 cache-level = <2>; 38 cache-level = <2>;
39 }; 39 };
40 40
41 L2_CA7: cache-controller-1 { 41 L2_CA7: cache-controller-1 {
42 compatible = "cache"; 42 compatible = "cache";
43 clocks = <&cpg_clocks 43 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
44 power-domains = <&pd_a 44 power-domains = <&pd_a3km>;
45 cache-unified; 45 cache-unified;
46 cache-level = <2>; 46 cache-level = <2>;
47 }; 47 };
48 }; 48 };
49 49
50 ptm { 50 ptm {
51 compatible = "arm,coresight-et 51 compatible = "arm,coresight-etm3x";
52 power-domains = <&pd_d4>; 52 power-domains = <&pd_d4>;
53 }; 53 };
54 54
55 timer { 55 timer {
56 compatible = "arm,armv7-timer" 56 compatible = "arm,armv7-timer";
57 interrupts = <GIC_PPI 13 (GIC_ 57 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
58 <GIC_PPI 14 (GIC_ 58 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
59 <GIC_PPI 11 (GIC_ 59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
60 <GIC_PPI 10 (GIC_ 60 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
61 interrupt-names = "sec-phys", <<
62 }; <<
63 <<
64 tmu0: timer@e61e0000 { <<
65 compatible = "renesas,tmu-r8a7 <<
66 reg = <0 0xe61e0000 0 0x30>; <<
67 interrupts = <GIC_SPI 136 IRQ_ <<
68 <GIC_SPI 137 IRQ_ <<
69 <GIC_SPI 138 IRQ_ <<
70 interrupt-names = "tuni0", "tu <<
71 clocks = <&mstp1_clks R8A73A4_ <<
72 clock-names = "fck"; <<
73 power-domains = <&pd_c5>; <<
74 status = "disabled"; <<
75 }; <<
76 <<
77 tmu3: timer@fff80000 { <<
78 compatible = "renesas,tmu-r8a7 <<
79 reg = <0 0xfff80000 0 0x30>; <<
80 interrupts = <GIC_SPI 131 IRQ_ <<
81 <GIC_SPI 132 IRQ_ <<
82 <GIC_SPI 133 IRQ_ <<
83 interrupt-names = "tuni0", "tu <<
84 clocks = <&mstp1_clks R8A73A4_ <<
85 clock-names = "fck"; <<
86 power-domains = <&pd_a3r>; <<
87 status = "disabled"; <<
88 }; 61 };
89 62
90 dbsc1: memory-controller@e6790000 { 63 dbsc1: memory-controller@e6790000 {
91 compatible = "renesas,dbsc-r8a 64 compatible = "renesas,dbsc-r8a73a4";
92 reg = <0 0xe6790000 0 0x10000> 65 reg = <0 0xe6790000 0 0x10000>;
93 power-domains = <&pd_a3bc>; 66 power-domains = <&pd_a3bc>;
94 }; 67 };
95 68
96 dbsc2: memory-controller@e67a0000 { 69 dbsc2: memory-controller@e67a0000 {
97 compatible = "renesas,dbsc-r8a 70 compatible = "renesas,dbsc-r8a73a4";
98 reg = <0 0xe67a0000 0 0x10000> 71 reg = <0 0xe67a0000 0 0x10000>;
99 power-domains = <&pd_a3bc>; 72 power-domains = <&pd_a3bc>;
100 }; 73 };
101 74
102 i2c5: i2c@e60b0000 { 75 i2c5: i2c@e60b0000 {
103 #address-cells = <1>; 76 #address-cells = <1>;
104 #size-cells = <0>; 77 #size-cells = <0>;
105 compatible = "renesas,iic-r8a7 78 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
106 reg = <0 0xe60b0000 0 0x428>; 79 reg = <0 0xe60b0000 0 0x428>;
107 interrupts = <GIC_SPI 179 IRQ_ 80 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&mstp4_clks R8A73A4_ 81 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
109 power-domains = <&pd_a3sp>; 82 power-domains = <&pd_a3sp>;
110 83
111 status = "disabled"; 84 status = "disabled";
112 }; 85 };
113 86
114 cmt1: timer@e6130000 { 87 cmt1: timer@e6130000 {
115 compatible = "renesas,r8a73a4- 88 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
116 reg = <0 0xe6130000 0 0x1004>; 89 reg = <0 0xe6130000 0 0x1004>;
117 interrupts = <GIC_SPI 120 IRQ_ 90 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 121 IRQ_ 91 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 122 IRQ_ 92 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 123 IRQ_ 93 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 124 IRQ_ 94 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 125 IRQ_ 95 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 126 IRQ_ 96 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 127 IRQ_ 97 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&mstp3_clks R8A73A4_ 98 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
126 clock-names = "fck"; 99 clock-names = "fck";
127 power-domains = <&pd_c5>; 100 power-domains = <&pd_c5>;
128 status = "disabled"; 101 status = "disabled";
129 }; 102 };
130 103
131 irqc0: interrupt-controller@e61c0000 { 104 irqc0: interrupt-controller@e61c0000 {
132 compatible = "renesas,irqc-r8a 105 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
133 #interrupt-cells = <2>; 106 #interrupt-cells = <2>;
134 interrupt-controller; 107 interrupt-controller;
135 reg = <0 0xe61c0000 0 0x200>; 108 reg = <0 0xe61c0000 0 0x200>;
136 interrupts = <GIC_SPI 0 IRQ_TY 109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 1 IRQ_TY 110 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 2 IRQ_TY 111 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 3 IRQ_TY 112 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 4 IRQ_TY 113 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 5 IRQ_TY 114 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 6 IRQ_TY 115 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 7 IRQ_TY 116 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 8 IRQ_TY 117 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 9 IRQ_TY 118 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 10 IRQ_T 119 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 11 IRQ_T 120 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 12 IRQ_T 121 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 13 IRQ_T 122 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 14 IRQ_T 123 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 15 IRQ_T 124 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 16 IRQ_T 125 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 17 IRQ_T 126 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 18 IRQ_T 127 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 19 IRQ_T 128 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 20 IRQ_T 129 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 21 IRQ_T 130 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 22 IRQ_T 131 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 23 IRQ_T 132 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 24 IRQ_T 133 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 25 IRQ_T 134 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 26 IRQ_T 135 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 27 IRQ_T 136 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 28 IRQ_T 137 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 29 IRQ_T 138 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 30 IRQ_T 139 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 31 IRQ_T 140 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&mstp4_clks R8A73A4_ 141 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
169 power-domains = <&pd_c4>; 142 power-domains = <&pd_c4>;
170 }; 143 };
171 144
172 irqc1: interrupt-controller@e61c0200 { 145 irqc1: interrupt-controller@e61c0200 {
173 compatible = "renesas,irqc-r8a 146 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
174 #interrupt-cells = <2>; 147 #interrupt-cells = <2>;
175 interrupt-controller; 148 interrupt-controller;
176 reg = <0 0xe61c0200 0 0x200>; 149 reg = <0 0xe61c0200 0 0x200>;
177 interrupts = <GIC_SPI 32 IRQ_T 150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 33 IRQ_T 151 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 34 IRQ_T 152 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 35 IRQ_T 153 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 36 IRQ_T 154 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 37 IRQ_T 155 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 38 IRQ_T 156 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 39 IRQ_T 157 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 40 IRQ_T 158 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 41 IRQ_T 159 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 42 IRQ_T 160 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 43 IRQ_T 161 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 44 IRQ_T 162 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 45 IRQ_T 163 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 46 IRQ_T 164 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 47 IRQ_T 165 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 48 IRQ_T 166 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 49 IRQ_T 167 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 50 IRQ_T 168 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 51 IRQ_T 169 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 52 IRQ_T 170 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 53 IRQ_T 171 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 54 IRQ_T 172 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 55 IRQ_T 173 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 56 IRQ_T 174 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 57 IRQ_T 175 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&mstp4_clks R8A73A4_ 176 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
204 power-domains = <&pd_c4>; 177 power-domains = <&pd_c4>;
205 }; 178 };
206 179
207 pfc: pinctrl@e6050000 { 180 pfc: pinctrl@e6050000 {
208 compatible = "renesas,pfc-r8a7 181 compatible = "renesas,pfc-r8a73a4";
209 reg = <0 0xe6050000 0 0x9000>; 182 reg = <0 0xe6050000 0 0x9000>;
210 gpio-controller; 183 gpio-controller;
211 #gpio-cells = <2>; 184 #gpio-cells = <2>;
212 gpio-ranges = 185 gpio-ranges =
213 <&pfc 0 0 31>, <&pfc 3 186 <&pfc 0 0 31>, <&pfc 32 32 9>,
214 <&pfc 64 64 22>, <&pfc 187 <&pfc 64 64 22>, <&pfc 96 96 31>,
215 <&pfc 128 128 7>, <&pf 188 <&pfc 128 128 7>, <&pfc 160 160 19>,
216 <&pfc 192 192 31>, <&p 189 <&pfc 192 192 31>, <&pfc 224 224 27>,
217 <&pfc 256 256 28>, <&p 190 <&pfc 256 256 28>, <&pfc 288 288 21>,
218 <&pfc 320 320 10>; 191 <&pfc 320 320 10>;
219 interrupts-extended = 192 interrupts-extended =
220 <&irqc0 0 0>, <&irqc0 193 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
221 <&irqc0 4 0>, <&irqc0 194 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
222 <&irqc0 8 0>, <&irqc0 195 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
223 <&irqc0 12 0>, <&irqc0 196 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
224 <&irqc0 16 0>, <&irqc0 197 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
225 <&irqc0 20 0>, <&irqc0 198 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
226 <&irqc0 24 0>, <&irqc0 199 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
227 <&irqc0 28 0>, <&irqc0 200 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
228 <&irqc1 0 0>, <&irqc1 201 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
229 <&irqc1 4 0>, <&irqc1 202 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
230 <&irqc1 8 0>, <&irqc1 203 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
231 <&irqc1 12 0>, <&irqc1 204 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
232 <&irqc1 16 0>, <&irqc1 205 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
233 <&irqc1 20 0>, <&irqc1 206 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
234 <&irqc1 24 0>, <&irqc1 207 <&irqc1 24 0>, <&irqc1 25 0>;
235 power-domains = <&pd_c5>; 208 power-domains = <&pd_c5>;
236 }; 209 };
237 210
238 thermal@e61f0000 { 211 thermal@e61f0000 {
239 compatible = "renesas,thermal- 212 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
240 reg = <0 0xe61f0000 0 0x14>, < 213 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
241 <0 0xe61f0200 0 0x38> 214 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
242 interrupts = <GIC_SPI 69 IRQ_T 215 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp5_clks R8A73A4_ 216 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
244 power-domains = <&pd_c5>; 217 power-domains = <&pd_c5>;
245 }; 218 };
246 219
247 i2c0: i2c@e6500000 { 220 i2c0: i2c@e6500000 {
248 #address-cells = <1>; 221 #address-cells = <1>;
249 #size-cells = <0>; 222 #size-cells = <0>;
250 compatible = "renesas,iic-r8a7 223 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
251 reg = <0 0xe6500000 0 0x428>; 224 reg = <0 0xe6500000 0 0x428>;
252 interrupts = <GIC_SPI 174 IRQ_ 225 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp3_clks R8A73A4_ 226 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
254 power-domains = <&pd_a3sp>; 227 power-domains = <&pd_a3sp>;
255 status = "disabled"; 228 status = "disabled";
256 }; 229 };
257 230
258 i2c1: i2c@e6510000 { 231 i2c1: i2c@e6510000 {
259 #address-cells = <1>; 232 #address-cells = <1>;
260 #size-cells = <0>; 233 #size-cells = <0>;
261 compatible = "renesas,iic-r8a7 234 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
262 reg = <0 0xe6510000 0 0x428>; 235 reg = <0 0xe6510000 0 0x428>;
263 interrupts = <GIC_SPI 175 IRQ_ 236 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp3_clks R8A73A4_ 237 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
265 power-domains = <&pd_a3sp>; 238 power-domains = <&pd_a3sp>;
266 status = "disabled"; 239 status = "disabled";
267 }; 240 };
268 241
269 i2c2: i2c@e6520000 { 242 i2c2: i2c@e6520000 {
270 #address-cells = <1>; 243 #address-cells = <1>;
271 #size-cells = <0>; 244 #size-cells = <0>;
272 compatible = "renesas,iic-r8a7 245 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
273 reg = <0 0xe6520000 0 0x428>; 246 reg = <0 0xe6520000 0 0x428>;
274 interrupts = <GIC_SPI 176 IRQ_ 247 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&mstp3_clks R8A73A4_ 248 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
276 power-domains = <&pd_a3sp>; 249 power-domains = <&pd_a3sp>;
277 status = "disabled"; 250 status = "disabled";
278 }; 251 };
279 252
280 i2c3: i2c@e6530000 { 253 i2c3: i2c@e6530000 {
281 #address-cells = <1>; 254 #address-cells = <1>;
282 #size-cells = <0>; 255 #size-cells = <0>;
283 compatible = "renesas,iic-r8a7 256 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
284 reg = <0 0xe6530000 0 0x428>; 257 reg = <0 0xe6530000 0 0x428>;
285 interrupts = <GIC_SPI 177 IRQ_ 258 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp4_clks R8A73A4_ 259 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
287 power-domains = <&pd_a3sp>; 260 power-domains = <&pd_a3sp>;
288 status = "disabled"; 261 status = "disabled";
289 }; 262 };
290 263
291 i2c4: i2c@e6540000 { 264 i2c4: i2c@e6540000 {
292 #address-cells = <1>; 265 #address-cells = <1>;
293 #size-cells = <0>; 266 #size-cells = <0>;
294 compatible = "renesas,iic-r8a7 267 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
295 reg = <0 0xe6540000 0 0x428>; 268 reg = <0 0xe6540000 0 0x428>;
296 interrupts = <GIC_SPI 178 IRQ_ 269 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp4_clks R8A73A4_ 270 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
298 power-domains = <&pd_a3sp>; 271 power-domains = <&pd_a3sp>;
299 status = "disabled"; 272 status = "disabled";
300 }; 273 };
301 274
302 i2c6: i2c@e6550000 { 275 i2c6: i2c@e6550000 {
303 #address-cells = <1>; 276 #address-cells = <1>;
304 #size-cells = <0>; 277 #size-cells = <0>;
305 compatible = "renesas,iic-r8a7 278 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
306 reg = <0 0xe6550000 0 0x428>; 279 reg = <0 0xe6550000 0 0x428>;
307 interrupts = <GIC_SPI 184 IRQ_ 280 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp3_clks R8A73A4_ 281 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
309 power-domains = <&pd_a3sp>; 282 power-domains = <&pd_a3sp>;
310 status = "disabled"; 283 status = "disabled";
311 }; 284 };
312 285
313 i2c7: i2c@e6560000 { 286 i2c7: i2c@e6560000 {
314 #address-cells = <1>; 287 #address-cells = <1>;
315 #size-cells = <0>; 288 #size-cells = <0>;
316 compatible = "renesas,iic-r8a7 289 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
317 reg = <0 0xe6560000 0 0x428>; 290 reg = <0 0xe6560000 0 0x428>;
318 interrupts = <GIC_SPI 185 IRQ_ 291 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp3_clks R8A73A4_ 292 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
320 power-domains = <&pd_a3sp>; 293 power-domains = <&pd_a3sp>;
321 status = "disabled"; 294 status = "disabled";
322 }; 295 };
323 296
324 i2c8: i2c@e6570000 { 297 i2c8: i2c@e6570000 {
325 #address-cells = <1>; 298 #address-cells = <1>;
326 #size-cells = <0>; 299 #size-cells = <0>;
327 compatible = "renesas,iic-r8a7 300 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
328 reg = <0 0xe6570000 0 0x428>; 301 reg = <0 0xe6570000 0 0x428>;
329 interrupts = <GIC_SPI 173 IRQ_ 302 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp5_clks R8A73A4_ 303 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
331 power-domains = <&pd_a3sp>; 304 power-domains = <&pd_a3sp>;
332 status = "disabled"; 305 status = "disabled";
333 }; 306 };
334 307
335 scifb0: serial@e6c20000 { 308 scifb0: serial@e6c20000 {
336 compatible = "renesas,scifb-r8 309 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
337 reg = <0 0xe6c20000 0 0x100>; 310 reg = <0 0xe6c20000 0 0x100>;
338 interrupts = <GIC_SPI 148 IRQ_ 311 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp2_clks R8A73A4_ 312 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
340 clock-names = "fck"; 313 clock-names = "fck";
341 power-domains = <&pd_a3sp>; 314 power-domains = <&pd_a3sp>;
342 status = "disabled"; 315 status = "disabled";
343 }; 316 };
344 317
345 scifb1: serial@e6c30000 { 318 scifb1: serial@e6c30000 {
346 compatible = "renesas,scifb-r8 319 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
347 reg = <0 0xe6c30000 0 0x100>; 320 reg = <0 0xe6c30000 0 0x100>;
348 interrupts = <GIC_SPI 149 IRQ_ 321 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp2_clks R8A73A4_ 322 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
350 clock-names = "fck"; 323 clock-names = "fck";
351 power-domains = <&pd_a3sp>; 324 power-domains = <&pd_a3sp>;
352 status = "disabled"; 325 status = "disabled";
353 }; 326 };
354 327
355 scifa0: serial@e6c40000 { 328 scifa0: serial@e6c40000 {
356 compatible = "renesas,scifa-r8 329 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
357 reg = <0 0xe6c40000 0 0x100>; 330 reg = <0 0xe6c40000 0 0x100>;
358 interrupts = <GIC_SPI 144 IRQ_ 331 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp2_clks R8A73A4_ 332 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
360 clock-names = "fck"; 333 clock-names = "fck";
361 power-domains = <&pd_a3sp>; 334 power-domains = <&pd_a3sp>;
362 status = "disabled"; 335 status = "disabled";
363 }; 336 };
364 337
365 scifa1: serial@e6c50000 { 338 scifa1: serial@e6c50000 {
366 compatible = "renesas,scifa-r8 339 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
367 reg = <0 0xe6c50000 0 0x100>; 340 reg = <0 0xe6c50000 0 0x100>;
368 interrupts = <GIC_SPI 145 IRQ_ 341 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&mstp2_clks R8A73A4_ 342 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
370 clock-names = "fck"; 343 clock-names = "fck";
371 power-domains = <&pd_a3sp>; 344 power-domains = <&pd_a3sp>;
372 status = "disabled"; 345 status = "disabled";
373 }; 346 };
374 347
375 scifb2: serial@e6ce0000 { 348 scifb2: serial@e6ce0000 {
376 compatible = "renesas,scifb-r8 349 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
377 reg = <0 0xe6ce0000 0 0x100>; 350 reg = <0 0xe6ce0000 0 0x100>;
378 interrupts = <GIC_SPI 150 IRQ_ 351 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp2_clks R8A73A4_ 352 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
380 clock-names = "fck"; 353 clock-names = "fck";
381 power-domains = <&pd_a3sp>; 354 power-domains = <&pd_a3sp>;
382 status = "disabled"; 355 status = "disabled";
383 }; 356 };
384 357
385 scifb3: serial@e6cf0000 { 358 scifb3: serial@e6cf0000 {
386 compatible = "renesas,scifb-r8 359 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
387 reg = <0 0xe6cf0000 0 0x100>; 360 reg = <0 0xe6cf0000 0 0x100>;
388 interrupts = <GIC_SPI 151 IRQ_ 361 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&mstp2_clks R8A73A4_ 362 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
390 clock-names = "fck"; 363 clock-names = "fck";
391 power-domains = <&pd_c4>; 364 power-domains = <&pd_c4>;
392 status = "disabled"; 365 status = "disabled";
393 }; 366 };
394 367
395 sdhi0: mmc@ee100000 { 368 sdhi0: mmc@ee100000 {
396 compatible = "renesas,sdhi-r8a 369 compatible = "renesas,sdhi-r8a73a4";
397 reg = <0 0xee100000 0 0x100>; 370 reg = <0 0xee100000 0 0x100>;
398 interrupts = <GIC_SPI 165 IRQ_ 371 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&mstp3_clks R8A73A4_ 372 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
400 power-domains = <&pd_a3sp>; 373 power-domains = <&pd_a3sp>;
401 cap-sd-highspeed; 374 cap-sd-highspeed;
402 status = "disabled"; 375 status = "disabled";
403 }; 376 };
404 377
405 sdhi1: mmc@ee120000 { 378 sdhi1: mmc@ee120000 {
406 compatible = "renesas,sdhi-r8a 379 compatible = "renesas,sdhi-r8a73a4";
407 reg = <0 0xee120000 0 0x100>; 380 reg = <0 0xee120000 0 0x100>;
408 interrupts = <GIC_SPI 166 IRQ_ 381 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&mstp3_clks R8A73A4_ 382 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
410 power-domains = <&pd_a3sp>; 383 power-domains = <&pd_a3sp>;
411 cap-sd-highspeed; 384 cap-sd-highspeed;
412 status = "disabled"; 385 status = "disabled";
413 }; 386 };
414 387
415 sdhi2: mmc@ee140000 { 388 sdhi2: mmc@ee140000 {
416 compatible = "renesas,sdhi-r8a 389 compatible = "renesas,sdhi-r8a73a4";
417 reg = <0 0xee140000 0 0x100>; 390 reg = <0 0xee140000 0 0x100>;
418 interrupts = <GIC_SPI 167 IRQ_ 391 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&mstp3_clks R8A73A4_ 392 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
420 power-domains = <&pd_a3sp>; 393 power-domains = <&pd_a3sp>;
421 cap-sd-highspeed; 394 cap-sd-highspeed;
422 status = "disabled"; 395 status = "disabled";
423 }; 396 };
424 397
425 mmcif0: mmc@ee200000 { 398 mmcif0: mmc@ee200000 {
426 compatible = "renesas,mmcif-r8 399 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
427 reg = <0 0xee200000 0 0x80>; 400 reg = <0 0xee200000 0 0x80>;
428 interrupts = <GIC_SPI 169 IRQ_ 401 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp3_clks R8A73A4_ 402 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
430 power-domains = <&pd_a3sp>; 403 power-domains = <&pd_a3sp>;
431 reg-io-width = <4>; 404 reg-io-width = <4>;
432 status = "disabled"; 405 status = "disabled";
433 }; 406 };
434 407
435 mmcif1: mmc@ee220000 { 408 mmcif1: mmc@ee220000 {
436 compatible = "renesas,mmcif-r8 409 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
437 reg = <0 0xee220000 0 0x80>; 410 reg = <0 0xee220000 0 0x80>;
438 interrupts = <GIC_SPI 170 IRQ_ 411 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&mstp3_clks R8A73A4_ 412 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
440 power-domains = <&pd_a3sp>; 413 power-domains = <&pd_a3sp>;
441 reg-io-width = <4>; 414 reg-io-width = <4>;
442 status = "disabled"; 415 status = "disabled";
443 }; 416 };
444 417
445 gic: interrupt-controller@f1001000 { 418 gic: interrupt-controller@f1001000 {
446 compatible = "arm,gic-400"; 419 compatible = "arm,gic-400";
447 #interrupt-cells = <3>; 420 #interrupt-cells = <3>;
448 #address-cells = <0>; 421 #address-cells = <0>;
449 interrupt-controller; 422 interrupt-controller;
450 reg = <0 0xf1001000 0 0x1000>, 423 reg = <0 0xf1001000 0 0x1000>,
451 <0 0xf1002000 0 0x2000 424 <0 0xf1002000 0 0x2000>,
452 <0 0xf1004000 0 0x2000 425 <0 0xf1004000 0 0x2000>,
453 <0 0xf1006000 0 0x2000 426 <0 0xf1006000 0 0x2000>;
454 interrupts = <GIC_PPI 9 (GIC_C 427 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
455 clocks = <&mstp4_clks R8A73A4_ 428 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
456 clock-names = "clk"; 429 clock-names = "clk";
457 power-domains = <&pd_c4>; 430 power-domains = <&pd_c4>;
458 }; 431 };
459 432
460 bsc: bus@fec10000 { 433 bsc: bus@fec10000 {
461 compatible = "renesas,bsc-r8a7 434 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
462 "simple-pm-bus"; 435 "simple-pm-bus";
463 #address-cells = <1>; 436 #address-cells = <1>;
464 #size-cells = <1>; 437 #size-cells = <1>;
465 ranges = <0 0 0 0x20000000>; 438 ranges = <0 0 0 0x20000000>;
466 reg = <0 0xfec10000 0 0x400>; 439 reg = <0 0xfec10000 0 0x400>;
467 clocks = <&zb_clk>; 440 clocks = <&zb_clk>;
468 power-domains = <&pd_c4>; 441 power-domains = <&pd_c4>;
469 }; 442 };
470 443
471 clocks { 444 clocks {
472 #address-cells = <2>; 445 #address-cells = <2>;
473 #size-cells = <2>; 446 #size-cells = <2>;
474 ranges; 447 ranges;
475 448
476 /* External root clocks */ 449 /* External root clocks */
477 extalr_clk: extalr { 450 extalr_clk: extalr {
478 compatible = "fixed-cl 451 compatible = "fixed-clock";
479 #clock-cells = <0>; 452 #clock-cells = <0>;
480 /* This value must be 453 /* This value must be overridden by the board. */
481 clock-frequency = <0>; 454 clock-frequency = <0>;
482 }; 455 };
483 extal1_clk: extal1 { 456 extal1_clk: extal1 {
484 compatible = "fixed-cl 457 compatible = "fixed-clock";
485 #clock-cells = <0>; 458 #clock-cells = <0>;
486 /* This value must be 459 /* This value must be overridden by the board. */
487 clock-frequency = <0>; 460 clock-frequency = <0>;
488 }; 461 };
489 extal2_clk: extal2 { 462 extal2_clk: extal2 {
490 compatible = "fixed-cl 463 compatible = "fixed-clock";
491 #clock-cells = <0>; 464 #clock-cells = <0>;
492 /* This value must be 465 /* This value must be overridden by the board. */
493 clock-frequency = <0>; 466 clock-frequency = <0>;
494 }; 467 };
495 fsiack_clk: fsiack { 468 fsiack_clk: fsiack {
496 compatible = "fixed-cl 469 compatible = "fixed-clock";
497 #clock-cells = <0>; 470 #clock-cells = <0>;
498 /* This value must be 471 /* This value must be overridden by the board. */
499 clock-frequency = <0>; 472 clock-frequency = <0>;
500 }; 473 };
501 fsibck_clk: fsibck { 474 fsibck_clk: fsibck {
502 compatible = "fixed-cl 475 compatible = "fixed-clock";
503 #clock-cells = <0>; 476 #clock-cells = <0>;
504 /* This value must be 477 /* This value must be overridden by the board. */
505 clock-frequency = <0>; 478 clock-frequency = <0>;
506 }; 479 };
507 480
508 /* Special CPG clocks */ 481 /* Special CPG clocks */
509 cpg_clocks: cpg_clocks@e615000 482 cpg_clocks: cpg_clocks@e6150000 {
510 compatible = "renesas, 483 compatible = "renesas,r8a73a4-cpg-clocks";
511 reg = <0 0xe6150000 0 484 reg = <0 0xe6150000 0 0x10000>;
512 clocks = <&extal1_clk> 485 clocks = <&extal1_clk>, <&extal2_clk>;
513 #clock-cells = <1>; 486 #clock-cells = <1>;
514 clock-output-names = " 487 clock-output-names = "main", "pll0", "pll1", "pll2",
515 " 488 "pll2s", "pll2h", "z", "z2",
516 " 489 "i", "m3", "b", "m1", "m2",
517 " 490 "zx", "zs", "hp";
518 }; 491 };
519 492
520 /* Variable factor clocks (DIV 493 /* Variable factor clocks (DIV6) */
521 zb_clk: zb_clk@e6150010 { 494 zb_clk: zb_clk@e6150010 {
522 compatible = "renesas, 495 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
523 reg = <0 0xe6150010 0 496 reg = <0 0xe6150010 0 4>;
524 clocks = <&pll1_div2_c 497 clocks = <&pll1_div2_clk>, <0>,
525 <&cpg_clocks 498 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
526 #clock-cells = <0>; 499 #clock-cells = <0>;
527 clock-output-names = " 500 clock-output-names = "zb";
528 }; 501 };
529 sdhi0_clk: sdhi0ck@e6150074 { 502 sdhi0_clk: sdhi0ck@e6150074 {
530 compatible = "renesas, 503 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
531 reg = <0 0xe6150074 0 504 reg = <0 0xe6150074 0 4>;
532 clocks = <&pll1_div2_c 505 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
533 <0>, <&extal2 506 <0>, <&extal2_clk>;
534 #clock-cells = <0>; 507 #clock-cells = <0>;
535 }; 508 };
536 sdhi1_clk: sdhi1ck@e6150078 { 509 sdhi1_clk: sdhi1ck@e6150078 {
537 compatible = "renesas, 510 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
538 reg = <0 0xe6150078 0 511 reg = <0 0xe6150078 0 4>;
539 clocks = <&pll1_div2_c 512 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
540 <0>, <&extal2 513 <0>, <&extal2_clk>;
541 #clock-cells = <0>; 514 #clock-cells = <0>;
542 }; 515 };
543 sdhi2_clk: sdhi2ck@e615007c { 516 sdhi2_clk: sdhi2ck@e615007c {
544 compatible = "renesas, 517 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
545 reg = <0 0xe615007c 0 518 reg = <0 0xe615007c 0 4>;
546 clocks = <&pll1_div2_c 519 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
547 <0>, <&extal2 520 <0>, <&extal2_clk>;
548 #clock-cells = <0>; 521 #clock-cells = <0>;
549 }; 522 };
550 mmc0_clk: mmc0@e6150240 { 523 mmc0_clk: mmc0@e6150240 {
551 compatible = "renesas, 524 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
552 reg = <0 0xe6150240 0 525 reg = <0 0xe6150240 0 4>;
553 clocks = <&pll1_div2_c 526 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
554 <0>, <&extal2 527 <0>, <&extal2_clk>;
555 #clock-cells = <0>; 528 #clock-cells = <0>;
556 }; 529 };
557 mmc1_clk: mmc1@e6150244 { 530 mmc1_clk: mmc1@e6150244 {
558 compatible = "renesas, 531 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
559 reg = <0 0xe6150244 0 532 reg = <0 0xe6150244 0 4>;
560 clocks = <&pll1_div2_c 533 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
561 <0>, <&extal2 534 <0>, <&extal2_clk>;
562 #clock-cells = <0>; 535 #clock-cells = <0>;
563 }; 536 };
564 vclk1_clk: vclk1@e6150008 { 537 vclk1_clk: vclk1@e6150008 {
565 compatible = "renesas, 538 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
566 reg = <0 0xe6150008 0 539 reg = <0 0xe6150008 0 4>;
567 clocks = <&pll1_div2_c 540 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
568 <0>, <&extal2 541 <0>, <&extal2_clk>, <&main_div2_clk>,
569 <&extalr_clk> 542 <&extalr_clk>, <0>, <0>;
570 #clock-cells = <0>; 543 #clock-cells = <0>;
571 }; 544 };
572 vclk2_clk: vclk2@e615000c { 545 vclk2_clk: vclk2@e615000c {
573 compatible = "renesas, 546 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
574 reg = <0 0xe615000c 0 547 reg = <0 0xe615000c 0 4>;
575 clocks = <&pll1_div2_c 548 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
576 <0>, <&extal2 549 <0>, <&extal2_clk>, <&main_div2_clk>,
577 <&extalr_clk> 550 <&extalr_clk>, <0>, <0>;
578 #clock-cells = <0>; 551 #clock-cells = <0>;
579 }; 552 };
580 vclk3_clk: vclk3@e615001c { 553 vclk3_clk: vclk3@e615001c {
581 compatible = "renesas, 554 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
582 reg = <0 0xe615001c 0 555 reg = <0 0xe615001c 0 4>;
583 clocks = <&pll1_div2_c 556 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
584 <0>, <&extal2 557 <0>, <&extal2_clk>, <&main_div2_clk>,
585 <&extalr_clk> 558 <&extalr_clk>, <0>, <0>;
586 #clock-cells = <0>; 559 #clock-cells = <0>;
587 }; 560 };
588 vclk4_clk: vclk4@e6150014 { 561 vclk4_clk: vclk4@e6150014 {
589 compatible = "renesas, 562 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
590 reg = <0 0xe6150014 0 563 reg = <0 0xe6150014 0 4>;
591 clocks = <&pll1_div2_c 564 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
592 <0>, <&extal2 565 <0>, <&extal2_clk>, <&main_div2_clk>,
593 <&extalr_clk> 566 <&extalr_clk>, <0>, <0>;
594 #clock-cells = <0>; 567 #clock-cells = <0>;
595 }; 568 };
596 vclk5_clk: vclk5@e6150034 { 569 vclk5_clk: vclk5@e6150034 {
597 compatible = "renesas, 570 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
598 reg = <0 0xe6150034 0 571 reg = <0 0xe6150034 0 4>;
599 clocks = <&pll1_div2_c 572 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
600 <0>, <&extal2 573 <0>, <&extal2_clk>, <&main_div2_clk>,
601 <&extalr_clk> 574 <&extalr_clk>, <0>, <0>;
602 #clock-cells = <0>; 575 #clock-cells = <0>;
603 }; 576 };
604 fsia_clk: fsia@e6150018 { 577 fsia_clk: fsia@e6150018 {
605 compatible = "renesas, 578 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
606 reg = <0 0xe6150018 0 579 reg = <0 0xe6150018 0 4>;
607 clocks = <&pll1_div2_c 580 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
608 <&fsiack_clk> 581 <&fsiack_clk>, <0>;
609 #clock-cells = <0>; 582 #clock-cells = <0>;
610 }; 583 };
611 fsib_clk: fsib@e6150090 { 584 fsib_clk: fsib@e6150090 {
612 compatible = "renesas, 585 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
613 reg = <0 0xe6150090 0 586 reg = <0 0xe6150090 0 4>;
614 clocks = <&pll1_div2_c 587 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
615 <&fsibck_clk> 588 <&fsibck_clk>, <0>;
616 #clock-cells = <0>; 589 #clock-cells = <0>;
617 }; 590 };
618 mp_clk: mp@e6150080 { 591 mp_clk: mp@e6150080 {
619 compatible = "renesas, 592 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
620 reg = <0 0xe6150080 0 593 reg = <0 0xe6150080 0 4>;
621 clocks = <&pll1_div2_c 594 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
622 <&extal2_clk> 595 <&extal2_clk>, <&extal2_clk>;
623 #clock-cells = <0>; 596 #clock-cells = <0>;
624 }; 597 };
625 m4_clk: m4@e6150098 { 598 m4_clk: m4@e6150098 {
626 compatible = "renesas, 599 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
627 reg = <0 0xe6150098 0 600 reg = <0 0xe6150098 0 4>;
628 clocks = <&cpg_clocks 601 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
629 #clock-cells = <0>; 602 #clock-cells = <0>;
630 }; 603 };
631 hsi_clk: hsi@e615026c { 604 hsi_clk: hsi@e615026c {
632 compatible = "renesas, 605 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
633 reg = <0 0xe615026c 0 606 reg = <0 0xe615026c 0 4>;
634 clocks = <&cpg_clocks 607 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
635 <&cpg_clocks 608 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
636 #clock-cells = <0>; 609 #clock-cells = <0>;
637 }; 610 };
638 spuv_clk: spuv@e6150094 { 611 spuv_clk: spuv@e6150094 {
639 compatible = "renesas, 612 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
640 reg = <0 0xe6150094 0 613 reg = <0 0xe6150094 0 4>;
641 clocks = <&pll1_div2_c 614 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
642 <&extal2_clk> 615 <&extal2_clk>, <&extal2_clk>;
643 #clock-cells = <0>; 616 #clock-cells = <0>;
644 }; 617 };
645 618
646 /* Fixed factor clocks */ 619 /* Fixed factor clocks */
647 main_div2_clk: main_div2 { 620 main_div2_clk: main_div2 {
648 compatible = "fixed-fa 621 compatible = "fixed-factor-clock";
649 clocks = <&cpg_clocks 622 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
650 #clock-cells = <0>; 623 #clock-cells = <0>;
651 clock-div = <2>; 624 clock-div = <2>;
652 clock-mult = <1>; 625 clock-mult = <1>;
653 }; 626 };
654 cp_clk: cp { <<
655 compatible = "fixed-fa <<
656 clocks = <&main_div2_c <<
657 #clock-cells = <0>; <<
658 clock-div = <1>; <<
659 clock-mult = <1>; <<
660 }; <<
661 pll0_div2_clk: pll0_div2 { 627 pll0_div2_clk: pll0_div2 {
662 compatible = "fixed-fa 628 compatible = "fixed-factor-clock";
663 clocks = <&cpg_clocks 629 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
664 #clock-cells = <0>; 630 #clock-cells = <0>;
665 clock-div = <2>; 631 clock-div = <2>;
666 clock-mult = <1>; 632 clock-mult = <1>;
667 }; 633 };
668 pll1_div2_clk: pll1_div2 { 634 pll1_div2_clk: pll1_div2 {
669 compatible = "fixed-fa 635 compatible = "fixed-factor-clock";
670 clocks = <&cpg_clocks 636 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
671 #clock-cells = <0>; 637 #clock-cells = <0>;
672 clock-div = <2>; 638 clock-div = <2>;
673 clock-mult = <1>; 639 clock-mult = <1>;
674 }; 640 };
675 extal1_div2_clk: extal1_div2 { 641 extal1_div2_clk: extal1_div2 {
676 compatible = "fixed-fa 642 compatible = "fixed-factor-clock";
677 clocks = <&extal1_clk> 643 clocks = <&extal1_clk>;
678 #clock-cells = <0>; 644 #clock-cells = <0>;
679 clock-div = <2>; 645 clock-div = <2>;
680 clock-mult = <1>; 646 clock-mult = <1>;
681 }; 647 };
682 648
683 /* Gate clocks */ 649 /* Gate clocks */
684 mstp1_clks: mstp1_clks@e615013 <<
685 compatible = "renesas, <<
686 reg = <0 0xe6150134 0 <<
687 clocks = <&cp_clk>, <& <<
688 #clock-cells = <1>; <<
689 clock-indices = < <<
690 R8A73A4_CLK_TM <<
691 >; <<
692 clock-output-names = <<
693 "tmu0", "tmu3" <<
694 }; <<
695 mstp2_clks: mstp2_clks@e615013 650 mstp2_clks: mstp2_clks@e6150138 {
696 compatible = "renesas, 651 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
697 reg = <0 0xe6150138 0 652 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
698 clocks = <&mp_clk>, <& 653 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
699 <&mp_clk>, <& 654 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
700 #clock-cells = <1>; 655 #clock-cells = <1>;
701 clock-indices = < 656 clock-indices = <
702 R8A73A4_CLK_SC 657 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
703 R8A73A4_CLK_SC 658 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
704 R8A73A4_CLK_SC 659 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
705 R8A73A4_CLK_DM 660 R8A73A4_CLK_DMAC
706 >; 661 >;
707 clock-output-names = 662 clock-output-names =
708 "scifa0", "sci 663 "scifa0", "scifa1", "scifb0", "scifb1",
709 "scifb2", "sci 664 "scifb2", "scifb3", "dmac";
710 }; 665 };
711 mstp3_clks: mstp3_clks@e615013 666 mstp3_clks: mstp3_clks@e615013c {
712 compatible = "renesas, 667 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
713 reg = <0 0xe615013c 0 668 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
714 clocks = <&cpg_clocks 669 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
715 <&sdhi2_clk>, 670 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
716 <&mmc0_clk>, 671 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
717 <&cpg_clocks 672 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
718 R8A73A4_CLK_H 673 R8A73A4_CLK_HP>, <&cpg_clocks
719 R8A73A4_CLK_H 674 R8A73A4_CLK_HP>, <&extalr_clk>;
720 #clock-cells = <1>; 675 #clock-cells = <1>;
721 clock-indices = < 676 clock-indices = <
722 R8A73A4_CLK_II 677 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
723 R8A73A4_CLK_SD 678 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
724 R8A73A4_CLK_SD 679 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
725 R8A73A4_CLK_II 680 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
726 R8A73A4_CLK_II 681 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
727 R8A73A4_CLK_CM 682 R8A73A4_CLK_CMT1
728 >; 683 >;
729 clock-output-names = 684 clock-output-names =
730 "iic2", "mmcif 685 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
731 "mmcif0", "iic 686 "mmcif0", "iic6", "iic7", "iic0", "iic1",
732 "cmt1"; 687 "cmt1";
733 }; 688 };
734 mstp4_clks: mstp4_clks@e615014 689 mstp4_clks: mstp4_clks@e6150140 {
735 compatible = "renesas, 690 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
736 reg = <0 0xe6150140 0 691 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
737 clocks = <&cp_clk>, <& !! 692 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
738 <&cp_clk>, <& !! 693 <&main_div2_clk>,
>> 694 <&cpg_clocks R8A73A4_CLK_HP>,
739 <&cpg_clocks 695 <&cpg_clocks R8A73A4_CLK_HP>;
740 #clock-cells = <1>; 696 #clock-cells = <1>;
741 clock-indices = < 697 clock-indices = <
742 R8A73A4_CLK_IR 698 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
743 R8A73A4_CLK_II 699 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
744 R8A73A4_CLK_II 700 R8A73A4_CLK_IIC3
745 >; 701 >;
746 clock-output-names = 702 clock-output-names =
747 "irqc", "intc- 703 "irqc", "intc-sys", "iic5", "iic4", "iic3";
748 }; 704 };
749 mstp5_clks: mstp5_clks@e615014 705 mstp5_clks: mstp5_clks@e6150144 {
750 compatible = "renesas, 706 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
751 reg = <0 0xe6150144 0 707 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
752 clocks = <&cp_clk>, <& !! 708 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
753 #clock-cells = <1>; 709 #clock-cells = <1>;
754 clock-indices = < 710 clock-indices = <
755 R8A73A4_CLK_TH 711 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
756 >; 712 >;
757 clock-output-names = 713 clock-output-names =
758 "thermal", "ii 714 "thermal", "iic8";
759 }; 715 };
760 }; 716 };
761 717
762 prr: chipid@ff000044 { 718 prr: chipid@ff000044 {
763 compatible = "renesas,prr"; 719 compatible = "renesas,prr";
764 reg = <0 0xff000044 0 4>; 720 reg = <0 0xff000044 0 4>;
765 }; 721 };
766 722
767 sysc: system-controller@e6180000 { 723 sysc: system-controller@e6180000 {
768 compatible = "renesas,sysc-r8a 724 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
769 reg = <0 0xe6180000 0 0x8000>, 725 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
770 726
771 pm-domains { 727 pm-domains {
772 pd_c5: c5 { 728 pd_c5: c5 {
773 #address-cells 729 #address-cells = <1>;
774 #size-cells = 730 #size-cells = <0>;
775 #power-domain- 731 #power-domain-cells = <0>;
776 732
777 pd_c4: c4@0 { 733 pd_c4: c4@0 {
778 reg = 734 reg = <0>;
779 #addre 735 #address-cells = <1>;
780 #size- 736 #size-cells = <0>;
781 #power 737 #power-domain-cells = <0>;
782 738
783 pd_a3s 739 pd_a3sg: a3sg@16 {
784 740 reg = <16>;
785 741 #power-domain-cells = <0>;
786 }; 742 };
787 743
788 pd_a3e 744 pd_a3ex: a3ex@17 {
789 745 reg = <17>;
790 746 #power-domain-cells = <0>;
791 }; 747 };
792 748
793 pd_a3s 749 pd_a3sp: a3sp@18 {
794 750 reg = <18>;
795 751 #address-cells = <1>;
796 752 #size-cells = <0>;
797 753 #power-domain-cells = <0>;
798 754
799 755 pd_a2us: a2us@19 {
800 756 reg = <19>;
801 757 #power-domain-cells = <0>;
802 758 };
803 }; 759 };
804 760
805 pd_a3s 761 pd_a3sm: a3sm@20 {
806 762 reg = <20>;
807 763 #address-cells = <1>;
808 764 #size-cells = <0>;
809 765 #power-domain-cells = <0>;
810 766
811 767 pd_a2sl: a2sl@21 {
812 768 reg = <21>;
813 769 #power-domain-cells = <0>;
814 770 };
815 }; 771 };
816 772
817 pd_a3k 773 pd_a3km: a3km@22 {
818 774 reg = <22>;
819 775 #address-cells = <1>;
820 776 #size-cells = <0>;
821 777 #power-domain-cells = <0>;
822 778
823 779 pd_a2kl: a2kl@23 {
824 780 reg = <23>;
825 781 #power-domain-cells = <0>;
826 782 };
827 }; 783 };
828 }; 784 };
829 785
830 pd_c4ma: c4ma@ 786 pd_c4ma: c4ma@1 {
831 reg = 787 reg = <1>;
832 #power 788 #power-domain-cells = <0>;
833 }; 789 };
834 790
835 pd_c4cl: c4cl@ 791 pd_c4cl: c4cl@2 {
836 reg = 792 reg = <2>;
837 #power 793 #power-domain-cells = <0>;
838 }; 794 };
839 795
840 pd_d4: d4@3 { 796 pd_d4: d4@3 {
841 reg = 797 reg = <3>;
842 #power 798 #power-domain-cells = <0>;
843 }; 799 };
844 800
845 pd_a4bc: a4bc@ 801 pd_a4bc: a4bc@4 {
846 reg = 802 reg = <4>;
847 #addre 803 #address-cells = <1>;
848 #size- 804 #size-cells = <0>;
849 #power 805 #power-domain-cells = <0>;
850 806
851 pd_a3b 807 pd_a3bc: a3bc@5 {
852 808 reg = <5>;
853 809 #power-domain-cells = <0>;
854 }; 810 };
855 }; 811 };
856 812
857 pd_a4l: a4l@6 813 pd_a4l: a4l@6 {
858 reg = 814 reg = <6>;
859 #power 815 #power-domain-cells = <0>;
860 }; 816 };
861 817
862 pd_a4lc: a4lc@ 818 pd_a4lc: a4lc@7 {
863 reg = 819 reg = <7>;
864 #power 820 #power-domain-cells = <0>;
865 }; 821 };
866 822
867 pd_a4mp: a4mp@ 823 pd_a4mp: a4mp@8 {
868 reg = 824 reg = <8>;
869 #addre 825 #address-cells = <1>;
870 #size- 826 #size-cells = <0>;
871 #power 827 #power-domain-cells = <0>;
872 828
873 pd_a3m 829 pd_a3mp: a3mp@9 {
874 830 reg = <9>;
875 831 #power-domain-cells = <0>;
876 }; 832 };
877 833
878 pd_a3v 834 pd_a3vc: a3vc@10 {
879 835 reg = <10>;
880 836 #power-domain-cells = <0>;
881 }; 837 };
882 }; 838 };
883 839
884 pd_a4sf: a4sf@ 840 pd_a4sf: a4sf@11 {
885 reg = 841 reg = <11>;
886 #power 842 #power-domain-cells = <0>;
887 }; 843 };
888 844
889 pd_a3r: a3r@12 845 pd_a3r: a3r@12 {
890 reg = 846 reg = <12>;
891 #addre 847 #address-cells = <1>;
892 #size- 848 #size-cells = <0>;
893 #power 849 #power-domain-cells = <0>;
894 850
895 pd_a2r 851 pd_a2rv: a2rv@13 {
896 852 reg = <13>;
897 853 #power-domain-cells = <0>;
898 }; 854 };
899 855
900 pd_a2i 856 pd_a2is: a2is@14 {
901 857 reg = <14>;
902 858 #power-domain-cells = <0>;
903 }; 859 };
904 }; 860 };
905 }; 861 };
906 }; 862 };
907 }; 863 };
908 }; 864 };
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