1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Mobile A1 (R8A 3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
4 * 4 *
5 * Copyright (C) 2012 Renesas Solutions Corp. 5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7740-clock.h> 8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a7740"; 13 compatible = "renesas,r8a7740";
14 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 17
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 cpu@0 { 21 cpu@0 {
22 compatible = "arm,cort 22 compatible = "arm,cortex-a9";
23 device_type = "cpu"; 23 device_type = "cpu";
24 reg = <0x0>; 24 reg = <0x0>;
25 clock-frequency = <800 25 clock-frequency = <800000000>;
26 power-domains = <&pd_a 26 power-domains = <&pd_a3sm>;
27 next-level-cache = <&L 27 next-level-cache = <&L2>;
28 }; 28 };
29 }; 29 };
30 30
31 gic: interrupt-controller@c2800000 { 31 gic: interrupt-controller@c2800000 {
32 compatible = "arm,pl390"; 32 compatible = "arm,pl390";
33 #interrupt-cells = <3>; 33 #interrupt-cells = <3>;
34 interrupt-controller; 34 interrupt-controller;
35 reg = <0xc2800000 0x1000>, 35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>; 36 <0xc2000000 0x1000>;
37 }; 37 };
38 38
39 L2: cache-controller@f0100000 { 39 L2: cache-controller@f0100000 {
40 compatible = "arm,pl310-cache" 40 compatible = "arm,pl310-cache";
41 reg = <0xf0100000 0x1000>; 41 reg = <0xf0100000 0x1000>;
42 interrupts = <GIC_SPI 84 IRQ_T 42 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
43 power-domains = <&pd_a3sm>; 43 power-domains = <&pd_a3sm>;
44 arm,data-latency = <3 3 3>; 44 arm,data-latency = <3 3 3>;
45 arm,tag-latency = <2 2 2>; 45 arm,tag-latency = <2 2 2>;
46 arm,shared-override; 46 arm,shared-override;
47 cache-unified; 47 cache-unified;
48 cache-level = <2>; 48 cache-level = <2>;
49 }; 49 };
50 50
51 dbsc3: memory-controller@fe400000 { 51 dbsc3: memory-controller@fe400000 {
52 compatible = "renesas,dbsc3-r8 52 compatible = "renesas,dbsc3-r8a7740";
53 reg = <0xfe400000 0x400>; 53 reg = <0xfe400000 0x400>;
54 power-domains = <&pd_a4s>; 54 power-domains = <&pd_a4s>;
55 }; 55 };
56 56
57 pmu { 57 pmu {
58 compatible = "arm,cortex-a9-pm 58 compatible = "arm,cortex-a9-pmu";
59 interrupts = <GIC_SPI 83 IRQ_T 59 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
60 }; 60 };
61 61
62 ptm { 62 ptm {
63 compatible = "arm,coresight-et 63 compatible = "arm,coresight-etm3x";
64 power-domains = <&pd_d4>; 64 power-domains = <&pd_d4>;
65 }; 65 };
66 66
67 ceu0: ceu@fe910000 { 67 ceu0: ceu@fe910000 {
68 reg = <0xfe910000 0x3000>; 68 reg = <0xfe910000 0x3000>;
69 compatible = "renesas,r8a7740- 69 compatible = "renesas,r8a7740-ceu";
70 interrupts = <GIC_SPI 160 IRQ_ 70 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&mstp1_clks R8A7740_ 71 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
72 power-domains = <&pd_a4r>; 72 power-domains = <&pd_a4r>;
73 status = "disabled"; 73 status = "disabled";
74 }; 74 };
75 75
76 ceu1: ceu@fe914000 { 76 ceu1: ceu@fe914000 {
77 reg = <0xfe914000 0x3000>; 77 reg = <0xfe914000 0x3000>;
78 compatible = "renesas,r8a7740- 78 compatible = "renesas,r8a7740-ceu";
79 interrupts = <GIC_SPI 159 IRQ_ 79 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&mstp1_clks R8A7740_ 80 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
81 power-domains = <&pd_a4r>; 81 power-domains = <&pd_a4r>;
82 status = "disabled"; 82 status = "disabled";
83 }; 83 };
84 84
85 cmt1: timer@e6138000 { 85 cmt1: timer@e6138000 {
86 compatible = "renesas,r8a7740- 86 compatible = "renesas,r8a7740-cmt1";
87 reg = <0xe6138000 0x170>; 87 reg = <0xe6138000 0x170>;
88 interrupts = <GIC_SPI 58 IRQ_T 88 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&mstp3_clks R8A7740_ 89 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
90 clock-names = "fck"; 90 clock-names = "fck";
91 power-domains = <&pd_c5>; 91 power-domains = <&pd_c5>;
92 status = "disabled"; 92 status = "disabled";
93 }; 93 };
94 94
95 /* irqpin0: IRQ0 - IRQ7 */ 95 /* irqpin0: IRQ0 - IRQ7 */
96 irqpin0: interrupt-controller@e6900000 96 irqpin0: interrupt-controller@e6900000 {
97 compatible = "renesas,intc-irq 97 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
98 #interrupt-cells = <2>; 98 #interrupt-cells = <2>;
99 interrupt-controller; 99 interrupt-controller;
100 reg = <0xe6900000 4>, 100 reg = <0xe6900000 4>,
101 <0xe6900010 4>, 101 <0xe6900010 4>,
102 <0xe6900020 1>, 102 <0xe6900020 1>,
103 <0xe6900040 1>, 103 <0xe6900040 1>,
104 <0xe6900060 1>; 104 <0xe6900060 1>;
105 interrupts = <GIC_SPI 149 IRQ_ 105 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 149 IRQ_ 106 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 149 IRQ_ 107 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 149 IRQ_ 108 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 149 IRQ_ 109 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 149 IRQ_ 110 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 149 IRQ_ 111 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 149 IRQ_ 112 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&mstp2_clks R8A7740_ 113 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
114 power-domains = <&pd_a4s>; 114 power-domains = <&pd_a4s>;
115 }; 115 };
116 116
117 /* irqpin1: IRQ8 - IRQ15 */ 117 /* irqpin1: IRQ8 - IRQ15 */
118 irqpin1: interrupt-controller@e6900004 118 irqpin1: interrupt-controller@e6900004 {
119 compatible = "renesas,intc-irq 119 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
120 #interrupt-cells = <2>; 120 #interrupt-cells = <2>;
121 interrupt-controller; 121 interrupt-controller;
122 reg = <0xe6900004 4>, 122 reg = <0xe6900004 4>,
123 <0xe6900014 4>, 123 <0xe6900014 4>,
124 <0xe6900024 1>, 124 <0xe6900024 1>,
125 <0xe6900044 1>, 125 <0xe6900044 1>,
126 <0xe6900064 1>; 126 <0xe6900064 1>;
127 interrupts = <GIC_SPI 149 IRQ_ 127 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 149 IRQ_ 128 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 149 IRQ_ 129 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 149 IRQ_ 130 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 149 IRQ_ 131 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 149 IRQ_ 132 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 149 IRQ_ 133 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 149 IRQ_ 134 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&mstp2_clks R8A7740_ 135 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
136 power-domains = <&pd_a4s>; 136 power-domains = <&pd_a4s>;
137 }; 137 };
138 138
139 /* irqpin2: IRQ16 - IRQ23 */ 139 /* irqpin2: IRQ16 - IRQ23 */
140 irqpin2: interrupt-controller@e6900008 140 irqpin2: interrupt-controller@e6900008 {
141 compatible = "renesas,intc-irq 141 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
142 #interrupt-cells = <2>; 142 #interrupt-cells = <2>;
143 interrupt-controller; 143 interrupt-controller;
144 reg = <0xe6900008 4>, 144 reg = <0xe6900008 4>,
145 <0xe6900018 4>, 145 <0xe6900018 4>,
146 <0xe6900028 1>, 146 <0xe6900028 1>,
147 <0xe6900048 1>, 147 <0xe6900048 1>,
148 <0xe6900068 1>; 148 <0xe6900068 1>;
149 interrupts = <GIC_SPI 149 IRQ_ 149 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 149 IRQ_ 150 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 149 IRQ_ 151 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 149 IRQ_ 152 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 149 IRQ_ 153 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 149 IRQ_ 154 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 149 IRQ_ 155 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 149 IRQ_ 156 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&mstp2_clks R8A7740_ 157 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
158 power-domains = <&pd_a4s>; 158 power-domains = <&pd_a4s>;
159 }; 159 };
160 160
161 /* irqpin3: IRQ24 - IRQ31 */ 161 /* irqpin3: IRQ24 - IRQ31 */
162 irqpin3: interrupt-controller@e690000c 162 irqpin3: interrupt-controller@e690000c {
163 compatible = "renesas,intc-irq 163 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
164 #interrupt-cells = <2>; 164 #interrupt-cells = <2>;
165 interrupt-controller; 165 interrupt-controller;
166 reg = <0xe690000c 4>, 166 reg = <0xe690000c 4>,
167 <0xe690001c 4>, 167 <0xe690001c 4>,
168 <0xe690002c 1>, 168 <0xe690002c 1>,
169 <0xe690004c 1>, 169 <0xe690004c 1>,
170 <0xe690006c 1>; 170 <0xe690006c 1>;
171 interrupts = <GIC_SPI 149 IRQ_ 171 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 149 IRQ_ 172 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 149 IRQ_ 173 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 149 IRQ_ 174 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 149 IRQ_ 175 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 149 IRQ_ 176 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 149 IRQ_ 177 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 149 IRQ_ 178 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp2_clks R8A7740_ 179 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
180 power-domains = <&pd_a4s>; 180 power-domains = <&pd_a4s>;
181 }; 181 };
182 182
183 ether: ethernet@e9a00000 { 183 ether: ethernet@e9a00000 {
184 compatible = "renesas,gether-r 184 compatible = "renesas,gether-r8a7740";
185 reg = <0xe9a00000 0x800>, 185 reg = <0xe9a00000 0x800>,
186 <0xe9a01800 0x800>; 186 <0xe9a01800 0x800>;
187 interrupts = <GIC_SPI 110 IRQ_ 187 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&mstp3_clks R8A7740_ 188 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
189 power-domains = <&pd_a4s>; 189 power-domains = <&pd_a4s>;
190 phy-mode = "mii"; 190 phy-mode = "mii";
191 #address-cells = <1>; 191 #address-cells = <1>;
192 #size-cells = <0>; 192 #size-cells = <0>;
193 status = "disabled"; 193 status = "disabled";
194 }; 194 };
195 195
196 i2c0: i2c@fff20000 { 196 i2c0: i2c@fff20000 {
197 #address-cells = <1>; 197 #address-cells = <1>;
198 #size-cells = <0>; 198 #size-cells = <0>;
199 compatible = "renesas,iic-r8a7 199 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
200 reg = <0xfff20000 0x425>; 200 reg = <0xfff20000 0x425>;
201 interrupts = <GIC_SPI 201 IRQ_ 201 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 202 IRQ_ 202 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 203 IRQ_ 203 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 204 IRQ_ 204 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp1_clks R8A7740_ 205 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
206 power-domains = <&pd_a4r>; 206 power-domains = <&pd_a4r>;
207 status = "disabled"; 207 status = "disabled";
208 }; 208 };
209 209
210 i2c1: i2c@e6c20000 { 210 i2c1: i2c@e6c20000 {
211 #address-cells = <1>; 211 #address-cells = <1>;
212 #size-cells = <0>; 212 #size-cells = <0>;
213 compatible = "renesas,iic-r8a7 213 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
214 reg = <0xe6c20000 0x425>; 214 reg = <0xe6c20000 0x425>;
215 interrupts = <GIC_SPI 70 IRQ_T 215 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 71 IRQ_T 216 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 72 IRQ_T 217 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 73 IRQ_T 218 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7740_ 219 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
220 power-domains = <&pd_a3sp>; 220 power-domains = <&pd_a3sp>;
221 status = "disabled"; 221 status = "disabled";
222 }; 222 };
223 223
224 scifa0: serial@e6c40000 { 224 scifa0: serial@e6c40000 {
225 compatible = "renesas,scifa-r8 225 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
226 reg = <0xe6c40000 0x100>; 226 reg = <0xe6c40000 0x100>;
227 interrupts = <GIC_SPI 100 IRQ_ 227 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&mstp2_clks R8A7740_ 228 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
229 clock-names = "fck"; 229 clock-names = "fck";
230 power-domains = <&pd_a3sp>; 230 power-domains = <&pd_a3sp>;
231 status = "disabled"; 231 status = "disabled";
232 }; 232 };
233 233
234 scifa1: serial@e6c50000 { 234 scifa1: serial@e6c50000 {
235 compatible = "renesas,scifa-r8 235 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
236 reg = <0xe6c50000 0x100>; 236 reg = <0xe6c50000 0x100>;
237 interrupts = <GIC_SPI 101 IRQ_ 237 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&mstp2_clks R8A7740_ 238 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
239 clock-names = "fck"; 239 clock-names = "fck";
240 power-domains = <&pd_a3sp>; 240 power-domains = <&pd_a3sp>;
241 status = "disabled"; 241 status = "disabled";
242 }; 242 };
243 243
244 scifa2: serial@e6c60000 { 244 scifa2: serial@e6c60000 {
245 compatible = "renesas,scifa-r8 245 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
246 reg = <0xe6c60000 0x100>; 246 reg = <0xe6c60000 0x100>;
247 interrupts = <GIC_SPI 102 IRQ_ 247 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&mstp2_clks R8A7740_ 248 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
249 clock-names = "fck"; 249 clock-names = "fck";
250 power-domains = <&pd_a3sp>; 250 power-domains = <&pd_a3sp>;
251 status = "disabled"; 251 status = "disabled";
252 }; 252 };
253 253
254 scifa3: serial@e6c70000 { 254 scifa3: serial@e6c70000 {
255 compatible = "renesas,scifa-r8 255 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
256 reg = <0xe6c70000 0x100>; 256 reg = <0xe6c70000 0x100>;
257 interrupts = <GIC_SPI 103 IRQ_ 257 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp2_clks R8A7740_ 258 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
259 clock-names = "fck"; 259 clock-names = "fck";
260 power-domains = <&pd_a3sp>; 260 power-domains = <&pd_a3sp>;
261 status = "disabled"; 261 status = "disabled";
262 }; 262 };
263 263
264 scifa4: serial@e6c80000 { 264 scifa4: serial@e6c80000 {
265 compatible = "renesas,scifa-r8 265 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
266 reg = <0xe6c80000 0x100>; 266 reg = <0xe6c80000 0x100>;
267 interrupts = <GIC_SPI 104 IRQ_ 267 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp2_clks R8A7740_ 268 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
269 clock-names = "fck"; 269 clock-names = "fck";
270 power-domains = <&pd_a3sp>; 270 power-domains = <&pd_a3sp>;
271 status = "disabled"; 271 status = "disabled";
272 }; 272 };
273 273
274 scifa5: serial@e6cb0000 { 274 scifa5: serial@e6cb0000 {
275 compatible = "renesas,scifa-r8 275 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
276 reg = <0xe6cb0000 0x100>; 276 reg = <0xe6cb0000 0x100>;
277 interrupts = <GIC_SPI 105 IRQ_ 277 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&mstp2_clks R8A7740_ 278 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
279 clock-names = "fck"; 279 clock-names = "fck";
280 power-domains = <&pd_a3sp>; 280 power-domains = <&pd_a3sp>;
281 status = "disabled"; 281 status = "disabled";
282 }; 282 };
283 283
284 scifa6: serial@e6cc0000 { 284 scifa6: serial@e6cc0000 {
285 compatible = "renesas,scifa-r8 285 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
286 reg = <0xe6cc0000 0x100>; 286 reg = <0xe6cc0000 0x100>;
287 interrupts = <GIC_SPI 106 IRQ_ 287 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp2_clks R8A7740_ 288 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
289 clock-names = "fck"; 289 clock-names = "fck";
290 power-domains = <&pd_a3sp>; 290 power-domains = <&pd_a3sp>;
291 status = "disabled"; 291 status = "disabled";
292 }; 292 };
293 293
294 scifa7: serial@e6cd0000 { 294 scifa7: serial@e6cd0000 {
295 compatible = "renesas,scifa-r8 295 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
296 reg = <0xe6cd0000 0x100>; 296 reg = <0xe6cd0000 0x100>;
297 interrupts = <GIC_SPI 107 IRQ_ 297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp2_clks R8A7740_ 298 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
299 clock-names = "fck"; 299 clock-names = "fck";
300 power-domains = <&pd_a3sp>; 300 power-domains = <&pd_a3sp>;
301 status = "disabled"; 301 status = "disabled";
302 }; 302 };
303 303
304 scifb: serial@e6c30000 { 304 scifb: serial@e6c30000 {
305 compatible = "renesas,scifb-r8 305 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
306 reg = <0xe6c30000 0x100>; 306 reg = <0xe6c30000 0x100>;
307 interrupts = <GIC_SPI 108 IRQ_ 307 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp2_clks R8A7740_ 308 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
309 clock-names = "fck"; 309 clock-names = "fck";
310 power-domains = <&pd_a3sp>; 310 power-domains = <&pd_a3sp>;
311 status = "disabled"; 311 status = "disabled";
312 }; 312 };
313 313
314 pfc: pinctrl@e6050000 { 314 pfc: pinctrl@e6050000 {
315 compatible = "renesas,pfc-r8a7 315 compatible = "renesas,pfc-r8a7740";
316 reg = <0xe6050000 0x8000>, 316 reg = <0xe6050000 0x8000>,
317 <0xe605800c 0x20>; 317 <0xe605800c 0x20>;
318 gpio-controller; 318 gpio-controller;
319 #gpio-cells = <2>; 319 #gpio-cells = <2>;
320 gpio-ranges = <&pfc 0 0 212>; 320 gpio-ranges = <&pfc 0 0 212>;
321 interrupts-extended = 321 interrupts-extended =
322 <&irqpin0 0 0>, <&irqp 322 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
323 <&irqpin0 4 0>, <&irqp 323 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
324 <&irqpin1 0 0>, <&irqp 324 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
325 <&irqpin1 4 0>, <&irqp 325 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
326 <&irqpin2 0 0>, <&irqp 326 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
327 <&irqpin2 4 0>, <&irqp 327 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
328 <&irqpin3 0 0>, <&irqp 328 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
329 <&irqpin3 4 0>, <&irqp 329 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
330 power-domains = <&pd_c5>; 330 power-domains = <&pd_c5>;
331 }; 331 };
332 332
333 tpu: pwm@e6600000 { 333 tpu: pwm@e6600000 {
334 compatible = "renesas,tpu-r8a7 334 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
335 reg = <0xe6600000 0x148>; 335 reg = <0xe6600000 0x148>;
336 clocks = <&mstp3_clks R8A7740_ 336 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
337 power-domains = <&pd_a3sp>; 337 power-domains = <&pd_a3sp>;
338 status = "disabled"; 338 status = "disabled";
339 #pwm-cells = <3>; 339 #pwm-cells = <3>;
340 }; 340 };
341 341
342 mmcif0: mmc@e6bd0000 { 342 mmcif0: mmc@e6bd0000 {
343 compatible = "renesas,mmcif-r8 343 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
344 reg = <0xe6bd0000 0x100>; 344 reg = <0xe6bd0000 0x100>;
345 interrupts = <GIC_SPI 56 IRQ_T 345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 57 IRQ_T 346 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp3_clks R8A7740_ 347 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
348 power-domains = <&pd_a3sp>; 348 power-domains = <&pd_a3sp>;
349 status = "disabled"; 349 status = "disabled";
350 }; 350 };
351 351
352 sdhi0: mmc@e6850000 { 352 sdhi0: mmc@e6850000 {
353 compatible = "renesas,sdhi-r8a 353 compatible = "renesas,sdhi-r8a7740";
354 reg = <0xe6850000 0x100>; 354 reg = <0xe6850000 0x100>;
355 interrupts = <GIC_SPI 117 IRQ_ 355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 118 IRQ_ 356 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 119 IRQ_ 357 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp3_clks R8A7740_ 358 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
359 power-domains = <&pd_a3sp>; 359 power-domains = <&pd_a3sp>;
360 cap-sd-highspeed; 360 cap-sd-highspeed;
361 cap-sdio-irq; 361 cap-sdio-irq;
362 status = "disabled"; 362 status = "disabled";
363 }; 363 };
364 364
365 sdhi1: mmc@e6860000 { 365 sdhi1: mmc@e6860000 {
366 compatible = "renesas,sdhi-r8a 366 compatible = "renesas,sdhi-r8a7740";
367 reg = <0xe6860000 0x100>; 367 reg = <0xe6860000 0x100>;
368 interrupts = <GIC_SPI 121 IRQ_ 368 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 122 IRQ_ 369 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 123 IRQ_ 370 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7740_ 371 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
372 power-domains = <&pd_a3sp>; 372 power-domains = <&pd_a3sp>;
373 cap-sd-highspeed; 373 cap-sd-highspeed;
374 cap-sdio-irq; 374 cap-sdio-irq;
375 status = "disabled"; 375 status = "disabled";
376 }; 376 };
377 377
378 sdhi2: mmc@e6870000 { 378 sdhi2: mmc@e6870000 {
379 compatible = "renesas,sdhi-r8a 379 compatible = "renesas,sdhi-r8a7740";
380 reg = <0xe6870000 0x100>; 380 reg = <0xe6870000 0x100>;
381 interrupts = <GIC_SPI 125 IRQ_ 381 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 126 IRQ_ 382 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 127 IRQ_ 383 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp4_clks R8A7740_ 384 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
385 power-domains = <&pd_a3sp>; 385 power-domains = <&pd_a3sp>;
386 cap-sd-highspeed; 386 cap-sd-highspeed;
387 cap-sdio-irq; 387 cap-sdio-irq;
388 status = "disabled"; 388 status = "disabled";
389 }; 389 };
390 390
391 sh_fsi2: sound@fe1f0000 { 391 sh_fsi2: sound@fe1f0000 {
392 #sound-dai-cells = <1>; 392 #sound-dai-cells = <1>;
393 compatible = "renesas,fsi2-r8a 393 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
394 reg = <0xfe1f0000 0x400>; 394 reg = <0xfe1f0000 0x400>;
395 interrupts = <GIC_SPI 9 0x4>; 395 interrupts = <GIC_SPI 9 0x4>;
396 clocks = <&mstp3_clks R8A7740_ 396 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
397 power-domains = <&pd_a4mp>; 397 power-domains = <&pd_a4mp>;
398 status = "disabled"; 398 status = "disabled";
399 }; 399 };
400 400
401 lcdc0: lcd-controller@fe940000 { 401 lcdc0: lcd-controller@fe940000 {
402 compatible = "renesas,r8a7740- 402 compatible = "renesas,r8a7740-lcdc";
403 reg = <0xfe940000 0x4000>; 403 reg = <0xfe940000 0x4000>;
404 interrupts = <GIC_SPI 177 IRQ_ 404 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp1_clks R8A7740_ 405 clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
406 <&cpg_clocks R8A7740_ 406 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
407 <&vou_clk>; 407 <&vou_clk>;
408 clock-names = "fck", "media", 408 clock-names = "fck", "media", "lclk", "video";
409 power-domains = <&pd_a4lc>; 409 power-domains = <&pd_a4lc>;
410 status = "disabled"; 410 status = "disabled";
411 411
412 ports { 412 ports {
413 #address-cells = <1>; 413 #address-cells = <1>;
414 #size-cells = <0>; 414 #size-cells = <0>;
415 415
416 port@0 { 416 port@0 {
417 reg = <0>; 417 reg = <0>;
418 418
419 lcdc0_rgb: end 419 lcdc0_rgb: endpoint {
420 }; 420 };
421 }; 421 };
422 }; 422 };
423 }; 423 };
424 424
425 lcdc1: lcd-controller@fe944000 { 425 lcdc1: lcd-controller@fe944000 {
426 compatible = "renesas,r8a7740- 426 compatible = "renesas,r8a7740-lcdc";
427 reg = <0xfe944000 0x4000>; 427 reg = <0xfe944000 0x4000>;
428 interrupts = <GIC_SPI 178 IRQ_ 428 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp1_clks R8A7740_ 429 clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
430 <&cpg_clocks R8A7740_ 430 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>,
431 <&vou_clk>; 431 <&vou_clk>;
432 clock-names = "fck", "media", 432 clock-names = "fck", "media", "lclk", "video";
433 power-domains = <&pd_a4lc>; 433 power-domains = <&pd_a4lc>;
434 status = "disabled"; 434 status = "disabled";
435 435
436 ports { 436 ports {
437 #address-cells = <1>; 437 #address-cells = <1>;
438 #size-cells = <0>; 438 #size-cells = <0>;
439 439
440 port@0 { 440 port@0 {
441 reg = <0>; 441 reg = <0>;
442 442
443 lcdc1_rgb: end 443 lcdc1_rgb: endpoint {
444 }; 444 };
445 }; 445 };
446 446
447 port@1 { 447 port@1 {
448 reg = <1>; 448 reg = <1>;
449 449
450 lcdc1_hdmi: en 450 lcdc1_hdmi: endpoint {
451 }; 451 };
452 }; 452 };
453 }; 453 };
454 }; 454 };
455 455
456 tmu0: timer@fff80000 { 456 tmu0: timer@fff80000 {
457 compatible = "renesas,tmu-r8a7 457 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
458 reg = <0xfff80000 0x2c>; 458 reg = <0xfff80000 0x2c>;
459 interrupts = <GIC_SPI 198 IRQ_ 459 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 199 IRQ_ 460 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 200 IRQ_ 461 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "tuni0", "tu <<
463 clocks = <&mstp1_clks R8A7740_ 462 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
464 clock-names = "fck"; 463 clock-names = "fck";
465 power-domains = <&pd_a4r>; 464 power-domains = <&pd_a4r>;
466 465
467 #renesas,channels = <3>; 466 #renesas,channels = <3>;
468 467
469 status = "disabled"; 468 status = "disabled";
470 }; 469 };
471 470
472 tmu1: timer@fff90000 { 471 tmu1: timer@fff90000 {
473 compatible = "renesas,tmu-r8a7 472 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
474 reg = <0xfff90000 0x2c>; 473 reg = <0xfff90000 0x2c>;
475 interrupts = <GIC_SPI 170 IRQ_ 474 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 171 IRQ_ 475 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 172 IRQ_ 476 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
478 interrupt-names = "tuni0", "tu <<
479 clocks = <&mstp1_clks R8A7740_ 477 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
480 clock-names = "fck"; 478 clock-names = "fck";
481 power-domains = <&pd_a4r>; 479 power-domains = <&pd_a4r>;
482 480
483 #renesas,channels = <3>; 481 #renesas,channels = <3>;
484 482
485 status = "disabled"; 483 status = "disabled";
486 }; 484 };
487 485
488 clocks { 486 clocks {
489 #address-cells = <1>; 487 #address-cells = <1>;
490 #size-cells = <1>; 488 #size-cells = <1>;
491 ranges; 489 ranges;
492 490
493 /* External root clock */ 491 /* External root clock */
494 extalr_clk: extalr { 492 extalr_clk: extalr {
495 compatible = "fixed-cl 493 compatible = "fixed-clock";
496 #clock-cells = <0>; 494 #clock-cells = <0>;
497 clock-frequency = <327 495 clock-frequency = <32768>;
498 }; 496 };
499 extal1_clk: extal1 { 497 extal1_clk: extal1 {
500 compatible = "fixed-cl 498 compatible = "fixed-clock";
501 #clock-cells = <0>; 499 #clock-cells = <0>;
502 clock-frequency = <0>; 500 clock-frequency = <0>;
503 }; 501 };
504 extal2_clk: extal2 { 502 extal2_clk: extal2 {
505 compatible = "fixed-cl 503 compatible = "fixed-clock";
506 #clock-cells = <0>; 504 #clock-cells = <0>;
507 clock-frequency = <0>; 505 clock-frequency = <0>;
508 }; 506 };
509 dv_clk: dv { 507 dv_clk: dv {
510 compatible = "fixed-cl 508 compatible = "fixed-clock";
511 #clock-cells = <0>; 509 #clock-cells = <0>;
512 clock-frequency = <270 510 clock-frequency = <27000000>;
513 }; 511 };
514 fmsick_clk: fmsick { 512 fmsick_clk: fmsick {
515 compatible = "fixed-cl 513 compatible = "fixed-clock";
516 #clock-cells = <0>; 514 #clock-cells = <0>;
517 clock-frequency = <0>; 515 clock-frequency = <0>;
518 }; 516 };
519 fmsock_clk: fmsock { 517 fmsock_clk: fmsock {
520 compatible = "fixed-cl 518 compatible = "fixed-clock";
521 #clock-cells = <0>; 519 #clock-cells = <0>;
522 clock-frequency = <0>; 520 clock-frequency = <0>;
523 }; 521 };
524 fsiack_clk: fsiack { 522 fsiack_clk: fsiack {
525 compatible = "fixed-cl 523 compatible = "fixed-clock";
526 #clock-cells = <0>; 524 #clock-cells = <0>;
527 clock-frequency = <0>; 525 clock-frequency = <0>;
528 }; 526 };
529 fsibck_clk: fsibck { 527 fsibck_clk: fsibck {
530 compatible = "fixed-cl 528 compatible = "fixed-clock";
531 #clock-cells = <0>; 529 #clock-cells = <0>;
532 clock-frequency = <0>; 530 clock-frequency = <0>;
533 }; 531 };
534 lcdlclk0_clk: lcdlclk0 { 532 lcdlclk0_clk: lcdlclk0 {
535 compatible = "fixed-cl 533 compatible = "fixed-clock";
536 #clock-cells = <0>; 534 #clock-cells = <0>;
537 clock-frequency = <0>; 535 clock-frequency = <0>;
538 }; 536 };
539 lcdlclk1_clk: lcdlclk1 { 537 lcdlclk1_clk: lcdlclk1 {
540 compatible = "fixed-cl 538 compatible = "fixed-clock";
541 #clock-cells = <0>; 539 #clock-cells = <0>;
542 clock-frequency = <0>; 540 clock-frequency = <0>;
543 }; 541 };
544 542
545 /* Special CPG clocks */ 543 /* Special CPG clocks */
546 cpg_clocks: cpg_clocks@e615000 544 cpg_clocks: cpg_clocks@e6150000 {
547 compatible = "renesas, 545 compatible = "renesas,r8a7740-cpg-clocks";
548 reg = <0xe6150000 0x10 546 reg = <0xe6150000 0x10000>;
549 clocks = <&extal1_clk> 547 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
550 #clock-cells = <1>; 548 #clock-cells = <1>;
551 clock-output-names = " 549 clock-output-names = "system", "pllc0", "pllc1",
552 " 550 "pllc2", "r",
553 " 551 "usb24s",
554 " 552 "i", "zg", "b", "m1", "hp",
555 " 553 "hpp", "usbp", "s", "zb", "m3",
556 " 554 "cp";
557 }; 555 };
558 556
559 /* Variable factor clocks (DIV 557 /* Variable factor clocks (DIV6) */
560 vclk1_clk: vclk1@e6150008 { 558 vclk1_clk: vclk1@e6150008 {
561 compatible = "renesas, 559 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
562 reg = <0xe6150008 4>; 560 reg = <0xe6150008 4>;
563 clocks = <&pllc1_div2_ 561 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
564 <&cpg_clocks 562 <&cpg_clocks R8A7740_CLK_USB24S>,
565 <&extal1_div2 563 <&extal1_div2_clk>, <&extalr_clk>, <0>,
566 <0>; 564 <0>;
567 #clock-cells = <0>; 565 #clock-cells = <0>;
568 }; 566 };
569 vclk2_clk: vclk2@e615000c { 567 vclk2_clk: vclk2@e615000c {
570 compatible = "renesas, 568 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
571 reg = <0xe615000c 4>; 569 reg = <0xe615000c 4>;
572 clocks = <&pllc1_div2_ 570 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
573 <&cpg_clocks 571 <&cpg_clocks R8A7740_CLK_USB24S>,
574 <&extal1_div2 572 <&extal1_div2_clk>, <&extalr_clk>, <0>,
575 <0>; 573 <0>;
576 #clock-cells = <0>; 574 #clock-cells = <0>;
577 }; 575 };
578 fmsi_clk: fmsi@e6150010 { 576 fmsi_clk: fmsi@e6150010 {
579 compatible = "renesas, 577 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
580 reg = <0xe6150010 4>; 578 reg = <0xe6150010 4>;
581 clocks = <&pllc1_div2_ 579 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
582 #clock-cells = <0>; 580 #clock-cells = <0>;
583 }; 581 };
584 fmso_clk: fmso@e6150014 { 582 fmso_clk: fmso@e6150014 {
585 compatible = "renesas, 583 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
586 reg = <0xe6150014 4>; 584 reg = <0xe6150014 4>;
587 clocks = <&pllc1_div2_ 585 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
588 #clock-cells = <0>; 586 #clock-cells = <0>;
589 }; 587 };
590 fsia_clk: fsia@e6150018 { 588 fsia_clk: fsia@e6150018 {
591 compatible = "renesas, 589 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
592 reg = <0xe6150018 4>; 590 reg = <0xe6150018 4>;
593 clocks = <&pllc1_div2_ 591 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
594 #clock-cells = <0>; 592 #clock-cells = <0>;
595 }; 593 };
596 sub_clk: sub@e6150080 { 594 sub_clk: sub@e6150080 {
597 compatible = "renesas, 595 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
598 reg = <0xe6150080 4>; 596 reg = <0xe6150080 4>;
599 clocks = <&pllc1_div2_ 597 clocks = <&pllc1_div2_clk>,
600 <&cpg_clocks 598 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
601 #clock-cells = <0>; 599 #clock-cells = <0>;
602 }; 600 };
603 spu_clk: spu@e6150084 { 601 spu_clk: spu@e6150084 {
604 compatible = "renesas, 602 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
605 reg = <0xe6150084 4>; 603 reg = <0xe6150084 4>;
606 clocks = <&pllc1_div2_ 604 clocks = <&pllc1_div2_clk>,
607 <&cpg_clocks 605 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
608 #clock-cells = <0>; 606 #clock-cells = <0>;
609 }; 607 };
610 vou_clk: vou@e6150088 { 608 vou_clk: vou@e6150088 {
611 compatible = "renesas, 609 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
612 reg = <0xe6150088 4>; 610 reg = <0xe6150088 4>;
613 clocks = <&pllc1_div2_ 611 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
614 <0>; 612 <0>;
615 #clock-cells = <0>; 613 #clock-cells = <0>;
616 }; 614 };
617 stpro_clk: stpro@e615009c { 615 stpro_clk: stpro@e615009c {
618 compatible = "renesas, 616 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
619 reg = <0xe615009c 4>; 617 reg = <0xe615009c 4>;
620 clocks = <&cpg_clocks 618 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
621 #clock-cells = <0>; 619 #clock-cells = <0>;
622 }; 620 };
623 621
624 /* Fixed factor clocks */ 622 /* Fixed factor clocks */
625 pllc1_div2_clk: pllc1_div2 { 623 pllc1_div2_clk: pllc1_div2 {
626 compatible = "fixed-fa 624 compatible = "fixed-factor-clock";
627 clocks = <&cpg_clocks 625 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
628 #clock-cells = <0>; 626 #clock-cells = <0>;
629 clock-div = <2>; 627 clock-div = <2>;
630 clock-mult = <1>; 628 clock-mult = <1>;
631 }; 629 };
632 extal1_div2_clk: extal1_div2 { 630 extal1_div2_clk: extal1_div2 {
633 compatible = "fixed-fa 631 compatible = "fixed-factor-clock";
634 clocks = <&extal1_clk> 632 clocks = <&extal1_clk>;
635 #clock-cells = <0>; 633 #clock-cells = <0>;
636 clock-div = <2>; 634 clock-div = <2>;
637 clock-mult = <1>; 635 clock-mult = <1>;
638 }; 636 };
639 637
640 /* Gate clocks */ 638 /* Gate clocks */
641 subck_clks: subck_clks@e615008 639 subck_clks: subck_clks@e6150080 {
642 compatible = "renesas, 640 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
643 reg = <0xe6150080 4>; 641 reg = <0xe6150080 4>;
644 clocks = <&sub_clk>, < 642 clocks = <&sub_clk>, <&sub_clk>;
645 #clock-cells = <1>; 643 #clock-cells = <1>;
646 clock-indices = < 644 clock-indices = <
647 R8A7740_CLK_SU 645 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
648 >; 646 >;
649 clock-output-names = 647 clock-output-names =
650 "subck", "subc 648 "subck", "subck2";
651 }; 649 };
652 mstp1_clks: mstp1_clks@e615013 650 mstp1_clks: mstp1_clks@e6150134 {
653 compatible = "renesas, 651 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
654 reg = <0xe6150134 4>, 652 reg = <0xe6150134 4>, <0xe6150038 4>;
655 clocks = <&cpg_clocks 653 clocks = <&cpg_clocks R8A7740_CLK_S>,
656 <&cpg_clocks 654 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
657 <&cpg_clocks 655 <&cpg_clocks R8A7740_CLK_B>,
658 <&cpg_clocks 656 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
659 <&cpg_clocks 657 <&cpg_clocks R8A7740_CLK_B>;
660 #clock-cells = <1>; 658 #clock-cells = <1>;
661 clock-indices = < 659 clock-indices = <
662 R8A7740_CLK_CE 660 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
663 R8A7740_CLK_LC 661 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
664 R8A7740_CLK_LC 662 R8A7740_CLK_LCDC0
665 >; 663 >;
666 clock-output-names = 664 clock-output-names =
667 "ceu21", "ceu2 665 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
668 "tmu1", "lcdc0 666 "tmu1", "lcdc0";
669 }; 667 };
670 mstp2_clks: mstp2_clks@e615013 668 mstp2_clks: mstp2_clks@e6150138 {
671 compatible = "renesas, 669 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
672 reg = <0xe6150138 4>, 670 reg = <0xe6150138 4>, <0xe6150040 4>;
673 clocks = <&sub_clk>, < 671 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
674 <&sub_clk>, < 672 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
675 <&cpg_clocks 673 <&cpg_clocks R8A7740_CLK_HP>,
676 <&cpg_clocks 674 <&cpg_clocks R8A7740_CLK_HP>,
677 <&cpg_clocks 675 <&cpg_clocks R8A7740_CLK_HP>,
678 <&sub_clk>, < 676 <&sub_clk>, <&sub_clk>, <&sub_clk>,
679 <&sub_clk>, < 677 <&sub_clk>, <&sub_clk>, <&sub_clk>,
680 <&sub_clk>; 678 <&sub_clk>;
681 #clock-cells = <1>; 679 #clock-cells = <1>;
682 clock-indices = < 680 clock-indices = <
683 R8A7740_CLK_SC 681 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
684 R8A7740_CLK_SC 682 R8A7740_CLK_SCIFA7
685 R8A7740_CLK_DM 683 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
686 R8A7740_CLK_DM 684 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
687 R8A7740_CLK_SC 685 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
688 R8A7740_CLK_SC 686 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
689 R8A7740_CLK_SC 687 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
690 R8A7740_CLK_SC 688 R8A7740_CLK_SCIFA4
691 >; 689 >;
692 clock-output-names = 690 clock-output-names =
693 "scifa6", "int 691 "scifa6", "intca",
694 "scifa7", "dma 692 "scifa7", "dmac1", "dmac2", "dmac3",
695 "usbdmac", "sc 693 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
696 "scifa2", "sci 694 "scifa2", "scifa3", "scifa4";
697 }; 695 };
698 mstp3_clks: mstp3_clks@e615013 696 mstp3_clks: mstp3_clks@e615013c {
699 compatible = "renesas, 697 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
700 reg = <0xe615013c 4>, 698 reg = <0xe615013c 4>, <0xe6150048 4>;
701 clocks = <&cpg_clocks 699 clocks = <&cpg_clocks R8A7740_CLK_R>,
702 <&cpg_clocks 700 <&cpg_clocks R8A7740_CLK_HP>,
703 <&sub_clk>, 701 <&sub_clk>,
704 <&cpg_clocks 702 <&cpg_clocks R8A7740_CLK_HP>,
705 <&cpg_clocks 703 <&cpg_clocks R8A7740_CLK_HP>,
706 <&cpg_clocks 704 <&cpg_clocks R8A7740_CLK_HP>,
707 <&cpg_clocks 705 <&cpg_clocks R8A7740_CLK_HP>,
708 <&cpg_clocks 706 <&cpg_clocks R8A7740_CLK_HP>,
709 <&cpg_clocks 707 <&cpg_clocks R8A7740_CLK_HP>;
710 #clock-cells = <1>; 708 #clock-cells = <1>;
711 clock-indices = < 709 clock-indices = <
712 R8A7740_CLK_CM 710 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
713 R8A7740_CLK_US 711 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
714 R8A7740_CLK_MM 712 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
715 >; 713 >;
716 clock-output-names = 714 clock-output-names =
717 "cmt1", "fsi", 715 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
718 "mmc", "gether 716 "mmc", "gether", "tpu0";
719 }; 717 };
720 mstp4_clks: mstp4_clks@e615014 718 mstp4_clks: mstp4_clks@e6150140 {
721 compatible = "renesas, 719 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
722 reg = <0xe6150140 4>, 720 reg = <0xe6150140 4>, <0xe615004c 4>;
723 clocks = <&cpg_clocks 721 clocks = <&cpg_clocks R8A7740_CLK_HP>,
724 <&cpg_clocks 722 <&cpg_clocks R8A7740_CLK_HP>,
725 <&cpg_clocks 723 <&cpg_clocks R8A7740_CLK_HP>,
726 <&cpg_clocks 724 <&cpg_clocks R8A7740_CLK_HP>;
727 #clock-cells = <1>; 725 #clock-cells = <1>;
728 clock-indices = < 726 clock-indices = <
729 R8A7740_CLK_US 727 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
730 R8A7740_CLK_US 728 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
731 >; 729 >;
732 clock-output-names = 730 clock-output-names =
733 "usbhost", "sd 731 "usbhost", "sdhi2", "usbfunc", "usphy";
734 }; 732 };
735 }; 733 };
736 734
737 sysc: system-controller@e6180000 { 735 sysc: system-controller@e6180000 {
738 compatible = "renesas,sysc-r8a 736 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
739 reg = <0xe6180000 0x8000>, <0x 737 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
740 738
741 pm-domains { 739 pm-domains {
742 pd_c5: c5 { 740 pd_c5: c5 {
743 #address-cells 741 #address-cells = <1>;
744 #size-cells = 742 #size-cells = <0>;
745 #power-domain- 743 #power-domain-cells = <0>;
746 744
747 pd_a4lc: a4lc@ 745 pd_a4lc: a4lc@1 {
748 reg = 746 reg = <1>;
749 #power 747 #power-domain-cells = <0>;
750 }; 748 };
751 749
752 pd_a4mp: a4mp@ 750 pd_a4mp: a4mp@2 {
753 reg = 751 reg = <2>;
754 #power 752 #power-domain-cells = <0>;
755 }; 753 };
756 754
757 pd_d4: d4@3 { 755 pd_d4: d4@3 {
758 reg = 756 reg = <3>;
759 #power 757 #power-domain-cells = <0>;
760 }; 758 };
761 759
762 pd_a4r: a4r@5 760 pd_a4r: a4r@5 {
763 reg = 761 reg = <5>;
764 #addre 762 #address-cells = <1>;
765 #size- 763 #size-cells = <0>;
766 #power 764 #power-domain-cells = <0>;
767 765
768 pd_a3r 766 pd_a3rv: a3rv@6 {
769 767 reg = <6>;
770 768 #power-domain-cells = <0>;
771 }; 769 };
772 }; 770 };
773 771
774 pd_a4s: a4s@10 772 pd_a4s: a4s@10 {
775 reg = 773 reg = <10>;
776 #addre 774 #address-cells = <1>;
777 #size- 775 #size-cells = <0>;
778 #power 776 #power-domain-cells = <0>;
779 777
780 pd_a3s 778 pd_a3sp: a3sp@11 {
781 779 reg = <11>;
782 780 #power-domain-cells = <0>;
783 }; 781 };
784 782
785 pd_a3s 783 pd_a3sm: a3sm@12 {
786 784 reg = <12>;
787 785 #power-domain-cells = <0>;
788 }; 786 };
789 787
790 pd_a3s 788 pd_a3sg: a3sg@13 {
791 789 reg = <13>;
792 790 #power-domain-cells = <0>;
793 }; 791 };
794 }; 792 };
795 793
796 pd_a4su: a4su@ 794 pd_a4su: a4su@20 {
797 reg = 795 reg = <20>;
798 #power 796 #power-domain-cells = <0>;
799 }; 797 };
800 }; 798 };
801 }; 799 };
802 }; 800 };
803 }; 801 };
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