1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the r8a7744 SoC 3 * Device Tree Source for the r8a7744 SoC
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h 10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
11 #include <dt-bindings/power/r8a7744-sysc.h> 11 #include <dt-bindings/power/r8a7744-sysc.h>
12 12
13 / { 13 / {
14 compatible = "renesas,r8a7744"; 14 compatible = "renesas,r8a7744";
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 17
18 /* 18 /*
19 * The external audio clocks are confi 19 * The external audio clocks are configured as 0 Hz fixed frequency
20 * clocks by default. 20 * clocks by default.
21 * Boards that provide audio clocks sh 21 * Boards that provide audio clocks should override them.
22 */ 22 */
23 audio_clk_a: audio_clk_a { 23 audio_clk_a: audio_clk_a {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 clock-frequency = <0>; 26 clock-frequency = <0>;
27 }; 27 };
28 28
29 audio_clk_b: audio_clk_b { 29 audio_clk_b: audio_clk_b {
30 compatible = "fixed-clock"; 30 compatible = "fixed-clock";
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 }; 33 };
34 34
35 audio_clk_c: audio_clk_c { 35 audio_clk_c: audio_clk_c {
36 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
37 #clock-cells = <0>; 37 #clock-cells = <0>;
38 clock-frequency = <0>; 38 clock-frequency = <0>;
39 }; 39 };
40 40
41 /* External CAN clock */ 41 /* External CAN clock */
42 can_clk: can { 42 can_clk: can {
43 compatible = "fixed-clock"; 43 compatible = "fixed-clock";
44 #clock-cells = <0>; 44 #clock-cells = <0>;
45 /* This value must be overridd 45 /* This value must be overridden by the board. */
46 clock-frequency = <0>; 46 clock-frequency = <0>;
47 }; 47 };
48 48
49 cpus { 49 cpus {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 52
53 cpu0: cpu@0 { 53 cpu0: cpu@0 {
54 device_type = "cpu"; 54 device_type = "cpu";
55 compatible = "arm,cort 55 compatible = "arm,cortex-a15";
56 reg = <0>; 56 reg = <0>;
57 clock-frequency = <150 57 clock-frequency = <1500000000>;
58 clocks = <&cpg CPG_COR 58 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
59 clock-latency = <30000 59 clock-latency = <300000>; /* 300 us */
60 power-domains = <&sysc 60 power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
61 enable-method = "renes 61 enable-method = "renesas,apmu";
62 next-level-cache = <&L 62 next-level-cache = <&L2_CA15>;
63 63
64 /* kHz - uV - OPPs unk 64 /* kHz - uV - OPPs unknown yet */
65 operating-points = <15 65 operating-points = <1500000 1000000>,
66 <13 66 <1312500 1000000>,
67 <11 67 <1125000 1000000>,
68 < 9 68 < 937500 1000000>,
69 < 7 69 < 750000 1000000>,
70 < 3 70 < 375000 1000000>;
71 }; 71 };
72 72
73 cpu1: cpu@1 { 73 cpu1: cpu@1 {
74 device_type = "cpu"; 74 device_type = "cpu";
75 compatible = "arm,cort 75 compatible = "arm,cortex-a15";
76 reg = <1>; 76 reg = <1>;
77 clock-frequency = <150 77 clock-frequency = <1500000000>;
78 clocks = <&cpg CPG_COR 78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
79 clock-latency = <30000 79 clock-latency = <300000>; /* 300 us */
80 power-domains = <&sysc 80 power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
81 enable-method = "renes 81 enable-method = "renesas,apmu";
82 next-level-cache = <&L 82 next-level-cache = <&L2_CA15>;
83 83
84 /* kHz - uV - OPPs unk 84 /* kHz - uV - OPPs unknown yet */
85 operating-points = <15 85 operating-points = <1500000 1000000>,
86 <13 86 <1312500 1000000>,
87 <11 87 <1125000 1000000>,
88 < 9 88 < 937500 1000000>,
89 < 7 89 < 750000 1000000>,
90 < 3 90 < 375000 1000000>;
91 }; 91 };
92 92
93 L2_CA15: cache-controller-0 { 93 L2_CA15: cache-controller-0 {
94 compatible = "cache"; 94 compatible = "cache";
95 cache-unified; 95 cache-unified;
96 cache-level = <2>; 96 cache-level = <2>;
97 power-domains = <&sysc 97 power-domains = <&sysc R8A7744_PD_CA15_SCU>;
98 }; 98 };
99 }; 99 };
100 100
101 /* External root clock */ 101 /* External root clock */
102 extal_clk: extal { 102 extal_clk: extal {
103 compatible = "fixed-clock"; 103 compatible = "fixed-clock";
104 #clock-cells = <0>; 104 #clock-cells = <0>;
105 /* This value must be overridd 105 /* This value must be overridden by the board. */
106 clock-frequency = <0>; 106 clock-frequency = <0>;
107 }; 107 };
108 108
109 /* External PCIe clock - can be overri 109 /* External PCIe clock - can be overridden by the board */
110 pcie_bus_clk: pcie_bus { 110 pcie_bus_clk: pcie_bus {
111 compatible = "fixed-clock"; 111 compatible = "fixed-clock";
112 #clock-cells = <0>; 112 #clock-cells = <0>;
113 clock-frequency = <0>; 113 clock-frequency = <0>;
114 }; 114 };
115 115
116 pmu { 116 pmu {
117 compatible = "arm,cortex-a15-p 117 compatible = "arm,cortex-a15-pmu";
118 interrupts-extended = <&gic GI 118 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
119 <&gic GI 119 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
120 interrupt-affinity = <&cpu0>, 120 interrupt-affinity = <&cpu0>, <&cpu1>;
121 }; 121 };
122 122
123 /* External SCIF clock */ 123 /* External SCIF clock */
124 scif_clk: scif { 124 scif_clk: scif {
125 compatible = "fixed-clock"; 125 compatible = "fixed-clock";
126 #clock-cells = <0>; 126 #clock-cells = <0>;
127 /* This value must be overridd 127 /* This value must be overridden by the board. */
128 clock-frequency = <0>; 128 clock-frequency = <0>;
129 }; 129 };
130 130
131 soc { 131 soc {
132 compatible = "simple-bus"; 132 compatible = "simple-bus";
133 interrupt-parent = <&gic>; 133 interrupt-parent = <&gic>;
134 134
135 #address-cells = <2>; 135 #address-cells = <2>;
136 #size-cells = <2>; 136 #size-cells = <2>;
137 ranges; 137 ranges;
138 138
139 rwdt: watchdog@e6020000 { 139 rwdt: watchdog@e6020000 {
140 compatible = "renesas, 140 compatible = "renesas,r8a7744-wdt",
141 "renesas, 141 "renesas,rcar-gen2-wdt";
142 reg = <0 0xe6020000 0 142 reg = <0 0xe6020000 0 0x0c>;
143 interrupts = <GIC_SPI 143 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cpg CPG_MOD 144 clocks = <&cpg CPG_MOD 402>;
145 power-domains = <&sysc 145 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
146 resets = <&cpg 402>; 146 resets = <&cpg 402>;
147 status = "disabled"; 147 status = "disabled";
148 }; 148 };
149 149
150 gpio0: gpio@e6050000 { 150 gpio0: gpio@e6050000 {
151 compatible = "renesas, 151 compatible = "renesas,gpio-r8a7744",
152 "renesas, 152 "renesas,rcar-gen2-gpio";
153 reg = <0 0xe6050000 0 153 reg = <0 0xe6050000 0 0x50>;
154 interrupts = <GIC_SPI 154 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
155 #gpio-cells = <2>; 155 #gpio-cells = <2>;
156 gpio-controller; 156 gpio-controller;
157 gpio-ranges = <&pfc 0 157 gpio-ranges = <&pfc 0 0 32>;
158 #interrupt-cells = <2> 158 #interrupt-cells = <2>;
159 interrupt-controller; 159 interrupt-controller;
160 clocks = <&cpg CPG_MOD 160 clocks = <&cpg CPG_MOD 912>;
161 power-domains = <&sysc 161 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
162 resets = <&cpg 912>; 162 resets = <&cpg 912>;
163 }; 163 };
164 164
165 gpio1: gpio@e6051000 { 165 gpio1: gpio@e6051000 {
166 compatible = "renesas, 166 compatible = "renesas,gpio-r8a7744",
167 "renesas, 167 "renesas,rcar-gen2-gpio";
168 reg = <0 0xe6051000 0 168 reg = <0 0xe6051000 0 0x50>;
169 interrupts = <GIC_SPI 169 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>; 170 #gpio-cells = <2>;
171 gpio-controller; 171 gpio-controller;
172 gpio-ranges = <&pfc 0 172 gpio-ranges = <&pfc 0 32 26>;
173 #interrupt-cells = <2> 173 #interrupt-cells = <2>;
174 interrupt-controller; 174 interrupt-controller;
175 clocks = <&cpg CPG_MOD 175 clocks = <&cpg CPG_MOD 911>;
176 power-domains = <&sysc 176 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
177 resets = <&cpg 911>; 177 resets = <&cpg 911>;
178 }; 178 };
179 179
180 gpio2: gpio@e6052000 { 180 gpio2: gpio@e6052000 {
181 compatible = "renesas, 181 compatible = "renesas,gpio-r8a7744",
182 "renesas, 182 "renesas,rcar-gen2-gpio";
183 reg = <0 0xe6052000 0 183 reg = <0 0xe6052000 0 0x50>;
184 interrupts = <GIC_SPI 184 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
185 #gpio-cells = <2>; 185 #gpio-cells = <2>;
186 gpio-controller; 186 gpio-controller;
187 gpio-ranges = <&pfc 0 187 gpio-ranges = <&pfc 0 64 32>;
188 #interrupt-cells = <2> 188 #interrupt-cells = <2>;
189 interrupt-controller; 189 interrupt-controller;
190 clocks = <&cpg CPG_MOD 190 clocks = <&cpg CPG_MOD 910>;
191 power-domains = <&sysc 191 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
192 resets = <&cpg 910>; 192 resets = <&cpg 910>;
193 }; 193 };
194 194
195 gpio3: gpio@e6053000 { 195 gpio3: gpio@e6053000 {
196 compatible = "renesas, 196 compatible = "renesas,gpio-r8a7744",
197 "renesas, 197 "renesas,rcar-gen2-gpio";
198 reg = <0 0xe6053000 0 198 reg = <0 0xe6053000 0 0x50>;
199 interrupts = <GIC_SPI 199 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
200 #gpio-cells = <2>; 200 #gpio-cells = <2>;
201 gpio-controller; 201 gpio-controller;
202 gpio-ranges = <&pfc 0 202 gpio-ranges = <&pfc 0 96 32>;
203 #interrupt-cells = <2> 203 #interrupt-cells = <2>;
204 interrupt-controller; 204 interrupt-controller;
205 clocks = <&cpg CPG_MOD 205 clocks = <&cpg CPG_MOD 909>;
206 power-domains = <&sysc 206 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
207 resets = <&cpg 909>; 207 resets = <&cpg 909>;
208 }; 208 };
209 209
210 gpio4: gpio@e6054000 { 210 gpio4: gpio@e6054000 {
211 compatible = "renesas, 211 compatible = "renesas,gpio-r8a7744",
212 "renesas, 212 "renesas,rcar-gen2-gpio";
213 reg = <0 0xe6054000 0 213 reg = <0 0xe6054000 0 0x50>;
214 interrupts = <GIC_SPI 214 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
215 #gpio-cells = <2>; 215 #gpio-cells = <2>;
216 gpio-controller; 216 gpio-controller;
217 gpio-ranges = <&pfc 0 217 gpio-ranges = <&pfc 0 128 32>;
218 #interrupt-cells = <2> 218 #interrupt-cells = <2>;
219 interrupt-controller; 219 interrupt-controller;
220 clocks = <&cpg CPG_MOD 220 clocks = <&cpg CPG_MOD 908>;
221 power-domains = <&sysc 221 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
222 resets = <&cpg 908>; 222 resets = <&cpg 908>;
223 }; 223 };
224 224
225 gpio5: gpio@e6055000 { 225 gpio5: gpio@e6055000 {
226 compatible = "renesas, 226 compatible = "renesas,gpio-r8a7744",
227 "renesas, 227 "renesas,rcar-gen2-gpio";
228 reg = <0 0xe6055000 0 228 reg = <0 0xe6055000 0 0x50>;
229 interrupts = <GIC_SPI 229 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
230 #gpio-cells = <2>; 230 #gpio-cells = <2>;
231 gpio-controller; 231 gpio-controller;
232 gpio-ranges = <&pfc 0 232 gpio-ranges = <&pfc 0 160 32>;
233 #interrupt-cells = <2> 233 #interrupt-cells = <2>;
234 interrupt-controller; 234 interrupt-controller;
235 clocks = <&cpg CPG_MOD 235 clocks = <&cpg CPG_MOD 907>;
236 power-domains = <&sysc 236 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
237 resets = <&cpg 907>; 237 resets = <&cpg 907>;
238 }; 238 };
239 239
240 gpio6: gpio@e6055400 { 240 gpio6: gpio@e6055400 {
241 compatible = "renesas, 241 compatible = "renesas,gpio-r8a7744",
242 "renesas, 242 "renesas,rcar-gen2-gpio";
243 reg = <0 0xe6055400 0 243 reg = <0 0xe6055400 0 0x50>;
244 interrupts = <GIC_SPI 244 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
245 #gpio-cells = <2>; 245 #gpio-cells = <2>;
246 gpio-controller; 246 gpio-controller;
247 gpio-ranges = <&pfc 0 247 gpio-ranges = <&pfc 0 192 32>;
248 #interrupt-cells = <2> 248 #interrupt-cells = <2>;
249 interrupt-controller; 249 interrupt-controller;
250 clocks = <&cpg CPG_MOD 250 clocks = <&cpg CPG_MOD 905>;
251 power-domains = <&sysc 251 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
252 resets = <&cpg 905>; 252 resets = <&cpg 905>;
253 }; 253 };
254 254
255 gpio7: gpio@e6055800 { 255 gpio7: gpio@e6055800 {
256 compatible = "renesas, 256 compatible = "renesas,gpio-r8a7744",
257 "renesas, 257 "renesas,rcar-gen2-gpio";
258 reg = <0 0xe6055800 0 258 reg = <0 0xe6055800 0 0x50>;
259 interrupts = <GIC_SPI 259 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
260 #gpio-cells = <2>; 260 #gpio-cells = <2>;
261 gpio-controller; 261 gpio-controller;
262 gpio-ranges = <&pfc 0 262 gpio-ranges = <&pfc 0 224 26>;
263 #interrupt-cells = <2> 263 #interrupt-cells = <2>;
264 interrupt-controller; 264 interrupt-controller;
265 clocks = <&cpg CPG_MOD 265 clocks = <&cpg CPG_MOD 904>;
266 power-domains = <&sysc 266 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
267 resets = <&cpg 904>; 267 resets = <&cpg 904>;
268 }; 268 };
269 269
270 pfc: pinctrl@e6060000 { 270 pfc: pinctrl@e6060000 {
271 compatible = "renesas, 271 compatible = "renesas,pfc-r8a7744";
272 reg = <0 0xe6060000 0 272 reg = <0 0xe6060000 0 0x250>;
273 }; 273 };
274 274
275 tpu: pwm@e60f0000 { 275 tpu: pwm@e60f0000 {
276 compatible = "renesas, 276 compatible = "renesas,tpu-r8a7744", "renesas,tpu";
277 reg = <0 0xe60f0000 0 277 reg = <0 0xe60f0000 0 0x148>;
278 clocks = <&cpg CPG_MOD 278 clocks = <&cpg CPG_MOD 304>;
279 power-domains = <&sysc 279 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
280 resets = <&cpg 304>; 280 resets = <&cpg 304>;
281 #pwm-cells = <3>; 281 #pwm-cells = <3>;
282 status = "disabled"; 282 status = "disabled";
283 }; 283 };
284 284
285 cpg: clock-controller@e6150000 285 cpg: clock-controller@e6150000 {
286 compatible = "renesas, 286 compatible = "renesas,r8a7744-cpg-mssr";
287 reg = <0 0xe6150000 0 287 reg = <0 0xe6150000 0 0x1000>;
288 clocks = <&extal_clk>, 288 clocks = <&extal_clk>, <&usb_extal_clk>;
289 clock-names = "extal", 289 clock-names = "extal", "usb_extal";
290 #clock-cells = <2>; 290 #clock-cells = <2>;
291 #power-domain-cells = 291 #power-domain-cells = <0>;
292 #reset-cells = <1>; 292 #reset-cells = <1>;
293 }; 293 };
294 294
295 apmu@e6152000 { 295 apmu@e6152000 {
296 compatible = "renesas, 296 compatible = "renesas,r8a7744-apmu", "renesas,apmu";
297 reg = <0 0xe6152000 0 297 reg = <0 0xe6152000 0 0x188>;
298 cpus = <&cpu0>, <&cpu1 298 cpus = <&cpu0>, <&cpu1>;
299 }; 299 };
300 300
301 rst: reset-controller@e6160000 301 rst: reset-controller@e6160000 {
302 compatible = "renesas, 302 compatible = "renesas,r8a7744-rst";
303 reg = <0 0xe6160000 0 303 reg = <0 0xe6160000 0 0x100>;
304 }; 304 };
305 305
306 sysc: system-controller@e61800 306 sysc: system-controller@e6180000 {
307 compatible = "renesas, 307 compatible = "renesas,r8a7744-sysc";
308 reg = <0 0xe6180000 0 308 reg = <0 0xe6180000 0 0x200>;
309 #power-domain-cells = 309 #power-domain-cells = <1>;
310 }; 310 };
311 311
312 irqc: interrupt-controller@e61 312 irqc: interrupt-controller@e61c0000 {
313 compatible = "renesas, 313 compatible = "renesas,irqc-r8a7744", "renesas,irqc";
314 #interrupt-cells = <2> 314 #interrupt-cells = <2>;
315 interrupt-controller; 315 interrupt-controller;
316 reg = <0 0xe61c0000 0 316 reg = <0 0xe61c0000 0 0x200>;
317 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 318 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 319 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 320 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 321 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 322 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 323 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 324 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 325 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 326 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&cpg CPG_MOD 327 clocks = <&cpg CPG_MOD 407>;
328 power-domains = <&sysc 328 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
329 resets = <&cpg 407>; 329 resets = <&cpg 407>;
330 }; 330 };
331 331
332 tmu0: timer@e61e0000 { 332 tmu0: timer@e61e0000 {
333 compatible = "renesas, 333 compatible = "renesas,tmu-r8a7744", "renesas,tmu";
334 reg = <0 0xe61e0000 0 334 reg = <0 0xe61e0000 0 0x30>;
335 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "tun 338 interrupt-names = "tuni0", "tuni1", "tuni2";
339 clocks = <&cpg CPG_MOD 339 clocks = <&cpg CPG_MOD 125>;
340 clock-names = "fck"; 340 clock-names = "fck";
341 power-domains = <&sysc 341 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
342 resets = <&cpg 125>; 342 resets = <&cpg 125>;
343 status = "disabled"; 343 status = "disabled";
344 }; 344 };
345 345
346 tmu1: timer@fff60000 { 346 tmu1: timer@fff60000 {
347 compatible = "renesas, 347 compatible = "renesas,tmu-r8a7744", "renesas,tmu";
348 reg = <0 0xfff60000 0 348 reg = <0 0xfff60000 0 0x30>;
349 interrupts = <GIC_SPI 349 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 350 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 351 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 352 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
353 interrupt-names = "tun 353 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
354 clocks = <&cpg CPG_MOD 354 clocks = <&cpg CPG_MOD 111>;
355 clock-names = "fck"; 355 clock-names = "fck";
356 power-domains = <&sysc 356 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
357 resets = <&cpg 111>; 357 resets = <&cpg 111>;
358 status = "disabled"; 358 status = "disabled";
359 }; 359 };
360 360
361 tmu2: timer@fff70000 { 361 tmu2: timer@fff70000 {
362 compatible = "renesas, 362 compatible = "renesas,tmu-r8a7744", "renesas,tmu";
363 reg = <0 0xfff70000 0 363 reg = <0 0xfff70000 0 0x30>;
364 interrupts = <GIC_SPI 364 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 365 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 366 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 367 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "tun 368 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
369 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD 122>;
370 clock-names = "fck"; 370 clock-names = "fck";
371 power-domains = <&sysc 371 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
372 resets = <&cpg 122>; 372 resets = <&cpg 122>;
373 status = "disabled"; 373 status = "disabled";
374 }; 374 };
375 375
376 tmu3: timer@fff80000 { 376 tmu3: timer@fff80000 {
377 compatible = "renesas, 377 compatible = "renesas,tmu-r8a7744", "renesas,tmu";
378 reg = <0 0xfff80000 0 378 reg = <0 0xfff80000 0 0x30>;
379 interrupts = <GIC_SPI 379 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 380 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 381 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "tun 382 interrupt-names = "tuni0", "tuni1", "tuni2";
383 clocks = <&cpg CPG_MOD 383 clocks = <&cpg CPG_MOD 121>;
384 clock-names = "fck"; 384 clock-names = "fck";
385 power-domains = <&sysc 385 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
386 resets = <&cpg 121>; 386 resets = <&cpg 121>;
387 status = "disabled"; 387 status = "disabled";
388 }; 388 };
389 389
390 thermal: thermal@e61f0000 { 390 thermal: thermal@e61f0000 {
391 compatible = "renesas, 391 compatible = "renesas,thermal-r8a7744",
392 "renesas, 392 "renesas,rcar-gen2-thermal";
393 reg = <0 0xe61f0000 0 393 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
394 interrupts = <GIC_SPI 394 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cpg CPG_MOD 395 clocks = <&cpg CPG_MOD 522>;
396 power-domains = <&sysc 396 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
397 resets = <&cpg 522>; 397 resets = <&cpg 522>;
398 #thermal-sensor-cells 398 #thermal-sensor-cells = <0>;
399 }; 399 };
400 400
401 ipmmu_sy0: iommu@e6280000 { 401 ipmmu_sy0: iommu@e6280000 {
402 compatible = "renesas, 402 compatible = "renesas,ipmmu-r8a7744",
403 "renesas, 403 "renesas,ipmmu-vmsa";
404 reg = <0 0xe6280000 0 404 reg = <0 0xe6280000 0 0x1000>;
405 interrupts = <GIC_SPI 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 406 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
407 #iommu-cells = <1>; 407 #iommu-cells = <1>;
408 status = "disabled"; 408 status = "disabled";
409 }; 409 };
410 410
411 ipmmu_sy1: iommu@e6290000 { 411 ipmmu_sy1: iommu@e6290000 {
412 compatible = "renesas, 412 compatible = "renesas,ipmmu-r8a7744",
413 "renesas, 413 "renesas,ipmmu-vmsa";
414 reg = <0 0xe6290000 0 414 reg = <0 0xe6290000 0 0x1000>;
415 interrupts = <GIC_SPI 415 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
416 #iommu-cells = <1>; 416 #iommu-cells = <1>;
417 status = "disabled"; 417 status = "disabled";
418 }; 418 };
419 419
420 ipmmu_ds: iommu@e6740000 { 420 ipmmu_ds: iommu@e6740000 {
421 compatible = "renesas, 421 compatible = "renesas,ipmmu-r8a7744",
422 "renesas, 422 "renesas,ipmmu-vmsa";
423 reg = <0 0xe6740000 0 423 reg = <0 0xe6740000 0 0x1000>;
424 interrupts = <GIC_SPI 424 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 425 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
426 #iommu-cells = <1>; 426 #iommu-cells = <1>;
427 status = "disabled"; 427 status = "disabled";
428 }; 428 };
429 429
430 ipmmu_mp: iommu@ec680000 { 430 ipmmu_mp: iommu@ec680000 {
431 compatible = "renesas, 431 compatible = "renesas,ipmmu-r8a7744",
432 "renesas, 432 "renesas,ipmmu-vmsa";
433 reg = <0 0xec680000 0 433 reg = <0 0xec680000 0 0x1000>;
434 interrupts = <GIC_SPI 434 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
435 #iommu-cells = <1>; 435 #iommu-cells = <1>;
436 status = "disabled"; 436 status = "disabled";
437 }; 437 };
438 438
439 ipmmu_mx: iommu@fe951000 { 439 ipmmu_mx: iommu@fe951000 {
440 compatible = "renesas, 440 compatible = "renesas,ipmmu-r8a7744",
441 "renesas, 441 "renesas,ipmmu-vmsa";
442 reg = <0 0xfe951000 0 442 reg = <0 0xfe951000 0 0x1000>;
443 interrupts = <GIC_SPI 443 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 444 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
445 #iommu-cells = <1>; 445 #iommu-cells = <1>;
446 status = "disabled"; 446 status = "disabled";
447 }; 447 };
448 448
449 ipmmu_gp: iommu@e62a0000 { 449 ipmmu_gp: iommu@e62a0000 {
450 compatible = "renesas, 450 compatible = "renesas,ipmmu-r8a7744",
451 "renesas, 451 "renesas,ipmmu-vmsa";
452 reg = <0 0xe62a0000 0 452 reg = <0 0xe62a0000 0 0x1000>;
453 interrupts = <GIC_SPI 453 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 454 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
455 #iommu-cells = <1>; 455 #iommu-cells = <1>;
456 status = "disabled"; 456 status = "disabled";
457 }; 457 };
458 458
459 icram0: sram@e63a0000 { 459 icram0: sram@e63a0000 {
460 compatible = "mmio-sra 460 compatible = "mmio-sram";
461 reg = <0 0xe63a0000 0 461 reg = <0 0xe63a0000 0 0x12000>;
462 #address-cells = <1>; 462 #address-cells = <1>;
463 #size-cells = <1>; 463 #size-cells = <1>;
464 ranges = <0 0 0xe63a00 464 ranges = <0 0 0xe63a0000 0x12000>;
465 }; 465 };
466 466
467 icram1: sram@e63c0000 { 467 icram1: sram@e63c0000 {
468 compatible = "mmio-sra 468 compatible = "mmio-sram";
469 reg = <0 0xe63c0000 0 469 reg = <0 0xe63c0000 0 0x1000>;
470 #address-cells = <1>; 470 #address-cells = <1>;
471 #size-cells = <1>; 471 #size-cells = <1>;
472 ranges = <0 0 0xe63c00 472 ranges = <0 0 0xe63c0000 0x1000>;
473 473
474 smp-sram@0 { 474 smp-sram@0 {
475 compatible = " 475 compatible = "renesas,smp-sram";
476 reg = <0 0x100 476 reg = <0 0x100>;
477 }; 477 };
478 }; 478 };
479 479
480 icram2: sram@e6300000 { 480 icram2: sram@e6300000 {
481 compatible = "mmio-sra 481 compatible = "mmio-sram";
482 reg = <0 0xe6300000 0 482 reg = <0 0xe6300000 0 0x40000>;
483 #address-cells = <1>; 483 #address-cells = <1>;
484 #size-cells = <1>; 484 #size-cells = <1>;
485 ranges = <0 0 0xe63000 485 ranges = <0 0 0xe6300000 0x40000>;
486 }; 486 };
487 487
488 /* The memory map in the User' 488 /* The memory map in the User's Manual maps the cores to
489 * bus numbers 489 * bus numbers
490 */ 490 */
491 i2c0: i2c@e6508000 { 491 i2c0: i2c@e6508000 {
492 #address-cells = <1>; 492 #address-cells = <1>;
493 #size-cells = <0>; 493 #size-cells = <0>;
494 compatible = "renesas, 494 compatible = "renesas,i2c-r8a7744",
495 "renesas, 495 "renesas,rcar-gen2-i2c";
496 reg = <0 0xe6508000 0 496 reg = <0 0xe6508000 0 0x40>;
497 interrupts = <GIC_SPI 497 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 498 clocks = <&cpg CPG_MOD 931>;
499 power-domains = <&sysc 499 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
500 resets = <&cpg 931>; 500 resets = <&cpg 931>;
501 i2c-scl-internal-delay 501 i2c-scl-internal-delay-ns = <6>;
502 status = "disabled"; 502 status = "disabled";
503 }; 503 };
504 504
505 i2c1: i2c@e6518000 { 505 i2c1: i2c@e6518000 {
506 #address-cells = <1>; 506 #address-cells = <1>;
507 #size-cells = <0>; 507 #size-cells = <0>;
508 compatible = "renesas, 508 compatible = "renesas,i2c-r8a7744",
509 "renesas, 509 "renesas,rcar-gen2-i2c";
510 reg = <0 0xe6518000 0 510 reg = <0 0xe6518000 0 0x40>;
511 interrupts = <GIC_SPI 511 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cpg CPG_MOD 512 clocks = <&cpg CPG_MOD 930>;
513 power-domains = <&sysc 513 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
514 resets = <&cpg 930>; 514 resets = <&cpg 930>;
515 i2c-scl-internal-delay 515 i2c-scl-internal-delay-ns = <6>;
516 status = "disabled"; 516 status = "disabled";
517 }; 517 };
518 518
519 i2c2: i2c@e6530000 { 519 i2c2: i2c@e6530000 {
520 #address-cells = <1>; 520 #address-cells = <1>;
521 #size-cells = <0>; 521 #size-cells = <0>;
522 compatible = "renesas, 522 compatible = "renesas,i2c-r8a7744",
523 "renesas, 523 "renesas,rcar-gen2-i2c";
524 reg = <0 0xe6530000 0 524 reg = <0 0xe6530000 0 0x40>;
525 interrupts = <GIC_SPI 525 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cpg CPG_MOD 526 clocks = <&cpg CPG_MOD 929>;
527 power-domains = <&sysc 527 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
528 resets = <&cpg 929>; 528 resets = <&cpg 929>;
529 i2c-scl-internal-delay 529 i2c-scl-internal-delay-ns = <6>;
530 status = "disabled"; 530 status = "disabled";
531 }; 531 };
532 532
533 i2c3: i2c@e6540000 { 533 i2c3: i2c@e6540000 {
534 #address-cells = <1>; 534 #address-cells = <1>;
535 #size-cells = <0>; 535 #size-cells = <0>;
536 compatible = "renesas, 536 compatible = "renesas,i2c-r8a7744",
537 "renesas, 537 "renesas,rcar-gen2-i2c";
538 reg = <0 0xe6540000 0 538 reg = <0 0xe6540000 0 0x40>;
539 interrupts = <GIC_SPI 539 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cpg CPG_MOD 540 clocks = <&cpg CPG_MOD 928>;
541 power-domains = <&sysc 541 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
542 resets = <&cpg 928>; 542 resets = <&cpg 928>;
543 i2c-scl-internal-delay 543 i2c-scl-internal-delay-ns = <6>;
544 status = "disabled"; 544 status = "disabled";
545 }; 545 };
546 546
547 i2c4: i2c@e6520000 { 547 i2c4: i2c@e6520000 {
548 #address-cells = <1>; 548 #address-cells = <1>;
549 #size-cells = <0>; 549 #size-cells = <0>;
550 compatible = "renesas, 550 compatible = "renesas,i2c-r8a7744",
551 "renesas, 551 "renesas,rcar-gen2-i2c";
552 reg = <0 0xe6520000 0 552 reg = <0 0xe6520000 0 0x40>;
553 interrupts = <GIC_SPI 553 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cpg CPG_MOD 554 clocks = <&cpg CPG_MOD 927>;
555 power-domains = <&sysc 555 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
556 resets = <&cpg 927>; 556 resets = <&cpg 927>;
557 i2c-scl-internal-delay 557 i2c-scl-internal-delay-ns = <6>;
558 status = "disabled"; 558 status = "disabled";
559 }; 559 };
560 560
561 i2c5: i2c@e6528000 { 561 i2c5: i2c@e6528000 {
562 /* doesn't need pinmux 562 /* doesn't need pinmux */
563 #address-cells = <1>; 563 #address-cells = <1>;
564 #size-cells = <0>; 564 #size-cells = <0>;
565 compatible = "renesas, 565 compatible = "renesas,i2c-r8a7744",
566 "renesas, 566 "renesas,rcar-gen2-i2c";
567 reg = <0 0xe6528000 0 567 reg = <0 0xe6528000 0 0x40>;
568 interrupts = <GIC_SPI 568 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&cpg CPG_MOD 569 clocks = <&cpg CPG_MOD 925>;
570 power-domains = <&sysc 570 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
571 resets = <&cpg 925>; 571 resets = <&cpg 925>;
572 i2c-scl-internal-delay 572 i2c-scl-internal-delay-ns = <110>;
573 status = "disabled"; 573 status = "disabled";
574 }; 574 };
575 575
576 iic0: i2c@e6500000 { 576 iic0: i2c@e6500000 {
577 #address-cells = <1>; 577 #address-cells = <1>;
578 #size-cells = <0>; 578 #size-cells = <0>;
579 compatible = "renesas, 579 compatible = "renesas,iic-r8a7744",
580 "renesas, 580 "renesas,rcar-gen2-iic",
581 "renesas, 581 "renesas,rmobile-iic";
582 reg = <0 0xe6500000 0 582 reg = <0 0xe6500000 0 0x425>;
583 interrupts = <GIC_SPI 583 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cpg CPG_MOD 584 clocks = <&cpg CPG_MOD 318>;
585 dmas = <&dmac0 0x61>, 585 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
586 <&dmac1 0x61>, 586 <&dmac1 0x61>, <&dmac1 0x62>;
587 dma-names = "tx", "rx" 587 dma-names = "tx", "rx", "tx", "rx";
588 power-domains = <&sysc 588 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
589 resets = <&cpg 318>; 589 resets = <&cpg 318>;
590 status = "disabled"; 590 status = "disabled";
591 }; 591 };
592 592
593 iic1: i2c@e6510000 { 593 iic1: i2c@e6510000 {
594 #address-cells = <1>; 594 #address-cells = <1>;
595 #size-cells = <0>; 595 #size-cells = <0>;
596 compatible = "renesas, 596 compatible = "renesas,iic-r8a7744",
597 "renesas, 597 "renesas,rcar-gen2-iic",
598 "renesas, 598 "renesas,rmobile-iic";
599 reg = <0 0xe6510000 0 599 reg = <0 0xe6510000 0 0x425>;
600 interrupts = <GIC_SPI 600 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cpg CPG_MOD 601 clocks = <&cpg CPG_MOD 323>;
602 dmas = <&dmac0 0x65>, 602 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
603 <&dmac1 0x65>, 603 <&dmac1 0x65>, <&dmac1 0x66>;
604 dma-names = "tx", "rx" 604 dma-names = "tx", "rx", "tx", "rx";
605 power-domains = <&sysc 605 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
606 resets = <&cpg 323>; 606 resets = <&cpg 323>;
607 status = "disabled"; 607 status = "disabled";
608 }; 608 };
609 609
610 iic3: i2c@e60b0000 { 610 iic3: i2c@e60b0000 {
611 /* doesn't need pinmux 611 /* doesn't need pinmux */
612 #address-cells = <1>; 612 #address-cells = <1>;
613 #size-cells = <0>; 613 #size-cells = <0>;
614 compatible = "renesas, 614 compatible = "renesas,iic-r8a7744",
615 "renesas, 615 "renesas,rcar-gen2-iic",
616 "renesas, 616 "renesas,rmobile-iic";
617 reg = <0 0xe60b0000 0 617 reg = <0 0xe60b0000 0 0x425>;
618 interrupts = <GIC_SPI 618 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 619 clocks = <&cpg CPG_MOD 926>;
620 dmas = <&dmac0 0x77>, 620 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
621 <&dmac1 0x77>, 621 <&dmac1 0x77>, <&dmac1 0x78>;
622 dma-names = "tx", "rx" 622 dma-names = "tx", "rx", "tx", "rx";
623 power-domains = <&sysc 623 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
624 resets = <&cpg 926>; 624 resets = <&cpg 926>;
625 status = "disabled"; 625 status = "disabled";
626 }; 626 };
627 627
628 hsusb: usb@e6590000 { 628 hsusb: usb@e6590000 {
629 compatible = "renesas, 629 compatible = "renesas,usbhs-r8a7744",
630 "renesas, 630 "renesas,rcar-gen2-usbhs";
631 reg = <0 0xe6590000 0 631 reg = <0 0xe6590000 0 0x100>;
632 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cpg CPG_MOD 633 clocks = <&cpg CPG_MOD 704>;
634 dmas = <&usb_dmac0 0>, 634 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
635 <&usb_dmac1 0>, 635 <&usb_dmac1 0>, <&usb_dmac1 1>;
636 dma-names = "ch0", "ch 636 dma-names = "ch0", "ch1", "ch2", "ch3";
637 power-domains = <&sysc 637 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
638 resets = <&cpg 704>; 638 resets = <&cpg 704>;
639 renesas,buswait = <4>; 639 renesas,buswait = <4>;
640 phys = <&usb0 1>; 640 phys = <&usb0 1>;
641 phy-names = "usb"; 641 phy-names = "usb";
642 status = "disabled"; 642 status = "disabled";
643 }; 643 };
644 644
645 usbphy: usb-phy-controller@e65 645 usbphy: usb-phy-controller@e6590100 {
646 compatible = "renesas, 646 compatible = "renesas,usb-phy-r8a7744",
647 "renesas, 647 "renesas,rcar-gen2-usb-phy";
648 reg = <0 0xe6590100 0 648 reg = <0 0xe6590100 0 0x100>;
649 #address-cells = <1>; 649 #address-cells = <1>;
650 #size-cells = <0>; 650 #size-cells = <0>;
651 clocks = <&cpg CPG_MOD 651 clocks = <&cpg CPG_MOD 704>;
652 clock-names = "usbhs"; 652 clock-names = "usbhs";
653 power-domains = <&sysc 653 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
654 resets = <&cpg 704>; 654 resets = <&cpg 704>;
655 status = "disabled"; 655 status = "disabled";
656 656
657 usb0: usb-phy@0 { 657 usb0: usb-phy@0 {
658 reg = <0>; 658 reg = <0>;
659 #phy-cells = < 659 #phy-cells = <1>;
660 }; 660 };
661 usb2: usb-phy@2 { 661 usb2: usb-phy@2 {
662 reg = <2>; 662 reg = <2>;
663 #phy-cells = < 663 #phy-cells = <1>;
664 }; 664 };
665 }; 665 };
666 666
667 usb_dmac0: dma-controller@e65a 667 usb_dmac0: dma-controller@e65a0000 {
668 compatible = "renesas, 668 compatible = "renesas,r8a7744-usb-dmac",
669 "renesas, 669 "renesas,usb-dmac";
670 reg = <0 0xe65a0000 0 670 reg = <0 0xe65a0000 0 0x100>;
671 interrupts = <GIC_SPI 671 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 672 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "ch0 673 interrupt-names = "ch0", "ch1";
674 clocks = <&cpg CPG_MOD 674 clocks = <&cpg CPG_MOD 330>;
675 power-domains = <&sysc 675 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
676 resets = <&cpg 330>; 676 resets = <&cpg 330>;
677 #dma-cells = <1>; 677 #dma-cells = <1>;
678 dma-channels = <2>; 678 dma-channels = <2>;
679 }; 679 };
680 680
681 usb_dmac1: dma-controller@e65b 681 usb_dmac1: dma-controller@e65b0000 {
682 compatible = "renesas, 682 compatible = "renesas,r8a7744-usb-dmac",
683 "renesas, 683 "renesas,usb-dmac";
684 reg = <0 0xe65b0000 0 684 reg = <0 0xe65b0000 0 0x100>;
685 interrupts = <GIC_SPI 685 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 686 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
687 interrupt-names = "ch0 687 interrupt-names = "ch0", "ch1";
688 clocks = <&cpg CPG_MOD 688 clocks = <&cpg CPG_MOD 331>;
689 power-domains = <&sysc 689 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
690 resets = <&cpg 331>; 690 resets = <&cpg 331>;
691 #dma-cells = <1>; 691 #dma-cells = <1>;
692 dma-channels = <2>; 692 dma-channels = <2>;
693 }; 693 };
694 694
695 dmac0: dma-controller@e6700000 695 dmac0: dma-controller@e6700000 {
696 compatible = "renesas, 696 compatible = "renesas,dmac-r8a7744",
697 "renesas, 697 "renesas,rcar-dmac";
698 reg = <0 0xe6700000 0 698 reg = <0 0xe6700000 0 0x20000>;
699 interrupts = <GIC_SPI 699 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 700 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 701 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 702 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 703 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 704 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 705 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 706 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 707 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 708 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 709 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 710 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 711 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 712 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 713 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 714 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
715 interrupt-names = "err 715 interrupt-names = "error",
716 "ch0 716 "ch0", "ch1", "ch2", "ch3",
717 "ch4 717 "ch4", "ch5", "ch6", "ch7",
718 "ch8 718 "ch8", "ch9", "ch10", "ch11",
719 "ch1 719 "ch12", "ch13", "ch14";
720 clocks = <&cpg CPG_MOD 720 clocks = <&cpg CPG_MOD 219>;
721 clock-names = "fck"; 721 clock-names = "fck";
722 power-domains = <&sysc 722 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
723 resets = <&cpg 219>; 723 resets = <&cpg 219>;
724 #dma-cells = <1>; 724 #dma-cells = <1>;
725 dma-channels = <15>; 725 dma-channels = <15>;
726 }; 726 };
727 727
728 dmac1: dma-controller@e6720000 728 dmac1: dma-controller@e6720000 {
729 compatible = "renesas, 729 compatible = "renesas,dmac-r8a7744",
730 "renesas, 730 "renesas,rcar-dmac";
731 reg = <0 0xe6720000 0 731 reg = <0 0xe6720000 0 0x20000>;
732 interrupts = <GIC_SPI 732 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 733 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 734 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 735 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 736 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 737 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 738 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 739 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 740 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 741 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 742 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 743 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 744 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 745 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 746 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 747 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
748 interrupt-names = "err 748 interrupt-names = "error",
749 "ch0 749 "ch0", "ch1", "ch2", "ch3",
750 "ch4 750 "ch4", "ch5", "ch6", "ch7",
751 "ch8 751 "ch8", "ch9", "ch10", "ch11",
752 "ch1 752 "ch12", "ch13", "ch14";
753 clocks = <&cpg CPG_MOD 753 clocks = <&cpg CPG_MOD 218>;
754 clock-names = "fck"; 754 clock-names = "fck";
755 power-domains = <&sysc 755 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
756 resets = <&cpg 218>; 756 resets = <&cpg 218>;
757 #dma-cells = <1>; 757 #dma-cells = <1>;
758 dma-channels = <15>; 758 dma-channels = <15>;
759 }; 759 };
760 760
761 avb: ethernet@e6800000 { 761 avb: ethernet@e6800000 {
762 compatible = "renesas, 762 compatible = "renesas,etheravb-r8a7744",
763 "renesas, 763 "renesas,etheravb-rcar-gen2";
764 reg = <0 0xe6800000 0 764 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
765 interrupts = <GIC_SPI 765 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&cpg CPG_MOD 766 clocks = <&cpg CPG_MOD 812>;
767 clock-names = "fck"; 767 clock-names = "fck";
768 power-domains = <&sysc 768 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
769 resets = <&cpg 812>; 769 resets = <&cpg 812>;
770 #address-cells = <1>; 770 #address-cells = <1>;
771 #size-cells = <0>; 771 #size-cells = <0>;
772 status = "disabled"; 772 status = "disabled";
773 }; 773 };
774 774
775 qspi: spi@e6b10000 { 775 qspi: spi@e6b10000 {
776 compatible = "renesas, 776 compatible = "renesas,qspi-r8a7744", "renesas,qspi";
777 reg = <0 0xe6b10000 0 777 reg = <0 0xe6b10000 0 0x2c>;
778 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&cpg CPG_MOD 779 clocks = <&cpg CPG_MOD 917>;
780 dmas = <&dmac0 0x17>, 780 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
781 <&dmac1 0x17>, 781 <&dmac1 0x17>, <&dmac1 0x18>;
782 dma-names = "tx", "rx" 782 dma-names = "tx", "rx", "tx", "rx";
783 power-domains = <&sysc 783 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
784 num-cs = <1>; 784 num-cs = <1>;
785 #address-cells = <1>; 785 #address-cells = <1>;
786 #size-cells = <0>; 786 #size-cells = <0>;
787 resets = <&cpg 917>; 787 resets = <&cpg 917>;
788 status = "disabled"; 788 status = "disabled";
789 }; 789 };
790 790
791 scifa0: serial@e6c40000 { 791 scifa0: serial@e6c40000 {
792 compatible = "renesas, 792 compatible = "renesas,scifa-r8a7744",
793 "renesas, 793 "renesas,rcar-gen2-scifa", "renesas,scifa";
794 reg = <0 0xe6c40000 0 794 reg = <0 0xe6c40000 0 0x40>;
795 interrupts = <GIC_SPI 795 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&cpg CPG_MOD 796 clocks = <&cpg CPG_MOD 204>;
797 clock-names = "fck"; 797 clock-names = "fck";
798 dmas = <&dmac0 0x21>, 798 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
799 <&dmac1 0x21>, 799 <&dmac1 0x21>, <&dmac1 0x22>;
800 dma-names = "tx", "rx" 800 dma-names = "tx", "rx", "tx", "rx";
801 power-domains = <&sysc 801 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
802 resets = <&cpg 204>; 802 resets = <&cpg 204>;
803 status = "disabled"; 803 status = "disabled";
804 }; 804 };
805 805
806 scifa1: serial@e6c50000 { 806 scifa1: serial@e6c50000 {
807 compatible = "renesas, 807 compatible = "renesas,scifa-r8a7744",
808 "renesas, 808 "renesas,rcar-gen2-scifa", "renesas,scifa";
809 reg = <0 0xe6c50000 0 809 reg = <0 0xe6c50000 0 0x40>;
810 interrupts = <GIC_SPI 810 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&cpg CPG_MOD 811 clocks = <&cpg CPG_MOD 203>;
812 clock-names = "fck"; 812 clock-names = "fck";
813 dmas = <&dmac0 0x25>, 813 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
814 <&dmac1 0x25>, 814 <&dmac1 0x25>, <&dmac1 0x26>;
815 dma-names = "tx", "rx" 815 dma-names = "tx", "rx", "tx", "rx";
816 power-domains = <&sysc 816 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
817 resets = <&cpg 203>; 817 resets = <&cpg 203>;
818 status = "disabled"; 818 status = "disabled";
819 }; 819 };
820 820
821 scifa2: serial@e6c60000 { 821 scifa2: serial@e6c60000 {
822 compatible = "renesas, 822 compatible = "renesas,scifa-r8a7744",
823 "renesas, 823 "renesas,rcar-gen2-scifa", "renesas,scifa";
824 reg = <0 0xe6c60000 0 824 reg = <0 0xe6c60000 0 0x40>;
825 interrupts = <GIC_SPI 825 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&cpg CPG_MOD 826 clocks = <&cpg CPG_MOD 202>;
827 clock-names = "fck"; 827 clock-names = "fck";
828 dmas = <&dmac0 0x27>, 828 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
829 <&dmac1 0x27>, 829 <&dmac1 0x27>, <&dmac1 0x28>;
830 dma-names = "tx", "rx" 830 dma-names = "tx", "rx", "tx", "rx";
831 power-domains = <&sysc 831 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
832 resets = <&cpg 202>; 832 resets = <&cpg 202>;
833 status = "disabled"; 833 status = "disabled";
834 }; 834 };
835 835
836 scifa3: serial@e6c70000 { 836 scifa3: serial@e6c70000 {
837 compatible = "renesas, 837 compatible = "renesas,scifa-r8a7744",
838 "renesas, 838 "renesas,rcar-gen2-scifa", "renesas,scifa";
839 reg = <0 0xe6c70000 0 839 reg = <0 0xe6c70000 0 0x40>;
840 interrupts = <GIC_SPI 840 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&cpg CPG_MOD 841 clocks = <&cpg CPG_MOD 1106>;
842 clock-names = "fck"; 842 clock-names = "fck";
843 dmas = <&dmac0 0x1b>, 843 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
844 <&dmac1 0x1b>, 844 <&dmac1 0x1b>, <&dmac1 0x1c>;
845 dma-names = "tx", "rx" 845 dma-names = "tx", "rx", "tx", "rx";
846 power-domains = <&sysc 846 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
847 resets = <&cpg 1106>; 847 resets = <&cpg 1106>;
848 status = "disabled"; 848 status = "disabled";
849 }; 849 };
850 850
851 scifa4: serial@e6c78000 { 851 scifa4: serial@e6c78000 {
852 compatible = "renesas, 852 compatible = "renesas,scifa-r8a7744",
853 "renesas, 853 "renesas,rcar-gen2-scifa", "renesas,scifa";
854 reg = <0 0xe6c78000 0 854 reg = <0 0xe6c78000 0 0x40>;
855 interrupts = <GIC_SPI 855 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&cpg CPG_MOD 856 clocks = <&cpg CPG_MOD 1107>;
857 clock-names = "fck"; 857 clock-names = "fck";
858 dmas = <&dmac0 0x1f>, 858 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
859 <&dmac1 0x1f>, 859 <&dmac1 0x1f>, <&dmac1 0x20>;
860 dma-names = "tx", "rx" 860 dma-names = "tx", "rx", "tx", "rx";
861 power-domains = <&sysc 861 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
862 resets = <&cpg 1107>; 862 resets = <&cpg 1107>;
863 status = "disabled"; 863 status = "disabled";
864 }; 864 };
865 865
866 scifa5: serial@e6c80000 { 866 scifa5: serial@e6c80000 {
867 compatible = "renesas, 867 compatible = "renesas,scifa-r8a7744",
868 "renesas, 868 "renesas,rcar-gen2-scifa", "renesas,scifa";
869 reg = <0 0xe6c80000 0 869 reg = <0 0xe6c80000 0 0x40>;
870 interrupts = <GIC_SPI 870 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 871 clocks = <&cpg CPG_MOD 1108>;
872 clock-names = "fck"; 872 clock-names = "fck";
873 dmas = <&dmac0 0x23>, 873 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
874 <&dmac1 0x23>, 874 <&dmac1 0x23>, <&dmac1 0x24>;
875 dma-names = "tx", "rx" 875 dma-names = "tx", "rx", "tx", "rx";
876 power-domains = <&sysc 876 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
877 resets = <&cpg 1108>; 877 resets = <&cpg 1108>;
878 status = "disabled"; 878 status = "disabled";
879 }; 879 };
880 880
881 scifb0: serial@e6c20000 { 881 scifb0: serial@e6c20000 {
882 compatible = "renesas, 882 compatible = "renesas,scifb-r8a7744",
883 "renesas, 883 "renesas,rcar-gen2-scifb", "renesas,scifb";
884 reg = <0 0xe6c20000 0 884 reg = <0 0xe6c20000 0 0x100>;
885 interrupts = <GIC_SPI 885 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&cpg CPG_MOD 886 clocks = <&cpg CPG_MOD 206>;
887 clock-names = "fck"; 887 clock-names = "fck";
888 dmas = <&dmac0 0x3d>, 888 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
889 <&dmac1 0x3d>, 889 <&dmac1 0x3d>, <&dmac1 0x3e>;
890 dma-names = "tx", "rx" 890 dma-names = "tx", "rx", "tx", "rx";
891 power-domains = <&sysc 891 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
892 resets = <&cpg 206>; 892 resets = <&cpg 206>;
893 status = "disabled"; 893 status = "disabled";
894 }; 894 };
895 895
896 scifb1: serial@e6c30000 { 896 scifb1: serial@e6c30000 {
897 compatible = "renesas, 897 compatible = "renesas,scifb-r8a7744",
898 "renesas, 898 "renesas,rcar-gen2-scifb", "renesas,scifb";
899 reg = <0 0xe6c30000 0 899 reg = <0 0xe6c30000 0 0x100>;
900 interrupts = <GIC_SPI 900 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&cpg CPG_MOD 901 clocks = <&cpg CPG_MOD 207>;
902 clock-names = "fck"; 902 clock-names = "fck";
903 dmas = <&dmac0 0x19>, 903 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
904 <&dmac1 0x19>, 904 <&dmac1 0x19>, <&dmac1 0x1a>;
905 dma-names = "tx", "rx" 905 dma-names = "tx", "rx", "tx", "rx";
906 power-domains = <&sysc 906 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
907 resets = <&cpg 207>; 907 resets = <&cpg 207>;
908 status = "disabled"; 908 status = "disabled";
909 }; 909 };
910 910
911 scifb2: serial@e6ce0000 { 911 scifb2: serial@e6ce0000 {
912 compatible = "renesas, 912 compatible = "renesas,scifb-r8a7744",
913 "renesas, 913 "renesas,rcar-gen2-scifb", "renesas,scifb";
914 reg = <0 0xe6ce0000 0 914 reg = <0 0xe6ce0000 0 0x100>;
915 interrupts = <GIC_SPI 915 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&cpg CPG_MOD 916 clocks = <&cpg CPG_MOD 216>;
917 clock-names = "fck"; 917 clock-names = "fck";
918 dmas = <&dmac0 0x1d>, 918 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
919 <&dmac1 0x1d>, 919 <&dmac1 0x1d>, <&dmac1 0x1e>;
920 dma-names = "tx", "rx" 920 dma-names = "tx", "rx", "tx", "rx";
921 power-domains = <&sysc 921 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
922 resets = <&cpg 216>; 922 resets = <&cpg 216>;
923 status = "disabled"; 923 status = "disabled";
924 }; 924 };
925 925
926 scif0: serial@e6e60000 { 926 scif0: serial@e6e60000 {
927 compatible = "renesas, 927 compatible = "renesas,scif-r8a7744",
928 "renesas, 928 "renesas,rcar-gen2-scif", "renesas,scif";
929 reg = <0 0xe6e60000 0 929 reg = <0 0xe6e60000 0 0x40>;
930 interrupts = <GIC_SPI 930 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&cpg CPG_MOD 931 clocks = <&cpg CPG_MOD 721>,
932 <&cpg CPG_COR 932 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
933 clock-names = "fck", " 933 clock-names = "fck", "brg_int", "scif_clk";
934 dmas = <&dmac0 0x29>, 934 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
935 <&dmac1 0x29>, 935 <&dmac1 0x29>, <&dmac1 0x2a>;
936 dma-names = "tx", "rx" 936 dma-names = "tx", "rx", "tx", "rx";
937 power-domains = <&sysc 937 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
938 resets = <&cpg 721>; 938 resets = <&cpg 721>;
939 status = "disabled"; 939 status = "disabled";
940 }; 940 };
941 941
942 scif1: serial@e6e68000 { 942 scif1: serial@e6e68000 {
943 compatible = "renesas, 943 compatible = "renesas,scif-r8a7744",
944 "renesas, 944 "renesas,rcar-gen2-scif", "renesas,scif";
945 reg = <0 0xe6e68000 0 945 reg = <0 0xe6e68000 0 0x40>;
946 interrupts = <GIC_SPI 946 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&cpg CPG_MOD 947 clocks = <&cpg CPG_MOD 720>,
948 <&cpg CPG_COR 948 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
949 clock-names = "fck", " 949 clock-names = "fck", "brg_int", "scif_clk";
950 dmas = <&dmac0 0x2d>, 950 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
951 <&dmac1 0x2d>, 951 <&dmac1 0x2d>, <&dmac1 0x2e>;
952 dma-names = "tx", "rx" 952 dma-names = "tx", "rx", "tx", "rx";
953 power-domains = <&sysc 953 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
954 resets = <&cpg 720>; 954 resets = <&cpg 720>;
955 status = "disabled"; 955 status = "disabled";
956 }; 956 };
957 957
958 scif2: serial@e6e58000 { 958 scif2: serial@e6e58000 {
959 compatible = "renesas, 959 compatible = "renesas,scif-r8a7744",
960 "renesas, 960 "renesas,rcar-gen2-scif", "renesas,scif";
961 reg = <0 0xe6e58000 0 961 reg = <0 0xe6e58000 0 0x40>;
962 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cpg CPG_MOD 963 clocks = <&cpg CPG_MOD 719>,
964 <&cpg CPG_COR 964 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
965 clock-names = "fck", " 965 clock-names = "fck", "brg_int", "scif_clk";
966 dmas = <&dmac0 0x2b>, 966 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
967 <&dmac1 0x2b>, 967 <&dmac1 0x2b>, <&dmac1 0x2c>;
968 dma-names = "tx", "rx" 968 dma-names = "tx", "rx", "tx", "rx";
969 power-domains = <&sysc 969 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
970 resets = <&cpg 719>; 970 resets = <&cpg 719>;
971 status = "disabled"; 971 status = "disabled";
972 }; 972 };
973 973
974 scif3: serial@e6ea8000 { 974 scif3: serial@e6ea8000 {
975 compatible = "renesas, 975 compatible = "renesas,scif-r8a7744",
976 "renesas, 976 "renesas,rcar-gen2-scif", "renesas,scif";
977 reg = <0 0xe6ea8000 0 977 reg = <0 0xe6ea8000 0 0x40>;
978 interrupts = <GIC_SPI 978 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&cpg CPG_MOD 979 clocks = <&cpg CPG_MOD 718>,
980 <&cpg CPG_COR 980 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
981 clock-names = "fck", " 981 clock-names = "fck", "brg_int", "scif_clk";
982 dmas = <&dmac0 0x2f>, 982 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
983 <&dmac1 0x2f>, 983 <&dmac1 0x2f>, <&dmac1 0x30>;
984 dma-names = "tx", "rx" 984 dma-names = "tx", "rx", "tx", "rx";
985 power-domains = <&sysc 985 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
986 resets = <&cpg 718>; 986 resets = <&cpg 718>;
987 status = "disabled"; 987 status = "disabled";
988 }; 988 };
989 989
990 scif4: serial@e6ee0000 { 990 scif4: serial@e6ee0000 {
991 compatible = "renesas, 991 compatible = "renesas,scif-r8a7744",
992 "renesas, 992 "renesas,rcar-gen2-scif", "renesas,scif";
993 reg = <0 0xe6ee0000 0 993 reg = <0 0xe6ee0000 0 0x40>;
994 interrupts = <GIC_SPI 994 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&cpg CPG_MOD 995 clocks = <&cpg CPG_MOD 715>,
996 <&cpg CPG_COR 996 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
997 clock-names = "fck", " 997 clock-names = "fck", "brg_int", "scif_clk";
998 dmas = <&dmac0 0xfb>, 998 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
999 <&dmac1 0xfb>, 999 <&dmac1 0xfb>, <&dmac1 0xfc>;
1000 dma-names = "tx", "rx 1000 dma-names = "tx", "rx", "tx", "rx";
1001 power-domains = <&sys 1001 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1002 resets = <&cpg 715>; 1002 resets = <&cpg 715>;
1003 status = "disabled"; 1003 status = "disabled";
1004 }; 1004 };
1005 1005
1006 scif5: serial@e6ee8000 { 1006 scif5: serial@e6ee8000 {
1007 compatible = "renesas 1007 compatible = "renesas,scif-r8a7744",
1008 "renesas 1008 "renesas,rcar-gen2-scif", "renesas,scif";
1009 reg = <0 0xe6ee8000 0 1009 reg = <0 0xe6ee8000 0 0x40>;
1010 interrupts = <GIC_SPI 1010 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&cpg CPG_MO 1011 clocks = <&cpg CPG_MOD 714>,
1012 <&cpg CPG_CO 1012 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
1013 clock-names = "fck", 1013 clock-names = "fck", "brg_int", "scif_clk";
1014 dmas = <&dmac0 0xfd>, 1014 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
1015 <&dmac1 0xfd>, 1015 <&dmac1 0xfd>, <&dmac1 0xfe>;
1016 dma-names = "tx", "rx 1016 dma-names = "tx", "rx", "tx", "rx";
1017 power-domains = <&sys 1017 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1018 resets = <&cpg 714>; 1018 resets = <&cpg 714>;
1019 status = "disabled"; 1019 status = "disabled";
1020 }; 1020 };
1021 1021
1022 hscif0: serial@e62c0000 { 1022 hscif0: serial@e62c0000 {
1023 compatible = "renesas 1023 compatible = "renesas,hscif-r8a7744",
1024 "renesas 1024 "renesas,rcar-gen2-hscif", "renesas,hscif";
1025 reg = <0 0xe62c0000 0 1025 reg = <0 0xe62c0000 0 0x60>;
1026 interrupts = <GIC_SPI 1026 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&cpg CPG_MO 1027 clocks = <&cpg CPG_MOD 717>,
1028 <&cpg CPG_CO 1028 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
1029 clock-names = "fck", 1029 clock-names = "fck", "brg_int", "scif_clk";
1030 dmas = <&dmac0 0x39>, 1030 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
1031 <&dmac1 0x39>, 1031 <&dmac1 0x39>, <&dmac1 0x3a>;
1032 dma-names = "tx", "rx 1032 dma-names = "tx", "rx", "tx", "rx";
1033 power-domains = <&sys 1033 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1034 resets = <&cpg 717>; 1034 resets = <&cpg 717>;
1035 status = "disabled"; 1035 status = "disabled";
1036 }; 1036 };
1037 1037
1038 hscif1: serial@e62c8000 { 1038 hscif1: serial@e62c8000 {
1039 compatible = "renesas 1039 compatible = "renesas,hscif-r8a7744",
1040 "renesas 1040 "renesas,rcar-gen2-hscif", "renesas,hscif";
1041 reg = <0 0xe62c8000 0 1041 reg = <0 0xe62c8000 0 0x60>;
1042 interrupts = <GIC_SPI 1042 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&cpg CPG_MO 1043 clocks = <&cpg CPG_MOD 716>,
1044 <&cpg CPG_CO 1044 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
1045 clock-names = "fck", 1045 clock-names = "fck", "brg_int", "scif_clk";
1046 dmas = <&dmac0 0x4d>, 1046 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
1047 <&dmac1 0x4d>, 1047 <&dmac1 0x4d>, <&dmac1 0x4e>;
1048 dma-names = "tx", "rx 1048 dma-names = "tx", "rx", "tx", "rx";
1049 power-domains = <&sys 1049 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1050 resets = <&cpg 716>; 1050 resets = <&cpg 716>;
1051 status = "disabled"; 1051 status = "disabled";
1052 }; 1052 };
1053 1053
1054 hscif2: serial@e62d0000 { 1054 hscif2: serial@e62d0000 {
1055 compatible = "renesas 1055 compatible = "renesas,hscif-r8a7744",
1056 "renesas 1056 "renesas,rcar-gen2-hscif", "renesas,hscif";
1057 reg = <0 0xe62d0000 0 1057 reg = <0 0xe62d0000 0 0x60>;
1058 interrupts = <GIC_SPI 1058 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&cpg CPG_MO 1059 clocks = <&cpg CPG_MOD 713>,
1060 <&cpg CPG_CO 1060 <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>;
1061 clock-names = "fck", 1061 clock-names = "fck", "brg_int", "scif_clk";
1062 dmas = <&dmac0 0x3b>, 1062 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
1063 <&dmac1 0x3b>, 1063 <&dmac1 0x3b>, <&dmac1 0x3c>;
1064 dma-names = "tx", "rx 1064 dma-names = "tx", "rx", "tx", "rx";
1065 power-domains = <&sys 1065 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1066 resets = <&cpg 713>; 1066 resets = <&cpg 713>;
1067 status = "disabled"; 1067 status = "disabled";
1068 }; 1068 };
1069 1069
1070 msiof0: spi@e6e20000 { 1070 msiof0: spi@e6e20000 {
1071 compatible = "renesas 1071 compatible = "renesas,msiof-r8a7744",
1072 "renesas 1072 "renesas,rcar-gen2-msiof";
1073 reg = <0 0xe6e20000 0 1073 reg = <0 0xe6e20000 0 0x0064>;
1074 interrupts = <GIC_SPI 1074 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&cpg CPG_MO 1075 clocks = <&cpg CPG_MOD 000>;
1076 dmas = <&dmac0 0x51>, 1076 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1077 <&dmac1 0x51>, 1077 <&dmac1 0x51>, <&dmac1 0x52>;
1078 dma-names = "tx", "rx 1078 dma-names = "tx", "rx", "tx", "rx";
1079 power-domains = <&sys 1079 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1080 #address-cells = <1>; 1080 #address-cells = <1>;
1081 #size-cells = <0>; 1081 #size-cells = <0>;
1082 resets = <&cpg 000>; 1082 resets = <&cpg 000>;
1083 status = "disabled"; 1083 status = "disabled";
1084 }; 1084 };
1085 1085
1086 msiof1: spi@e6e10000 { 1086 msiof1: spi@e6e10000 {
1087 compatible = "renesas 1087 compatible = "renesas,msiof-r8a7744",
1088 "renesas 1088 "renesas,rcar-gen2-msiof";
1089 reg = <0 0xe6e10000 0 1089 reg = <0 0xe6e10000 0 0x0064>;
1090 interrupts = <GIC_SPI 1090 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&cpg CPG_MO 1091 clocks = <&cpg CPG_MOD 208>;
1092 dmas = <&dmac0 0x55>, 1092 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1093 <&dmac1 0x55>, 1093 <&dmac1 0x55>, <&dmac1 0x56>;
1094 dma-names = "tx", "rx 1094 dma-names = "tx", "rx", "tx", "rx";
1095 power-domains = <&sys 1095 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1096 #address-cells = <1>; 1096 #address-cells = <1>;
1097 #size-cells = <0>; 1097 #size-cells = <0>;
1098 resets = <&cpg 208>; 1098 resets = <&cpg 208>;
1099 status = "disabled"; 1099 status = "disabled";
1100 }; 1100 };
1101 1101
1102 msiof2: spi@e6e00000 { 1102 msiof2: spi@e6e00000 {
1103 compatible = "renesas 1103 compatible = "renesas,msiof-r8a7744",
1104 "renesas 1104 "renesas,rcar-gen2-msiof";
1105 reg = <0 0xe6e00000 0 1105 reg = <0 0xe6e00000 0 0x0064>;
1106 interrupts = <GIC_SPI 1106 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&cpg CPG_MO 1107 clocks = <&cpg CPG_MOD 205>;
1108 dmas = <&dmac0 0x41>, 1108 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1109 <&dmac1 0x41>, 1109 <&dmac1 0x41>, <&dmac1 0x42>;
1110 dma-names = "tx", "rx 1110 dma-names = "tx", "rx", "tx", "rx";
1111 power-domains = <&sys 1111 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1112 #address-cells = <1>; 1112 #address-cells = <1>;
1113 #size-cells = <0>; 1113 #size-cells = <0>;
1114 resets = <&cpg 205>; 1114 resets = <&cpg 205>;
1115 status = "disabled"; 1115 status = "disabled";
1116 }; 1116 };
1117 1117
1118 pwm0: pwm@e6e30000 { 1118 pwm0: pwm@e6e30000 {
1119 compatible = "renesas 1119 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1120 reg = <0 0xe6e30000 0 1120 reg = <0 0xe6e30000 0 0x8>;
1121 clocks = <&cpg CPG_MO 1121 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 1122 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 1123 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 1124 #pwm-cells = <2>;
1125 status = "disabled"; 1125 status = "disabled";
1126 }; 1126 };
1127 1127
1128 pwm1: pwm@e6e31000 { 1128 pwm1: pwm@e6e31000 {
1129 compatible = "renesas 1129 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1130 reg = <0 0xe6e31000 0 1130 reg = <0 0xe6e31000 0 0x8>;
1131 clocks = <&cpg CPG_MO 1131 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 1132 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 1133 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 1134 #pwm-cells = <2>;
1135 status = "disabled"; 1135 status = "disabled";
1136 }; 1136 };
1137 1137
1138 pwm2: pwm@e6e32000 { 1138 pwm2: pwm@e6e32000 {
1139 compatible = "renesas 1139 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1140 reg = <0 0xe6e32000 0 1140 reg = <0 0xe6e32000 0 0x8>;
1141 clocks = <&cpg CPG_MO 1141 clocks = <&cpg CPG_MOD 523>;
1142 power-domains = <&sys 1142 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1143 resets = <&cpg 523>; 1143 resets = <&cpg 523>;
1144 #pwm-cells = <2>; 1144 #pwm-cells = <2>;
1145 status = "disabled"; 1145 status = "disabled";
1146 }; 1146 };
1147 1147
1148 pwm3: pwm@e6e33000 { 1148 pwm3: pwm@e6e33000 {
1149 compatible = "renesas 1149 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1150 reg = <0 0xe6e33000 0 1150 reg = <0 0xe6e33000 0 0x8>;
1151 clocks = <&cpg CPG_MO 1151 clocks = <&cpg CPG_MOD 523>;
1152 power-domains = <&sys 1152 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1153 resets = <&cpg 523>; 1153 resets = <&cpg 523>;
1154 #pwm-cells = <2>; 1154 #pwm-cells = <2>;
1155 status = "disabled"; 1155 status = "disabled";
1156 }; 1156 };
1157 1157
1158 pwm4: pwm@e6e34000 { 1158 pwm4: pwm@e6e34000 {
1159 compatible = "renesas 1159 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1160 reg = <0 0xe6e34000 0 1160 reg = <0 0xe6e34000 0 0x8>;
1161 clocks = <&cpg CPG_MO 1161 clocks = <&cpg CPG_MOD 523>;
1162 power-domains = <&sys 1162 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1163 resets = <&cpg 523>; 1163 resets = <&cpg 523>;
1164 #pwm-cells = <2>; 1164 #pwm-cells = <2>;
1165 status = "disabled"; 1165 status = "disabled";
1166 }; 1166 };
1167 1167
1168 pwm5: pwm@e6e35000 { 1168 pwm5: pwm@e6e35000 {
1169 compatible = "renesas 1169 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1170 reg = <0 0xe6e35000 0 1170 reg = <0 0xe6e35000 0 0x8>;
1171 clocks = <&cpg CPG_MO 1171 clocks = <&cpg CPG_MOD 523>;
1172 power-domains = <&sys 1172 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1173 resets = <&cpg 523>; 1173 resets = <&cpg 523>;
1174 #pwm-cells = <2>; 1174 #pwm-cells = <2>;
1175 status = "disabled"; 1175 status = "disabled";
1176 }; 1176 };
1177 1177
1178 pwm6: pwm@e6e36000 { 1178 pwm6: pwm@e6e36000 {
1179 compatible = "renesas 1179 compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
1180 reg = <0 0xe6e36000 0 1180 reg = <0 0xe6e36000 0 0x8>;
1181 clocks = <&cpg CPG_MO 1181 clocks = <&cpg CPG_MOD 523>;
1182 power-domains = <&sys 1182 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1183 resets = <&cpg 523>; 1183 resets = <&cpg 523>;
1184 #pwm-cells = <2>; 1184 #pwm-cells = <2>;
1185 status = "disabled"; 1185 status = "disabled";
1186 }; 1186 };
1187 1187
1188 can0: can@e6e80000 { 1188 can0: can@e6e80000 {
1189 compatible = "renesas 1189 compatible = "renesas,can-r8a7744",
1190 "renesas 1190 "renesas,rcar-gen2-can";
1191 reg = <0 0xe6e80000 0 1191 reg = <0 0xe6e80000 0 0x1000>;
1192 interrupts = <GIC_SPI 1192 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&cpg CPG_MO 1193 clocks = <&cpg CPG_MOD 916>,
1194 <&cpg CPG_CO 1194 <&cpg CPG_CORE R8A7744_CLK_RCAN>,
1195 <&can_clk>; 1195 <&can_clk>;
1196 clock-names = "clkp1" 1196 clock-names = "clkp1", "clkp2", "can_clk";
1197 power-domains = <&sys 1197 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1198 resets = <&cpg 916>; 1198 resets = <&cpg 916>;
1199 status = "disabled"; 1199 status = "disabled";
1200 }; 1200 };
1201 1201
1202 can1: can@e6e88000 { 1202 can1: can@e6e88000 {
1203 compatible = "renesas 1203 compatible = "renesas,can-r8a7744",
1204 "renesas 1204 "renesas,rcar-gen2-can";
1205 reg = <0 0xe6e88000 0 1205 reg = <0 0xe6e88000 0 0x1000>;
1206 interrupts = <GIC_SPI 1206 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&cpg CPG_MO 1207 clocks = <&cpg CPG_MOD 915>,
1208 <&cpg CPG_CO 1208 <&cpg CPG_CORE R8A7744_CLK_RCAN>,
1209 <&can_clk>; 1209 <&can_clk>;
1210 clock-names = "clkp1" 1210 clock-names = "clkp1", "clkp2", "can_clk";
1211 power-domains = <&sys 1211 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1212 resets = <&cpg 915>; 1212 resets = <&cpg 915>;
1213 status = "disabled"; 1213 status = "disabled";
1214 }; 1214 };
1215 1215
1216 vin0: video@e6ef0000 { 1216 vin0: video@e6ef0000 {
1217 compatible = "renesas 1217 compatible = "renesas,vin-r8a7744",
1218 "renesas 1218 "renesas,rcar-gen2-vin";
1219 reg = <0 0xe6ef0000 0 1219 reg = <0 0xe6ef0000 0 0x1000>;
1220 interrupts = <GIC_SPI 1220 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&cpg CPG_MO 1221 clocks = <&cpg CPG_MOD 811>;
1222 power-domains = <&sys 1222 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1223 resets = <&cpg 811>; 1223 resets = <&cpg 811>;
1224 status = "disabled"; 1224 status = "disabled";
1225 }; 1225 };
1226 1226
1227 vin1: video@e6ef1000 { 1227 vin1: video@e6ef1000 {
1228 compatible = "renesas 1228 compatible = "renesas,vin-r8a7744",
1229 "renesas 1229 "renesas,rcar-gen2-vin";
1230 reg = <0 0xe6ef1000 0 1230 reg = <0 0xe6ef1000 0 0x1000>;
1231 interrupts = <GIC_SPI 1231 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&cpg CPG_MO 1232 clocks = <&cpg CPG_MOD 810>;
1233 power-domains = <&sys 1233 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1234 resets = <&cpg 810>; 1234 resets = <&cpg 810>;
1235 status = "disabled"; 1235 status = "disabled";
1236 }; 1236 };
1237 1237
1238 vin2: video@e6ef2000 { 1238 vin2: video@e6ef2000 {
1239 compatible = "renesas 1239 compatible = "renesas,vin-r8a7744",
1240 "renesas 1240 "renesas,rcar-gen2-vin";
1241 reg = <0 0xe6ef2000 0 1241 reg = <0 0xe6ef2000 0 0x1000>;
1242 interrupts = <GIC_SPI 1242 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&cpg CPG_MO 1243 clocks = <&cpg CPG_MOD 809>;
1244 power-domains = <&sys 1244 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1245 resets = <&cpg 809>; 1245 resets = <&cpg 809>;
1246 status = "disabled"; 1246 status = "disabled";
1247 }; 1247 };
1248 1248
1249 rcar_sound: sound@ec500000 { 1249 rcar_sound: sound@ec500000 {
1250 /* 1250 /*
1251 * #sound-dai-cells i 1251 * #sound-dai-cells is required if simple-card
1252 * 1252 *
1253 * Single DAI : #soun 1253 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1254 * Multi DAI : #soun 1254 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1255 */ 1255 */
1256 compatible = "renesas 1256 compatible = "renesas,rcar_sound-r8a7744",
1257 "renesas 1257 "renesas,rcar_sound-gen2";
1258 reg = <0 0xec500000 0 1258 reg = <0 0xec500000 0 0x1000>, /* SCU */
1259 <0 0xec5a0000 0 1259 <0 0xec5a0000 0 0x100>, /* ADG */
1260 <0 0xec540000 0 1260 <0 0xec540000 0 0x1000>, /* SSIU */
1261 <0 0xec541000 0 1261 <0 0xec541000 0 0x280>, /* SSI */
1262 <0 0xec740000 0 1262 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1263 reg-names = "scu", "a 1263 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1264 1264
1265 clocks = <&cpg CPG_MO 1265 clocks = <&cpg CPG_MOD 1005>,
1266 <&cpg CPG_MO 1266 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1267 <&cpg CPG_MO 1267 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1268 <&cpg CPG_MO 1268 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1269 <&cpg CPG_MO 1269 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1270 <&cpg CPG_MO 1270 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1271 <&cpg CPG_MO 1271 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1272 <&cpg CPG_MO 1272 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1273 <&cpg CPG_MO 1273 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1274 <&cpg CPG_MO 1274 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1275 <&cpg CPG_MO 1275 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1276 <&cpg CPG_MO 1276 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1277 <&cpg CPG_MO 1277 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1278 <&cpg CPG_MO 1278 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1279 <&audio_clk_ 1279 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
1280 <&cpg CPG_CO 1280 <&cpg CPG_CORE R8A7744_CLK_M2>;
1281 clock-names = "ssi-al 1281 clock-names = "ssi-all",
1282 "ssi.9" 1282 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1283 "ssi.4" 1283 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1284 "src.9" 1284 "src.9", "src.8", "src.7", "src.6", "src.5",
1285 "src.4" 1285 "src.4", "src.3", "src.2", "src.1", "src.0",
1286 "ctu.0" 1286 "ctu.0", "ctu.1",
1287 "mix.0" 1287 "mix.0", "mix.1",
1288 "dvc.0" 1288 "dvc.0", "dvc.1",
1289 "clk_a" 1289 "clk_a", "clk_b", "clk_c", "clk_i";
1290 power-domains = <&sys 1290 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1291 resets = <&cpg 1005>, 1291 resets = <&cpg 1005>,
1292 <&cpg 1006>, 1292 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
1293 <&cpg 1010>, 1293 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
1294 <&cpg 1014>, 1294 <&cpg 1014>, <&cpg 1015>;
1295 reset-names = "ssi-al 1295 reset-names = "ssi-all",
1296 "ssi.9" 1296 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1297 "ssi.4" 1297 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
1298 status = "disabled"; 1298 status = "disabled";
1299 1299
1300 rcar_sound,dvc { 1300 rcar_sound,dvc {
1301 dvc0: dvc-0 { 1301 dvc0: dvc-0 {
1302 dmas 1302 dmas = <&audma1 0xbc>;
1303 dma-n 1303 dma-names = "tx";
1304 }; 1304 };
1305 dvc1: dvc-1 { 1305 dvc1: dvc-1 {
1306 dmas 1306 dmas = <&audma1 0xbe>;
1307 dma-n 1307 dma-names = "tx";
1308 }; 1308 };
1309 }; 1309 };
1310 1310
1311 rcar_sound,mix { 1311 rcar_sound,mix {
1312 mix0: mix-0 { 1312 mix0: mix-0 { };
1313 mix1: mix-1 { 1313 mix1: mix-1 { };
1314 }; 1314 };
1315 1315
1316 rcar_sound,ctu { 1316 rcar_sound,ctu {
1317 ctu00: ctu-0 1317 ctu00: ctu-0 { };
1318 ctu01: ctu-1 1318 ctu01: ctu-1 { };
1319 ctu02: ctu-2 1319 ctu02: ctu-2 { };
1320 ctu03: ctu-3 1320 ctu03: ctu-3 { };
1321 ctu10: ctu-4 1321 ctu10: ctu-4 { };
1322 ctu11: ctu-5 1322 ctu11: ctu-5 { };
1323 ctu12: ctu-6 1323 ctu12: ctu-6 { };
1324 ctu13: ctu-7 1324 ctu13: ctu-7 { };
1325 }; 1325 };
1326 1326
1327 rcar_sound,src { 1327 rcar_sound,src {
1328 src0: src-0 { 1328 src0: src-0 {
1329 inter 1329 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1330 dmas 1330 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1331 dma-n 1331 dma-names = "rx", "tx";
1332 }; 1332 };
1333 src1: src-1 { 1333 src1: src-1 {
1334 inter 1334 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1335 dmas 1335 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1336 dma-n 1336 dma-names = "rx", "tx";
1337 }; 1337 };
1338 src2: src-2 { 1338 src2: src-2 {
1339 inter 1339 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1340 dmas 1340 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1341 dma-n 1341 dma-names = "rx", "tx";
1342 }; 1342 };
1343 src3: src-3 { 1343 src3: src-3 {
1344 inter 1344 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1345 dmas 1345 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1346 dma-n 1346 dma-names = "rx", "tx";
1347 }; 1347 };
1348 src4: src-4 { 1348 src4: src-4 {
1349 inter 1349 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1350 dmas 1350 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1351 dma-n 1351 dma-names = "rx", "tx";
1352 }; 1352 };
1353 src5: src-5 { 1353 src5: src-5 {
1354 inter 1354 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1355 dmas 1355 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1356 dma-n 1356 dma-names = "rx", "tx";
1357 }; 1357 };
1358 src6: src-6 { 1358 src6: src-6 {
1359 inter 1359 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1360 dmas 1360 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1361 dma-n 1361 dma-names = "rx", "tx";
1362 }; 1362 };
1363 src7: src-7 { 1363 src7: src-7 {
1364 inter 1364 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1365 dmas 1365 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1366 dma-n 1366 dma-names = "rx", "tx";
1367 }; 1367 };
1368 src8: src-8 { 1368 src8: src-8 {
1369 inter 1369 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1370 dmas 1370 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1371 dma-n 1371 dma-names = "rx", "tx";
1372 }; 1372 };
1373 src9: src-9 { 1373 src9: src-9 {
1374 inter 1374 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1375 dmas 1375 dmas = <&audma0 0x97>, <&audma1 0xba>;
1376 dma-n 1376 dma-names = "rx", "tx";
1377 }; 1377 };
1378 }; 1378 };
1379 1379
1380 rcar_sound,ssi { 1380 rcar_sound,ssi {
1381 ssi0: ssi-0 { 1381 ssi0: ssi-0 {
1382 inter 1382 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1383 dmas 1383 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1384 dma-n 1384 dma-names = "rx", "tx", "rxu", "txu";
1385 }; 1385 };
1386 ssi1: ssi-1 { 1386 ssi1: ssi-1 {
1387 inter 1387 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1388 dmas 1388 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1389 dma-n 1389 dma-names = "rx", "tx", "rxu", "txu";
1390 }; 1390 };
1391 ssi2: ssi-2 { 1391 ssi2: ssi-2 {
1392 inter 1392 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1393 dmas 1393 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1394 dma-n 1394 dma-names = "rx", "tx", "rxu", "txu";
1395 }; 1395 };
1396 ssi3: ssi-3 { 1396 ssi3: ssi-3 {
1397 inter 1397 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1398 dmas 1398 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1399 dma-n 1399 dma-names = "rx", "tx", "rxu", "txu";
1400 }; 1400 };
1401 ssi4: ssi-4 { 1401 ssi4: ssi-4 {
1402 inter 1402 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1403 dmas 1403 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1404 dma-n 1404 dma-names = "rx", "tx", "rxu", "txu";
1405 }; 1405 };
1406 ssi5: ssi-5 { 1406 ssi5: ssi-5 {
1407 inter 1407 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1408 dmas 1408 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1409 dma-n 1409 dma-names = "rx", "tx", "rxu", "txu";
1410 }; 1410 };
1411 ssi6: ssi-6 { 1411 ssi6: ssi-6 {
1412 inter 1412 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1413 dmas 1413 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1414 dma-n 1414 dma-names = "rx", "tx", "rxu", "txu";
1415 }; 1415 };
1416 ssi7: ssi-7 { 1416 ssi7: ssi-7 {
1417 inter 1417 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1418 dmas 1418 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1419 dma-n 1419 dma-names = "rx", "tx", "rxu", "txu";
1420 }; 1420 };
1421 ssi8: ssi-8 { 1421 ssi8: ssi-8 {
1422 inter 1422 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1423 dmas 1423 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1424 dma-n 1424 dma-names = "rx", "tx", "rxu", "txu";
1425 }; 1425 };
1426 ssi9: ssi-9 { 1426 ssi9: ssi-9 {
1427 inter 1427 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1428 dmas 1428 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1429 dma-n 1429 dma-names = "rx", "tx", "rxu", "txu";
1430 }; 1430 };
1431 }; 1431 };
1432 }; 1432 };
1433 1433
1434 audma0: dma-controller@ec7000 1434 audma0: dma-controller@ec700000 {
1435 compatible = "renesas 1435 compatible = "renesas,dmac-r8a7744",
1436 "renesas 1436 "renesas,rcar-dmac";
1437 reg = <0 0xec700000 0 1437 reg = <0 0xec700000 0 0x10000>;
1438 interrupts = <GIC_SPI 1438 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 1439 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 1440 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 1441 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 1442 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 1443 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1444 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1445 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1446 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1447 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1448 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1449 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1450 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1451 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1452 interrupt-names = "er 1452 interrupt-names = "error",
1453 "ch 1453 "ch0", "ch1", "ch2", "ch3",
1454 "ch 1454 "ch4", "ch5", "ch6", "ch7",
1455 "ch 1455 "ch8", "ch9", "ch10", "ch11",
1456 "ch 1456 "ch12";
1457 clocks = <&cpg CPG_MO 1457 clocks = <&cpg CPG_MOD 502>;
1458 clock-names = "fck"; 1458 clock-names = "fck";
1459 power-domains = <&sys 1459 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1460 resets = <&cpg 502>; 1460 resets = <&cpg 502>;
1461 #dma-cells = <1>; 1461 #dma-cells = <1>;
1462 dma-channels = <13>; 1462 dma-channels = <13>;
1463 }; 1463 };
1464 1464
1465 audma1: dma-controller@ec7200 1465 audma1: dma-controller@ec720000 {
1466 compatible = "renesas 1466 compatible = "renesas,dmac-r8a7744",
1467 "renesas 1467 "renesas,rcar-dmac";
1468 reg = <0 0xec720000 0 1468 reg = <0 0xec720000 0 0x10000>;
1469 interrupts = <GIC_SPI 1469 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 1470 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 1471 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 1472 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 1473 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 1474 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 1475 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 1476 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 1477 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 1478 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 1479 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 1480 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 1481 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 1482 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1483 interrupt-names = "er 1483 interrupt-names = "error",
1484 "ch 1484 "ch0", "ch1", "ch2", "ch3",
1485 "ch 1485 "ch4", "ch5", "ch6", "ch7",
1486 "ch 1486 "ch8", "ch9", "ch10", "ch11",
1487 "ch 1487 "ch12";
1488 clocks = <&cpg CPG_MO 1488 clocks = <&cpg CPG_MOD 501>;
1489 clock-names = "fck"; 1489 clock-names = "fck";
1490 power-domains = <&sys 1490 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1491 resets = <&cpg 501>; 1491 resets = <&cpg 501>;
1492 #dma-cells = <1>; 1492 #dma-cells = <1>;
1493 dma-channels = <13>; 1493 dma-channels = <13>;
1494 }; 1494 };
1495 1495
1496 /* 1496 /*
1497 * pci1 and xhci share the sa 1497 * pci1 and xhci share the same phy, therefore only one of them
1498 * can be active at any one t 1498 * can be active at any one time. If both of them are enabled,
1499 * a race condition will dete 1499 * a race condition will determine who'll control the phy.
1500 * A firmware file is needed 1500 * A firmware file is needed by the xhci driver in order for
1501 * USB 3.0 to work properly. 1501 * USB 3.0 to work properly.
1502 */ 1502 */
1503 xhci: usb@ee000000 { 1503 xhci: usb@ee000000 {
1504 compatible = "renesas 1504 compatible = "renesas,xhci-r8a7744",
1505 "renesas 1505 "renesas,rcar-gen2-xhci";
1506 reg = <0 0xee000000 0 1506 reg = <0 0xee000000 0 0xc00>;
1507 interrupts = <GIC_SPI 1507 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cpg CPG_MO 1508 clocks = <&cpg CPG_MOD 328>;
1509 power-domains = <&sys 1509 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1510 resets = <&cpg 328>; 1510 resets = <&cpg 328>;
1511 phys = <&usb2 1>; 1511 phys = <&usb2 1>;
1512 phy-names = "usb"; 1512 phy-names = "usb";
1513 status = "disabled"; 1513 status = "disabled";
1514 }; 1514 };
1515 1515
1516 pci0: pci@ee090000 { 1516 pci0: pci@ee090000 {
1517 compatible = "renesas 1517 compatible = "renesas,pci-r8a7744",
1518 "renesas 1518 "renesas,pci-rcar-gen2";
1519 device_type = "pci"; 1519 device_type = "pci";
1520 reg = <0 0xee090000 0 1520 reg = <0 0xee090000 0 0xc00>,
1521 <0 0xee080000 0 1521 <0 0xee080000 0 0x1100>;
1522 interrupts = <GIC_SPI 1522 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&cpg CPG_MO 1523 clocks = <&cpg CPG_MOD 703>;
1524 power-domains = <&sys 1524 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1525 resets = <&cpg 703>; 1525 resets = <&cpg 703>;
1526 status = "disabled"; 1526 status = "disabled";
1527 1527
1528 bus-range = <0 0>; 1528 bus-range = <0 0>;
1529 #address-cells = <3>; 1529 #address-cells = <3>;
1530 #size-cells = <2>; 1530 #size-cells = <2>;
1531 #interrupt-cells = <1 1531 #interrupt-cells = <1>;
1532 ranges = <0x02000000 1532 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1533 interrupt-map-mask = 1533 interrupt-map-mask = <0xf800 0 0 0x7>;
1534 interrupt-map = <0x00 1534 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1535 <0x08 1535 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1536 <0x10 1536 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1537 1537
1538 usb@1,0 { 1538 usb@1,0 {
1539 reg = <0x800 1539 reg = <0x800 0 0 0 0>;
1540 phys = <&usb0 1540 phys = <&usb0 0>;
1541 phy-names = " 1541 phy-names = "usb";
1542 }; 1542 };
1543 1543
1544 usb@2,0 { 1544 usb@2,0 {
1545 reg = <0x1000 1545 reg = <0x1000 0 0 0 0>;
1546 phys = <&usb0 1546 phys = <&usb0 0>;
1547 phy-names = " 1547 phy-names = "usb";
1548 }; 1548 };
1549 }; 1549 };
1550 1550
1551 pci1: pci@ee0d0000 { 1551 pci1: pci@ee0d0000 {
1552 compatible = "renesas 1552 compatible = "renesas,pci-r8a7744",
1553 "renesas 1553 "renesas,pci-rcar-gen2";
1554 device_type = "pci"; 1554 device_type = "pci";
1555 reg = <0 0xee0d0000 0 1555 reg = <0 0xee0d0000 0 0xc00>,
1556 <0 0xee0c0000 0 1556 <0 0xee0c0000 0 0x1100>;
1557 interrupts = <GIC_SPI 1557 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1558 clocks = <&cpg CPG_MO 1558 clocks = <&cpg CPG_MOD 703>;
1559 power-domains = <&sys 1559 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1560 resets = <&cpg 703>; 1560 resets = <&cpg 703>;
1561 status = "disabled"; 1561 status = "disabled";
1562 1562
1563 bus-range = <1 1>; 1563 bus-range = <1 1>;
1564 #address-cells = <3>; 1564 #address-cells = <3>;
1565 #size-cells = <2>; 1565 #size-cells = <2>;
1566 #interrupt-cells = <1 1566 #interrupt-cells = <1>;
1567 ranges = <0x02000000 1567 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1568 interrupt-map-mask = 1568 interrupt-map-mask = <0xf800 0 0 0x7>;
1569 interrupt-map = <0x00 1569 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1570 <0x08 1570 <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1571 <0x10 1571 <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1572 1572
1573 usb@1,0 { 1573 usb@1,0 {
1574 reg = <0x1080 1574 reg = <0x10800 0 0 0 0>;
1575 phys = <&usb2 1575 phys = <&usb2 0>;
1576 phy-names = " 1576 phy-names = "usb";
1577 }; 1577 };
1578 1578
1579 usb@2,0 { 1579 usb@2,0 {
1580 reg = <0x1100 1580 reg = <0x11000 0 0 0 0>;
1581 phys = <&usb2 1581 phys = <&usb2 0>;
1582 phy-names = " 1582 phy-names = "usb";
1583 }; 1583 };
1584 }; 1584 };
1585 1585
1586 sdhi0: mmc@ee100000 { 1586 sdhi0: mmc@ee100000 {
1587 compatible = "renesas 1587 compatible = "renesas,sdhi-r8a7744",
1588 "renesas 1588 "renesas,rcar-gen2-sdhi";
1589 reg = <0 0xee100000 0 1589 reg = <0 0xee100000 0 0x328>;
1590 interrupts = <GIC_SPI 1590 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1591 clocks = <&cpg CPG_MO 1591 clocks = <&cpg CPG_MOD 314>;
1592 dmas = <&dmac0 0xcd>, 1592 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1593 <&dmac1 0xcd>, 1593 <&dmac1 0xcd>, <&dmac1 0xce>;
1594 dma-names = "tx", "rx 1594 dma-names = "tx", "rx", "tx", "rx";
1595 max-frequency = <1950 1595 max-frequency = <195000000>;
1596 power-domains = <&sys 1596 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1597 resets = <&cpg 314>; 1597 resets = <&cpg 314>;
1598 status = "disabled"; 1598 status = "disabled";
1599 }; 1599 };
1600 1600
1601 sdhi1: mmc@ee140000 { 1601 sdhi1: mmc@ee140000 {
1602 compatible = "renesas 1602 compatible = "renesas,sdhi-r8a7744",
1603 "renesas 1603 "renesas,rcar-gen2-sdhi";
1604 reg = <0 0xee140000 0 1604 reg = <0 0xee140000 0 0x100>;
1605 interrupts = <GIC_SPI 1605 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1606 clocks = <&cpg CPG_MO 1606 clocks = <&cpg CPG_MOD 312>;
1607 dmas = <&dmac0 0xc1>, 1607 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1608 <&dmac1 0xc1>, 1608 <&dmac1 0xc1>, <&dmac1 0xc2>;
1609 dma-names = "tx", "rx 1609 dma-names = "tx", "rx", "tx", "rx";
1610 max-frequency = <9750 1610 max-frequency = <97500000>;
1611 power-domains = <&sys 1611 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1612 resets = <&cpg 312>; 1612 resets = <&cpg 312>;
1613 status = "disabled"; 1613 status = "disabled";
1614 }; 1614 };
1615 1615
1616 sdhi2: mmc@ee160000 { 1616 sdhi2: mmc@ee160000 {
1617 compatible = "renesas 1617 compatible = "renesas,sdhi-r8a7744",
1618 "renesas 1618 "renesas,rcar-gen2-sdhi";
1619 reg = <0 0xee160000 0 1619 reg = <0 0xee160000 0 0x100>;
1620 interrupts = <GIC_SPI 1620 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1621 clocks = <&cpg CPG_MO 1621 clocks = <&cpg CPG_MOD 311>;
1622 dmas = <&dmac0 0xd3>, 1622 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1623 <&dmac1 0xd3>, 1623 <&dmac1 0xd3>, <&dmac1 0xd4>;
1624 dma-names = "tx", "rx 1624 dma-names = "tx", "rx", "tx", "rx";
1625 max-frequency = <9750 1625 max-frequency = <97500000>;
1626 power-domains = <&sys 1626 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1627 resets = <&cpg 311>; 1627 resets = <&cpg 311>;
1628 status = "disabled"; 1628 status = "disabled";
1629 }; 1629 };
1630 1630
1631 mmcif0: mmc@ee200000 { 1631 mmcif0: mmc@ee200000 {
1632 compatible = "renesas 1632 compatible = "renesas,mmcif-r8a7744",
1633 "renesas 1633 "renesas,sh-mmcif";
1634 reg = <0 0xee200000 0 1634 reg = <0 0xee200000 0 0x80>;
1635 interrupts = <GIC_SPI 1635 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1636 clocks = <&cpg CPG_MO 1636 clocks = <&cpg CPG_MOD 315>;
1637 dmas = <&dmac0 0xd1>, 1637 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1638 <&dmac1 0xd1>, 1638 <&dmac1 0xd1>, <&dmac1 0xd2>;
1639 dma-names = "tx", "rx 1639 dma-names = "tx", "rx", "tx", "rx";
1640 power-domains = <&sys 1640 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1641 resets = <&cpg 315>; 1641 resets = <&cpg 315>;
1642 reg-io-width = <4>; 1642 reg-io-width = <4>;
1643 max-frequency = <9750 1643 max-frequency = <97500000>;
1644 status = "disabled"; 1644 status = "disabled";
1645 }; 1645 };
1646 1646
1647 gic: interrupt-controller@f10 1647 gic: interrupt-controller@f1001000 {
1648 compatible = "arm,gic 1648 compatible = "arm,gic-400";
1649 #interrupt-cells = <3 1649 #interrupt-cells = <3>;
1650 #address-cells = <0>; 1650 #address-cells = <0>;
1651 interrupt-controller; 1651 interrupt-controller;
1652 reg = <0 0xf1001000 0 1652 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1653 <0 0xf1004000 0 1653 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1654 interrupts = <GIC_PPI 1654 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1655 clocks = <&cpg CPG_MO 1655 clocks = <&cpg CPG_MOD 408>;
1656 clock-names = "clk"; 1656 clock-names = "clk";
1657 power-domains = <&sys 1657 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1658 resets = <&cpg 408>; 1658 resets = <&cpg 408>;
1659 }; 1659 };
1660 1660
1661 pciec: pcie@fe000000 { 1661 pciec: pcie@fe000000 {
1662 compatible = "renesas 1662 compatible = "renesas,pcie-r8a7744",
1663 "renesas 1663 "renesas,pcie-rcar-gen2";
1664 reg = <0 0xfe000000 0 1664 reg = <0 0xfe000000 0 0x80000>;
1665 #address-cells = <3>; 1665 #address-cells = <3>;
1666 #size-cells = <2>; 1666 #size-cells = <2>;
1667 bus-range = <0x00 0xf 1667 bus-range = <0x00 0xff>;
1668 device_type = "pci"; 1668 device_type = "pci";
1669 ranges = <0x01000000 1669 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1670 <0x02000000 1670 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1671 <0x02000000 1671 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1672 <0x42000000 1672 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1673 /* Map all possible D 1673 /* Map all possible DDR as inbound ranges */
1674 dma-ranges = <0x42000 1674 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
1675 <0x43000 1675 <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1676 interrupts = <GIC_SPI 1676 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1677 <GIC_SPI 1677 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 1678 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1679 #interrupt-cells = <1 1679 #interrupt-cells = <1>;
1680 interrupt-map-mask = 1680 interrupt-map-mask = <0 0 0 0>;
1681 interrupt-map = <0 0 1681 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1682 clocks = <&cpg CPG_MO 1682 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1683 clock-names = "pcie", 1683 clock-names = "pcie", "pcie_bus";
1684 power-domains = <&sys 1684 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1685 resets = <&cpg 319>; 1685 resets = <&cpg 319>;
1686 status = "disabled"; 1686 status = "disabled";
1687 }; 1687 };
1688 1688
1689 vsp@fe928000 { 1689 vsp@fe928000 {
1690 compatible = "renesas 1690 compatible = "renesas,vsp1";
1691 reg = <0 0xfe928000 0 1691 reg = <0 0xfe928000 0 0x8000>;
1692 interrupts = <GIC_SPI 1692 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1693 clocks = <&cpg CPG_MO 1693 clocks = <&cpg CPG_MOD 131>;
1694 power-domains = <&sys 1694 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1695 resets = <&cpg 131>; 1695 resets = <&cpg 131>;
1696 }; 1696 };
1697 1697
1698 vsp@fe930000 { 1698 vsp@fe930000 {
1699 compatible = "renesas 1699 compatible = "renesas,vsp1";
1700 reg = <0 0xfe930000 0 1700 reg = <0 0xfe930000 0 0x8000>;
1701 interrupts = <GIC_SPI 1701 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1702 clocks = <&cpg CPG_MO 1702 clocks = <&cpg CPG_MOD 128>;
1703 power-domains = <&sys 1703 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1704 resets = <&cpg 128>; 1704 resets = <&cpg 128>;
1705 }; 1705 };
1706 1706
1707 vsp@fe938000 { 1707 vsp@fe938000 {
1708 compatible = "renesas 1708 compatible = "renesas,vsp1";
1709 reg = <0 0xfe938000 0 1709 reg = <0 0xfe938000 0 0x8000>;
1710 interrupts = <GIC_SPI 1710 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1711 clocks = <&cpg CPG_MO 1711 clocks = <&cpg CPG_MOD 127>;
1712 power-domains = <&sys 1712 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1713 resets = <&cpg 127>; 1713 resets = <&cpg 127>;
1714 }; 1714 };
1715 1715
1716 du: display@feb00000 { 1716 du: display@feb00000 {
1717 compatible = "renesas 1717 compatible = "renesas,du-r8a7744";
1718 reg = <0 0xfeb00000 0 1718 reg = <0 0xfeb00000 0 0x40000>;
1719 interrupts = <GIC_SPI 1719 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1720 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1721 clocks = <&cpg CPG_MO 1721 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1722 clock-names = "du.0", 1722 clock-names = "du.0", "du.1";
1723 resets = <&cpg 724>; 1723 resets = <&cpg 724>;
1724 reset-names = "du.0"; 1724 reset-names = "du.0";
1725 status = "disabled"; 1725 status = "disabled";
1726 1726
1727 ports { 1727 ports {
1728 #address-cell 1728 #address-cells = <1>;
1729 #size-cells = 1729 #size-cells = <0>;
1730 1730
1731 port@0 { 1731 port@0 {
1732 reg = 1732 reg = <0>;
1733 du_ou 1733 du_out_rgb: endpoint {
1734 }; 1734 };
1735 }; 1735 };
1736 port@1 { 1736 port@1 {
1737 reg = 1737 reg = <1>;
1738 du_ou 1738 du_out_lvds0: endpoint {
1739 1739 remote-endpoint = <&lvds0_in>;
1740 }; 1740 };
1741 }; 1741 };
1742 }; 1742 };
1743 }; 1743 };
1744 1744
1745 lvds0: lvds@feb90000 { 1745 lvds0: lvds@feb90000 {
1746 compatible = "renesas 1746 compatible = "renesas,r8a7744-lvds";
1747 reg = <0 0xfeb90000 0 1747 reg = <0 0xfeb90000 0 0x1c>;
1748 clocks = <&cpg CPG_MO 1748 clocks = <&cpg CPG_MOD 726>;
1749 power-domains = <&sys 1749 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1750 resets = <&cpg 726>; 1750 resets = <&cpg 726>;
1751 status = "disabled"; 1751 status = "disabled";
1752 1752
1753 ports { 1753 ports {
1754 #address-cell 1754 #address-cells = <1>;
1755 #size-cells = 1755 #size-cells = <0>;
1756 1756
1757 port@0 { 1757 port@0 {
1758 reg = 1758 reg = <0>;
1759 lvds0 1759 lvds0_in: endpoint {
1760 1760 remote-endpoint = <&du_out_lvds0>;
1761 }; 1761 };
1762 }; 1762 };
1763 port@1 { 1763 port@1 {
1764 reg = 1764 reg = <1>;
1765 lvds0 1765 lvds0_out: endpoint {
1766 }; 1766 };
1767 }; 1767 };
1768 }; 1768 };
1769 }; 1769 };
1770 1770
1771 prr: chipid@ff000044 { 1771 prr: chipid@ff000044 {
1772 compatible = "renesas 1772 compatible = "renesas,prr";
1773 reg = <0 0xff000044 0 1773 reg = <0 0xff000044 0 4>;
1774 }; 1774 };
1775 1775
1776 cmt0: timer@ffca0000 { 1776 cmt0: timer@ffca0000 {
1777 compatible = "renesas 1777 compatible = "renesas,r8a7744-cmt0",
1778 "renesas 1778 "renesas,rcar-gen2-cmt0";
1779 reg = <0 0xffca0000 0 1779 reg = <0 0xffca0000 0 0x1004>;
1780 interrupts = <GIC_SPI 1780 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 1781 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1782 clocks = <&cpg CPG_MO 1782 clocks = <&cpg CPG_MOD 124>;
1783 clock-names = "fck"; 1783 clock-names = "fck";
1784 power-domains = <&sys 1784 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1785 resets = <&cpg 124>; 1785 resets = <&cpg 124>;
1786 status = "disabled"; 1786 status = "disabled";
1787 }; 1787 };
1788 1788
1789 cmt1: timer@e6130000 { 1789 cmt1: timer@e6130000 {
1790 compatible = "renesas 1790 compatible = "renesas,r8a7744-cmt1",
1791 "renesas 1791 "renesas,rcar-gen2-cmt1";
1792 reg = <0 0xe6130000 0 1792 reg = <0 0xe6130000 0 0x1004>;
1793 interrupts = <GIC_SPI 1793 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 1794 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 1795 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 1796 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 1797 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 1798 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 1799 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 1800 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1801 clocks = <&cpg CPG_MO 1801 clocks = <&cpg CPG_MOD 329>;
1802 clock-names = "fck"; 1802 clock-names = "fck";
1803 power-domains = <&sys 1803 power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
1804 resets = <&cpg 329>; 1804 resets = <&cpg 329>;
1805 status = "disabled"; 1805 status = "disabled";
1806 }; 1806 };
1807 }; 1807 };
1808 1808
1809 thermal-zones { 1809 thermal-zones {
1810 cpu_thermal: cpu-thermal { 1810 cpu_thermal: cpu-thermal {
1811 polling-delay-passive 1811 polling-delay-passive = <0>;
1812 polling-delay = <0>; 1812 polling-delay = <0>;
1813 1813
1814 thermal-sensors = <&t 1814 thermal-sensors = <&thermal>;
1815 1815
1816 trips { 1816 trips {
1817 cpu-crit { 1817 cpu-crit {
1818 tempe 1818 temperature = <95000>;
1819 hyste 1819 hysteresis = <0>;
1820 type 1820 type = "critical";
1821 }; 1821 };
1822 }; 1822 };
1823 1823
1824 cooling-maps { 1824 cooling-maps {
1825 }; 1825 };
1826 }; 1826 };
1827 }; 1827 };
1828 1828
1829 timer { 1829 timer {
1830 compatible = "arm,armv7-timer 1830 compatible = "arm,armv7-timer";
1831 interrupts-extended = <&gic G 1831 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1832 <&gic G 1832 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1833 <&gic G 1833 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1834 <&gic G 1834 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1835 interrupt-names = "sec-phys", 1835 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1836 }; 1836 };
1837 1837
1838 /* External USB clock - can be overri 1838 /* External USB clock - can be overridden by the board */
1839 usb_extal_clk: usb_extal { 1839 usb_extal_clk: usb_extal {
1840 compatible = "fixed-clock"; 1840 compatible = "fixed-clock";
1841 #clock-cells = <0>; 1841 #clock-cells = <0>;
1842 clock-frequency = <48000000>; 1842 clock-frequency = <48000000>;
1843 }; 1843 };
1844 }; 1844 };
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