1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the SK-RZG1E board 3 * Device Tree Source for the SK-RZG1E board
4 * 4 *
5 * Copyright (C) 2016-2017 Cogent Embedded, In 5 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 #include "r8a7745.dtsi" 9 #include "r8a7745.dtsi"
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 11
12 / { 12 / {
13 model = "SK-RZG1E"; 13 model = "SK-RZG1E";
14 compatible = "renesas,sk-rzg1e", "rene 14 compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
15 15
16 aliases { 16 aliases {
17 serial0 = &scif2; 17 serial0 = &scif2;
18 }; 18 };
19 19
20 chosen { 20 chosen {
21 bootargs = "ignore_loglevel rw 21 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
22 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
23 }; 23 };
24 24
25 memory@40000000 { 25 memory@40000000 {
26 device_type = "memory"; 26 device_type = "memory";
27 reg = <0 0x40000000 0 0x400000 27 reg = <0 0x40000000 0 0x40000000>;
28 }; 28 };
29 }; 29 };
30 30
31 &extal_clk { 31 &extal_clk {
32 clock-frequency = <20000000>; 32 clock-frequency = <20000000>;
33 }; 33 };
34 34
35 &pfc { 35 &pfc {
36 scif2_pins: scif2 { 36 scif2_pins: scif2 {
37 groups = "scif2_data"; 37 groups = "scif2_data";
38 function = "scif2"; 38 function = "scif2";
39 }; 39 };
40 40
41 ether_pins: ether { 41 ether_pins: ether {
42 groups = "eth_link", "eth_mdio 42 groups = "eth_link", "eth_mdio", "eth_rmii";
43 function = "eth"; 43 function = "eth";
44 }; 44 };
45 45
46 phy1_pins: phy1 { 46 phy1_pins: phy1 {
47 groups = "intc_irq8"; 47 groups = "intc_irq8";
48 function = "intc"; 48 function = "intc";
49 }; 49 };
50 }; 50 };
51 51
52 &scif2 { 52 &scif2 {
53 pinctrl-0 = <&scif2_pins>; 53 pinctrl-0 = <&scif2_pins>;
54 pinctrl-names = "default"; 54 pinctrl-names = "default";
55 55
56 status = "okay"; 56 status = "okay";
57 }; 57 };
58 58
59 ðer { 59 ðer {
60 pinctrl-0 = <ðer_pins>, <&phy1_pins 60 pinctrl-0 = <ðer_pins>, <&phy1_pins>;
61 pinctrl-names = "default"; 61 pinctrl-names = "default";
62 62
63 phy-handle = <&phy1>; 63 phy-handle = <&phy1>;
64 renesas,ether-link-active-low; 64 renesas,ether-link-active-low;
65 status = "okay"; 65 status = "okay";
66 66
67 phy1: ethernet-phy@1 { 67 phy1: ethernet-phy@1 {
68 compatible = "ethernet-phy-id0 68 compatible = "ethernet-phy-id0022.1537",
69 "ethernet-phy-iee 69 "ethernet-phy-ieee802.3-c22";
70 reg = <1>; 70 reg = <1>;
71 interrupt-parent = <&irqc>; 71 interrupt-parent = <&irqc>;
72 interrupts = <8 IRQ_TYPE_LEVEL 72 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
73 micrel,led-mode = <1>; 73 micrel,led-mode = <1>;
74 reset-gpios = <&gpio1 24 GPIO_ 74 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
75 }; 75 };
76 }; 76 };
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