1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the SH-Mobile AG5 (R 3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
4 * 4 *
5 * Copyright (C) 2012 Renesas Solutions Corp. 5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/sh73a0-clock.h> 8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 11
12 / { 12 / {
13 compatible = "renesas,sh73a0"; 13 compatible = "renesas,sh73a0";
14 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 17
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 21
22 cpu0: cpu@0 { 22 cpu0: cpu@0 {
23 device_type = "cpu"; 23 device_type = "cpu";
24 compatible = "arm,cort 24 compatible = "arm,cortex-a9";
25 reg = <0>; 25 reg = <0>;
26 clock-frequency = <119 26 clock-frequency = <1196000000>;
27 clocks = <&cpg_clocks 27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
28 power-domains = <&pd_a 28 power-domains = <&pd_a2sl>;
29 next-level-cache = <&L 29 next-level-cache = <&L2>;
30 }; 30 };
31 cpu1: cpu@1 { 31 cpu1: cpu@1 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 compatible = "arm,cort 33 compatible = "arm,cortex-a9";
34 reg = <1>; 34 reg = <1>;
35 clock-frequency = <119 35 clock-frequency = <1196000000>;
36 clocks = <&cpg_clocks 36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
37 power-domains = <&pd_a 37 power-domains = <&pd_a2sl>;
38 next-level-cache = <&L 38 next-level-cache = <&L2>;
39 }; 39 };
40 }; 40 };
41 41
42 timer@f0000200 { 42 timer@f0000200 {
43 compatible = "arm,cortex-a9-gl 43 compatible = "arm,cortex-a9-global-timer";
44 reg = <0xf0000200 0x100>; 44 reg = <0xf0000200 0x100>;
45 interrupts = <GIC_PPI 11 (GIC_ 45 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
46 clocks = <&periph_clk>; 46 clocks = <&periph_clk>;
47 }; 47 };
48 48
49 timer@f0000600 { 49 timer@f0000600 {
50 compatible = "arm,cortex-a9-tw 50 compatible = "arm,cortex-a9-twd-timer";
51 reg = <0xf0000600 0x20>; 51 reg = <0xf0000600 0x20>;
52 interrupts = <GIC_PPI 13 (GIC_ 52 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
53 clocks = <&periph_clk>; 53 clocks = <&periph_clk>;
54 }; 54 };
55 55
56 gic: interrupt-controller@f0001000 { 56 gic: interrupt-controller@f0001000 {
57 compatible = "arm,cortex-a9-gi 57 compatible = "arm,cortex-a9-gic";
58 #interrupt-cells = <3>; 58 #interrupt-cells = <3>;
59 interrupt-controller; 59 interrupt-controller;
60 reg = <0xf0001000 0x1000>, 60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>; 61 <0xf0000100 0x100>;
62 }; 62 };
63 63
64 L2: cache-controller@f0100000 { 64 L2: cache-controller@f0100000 {
65 compatible = "arm,pl310-cache" 65 compatible = "arm,pl310-cache";
66 reg = <0xf0100000 0x1000>; 66 reg = <0xf0100000 0x1000>;
67 interrupts = <GIC_SPI 44 IRQ_T 67 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
68 power-domains = <&pd_a3sm>; 68 power-domains = <&pd_a3sm>;
69 arm,data-latency = <3 3 3>; 69 arm,data-latency = <3 3 3>;
70 arm,tag-latency = <2 2 2>; 70 arm,tag-latency = <2 2 2>;
71 arm,shared-override; 71 arm,shared-override;
72 cache-unified; 72 cache-unified;
73 cache-level = <2>; 73 cache-level = <2>;
74 }; 74 };
75 75
76 sbsc2: memory-controller@fb400000 { 76 sbsc2: memory-controller@fb400000 {
77 compatible = "renesas,sbsc-sh7 77 compatible = "renesas,sbsc-sh73a0";
78 reg = <0xfb400000 0x400>; 78 reg = <0xfb400000 0x400>;
79 interrupts = <GIC_SPI 37 IRQ_T 79 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 38 IRQ_T 80 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
81 interrupt-names = "sec", "temp 81 interrupt-names = "sec", "temp";
82 power-domains = <&pd_a4bc1>; 82 power-domains = <&pd_a4bc1>;
83 }; 83 };
84 84
85 sbsc1: memory-controller@fe400000 { 85 sbsc1: memory-controller@fe400000 {
86 compatible = "renesas,sbsc-sh7 86 compatible = "renesas,sbsc-sh73a0";
87 reg = <0xfe400000 0x400>; 87 reg = <0xfe400000 0x400>;
88 interrupts = <GIC_SPI 35 IRQ_T 88 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 36 IRQ_T 89 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
90 interrupt-names = "sec", "temp 90 interrupt-names = "sec", "temp";
91 power-domains = <&pd_a4bc0>; 91 power-domains = <&pd_a4bc0>;
92 }; 92 };
93 93
94 pmu { 94 pmu {
95 compatible = "arm,cortex-a9-pm 95 compatible = "arm,cortex-a9-pmu";
96 interrupts = <GIC_SPI 55 IRQ_T 96 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 56 IRQ_T 97 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
98 interrupt-affinity = <&cpu0>, 98 interrupt-affinity = <&cpu0>, <&cpu1>;
99 }; 99 };
100 100
101 cmt1: timer@e6138000 { 101 cmt1: timer@e6138000 {
102 compatible = "renesas,sh73a0-c 102 compatible = "renesas,sh73a0-cmt1";
103 reg = <0xe6138000 0x200>; 103 reg = <0xe6138000 0x200>;
104 interrupts = <GIC_SPI 65 IRQ_T 104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&mstp3_clks SH73A0_C 105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
106 clock-names = "fck"; 106 clock-names = "fck";
107 power-domains = <&pd_c5>; 107 power-domains = <&pd_c5>;
108 status = "disabled"; 108 status = "disabled";
109 }; 109 };
110 110
111 irqpin0: interrupt-controller@e6900000 111 irqpin0: interrupt-controller@e6900000 {
112 compatible = "renesas,intc-irq 112 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
113 #interrupt-cells = <2>; 113 #interrupt-cells = <2>;
114 interrupt-controller; 114 interrupt-controller;
115 reg = <0xe6900000 4>, 115 reg = <0xe6900000 4>,
116 <0xe6900010 4>, 116 <0xe6900010 4>,
117 <0xe6900020 1>, 117 <0xe6900020 1>,
118 <0xe6900040 1>, 118 <0xe6900040 1>,
119 <0xe6900060 1>; 119 <0xe6900060 1>;
120 interrupts = <GIC_SPI 1 IRQ_TY 120 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 2 IRQ_TY 121 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 3 IRQ_TY 122 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 4 IRQ_TY 123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 5 IRQ_TY 124 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 6 IRQ_TY 125 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 7 IRQ_TY 126 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 8 IRQ_TY 127 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&mstp5_clks SH73A0_C 128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
129 power-domains = <&pd_a4s>; 129 power-domains = <&pd_a4s>;
130 control-parent; 130 control-parent;
131 }; 131 };
132 132
133 irqpin1: interrupt-controller@e6900004 133 irqpin1: interrupt-controller@e6900004 {
134 compatible = "renesas,intc-irq 134 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
135 #interrupt-cells = <2>; 135 #interrupt-cells = <2>;
136 interrupt-controller; 136 interrupt-controller;
137 reg = <0xe6900004 4>, 137 reg = <0xe6900004 4>,
138 <0xe6900014 4>, 138 <0xe6900014 4>,
139 <0xe6900024 1>, 139 <0xe6900024 1>,
140 <0xe6900044 1>, 140 <0xe6900044 1>,
141 <0xe6900064 1>; 141 <0xe6900064 1>;
142 interrupts = <GIC_SPI 9 IRQ_T 142 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 10 IRQ_T 143 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 11 IRQ_T 144 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 12 IRQ_T 145 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 13 IRQ_T 146 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 14 IRQ_T 147 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 15 IRQ_T 148 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 16 IRQ_T 149 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&mstp5_clks SH73A0_C 150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
151 power-domains = <&pd_a4s>; 151 power-domains = <&pd_a4s>;
152 control-parent; 152 control-parent;
153 }; 153 };
154 154
155 irqpin2: interrupt-controller@e6900008 155 irqpin2: interrupt-controller@e6900008 {
156 compatible = "renesas,intc-irq 156 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
157 #interrupt-cells = <2>; 157 #interrupt-cells = <2>;
158 interrupt-controller; 158 interrupt-controller;
159 reg = <0xe6900008 4>, 159 reg = <0xe6900008 4>,
160 <0xe6900018 4>, 160 <0xe6900018 4>,
161 <0xe6900028 1>, 161 <0xe6900028 1>,
162 <0xe6900048 1>, 162 <0xe6900048 1>,
163 <0xe6900068 1>; 163 <0xe6900068 1>;
164 interrupts = <GIC_SPI 17 IRQ_T 164 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 18 IRQ_T 165 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 19 IRQ_T 166 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 20 IRQ_T 167 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 21 IRQ_T 168 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 22 IRQ_T 169 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 23 IRQ_T 170 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 24 IRQ_T 171 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&mstp5_clks SH73A0_C 172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
173 power-domains = <&pd_a4s>; 173 power-domains = <&pd_a4s>;
174 control-parent; 174 control-parent;
175 }; 175 };
176 176
177 irqpin3: interrupt-controller@e690000c 177 irqpin3: interrupt-controller@e690000c {
178 compatible = "renesas,intc-irq 178 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
179 #interrupt-cells = <2>; 179 #interrupt-cells = <2>;
180 interrupt-controller; 180 interrupt-controller;
181 reg = <0xe690000c 4>, 181 reg = <0xe690000c 4>,
182 <0xe690001c 4>, 182 <0xe690001c 4>,
183 <0xe690002c 1>, 183 <0xe690002c 1>,
184 <0xe690004c 1>, 184 <0xe690004c 1>,
185 <0xe690006c 1>; 185 <0xe690006c 1>;
186 interrupts = <GIC_SPI 25 IRQ_T 186 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 26 IRQ_T 187 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 27 IRQ_T 188 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 28 IRQ_T 189 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 29 IRQ_T 190 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 30 IRQ_T 191 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 31 IRQ_T 192 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 32 IRQ_T 193 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp5_clks SH73A0_C 194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
195 power-domains = <&pd_a4s>; 195 power-domains = <&pd_a4s>;
196 control-parent; 196 control-parent;
197 }; 197 };
198 198
199 i2c0: i2c@e6820000 { 199 i2c0: i2c@e6820000 {
200 #address-cells = <1>; 200 #address-cells = <1>;
201 #size-cells = <0>; 201 #size-cells = <0>;
202 compatible = "renesas,iic-sh73 202 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
203 reg = <0xe6820000 0x425>; 203 reg = <0xe6820000 0x425>;
204 interrupts = <GIC_SPI 167 IRQ_ 204 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 168 IRQ_ 205 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 169 IRQ_ 206 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 170 IRQ_ 207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp1_clks SH73A0_C 208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
209 power-domains = <&pd_a3sp>; 209 power-domains = <&pd_a3sp>;
210 status = "disabled"; 210 status = "disabled";
211 }; 211 };
212 212
213 i2c1: i2c@e6822000 { 213 i2c1: i2c@e6822000 {
214 #address-cells = <1>; 214 #address-cells = <1>;
215 #size-cells = <0>; 215 #size-cells = <0>;
216 compatible = "renesas,iic-sh73 216 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
217 reg = <0xe6822000 0x425>; 217 reg = <0xe6822000 0x425>;
218 interrupts = <GIC_SPI 51 IRQ_T 218 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 52 IRQ_T 219 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 53 IRQ_T 220 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 54 IRQ_T 221 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp3_clks SH73A0_C 222 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
223 power-domains = <&pd_a3sp>; 223 power-domains = <&pd_a3sp>;
224 status = "disabled"; 224 status = "disabled";
225 }; 225 };
226 226
227 i2c2: i2c@e6824000 { 227 i2c2: i2c@e6824000 {
228 #address-cells = <1>; 228 #address-cells = <1>;
229 #size-cells = <0>; 229 #size-cells = <0>;
230 compatible = "renesas,iic-sh73 230 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
231 reg = <0xe6824000 0x425>; 231 reg = <0xe6824000 0x425>;
232 interrupts = <GIC_SPI 171 IRQ_ 232 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 172 IRQ_ 233 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 173 IRQ_ 234 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 174 IRQ_ 235 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp0_clks SH73A0_C 236 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
237 power-domains = <&pd_a3sp>; 237 power-domains = <&pd_a3sp>;
238 status = "disabled"; 238 status = "disabled";
239 }; 239 };
240 240
241 i2c3: i2c@e6826000 { 241 i2c3: i2c@e6826000 {
242 #address-cells = <1>; 242 #address-cells = <1>;
243 #size-cells = <0>; 243 #size-cells = <0>;
244 compatible = "renesas,iic-sh73 244 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
245 reg = <0xe6826000 0x425>; 245 reg = <0xe6826000 0x425>;
246 interrupts = <GIC_SPI 183 IRQ_ 246 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 184 IRQ_ 247 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 185 IRQ_ 248 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 186 IRQ_ 249 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp4_clks SH73A0_C 250 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
251 power-domains = <&pd_a3sp>; 251 power-domains = <&pd_a3sp>;
252 status = "disabled"; 252 status = "disabled";
253 }; 253 };
254 254
255 i2c4: i2c@e6828000 { 255 i2c4: i2c@e6828000 {
256 #address-cells = <1>; 256 #address-cells = <1>;
257 #size-cells = <0>; 257 #size-cells = <0>;
258 compatible = "renesas,iic-sh73 258 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
259 reg = <0xe6828000 0x425>; 259 reg = <0xe6828000 0x425>;
260 interrupts = <GIC_SPI 187 IRQ_ 260 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 188 IRQ_ 261 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 189 IRQ_ 262 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 190 IRQ_ 263 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp4_clks SH73A0_C 264 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
265 power-domains = <&pd_c5>; 265 power-domains = <&pd_c5>;
266 status = "disabled"; 266 status = "disabled";
267 }; 267 };
268 268
269 mmcif: mmc@e6bd0000 { 269 mmcif: mmc@e6bd0000 {
270 compatible = "renesas,mmcif-sh 270 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
271 reg = <0xe6bd0000 0x100>; 271 reg = <0xe6bd0000 0x100>;
272 interrupts = <GIC_SPI 140 IRQ_ 272 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 141 IRQ_ 273 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp3_clks SH73A0_C 274 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
275 power-domains = <&pd_a3sp>; 275 power-domains = <&pd_a3sp>;
276 reg-io-width = <4>; 276 reg-io-width = <4>;
277 status = "disabled"; 277 status = "disabled";
278 }; 278 };
279 279
280 msiof0: spi@e6e20000 { 280 msiof0: spi@e6e20000 {
281 compatible = "renesas,msiof-sh 281 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
282 reg = <0xe6e20000 0x0064>; 282 reg = <0xe6e20000 0x0064>;
283 interrupts = <GIC_SPI 142 IRQ_ 283 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&mstp0_clks SH73A0_C 284 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
285 power-domains = <&pd_a3sp>; 285 power-domains = <&pd_a3sp>;
286 #address-cells = <1>; 286 #address-cells = <1>;
287 #size-cells = <0>; 287 #size-cells = <0>;
288 status = "disabled"; 288 status = "disabled";
289 }; 289 };
290 290
291 msiof1: spi@e6e10000 { 291 msiof1: spi@e6e10000 {
292 compatible = "renesas,msiof-sh 292 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
293 reg = <0xe6e10000 0x0064>; 293 reg = <0xe6e10000 0x0064>;
294 interrupts = <GIC_SPI 77 IRQ_T 294 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp2_clks SH73A0_C 295 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
296 power-domains = <&pd_a3sp>; 296 power-domains = <&pd_a3sp>;
297 #address-cells = <1>; 297 #address-cells = <1>;
298 #size-cells = <0>; 298 #size-cells = <0>;
299 status = "disabled"; 299 status = "disabled";
300 }; 300 };
301 301
302 msiof2: spi@e6e00000 { 302 msiof2: spi@e6e00000 {
303 compatible = "renesas,msiof-sh 303 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
304 reg = <0xe6e00000 0x0064>; 304 reg = <0xe6e00000 0x0064>;
305 interrupts = <GIC_SPI 76 IRQ_T 305 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp2_clks SH73A0_C 306 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
307 power-domains = <&pd_a3sp>; 307 power-domains = <&pd_a3sp>;
308 #address-cells = <1>; 308 #address-cells = <1>;
309 #size-cells = <0>; 309 #size-cells = <0>;
310 status = "disabled"; 310 status = "disabled";
311 }; 311 };
312 312
313 msiof3: spi@e6c90000 { 313 msiof3: spi@e6c90000 {
314 compatible = "renesas,msiof-sh 314 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
315 reg = <0xe6c90000 0x0064>; 315 reg = <0xe6c90000 0x0064>;
316 interrupts = <GIC_SPI 59 IRQ_T 316 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp2_clks SH73A0_C 317 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
318 power-domains = <&pd_a3sp>; 318 power-domains = <&pd_a3sp>;
319 #address-cells = <1>; 319 #address-cells = <1>;
320 #size-cells = <0>; 320 #size-cells = <0>;
321 status = "disabled"; 321 status = "disabled";
322 }; 322 };
323 323
324 sdhi0: mmc@ee100000 { 324 sdhi0: mmc@ee100000 {
325 compatible = "renesas,sdhi-sh7 325 compatible = "renesas,sdhi-sh73a0";
326 reg = <0xee100000 0x100>; 326 reg = <0xee100000 0x100>;
327 interrupts = <GIC_SPI 83 IRQ_T 327 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 84 IRQ_T 328 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 85 IRQ_T 329 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp3_clks SH73A0_C 330 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
331 power-domains = <&pd_a3sp>; 331 power-domains = <&pd_a3sp>;
332 cap-sd-highspeed; 332 cap-sd-highspeed;
333 status = "disabled"; 333 status = "disabled";
334 }; 334 };
335 335
336 /* SDHI1 and SDHI2 have no CD pins, no 336 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
337 sdhi1: mmc@ee120000 { 337 sdhi1: mmc@ee120000 {
338 compatible = "renesas,sdhi-sh7 338 compatible = "renesas,sdhi-sh73a0";
339 reg = <0xee120000 0x100>; 339 reg = <0xee120000 0x100>;
340 interrupts = <GIC_SPI 88 IRQ_T 340 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 89 IRQ_T 341 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp3_clks SH73A0_C 342 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
343 power-domains = <&pd_a3sp>; 343 power-domains = <&pd_a3sp>;
344 disable-wp; 344 disable-wp;
345 cap-sd-highspeed; 345 cap-sd-highspeed;
346 status = "disabled"; 346 status = "disabled";
347 }; 347 };
348 348
349 sdhi2: mmc@ee140000 { 349 sdhi2: mmc@ee140000 {
350 compatible = "renesas,sdhi-sh7 350 compatible = "renesas,sdhi-sh73a0";
351 reg = <0xee140000 0x100>; 351 reg = <0xee140000 0x100>;
352 interrupts = <GIC_SPI 104 IRQ_ 352 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 105 IRQ_ 353 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp3_clks SH73A0_C 354 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
355 power-domains = <&pd_a3sp>; 355 power-domains = <&pd_a3sp>;
356 disable-wp; 356 disable-wp;
357 cap-sd-highspeed; 357 cap-sd-highspeed;
358 status = "disabled"; 358 status = "disabled";
359 }; 359 };
360 360
361 scifa0: serial@e6c40000 { 361 scifa0: serial@e6c40000 {
362 compatible = "renesas,scifa-sh 362 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
363 reg = <0xe6c40000 0x100>; 363 reg = <0xe6c40000 0x100>;
364 interrupts = <GIC_SPI 72 IRQ_T 364 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&mstp2_clks SH73A0_C 365 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
366 clock-names = "fck"; 366 clock-names = "fck";
367 power-domains = <&pd_a3sp>; 367 power-domains = <&pd_a3sp>;
368 status = "disabled"; 368 status = "disabled";
369 }; 369 };
370 370
371 scifa1: serial@e6c50000 { 371 scifa1: serial@e6c50000 {
372 compatible = "renesas,scifa-sh 372 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
373 reg = <0xe6c50000 0x100>; 373 reg = <0xe6c50000 0x100>;
374 interrupts = <GIC_SPI 73 IRQ_T 374 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp2_clks SH73A0_C 375 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
376 clock-names = "fck"; 376 clock-names = "fck";
377 power-domains = <&pd_a3sp>; 377 power-domains = <&pd_a3sp>;
378 status = "disabled"; 378 status = "disabled";
379 }; 379 };
380 380
381 scifa2: serial@e6c60000 { 381 scifa2: serial@e6c60000 {
382 compatible = "renesas,scifa-sh 382 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
383 reg = <0xe6c60000 0x100>; 383 reg = <0xe6c60000 0x100>;
384 interrupts = <GIC_SPI 74 IRQ_T 384 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp2_clks SH73A0_C 385 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
386 clock-names = "fck"; 386 clock-names = "fck";
387 power-domains = <&pd_a3sp>; 387 power-domains = <&pd_a3sp>;
388 status = "disabled"; 388 status = "disabled";
389 }; 389 };
390 390
391 scifa3: serial@e6c70000 { 391 scifa3: serial@e6c70000 {
392 compatible = "renesas,scifa-sh 392 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
393 reg = <0xe6c70000 0x100>; 393 reg = <0xe6c70000 0x100>;
394 interrupts = <GIC_SPI 75 IRQ_T 394 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp2_clks SH73A0_C 395 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
396 clock-names = "fck"; 396 clock-names = "fck";
397 power-domains = <&pd_a3sp>; 397 power-domains = <&pd_a3sp>;
398 status = "disabled"; 398 status = "disabled";
399 }; 399 };
400 400
401 scifa4: serial@e6c80000 { 401 scifa4: serial@e6c80000 {
402 compatible = "renesas,scifa-sh 402 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
403 reg = <0xe6c80000 0x100>; 403 reg = <0xe6c80000 0x100>;
404 interrupts = <GIC_SPI 78 IRQ_T 404 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp2_clks SH73A0_C 405 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
406 clock-names = "fck"; 406 clock-names = "fck";
407 power-domains = <&pd_a3sp>; 407 power-domains = <&pd_a3sp>;
408 status = "disabled"; 408 status = "disabled";
409 }; 409 };
410 410
411 scifa5: serial@e6cb0000 { 411 scifa5: serial@e6cb0000 {
412 compatible = "renesas,scifa-sh 412 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
413 reg = <0xe6cb0000 0x100>; 413 reg = <0xe6cb0000 0x100>;
414 interrupts = <GIC_SPI 79 IRQ_T 414 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp2_clks SH73A0_C 415 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
416 clock-names = "fck"; 416 clock-names = "fck";
417 power-domains = <&pd_a3sp>; 417 power-domains = <&pd_a3sp>;
418 status = "disabled"; 418 status = "disabled";
419 }; 419 };
420 420
421 scifa6: serial@e6cc0000 { 421 scifa6: serial@e6cc0000 {
422 compatible = "renesas,scifa-sh 422 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
423 reg = <0xe6cc0000 0x100>; 423 reg = <0xe6cc0000 0x100>;
424 interrupts = <GIC_SPI 156 IRQ_ 424 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp3_clks SH73A0_C 425 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
426 clock-names = "fck"; 426 clock-names = "fck";
427 power-domains = <&pd_a3sp>; 427 power-domains = <&pd_a3sp>;
428 status = "disabled"; 428 status = "disabled";
429 }; 429 };
430 430
431 scifa7: serial@e6cd0000 { 431 scifa7: serial@e6cd0000 {
432 compatible = "renesas,scifa-sh 432 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
433 reg = <0xe6cd0000 0x100>; 433 reg = <0xe6cd0000 0x100>;
434 interrupts = <GIC_SPI 143 IRQ_ 434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&mstp2_clks SH73A0_C 435 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
436 clock-names = "fck"; 436 clock-names = "fck";
437 power-domains = <&pd_a3sp>; 437 power-domains = <&pd_a3sp>;
438 status = "disabled"; 438 status = "disabled";
439 }; 439 };
440 440
441 scifb: serial@e6c30000 { 441 scifb: serial@e6c30000 {
442 compatible = "renesas,scifb-sh 442 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
443 reg = <0xe6c30000 0x100>; 443 reg = <0xe6c30000 0x100>;
444 interrupts = <GIC_SPI 80 IRQ_T 444 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&mstp2_clks SH73A0_C 445 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
446 clock-names = "fck"; 446 clock-names = "fck";
447 power-domains = <&pd_a3sp>; 447 power-domains = <&pd_a3sp>;
448 status = "disabled"; 448 status = "disabled";
449 }; 449 };
450 450
451 pfc: pinctrl@e6050000 { 451 pfc: pinctrl@e6050000 {
452 compatible = "renesas,pfc-sh73 452 compatible = "renesas,pfc-sh73a0";
453 reg = <0xe6050000 0x8000>, 453 reg = <0xe6050000 0x8000>,
454 <0xe605801c 0x1c>; 454 <0xe605801c 0x1c>;
455 gpio-controller; 455 gpio-controller;
456 #gpio-cells = <2>; 456 #gpio-cells = <2>;
457 gpio-ranges = 457 gpio-ranges =
458 <&pfc 0 0 119>, <&pfc 458 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
459 <&pfc 288 288 22>; 459 <&pfc 288 288 22>;
460 interrupts-extended = 460 interrupts-extended =
461 <&irqpin0 0 0>, <&irqp 461 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
462 <&irqpin0 4 0>, <&irqp 462 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
463 <&irqpin1 0 0>, <&irqp 463 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
464 <&irqpin1 4 0>, <&irqp 464 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
465 <&irqpin2 0 0>, <&irqp 465 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
466 <&irqpin2 4 0>, <&irqp 466 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
467 <&irqpin3 0 0>, <&irqp 467 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
468 <&irqpin3 4 0>, <&irqp 468 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
469 power-domains = <&pd_c5>; 469 power-domains = <&pd_c5>;
470 }; 470 };
471 471
472 sysc: system-controller@e6180000 { 472 sysc: system-controller@e6180000 {
473 compatible = "renesas,sysc-sh7 473 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
474 reg = <0xe6180000 0x8000>, <0x 474 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
475 475
476 pm-domains { 476 pm-domains {
477 pd_c5: c5 { 477 pd_c5: c5 {
478 #address-cells 478 #address-cells = <1>;
479 #size-cells = 479 #size-cells = <0>;
480 #power-domain- 480 #power-domain-cells = <0>;
481 481
482 pd_c4: c4@0 { 482 pd_c4: c4@0 {
483 reg = 483 reg = <0>;
484 #power 484 #power-domain-cells = <0>;
485 }; 485 };
486 486
487 pd_d4: d4@1 { 487 pd_d4: d4@1 {
488 reg = 488 reg = <1>;
489 #power 489 #power-domain-cells = <0>;
490 }; 490 };
491 491
492 pd_a4bc0: a4bc 492 pd_a4bc0: a4bc0@4 {
493 reg = 493 reg = <4>;
494 #power 494 #power-domain-cells = <0>;
495 }; 495 };
496 496
497 pd_a4bc1: a4bc 497 pd_a4bc1: a4bc1@5 {
498 reg = 498 reg = <5>;
499 #power 499 #power-domain-cells = <0>;
500 }; 500 };
501 501
502 pd_a4lc0: a4lc 502 pd_a4lc0: a4lc0@6 {
503 reg = 503 reg = <6>;
504 #power 504 #power-domain-cells = <0>;
505 }; 505 };
506 506
507 pd_a4lc1: a4lc 507 pd_a4lc1: a4lc1@7 {
508 reg = 508 reg = <7>;
509 #power 509 #power-domain-cells = <0>;
510 }; 510 };
511 511
512 pd_a4mp: a4mp@ 512 pd_a4mp: a4mp@8 {
513 reg = 513 reg = <8>;
514 #addre 514 #address-cells = <1>;
515 #size- 515 #size-cells = <0>;
516 #power 516 #power-domain-cells = <0>;
517 517
518 pd_a3m 518 pd_a3mp: a3mp@9 {
519 519 reg = <9>;
520 520 #power-domain-cells = <0>;
521 }; 521 };
522 522
523 pd_a3v 523 pd_a3vc: a3vc@10 {
524 524 reg = <10>;
525 525 #power-domain-cells = <0>;
526 }; 526 };
527 }; 527 };
528 528
529 pd_a4rm: a4rm@ 529 pd_a4rm: a4rm@12 {
530 reg = 530 reg = <12>;
531 #addre 531 #address-cells = <1>;
532 #size- 532 #size-cells = <0>;
533 #power 533 #power-domain-cells = <0>;
534 534
535 pd_a3r 535 pd_a3r: a3r@13 {
536 536 reg = <13>;
537 537 #address-cells = <1>;
538 538 #size-cells = <0>;
539 539 #power-domain-cells = <0>;
540 540
541 541 pd_a2rv: a2rv@14 {
542 542 reg = <14>;
543 543 #address-cells = <1>;
544 544 #size-cells = <0>;
545 545 #power-domain-cells = <0>;
546 546 };
547 }; 547 };
548 }; 548 };
549 549
550 pd_a4s: a4s@16 550 pd_a4s: a4s@16 {
551 reg = 551 reg = <16>;
552 #addre 552 #address-cells = <1>;
553 #size- 553 #size-cells = <0>;
554 #power 554 #power-domain-cells = <0>;
555 555
556 pd_a3s 556 pd_a3sp: a3sp@17 {
557 557 reg = <17>;
558 558 #power-domain-cells = <0>;
559 }; 559 };
560 560
561 pd_a3s 561 pd_a3sg: a3sg@18 {
562 562 reg = <18>;
563 563 #power-domain-cells = <0>;
564 }; 564 };
565 565
566 pd_a3s 566 pd_a3sm: a3sm@19 {
567 567 reg = <19>;
568 568 #address-cells = <1>;
569 569 #size-cells = <0>;
570 570 #power-domain-cells = <0>;
571 571
572 572 pd_a2sl: a2sl@20 {
573 573 reg = <20>;
574 574 #power-domain-cells = <0>;
575 575 };
576 }; 576 };
577 }; 577 };
578 }; 578 };
579 }; 579 };
580 }; 580 };
581 581
582 sh_fsi2: sound@ec230000 { 582 sh_fsi2: sound@ec230000 {
583 #sound-dai-cells = <1>; 583 #sound-dai-cells = <1>;
584 compatible = "renesas,fsi2-sh7 584 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
585 reg = <0xec230000 0x400>; 585 reg = <0xec230000 0x400>;
586 interrupts = <GIC_SPI 146 0x4> 586 interrupts = <GIC_SPI 146 0x4>;
587 clocks = <&mstp3_clks SH73A0_C 587 clocks = <&mstp3_clks SH73A0_CLK_FSI>;
588 power-domains = <&pd_a4mp>; 588 power-domains = <&pd_a4mp>;
589 status = "disabled"; 589 status = "disabled";
590 }; 590 };
591 591
592 bsc: bus@fec10000 { 592 bsc: bus@fec10000 {
593 compatible = "renesas,bsc-sh73 593 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
594 "simple-pm-bus"; 594 "simple-pm-bus";
595 #address-cells = <1>; 595 #address-cells = <1>;
596 #size-cells = <1>; 596 #size-cells = <1>;
597 ranges = <0 0 0x20000000>; 597 ranges = <0 0 0x20000000>;
598 reg = <0xfec10000 0x400>; 598 reg = <0xfec10000 0x400>;
599 interrupts = <GIC_SPI 39 IRQ_T 599 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&zb_clk>; 600 clocks = <&zb_clk>;
601 power-domains = <&pd_a4s>; 601 power-domains = <&pd_a4s>;
602 }; 602 };
603 603
604 clocks { 604 clocks {
605 #address-cells = <1>; 605 #address-cells = <1>;
606 #size-cells = <1>; 606 #size-cells = <1>;
607 ranges; 607 ranges;
608 608
609 /* External root clocks */ 609 /* External root clocks */
610 extalr_clk: extalr { 610 extalr_clk: extalr {
611 compatible = "fixed-cl 611 compatible = "fixed-clock";
612 #clock-cells = <0>; 612 #clock-cells = <0>;
613 clock-frequency = <327 613 clock-frequency = <32768>;
614 }; 614 };
615 extal1_clk: extal1 { 615 extal1_clk: extal1 {
616 compatible = "fixed-cl 616 compatible = "fixed-clock";
617 #clock-cells = <0>; 617 #clock-cells = <0>;
618 clock-frequency = <260 618 clock-frequency = <26000000>;
619 }; 619 };
620 extal2_clk: extal2 { 620 extal2_clk: extal2 {
621 compatible = "fixed-cl 621 compatible = "fixed-clock";
622 #clock-cells = <0>; 622 #clock-cells = <0>;
623 /* This value must be 623 /* This value must be overridden by the board. */
624 clock-frequency = <0>; 624 clock-frequency = <0>;
625 }; 625 };
626 extcki_clk: extcki { 626 extcki_clk: extcki {
627 compatible = "fixed-cl 627 compatible = "fixed-clock";
628 #clock-cells = <0>; 628 #clock-cells = <0>;
629 /* This value can be o 629 /* This value can be overridden by the board. */
630 clock-frequency = <0>; 630 clock-frequency = <0>;
631 }; 631 };
632 fsiack_clk: fsiack { 632 fsiack_clk: fsiack {
633 compatible = "fixed-cl 633 compatible = "fixed-clock";
634 #clock-cells = <0>; 634 #clock-cells = <0>;
635 /* This value can be o 635 /* This value can be overridden by the board. */
636 clock-frequency = <0>; 636 clock-frequency = <0>;
637 }; 637 };
638 fsibck_clk: fsibck { 638 fsibck_clk: fsibck {
639 compatible = "fixed-cl 639 compatible = "fixed-clock";
640 #clock-cells = <0>; 640 #clock-cells = <0>;
641 /* This value can be o 641 /* This value can be overridden by the board. */
642 clock-frequency = <0>; 642 clock-frequency = <0>;
643 }; 643 };
644 644
645 /* Special CPG clocks */ 645 /* Special CPG clocks */
646 cpg_clocks: cpg_clocks@e615000 646 cpg_clocks: cpg_clocks@e6150000 {
647 compatible = "renesas, 647 compatible = "renesas,sh73a0-cpg-clocks";
648 reg = <0xe6150000 0x10 648 reg = <0xe6150000 0x10000>;
649 clocks = <&extal1_clk> 649 clocks = <&extal1_clk>, <&extal2_clk>;
650 #clock-cells = <1>; 650 #clock-cells = <1>;
651 clock-output-names = " 651 clock-output-names = "main", "pll0", "pll1", "pll2",
652 " 652 "pll3", "dsi0phy", "dsi1phy",
653 " 653 "zg", "m3", "b", "m1", "m2",
654 " 654 "z", "zx", "hp";
655 }; 655 };
656 656
657 /* Variable factor clocks (DIV 657 /* Variable factor clocks (DIV6) */
658 vclk1_clk: vclk1@e6150008 { 658 vclk1_clk: vclk1@e6150008 {
659 compatible = "renesas, 659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
660 reg = <0xe6150008 4>; 660 reg = <0xe6150008 4>;
661 clocks = <&pll1_div2_c 661 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
662 <&extcki_clk> 662 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
663 <&extalr_clk> 663 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
664 <0>; 664 <0>;
665 #clock-cells = <0>; 665 #clock-cells = <0>;
666 }; 666 };
667 vclk2_clk: vclk2@e615000c { 667 vclk2_clk: vclk2@e615000c {
668 compatible = "renesas, 668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
669 reg = <0xe615000c 4>; 669 reg = <0xe615000c 4>;
670 clocks = <&pll1_div2_c 670 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
671 <&extcki_clk> 671 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
672 <&extalr_clk> 672 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
673 <0>; 673 <0>;
674 #clock-cells = <0>; 674 #clock-cells = <0>;
675 }; 675 };
676 vclk3_clk: vclk3@e615001c { 676 vclk3_clk: vclk3@e615001c {
677 compatible = "renesas, 677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
678 reg = <0xe615001c 4>; 678 reg = <0xe615001c 4>;
679 clocks = <&pll1_div2_c 679 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
680 <&extcki_clk> 680 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
681 <&extalr_clk> 681 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
682 <0>; 682 <0>;
683 #clock-cells = <0>; 683 #clock-cells = <0>;
684 }; 684 };
685 zb_clk: zb_clk@e6150010 { 685 zb_clk: zb_clk@e6150010 {
686 compatible = "renesas, 686 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
687 reg = <0xe6150010 4>; 687 reg = <0xe6150010 4>;
688 clocks = <&pll1_div2_c 688 clocks = <&pll1_div2_clk>, <0>,
689 <&cpg_clocks 689 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
690 #clock-cells = <0>; 690 #clock-cells = <0>;
691 clock-output-names = " 691 clock-output-names = "zb";
692 }; 692 };
693 flctl_clk: flctlck@e6150014 { 693 flctl_clk: flctlck@e6150014 {
694 compatible = "renesas, 694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
695 reg = <0xe6150014 4>; 695 reg = <0xe6150014 4>;
696 clocks = <&pll1_div2_c 696 clocks = <&pll1_div2_clk>, <0>,
697 <&cpg_clocks 697 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
698 #clock-cells = <0>; 698 #clock-cells = <0>;
699 }; 699 };
700 sdhi0_clk: sdhi0ck@e6150074 { 700 sdhi0_clk: sdhi0ck@e6150074 {
701 compatible = "renesas, 701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 reg = <0xe6150074 4>; 702 reg = <0xe6150074 4>;
703 clocks = <&pll1_div2_c 703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
704 <&pll1_div13_ 704 <&pll1_div13_clk>, <0>;
705 #clock-cells = <0>; 705 #clock-cells = <0>;
706 }; 706 };
707 sdhi1_clk: sdhi1ck@e6150078 { 707 sdhi1_clk: sdhi1ck@e6150078 {
708 compatible = "renesas, 708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
709 reg = <0xe6150078 4>; 709 reg = <0xe6150078 4>;
710 clocks = <&pll1_div2_c 710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
711 <&pll1_div13_ 711 <&pll1_div13_clk>, <0>;
712 #clock-cells = <0>; 712 #clock-cells = <0>;
713 }; 713 };
714 sdhi2_clk: sdhi2ck@e615007c { 714 sdhi2_clk: sdhi2ck@e615007c {
715 compatible = "renesas, 715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
716 reg = <0xe615007c 4>; 716 reg = <0xe615007c 4>;
717 clocks = <&pll1_div2_c 717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
718 <&pll1_div13_ 718 <&pll1_div13_clk>, <0>;
719 #clock-cells = <0>; 719 #clock-cells = <0>;
720 }; 720 };
721 fsia_clk: fsia@e6150018 { 721 fsia_clk: fsia@e6150018 {
722 compatible = "renesas, 722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 reg = <0xe6150018 4>; 723 reg = <0xe6150018 4>;
724 clocks = <&pll1_div2_c 724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
725 <&fsiack_clk> 725 <&fsiack_clk>, <&fsiack_clk>;
726 #clock-cells = <0>; 726 #clock-cells = <0>;
727 }; 727 };
728 fsib_clk: fsib@e6150090 { 728 fsib_clk: fsib@e6150090 {
729 compatible = "renesas, 729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
730 reg = <0xe6150090 4>; 730 reg = <0xe6150090 4>;
731 clocks = <&pll1_div2_c 731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
732 <&fsibck_clk> 732 <&fsibck_clk>, <&fsibck_clk>;
733 #clock-cells = <0>; 733 #clock-cells = <0>;
734 }; 734 };
735 sub_clk: sub@e6150080 { 735 sub_clk: sub@e6150080 {
736 compatible = "renesas, 736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
737 reg = <0xe6150080 4>; 737 reg = <0xe6150080 4>;
738 clocks = <&pll1_div2_c 738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
739 <&extal2_clk> 739 <&extal2_clk>, <&extal2_clk>;
740 #clock-cells = <0>; 740 #clock-cells = <0>;
741 }; 741 };
742 spua_clk: spua@e6150084 { 742 spua_clk: spua@e6150084 {
743 compatible = "renesas, 743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
744 reg = <0xe6150084 4>; 744 reg = <0xe6150084 4>;
745 clocks = <&pll1_div2_c 745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
746 <&extal2_clk> 746 <&extal2_clk>, <&extal2_clk>;
747 #clock-cells = <0>; 747 #clock-cells = <0>;
748 }; 748 };
749 spuv_clk: spuv@e6150094 { 749 spuv_clk: spuv@e6150094 {
750 compatible = "renesas, 750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 reg = <0xe6150094 4>; 751 reg = <0xe6150094 4>;
752 clocks = <&pll1_div2_c 752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
753 <&extal2_clk> 753 <&extal2_clk>, <&extal2_clk>;
754 #clock-cells = <0>; 754 #clock-cells = <0>;
755 }; 755 };
756 msu_clk: msu@e6150088 { 756 msu_clk: msu@e6150088 {
757 compatible = "renesas, 757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
758 reg = <0xe6150088 4>; 758 reg = <0xe6150088 4>;
759 clocks = <&pll1_div2_c 759 clocks = <&pll1_div2_clk>, <0>,
760 <&cpg_clocks 760 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
761 #clock-cells = <0>; 761 #clock-cells = <0>;
762 }; 762 };
763 hsi_clk: hsi@e615008c { 763 hsi_clk: hsi@e615008c {
764 compatible = "renesas, 764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
765 reg = <0xe615008c 4>; 765 reg = <0xe615008c 4>;
766 clocks = <&pll1_div2_c 766 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
767 <&pll1_div7_c 767 <&pll1_div7_clk>, <0>;
768 #clock-cells = <0>; 768 #clock-cells = <0>;
769 }; 769 };
770 mfg1_clk: mfg1@e6150098 { 770 mfg1_clk: mfg1@e6150098 {
771 compatible = "renesas, 771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
772 reg = <0xe6150098 4>; 772 reg = <0xe6150098 4>;
773 clocks = <&pll1_div2_c 773 clocks = <&pll1_div2_clk>, <0>,
774 <&cpg_clocks 774 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
775 #clock-cells = <0>; 775 #clock-cells = <0>;
776 }; 776 };
777 mfg2_clk: mfg2@e615009c { 777 mfg2_clk: mfg2@e615009c {
778 compatible = "renesas, 778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
779 reg = <0xe615009c 4>; 779 reg = <0xe615009c 4>;
780 clocks = <&pll1_div2_c 780 clocks = <&pll1_div2_clk>, <0>,
781 <&cpg_clocks 781 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
782 #clock-cells = <0>; 782 #clock-cells = <0>;
783 }; 783 };
784 dsit_clk: dsit@e6150060 { 784 dsit_clk: dsit@e6150060 {
785 compatible = "renesas, 785 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
786 reg = <0xe6150060 4>; 786 reg = <0xe6150060 4>;
787 clocks = <&pll1_div2_c 787 clocks = <&pll1_div2_clk>, <0>,
788 <&cpg_clocks 788 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
789 #clock-cells = <0>; 789 #clock-cells = <0>;
790 }; 790 };
791 dsi0p_clk: dsi0pck@e6150064 { 791 dsi0p_clk: dsi0pck@e6150064 {
792 compatible = "renesas, 792 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
793 reg = <0xe6150064 4>; 793 reg = <0xe6150064 4>;
794 clocks = <&pll1_div2_c 794 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
795 <&cpg_clocks 795 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
796 <&extcki_clk> 796 <&extcki_clk>, <0>, <0>, <0>;
797 #clock-cells = <0>; 797 #clock-cells = <0>;
798 }; 798 };
799 799
800 /* Fixed factor clocks */ 800 /* Fixed factor clocks */
801 main_div2_clk: main_div2 { 801 main_div2_clk: main_div2 {
802 compatible = "fixed-fa 802 compatible = "fixed-factor-clock";
803 clocks = <&cpg_clocks 803 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
804 #clock-cells = <0>; 804 #clock-cells = <0>;
805 clock-div = <2>; 805 clock-div = <2>;
806 clock-mult = <1>; 806 clock-mult = <1>;
807 }; 807 };
808 pll1_div2_clk: pll1_div2 { 808 pll1_div2_clk: pll1_div2 {
809 compatible = "fixed-fa 809 compatible = "fixed-factor-clock";
810 clocks = <&cpg_clocks 810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
811 #clock-cells = <0>; 811 #clock-cells = <0>;
812 clock-div = <2>; 812 clock-div = <2>;
813 clock-mult = <1>; 813 clock-mult = <1>;
814 }; 814 };
815 pll1_div7_clk: pll1_div7 { 815 pll1_div7_clk: pll1_div7 {
816 compatible = "fixed-fa 816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks 817 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
818 #clock-cells = <0>; 818 #clock-cells = <0>;
819 clock-div = <7>; 819 clock-div = <7>;
820 clock-mult = <1>; 820 clock-mult = <1>;
821 }; 821 };
822 pll1_div13_clk: pll1_div13 { 822 pll1_div13_clk: pll1_div13 {
823 compatible = "fixed-fa 823 compatible = "fixed-factor-clock";
824 clocks = <&cpg_clocks 824 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
825 #clock-cells = <0>; 825 #clock-cells = <0>;
826 clock-div = <13>; 826 clock-div = <13>;
827 clock-mult = <1>; 827 clock-mult = <1>;
828 }; 828 };
829 periph_clk: periph { 829 periph_clk: periph {
830 compatible = "fixed-fa 830 compatible = "fixed-factor-clock";
831 clocks = <&cpg_clocks 831 clocks = <&cpg_clocks SH73A0_CLK_Z>;
832 #clock-cells = <0>; 832 #clock-cells = <0>;
833 clock-div = <4>; 833 clock-div = <4>;
834 clock-mult = <1>; 834 clock-mult = <1>;
835 }; 835 };
836 836
837 /* Gate clocks */ 837 /* Gate clocks */
838 mstp0_clks: mstp0_clks@e615013 838 mstp0_clks: mstp0_clks@e6150130 {
839 compatible = "renesas, 839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
840 reg = <0xe6150130 4>, 840 reg = <0xe6150130 4>, <0xe6150030 4>;
841 clocks = <&cpg_clocks 841 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
842 #clock-cells = <1>; 842 #clock-cells = <1>;
843 clock-indices = < 843 clock-indices = <
844 SH73A0_CLK_IIC 844 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
845 >; 845 >;
846 clock-output-names = 846 clock-output-names =
847 "iic2", "msiof 847 "iic2", "msiof0";
848 }; 848 };
849 mstp1_clks: mstp1_clks@e615013 849 mstp1_clks: mstp1_clks@e6150134 {
850 compatible = "renesas, 850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
851 reg = <0xe6150134 4>, 851 reg = <0xe6150134 4>, <0xe6150038 4>;
852 clocks = <&cpg_clocks 852 clocks = <&cpg_clocks SH73A0_CLK_B>,
853 <&cpg_clocks 853 <&cpg_clocks SH73A0_CLK_B>,
854 <&cpg_clocks 854 <&cpg_clocks SH73A0_CLK_B>,
855 <&cpg_clocks 855 <&cpg_clocks SH73A0_CLK_B>,
856 <&sub_clk>, < 856 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
857 <&cpg_clocks 857 <&cpg_clocks SH73A0_CLK_HP>,
858 <&cpg_clocks 858 <&cpg_clocks SH73A0_CLK_ZG>,
859 <&cpg_clocks 859 <&cpg_clocks SH73A0_CLK_B>;
860 #clock-cells = <1>; 860 #clock-cells = <1>;
861 clock-indices = < 861 clock-indices = <
862 SH73A0_CLK_CEU 862 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
863 SH73A0_CLK_CEU 863 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
864 SH73A0_CLK_TMU 864 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
865 SH73A0_CLK_IIC 865 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
866 SH73A0_CLK_LCD 866 SH73A0_CLK_LCDC0
867 >; 867 >;
868 clock-output-names = 868 clock-output-names =
869 "ceu1", "csi2_ 869 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
870 "tmu0", "dsitx 870 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
871 }; 871 };
872 mstp2_clks: mstp2_clks@e615013 872 mstp2_clks: mstp2_clks@e6150138 {
873 compatible = "renesas, 873 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
874 reg = <0xe6150138 4>, 874 reg = <0xe6150138 4>, <0xe6150040 4>;
875 clocks = <&sub_clk>, < 875 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
876 <&cpg_clocks 876 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
877 <&sub_clk>, < 877 <&sub_clk>, <&sub_clk>, <&sub_clk>,
878 <&sub_clk>, < 878 <&sub_clk>, <&sub_clk>, <&sub_clk>,
879 <&sub_clk>, < 879 <&sub_clk>, <&sub_clk>, <&sub_clk>;
880 #clock-cells = <1>; 880 #clock-cells = <1>;
881 clock-indices = < 881 clock-indices = <
882 SH73A0_CLK_SCI 882 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
883 SH73A0_CLK_MP_ 883 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
884 SH73A0_CLK_MSI 884 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
885 SH73A0_CLK_SCI 885 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
886 SH73A0_CLK_SCI 886 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
887 SH73A0_CLK_SCI 887 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
888 SH73A0_CLK_SCI 888 SH73A0_CLK_SCIFA4
889 >; 889 >;
890 clock-output-names = 890 clock-output-names =
891 "scifa7", "sy_ 891 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
892 "msiof1", "sci 892 "msiof1", "scifa5", "scifb", "msiof2",
893 "scifa0", "sci 893 "scifa0", "scifa1", "scifa2", "scifa3",
894 "scifa4"; 894 "scifa4";
895 }; 895 };
896 mstp3_clks: mstp3_clks@e615013 896 mstp3_clks: mstp3_clks@e615013c {
897 compatible = "renesas, 897 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
898 reg = <0xe615013c 4>, 898 reg = <0xe615013c 4>, <0xe6150048 4>;
899 clocks = <&sub_clk>, < 899 clocks = <&sub_clk>, <&extalr_clk>,
900 <&cpg_clocks 900 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
901 <&cpg_clocks 901 <&cpg_clocks SH73A0_CLK_HP>,
902 <&cpg_clocks 902 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
903 <&sdhi0_clk>, 903 <&sdhi0_clk>, <&sdhi1_clk>,
904 <&cpg_clocks 904 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
905 <&main_div2_c 905 <&main_div2_clk>, <&main_div2_clk>,
906 <&main_div2_c 906 <&main_div2_clk>, <&main_div2_clk>,
907 <&main_div2_c 907 <&main_div2_clk>;
908 #clock-cells = <1>; 908 #clock-cells = <1>;
909 clock-indices = < 909 clock-indices = <
910 SH73A0_CLK_SCI 910 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
911 SH73A0_CLK_FSI 911 SH73A0_CLK_FSI SH73A0_CLK_IRDA
912 SH73A0_CLK_IIC 912 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
913 SH73A0_CLK_SDH 913 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
914 SH73A0_CLK_MMC 914 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
915 SH73A0_CLK_TPU 915 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
916 SH73A0_CLK_TPU 916 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
917 SH73A0_CLK_TPU 917 SH73A0_CLK_TPU4
918 >; 918 >;
919 clock-output-names = 919 clock-output-names =
920 "scifa6", "cmt 920 "scifa6", "cmt1", "fsi", "irda", "iic1",
921 "usb", "flctl" 921 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
922 "tpu0", "tpu1" 922 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
923 }; 923 };
924 mstp4_clks: mstp4_clks@e615014 924 mstp4_clks: mstp4_clks@e6150140 {
925 compatible = "renesas, 925 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
926 reg = <0xe6150140 4>, 926 reg = <0xe6150140 4>, <0xe615004c 4>;
927 clocks = <&cpg_clocks 927 clocks = <&cpg_clocks SH73A0_CLK_HP>,
928 <&cpg_clocks 928 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
929 #clock-cells = <1>; 929 #clock-cells = <1>;
930 clock-indices = < 930 clock-indices = <
931 SH73A0_CLK_IIC 931 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
932 SH73A0_CLK_KEY 932 SH73A0_CLK_KEYSC
933 >; 933 >;
934 clock-output-names = 934 clock-output-names =
935 "iic3", "iic4" 935 "iic3", "iic4", "keysc";
936 }; 936 };
937 mstp5_clks: mstp5_clks@e615014 937 mstp5_clks: mstp5_clks@e6150144 {
938 compatible = "renesas, 938 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
939 reg = <0xe6150144 4>, 939 reg = <0xe6150144 4>, <0xe615003c 4>;
940 clocks = <&cpg_clocks 940 clocks = <&cpg_clocks SH73A0_CLK_HP>;
941 #clock-cells = <1>; 941 #clock-cells = <1>;
942 clock-indices = < 942 clock-indices = <
943 SH73A0_CLK_INT 943 SH73A0_CLK_INTCA0
944 >; 944 >;
945 clock-output-names = 945 clock-output-names =
946 "intca0"; 946 "intca0";
947 }; 947 };
948 }; 948 };
949 }; 949 };
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