1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the SH-Mobile AG5 (R
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/interrupt-controller/irq
11
12 / {
13 compatible = "renesas,sh73a0";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cort
25 reg = <0>;
26 clock-frequency = <119
27 clocks = <&cpg_clocks
28 power-domains = <&pd_a
29 next-level-cache = <&L
30 };
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cort
34 reg = <1>;
35 clock-frequency = <119
36 clocks = <&cpg_clocks
37 power-domains = <&pd_a
38 next-level-cache = <&L
39 };
40 };
41
42 timer@f0000200 {
43 compatible = "arm,cortex-a9-gl
44 reg = <0xf0000200 0x100>;
45 interrupts = <GIC_PPI 11 (GIC_
46 clocks = <&periph_clk>;
47 };
48
49 timer@f0000600 {
50 compatible = "arm,cortex-a9-tw
51 reg = <0xf0000600 0x20>;
52 interrupts = <GIC_PPI 13 (GIC_
53 clocks = <&periph_clk>;
54 };
55
56 gic: interrupt-controller@f0001000 {
57 compatible = "arm,cortex-a9-gi
58 #interrupt-cells = <3>;
59 interrupt-controller;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
62 };
63
64 L2: cache-controller@f0100000 {
65 compatible = "arm,pl310-cache"
66 reg = <0xf0100000 0x1000>;
67 interrupts = <GIC_SPI 44 IRQ_T
68 power-domains = <&pd_a3sm>;
69 arm,data-latency = <3 3 3>;
70 arm,tag-latency = <2 2 2>;
71 arm,shared-override;
72 cache-unified;
73 cache-level = <2>;
74 };
75
76 sbsc2: memory-controller@fb400000 {
77 compatible = "renesas,sbsc-sh7
78 reg = <0xfb400000 0x400>;
79 interrupts = <GIC_SPI 37 IRQ_T
80 <GIC_SPI 38 IRQ_T
81 interrupt-names = "sec", "temp
82 power-domains = <&pd_a4bc1>;
83 };
84
85 sbsc1: memory-controller@fe400000 {
86 compatible = "renesas,sbsc-sh7
87 reg = <0xfe400000 0x400>;
88 interrupts = <GIC_SPI 35 IRQ_T
89 <GIC_SPI 36 IRQ_T
90 interrupt-names = "sec", "temp
91 power-domains = <&pd_a4bc0>;
92 };
93
94 pmu {
95 compatible = "arm,cortex-a9-pm
96 interrupts = <GIC_SPI 55 IRQ_T
97 <GIC_SPI 56 IRQ_T
98 interrupt-affinity = <&cpu0>,
99 };
100
101 cmt1: timer@e6138000 {
102 compatible = "renesas,sh73a0-c
103 reg = <0xe6138000 0x200>;
104 interrupts = <GIC_SPI 65 IRQ_T
105 clocks = <&mstp3_clks SH73A0_C
106 clock-names = "fck";
107 power-domains = <&pd_c5>;
108 status = "disabled";
109 };
110
111 irqpin0: interrupt-controller@e6900000
112 compatible = "renesas,intc-irq
113 #interrupt-cells = <2>;
114 interrupt-controller;
115 reg = <0xe6900000 4>,
116 <0xe6900010 4>,
117 <0xe6900020 1>,
118 <0xe6900040 1>,
119 <0xe6900060 1>;
120 interrupts = <GIC_SPI 1 IRQ_TY
121 <GIC_SPI 2 IRQ_TY
122 <GIC_SPI 3 IRQ_TY
123 <GIC_SPI 4 IRQ_TY
124 <GIC_SPI 5 IRQ_TY
125 <GIC_SPI 6 IRQ_TY
126 <GIC_SPI 7 IRQ_TY
127 <GIC_SPI 8 IRQ_TY
128 clocks = <&mstp5_clks SH73A0_C
129 power-domains = <&pd_a4s>;
130 control-parent;
131 };
132
133 irqpin1: interrupt-controller@e6900004
134 compatible = "renesas,intc-irq
135 #interrupt-cells = <2>;
136 interrupt-controller;
137 reg = <0xe6900004 4>,
138 <0xe6900014 4>,
139 <0xe6900024 1>,
140 <0xe6900044 1>,
141 <0xe6900064 1>;
142 interrupts = <GIC_SPI 9 IRQ_T
143 <GIC_SPI 10 IRQ_T
144 <GIC_SPI 11 IRQ_T
145 <GIC_SPI 12 IRQ_T
146 <GIC_SPI 13 IRQ_T
147 <GIC_SPI 14 IRQ_T
148 <GIC_SPI 15 IRQ_T
149 <GIC_SPI 16 IRQ_T
150 clocks = <&mstp5_clks SH73A0_C
151 power-domains = <&pd_a4s>;
152 control-parent;
153 };
154
155 irqpin2: interrupt-controller@e6900008
156 compatible = "renesas,intc-irq
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 reg = <0xe6900008 4>,
160 <0xe6900018 4>,
161 <0xe6900028 1>,
162 <0xe6900048 1>,
163 <0xe6900068 1>;
164 interrupts = <GIC_SPI 17 IRQ_T
165 <GIC_SPI 18 IRQ_T
166 <GIC_SPI 19 IRQ_T
167 <GIC_SPI 20 IRQ_T
168 <GIC_SPI 21 IRQ_T
169 <GIC_SPI 22 IRQ_T
170 <GIC_SPI 23 IRQ_T
171 <GIC_SPI 24 IRQ_T
172 clocks = <&mstp5_clks SH73A0_C
173 power-domains = <&pd_a4s>;
174 control-parent;
175 };
176
177 irqpin3: interrupt-controller@e690000c
178 compatible = "renesas,intc-irq
179 #interrupt-cells = <2>;
180 interrupt-controller;
181 reg = <0xe690000c 4>,
182 <0xe690001c 4>,
183 <0xe690002c 1>,
184 <0xe690004c 1>,
185 <0xe690006c 1>;
186 interrupts = <GIC_SPI 25 IRQ_T
187 <GIC_SPI 26 IRQ_T
188 <GIC_SPI 27 IRQ_T
189 <GIC_SPI 28 IRQ_T
190 <GIC_SPI 29 IRQ_T
191 <GIC_SPI 30 IRQ_T
192 <GIC_SPI 31 IRQ_T
193 <GIC_SPI 32 IRQ_T
194 clocks = <&mstp5_clks SH73A0_C
195 power-domains = <&pd_a4s>;
196 control-parent;
197 };
198
199 i2c0: i2c@e6820000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,iic-sh73
203 reg = <0xe6820000 0x425>;
204 interrupts = <GIC_SPI 167 IRQ_
205 <GIC_SPI 168 IRQ_
206 <GIC_SPI 169 IRQ_
207 <GIC_SPI 170 IRQ_
208 clocks = <&mstp1_clks SH73A0_C
209 power-domains = <&pd_a3sp>;
210 status = "disabled";
211 };
212
213 i2c1: i2c@e6822000 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "renesas,iic-sh73
217 reg = <0xe6822000 0x425>;
218 interrupts = <GIC_SPI 51 IRQ_T
219 <GIC_SPI 52 IRQ_T
220 <GIC_SPI 53 IRQ_T
221 <GIC_SPI 54 IRQ_T
222 clocks = <&mstp3_clks SH73A0_C
223 power-domains = <&pd_a3sp>;
224 status = "disabled";
225 };
226
227 i2c2: i2c@e6824000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "renesas,iic-sh73
231 reg = <0xe6824000 0x425>;
232 interrupts = <GIC_SPI 171 IRQ_
233 <GIC_SPI 172 IRQ_
234 <GIC_SPI 173 IRQ_
235 <GIC_SPI 174 IRQ_
236 clocks = <&mstp0_clks SH73A0_C
237 power-domains = <&pd_a3sp>;
238 status = "disabled";
239 };
240
241 i2c3: i2c@e6826000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "renesas,iic-sh73
245 reg = <0xe6826000 0x425>;
246 interrupts = <GIC_SPI 183 IRQ_
247 <GIC_SPI 184 IRQ_
248 <GIC_SPI 185 IRQ_
249 <GIC_SPI 186 IRQ_
250 clocks = <&mstp4_clks SH73A0_C
251 power-domains = <&pd_a3sp>;
252 status = "disabled";
253 };
254
255 i2c4: i2c@e6828000 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "renesas,iic-sh73
259 reg = <0xe6828000 0x425>;
260 interrupts = <GIC_SPI 187 IRQ_
261 <GIC_SPI 188 IRQ_
262 <GIC_SPI 189 IRQ_
263 <GIC_SPI 190 IRQ_
264 clocks = <&mstp4_clks SH73A0_C
265 power-domains = <&pd_c5>;
266 status = "disabled";
267 };
268
269 mmcif: mmc@e6bd0000 {
270 compatible = "renesas,mmcif-sh
271 reg = <0xe6bd0000 0x100>;
272 interrupts = <GIC_SPI 140 IRQ_
273 <GIC_SPI 141 IRQ_
274 clocks = <&mstp3_clks SH73A0_C
275 power-domains = <&pd_a3sp>;
276 reg-io-width = <4>;
277 status = "disabled";
278 };
279
280 msiof0: spi@e6e20000 {
281 compatible = "renesas,msiof-sh
282 reg = <0xe6e20000 0x0064>;
283 interrupts = <GIC_SPI 142 IRQ_
284 clocks = <&mstp0_clks SH73A0_C
285 power-domains = <&pd_a3sp>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
290
291 msiof1: spi@e6e10000 {
292 compatible = "renesas,msiof-sh
293 reg = <0xe6e10000 0x0064>;
294 interrupts = <GIC_SPI 77 IRQ_T
295 clocks = <&mstp2_clks SH73A0_C
296 power-domains = <&pd_a3sp>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301
302 msiof2: spi@e6e00000 {
303 compatible = "renesas,msiof-sh
304 reg = <0xe6e00000 0x0064>;
305 interrupts = <GIC_SPI 76 IRQ_T
306 clocks = <&mstp2_clks SH73A0_C
307 power-domains = <&pd_a3sp>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 status = "disabled";
311 };
312
313 msiof3: spi@e6c90000 {
314 compatible = "renesas,msiof-sh
315 reg = <0xe6c90000 0x0064>;
316 interrupts = <GIC_SPI 59 IRQ_T
317 clocks = <&mstp2_clks SH73A0_C
318 power-domains = <&pd_a3sp>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 status = "disabled";
322 };
323
324 sdhi0: mmc@ee100000 {
325 compatible = "renesas,sdhi-sh7
326 reg = <0xee100000 0x100>;
327 interrupts = <GIC_SPI 83 IRQ_T
328 <GIC_SPI 84 IRQ_T
329 <GIC_SPI 85 IRQ_T
330 clocks = <&mstp3_clks SH73A0_C
331 power-domains = <&pd_a3sp>;
332 cap-sd-highspeed;
333 status = "disabled";
334 };
335
336 /* SDHI1 and SDHI2 have no CD pins, no
337 sdhi1: mmc@ee120000 {
338 compatible = "renesas,sdhi-sh7
339 reg = <0xee120000 0x100>;
340 interrupts = <GIC_SPI 88 IRQ_T
341 <GIC_SPI 89 IRQ_T
342 clocks = <&mstp3_clks SH73A0_C
343 power-domains = <&pd_a3sp>;
344 disable-wp;
345 cap-sd-highspeed;
346 status = "disabled";
347 };
348
349 sdhi2: mmc@ee140000 {
350 compatible = "renesas,sdhi-sh7
351 reg = <0xee140000 0x100>;
352 interrupts = <GIC_SPI 104 IRQ_
353 <GIC_SPI 105 IRQ_
354 clocks = <&mstp3_clks SH73A0_C
355 power-domains = <&pd_a3sp>;
356 disable-wp;
357 cap-sd-highspeed;
358 status = "disabled";
359 };
360
361 scifa0: serial@e6c40000 {
362 compatible = "renesas,scifa-sh
363 reg = <0xe6c40000 0x100>;
364 interrupts = <GIC_SPI 72 IRQ_T
365 clocks = <&mstp2_clks SH73A0_C
366 clock-names = "fck";
367 power-domains = <&pd_a3sp>;
368 status = "disabled";
369 };
370
371 scifa1: serial@e6c50000 {
372 compatible = "renesas,scifa-sh
373 reg = <0xe6c50000 0x100>;
374 interrupts = <GIC_SPI 73 IRQ_T
375 clocks = <&mstp2_clks SH73A0_C
376 clock-names = "fck";
377 power-domains = <&pd_a3sp>;
378 status = "disabled";
379 };
380
381 scifa2: serial@e6c60000 {
382 compatible = "renesas,scifa-sh
383 reg = <0xe6c60000 0x100>;
384 interrupts = <GIC_SPI 74 IRQ_T
385 clocks = <&mstp2_clks SH73A0_C
386 clock-names = "fck";
387 power-domains = <&pd_a3sp>;
388 status = "disabled";
389 };
390
391 scifa3: serial@e6c70000 {
392 compatible = "renesas,scifa-sh
393 reg = <0xe6c70000 0x100>;
394 interrupts = <GIC_SPI 75 IRQ_T
395 clocks = <&mstp2_clks SH73A0_C
396 clock-names = "fck";
397 power-domains = <&pd_a3sp>;
398 status = "disabled";
399 };
400
401 scifa4: serial@e6c80000 {
402 compatible = "renesas,scifa-sh
403 reg = <0xe6c80000 0x100>;
404 interrupts = <GIC_SPI 78 IRQ_T
405 clocks = <&mstp2_clks SH73A0_C
406 clock-names = "fck";
407 power-domains = <&pd_a3sp>;
408 status = "disabled";
409 };
410
411 scifa5: serial@e6cb0000 {
412 compatible = "renesas,scifa-sh
413 reg = <0xe6cb0000 0x100>;
414 interrupts = <GIC_SPI 79 IRQ_T
415 clocks = <&mstp2_clks SH73A0_C
416 clock-names = "fck";
417 power-domains = <&pd_a3sp>;
418 status = "disabled";
419 };
420
421 scifa6: serial@e6cc0000 {
422 compatible = "renesas,scifa-sh
423 reg = <0xe6cc0000 0x100>;
424 interrupts = <GIC_SPI 156 IRQ_
425 clocks = <&mstp3_clks SH73A0_C
426 clock-names = "fck";
427 power-domains = <&pd_a3sp>;
428 status = "disabled";
429 };
430
431 scifa7: serial@e6cd0000 {
432 compatible = "renesas,scifa-sh
433 reg = <0xe6cd0000 0x100>;
434 interrupts = <GIC_SPI 143 IRQ_
435 clocks = <&mstp2_clks SH73A0_C
436 clock-names = "fck";
437 power-domains = <&pd_a3sp>;
438 status = "disabled";
439 };
440
441 scifb: serial@e6c30000 {
442 compatible = "renesas,scifb-sh
443 reg = <0xe6c30000 0x100>;
444 interrupts = <GIC_SPI 80 IRQ_T
445 clocks = <&mstp2_clks SH73A0_C
446 clock-names = "fck";
447 power-domains = <&pd_a3sp>;
448 status = "disabled";
449 };
450
451 pfc: pinctrl@e6050000 {
452 compatible = "renesas,pfc-sh73
453 reg = <0xe6050000 0x8000>,
454 <0xe605801c 0x1c>;
455 gpio-controller;
456 #gpio-cells = <2>;
457 gpio-ranges =
458 <&pfc 0 0 119>, <&pfc
459 <&pfc 288 288 22>;
460 interrupts-extended =
461 <&irqpin0 0 0>, <&irqp
462 <&irqpin0 4 0>, <&irqp
463 <&irqpin1 0 0>, <&irqp
464 <&irqpin1 4 0>, <&irqp
465 <&irqpin2 0 0>, <&irqp
466 <&irqpin2 4 0>, <&irqp
467 <&irqpin3 0 0>, <&irqp
468 <&irqpin3 4 0>, <&irqp
469 power-domains = <&pd_c5>;
470 };
471
472 sysc: system-controller@e6180000 {
473 compatible = "renesas,sysc-sh7
474 reg = <0xe6180000 0x8000>, <0x
475
476 pm-domains {
477 pd_c5: c5 {
478 #address-cells
479 #size-cells =
480 #power-domain-
481
482 pd_c4: c4@0 {
483 reg =
484 #power
485 };
486
487 pd_d4: d4@1 {
488 reg =
489 #power
490 };
491
492 pd_a4bc0: a4bc
493 reg =
494 #power
495 };
496
497 pd_a4bc1: a4bc
498 reg =
499 #power
500 };
501
502 pd_a4lc0: a4lc
503 reg =
504 #power
505 };
506
507 pd_a4lc1: a4lc
508 reg =
509 #power
510 };
511
512 pd_a4mp: a4mp@
513 reg =
514 #addre
515 #size-
516 #power
517
518 pd_a3m
519
520
521 };
522
523 pd_a3v
524
525
526 };
527 };
528
529 pd_a4rm: a4rm@
530 reg =
531 #addre
532 #size-
533 #power
534
535 pd_a3r
536
537
538
539
540
541
542
543
544
545
546
547 };
548 };
549
550 pd_a4s: a4s@16
551 reg =
552 #addre
553 #size-
554 #power
555
556 pd_a3s
557
558
559 };
560
561 pd_a3s
562
563
564 };
565
566 pd_a3s
567
568
569
570
571
572
573
574
575
576 };
577 };
578 };
579 };
580 };
581
582 sh_fsi2: sound@ec230000 {
583 #sound-dai-cells = <1>;
584 compatible = "renesas,fsi2-sh7
585 reg = <0xec230000 0x400>;
586 interrupts = <GIC_SPI 146 0x4>
587 clocks = <&mstp3_clks SH73A0_C
588 power-domains = <&pd_a4mp>;
589 status = "disabled";
590 };
591
592 bsc: bus@fec10000 {
593 compatible = "renesas,bsc-sh73
594 "simple-pm-bus";
595 #address-cells = <1>;
596 #size-cells = <1>;
597 ranges = <0 0 0x20000000>;
598 reg = <0xfec10000 0x400>;
599 interrupts = <GIC_SPI 39 IRQ_T
600 clocks = <&zb_clk>;
601 power-domains = <&pd_a4s>;
602 };
603
604 clocks {
605 #address-cells = <1>;
606 #size-cells = <1>;
607 ranges;
608
609 /* External root clocks */
610 extalr_clk: extalr {
611 compatible = "fixed-cl
612 #clock-cells = <0>;
613 clock-frequency = <327
614 };
615 extal1_clk: extal1 {
616 compatible = "fixed-cl
617 #clock-cells = <0>;
618 clock-frequency = <260
619 };
620 extal2_clk: extal2 {
621 compatible = "fixed-cl
622 #clock-cells = <0>;
623 /* This value must be
624 clock-frequency = <0>;
625 };
626 extcki_clk: extcki {
627 compatible = "fixed-cl
628 #clock-cells = <0>;
629 /* This value can be o
630 clock-frequency = <0>;
631 };
632 fsiack_clk: fsiack {
633 compatible = "fixed-cl
634 #clock-cells = <0>;
635 /* This value can be o
636 clock-frequency = <0>;
637 };
638 fsibck_clk: fsibck {
639 compatible = "fixed-cl
640 #clock-cells = <0>;
641 /* This value can be o
642 clock-frequency = <0>;
643 };
644
645 /* Special CPG clocks */
646 cpg_clocks: cpg_clocks@e615000
647 compatible = "renesas,
648 reg = <0xe6150000 0x10
649 clocks = <&extal1_clk>
650 #clock-cells = <1>;
651 clock-output-names = "
652 "
653 "
654 "
655 };
656
657 /* Variable factor clocks (DIV
658 vclk1_clk: vclk1@e6150008 {
659 compatible = "renesas,
660 reg = <0xe6150008 4>;
661 clocks = <&pll1_div2_c
662 <&extcki_clk>
663 <&extalr_clk>
664 <0>;
665 #clock-cells = <0>;
666 };
667 vclk2_clk: vclk2@e615000c {
668 compatible = "renesas,
669 reg = <0xe615000c 4>;
670 clocks = <&pll1_div2_c
671 <&extcki_clk>
672 <&extalr_clk>
673 <0>;
674 #clock-cells = <0>;
675 };
676 vclk3_clk: vclk3@e615001c {
677 compatible = "renesas,
678 reg = <0xe615001c 4>;
679 clocks = <&pll1_div2_c
680 <&extcki_clk>
681 <&extalr_clk>
682 <0>;
683 #clock-cells = <0>;
684 };
685 zb_clk: zb_clk@e6150010 {
686 compatible = "renesas,
687 reg = <0xe6150010 4>;
688 clocks = <&pll1_div2_c
689 <&cpg_clocks
690 #clock-cells = <0>;
691 clock-output-names = "
692 };
693 flctl_clk: flctlck@e6150014 {
694 compatible = "renesas,
695 reg = <0xe6150014 4>;
696 clocks = <&pll1_div2_c
697 <&cpg_clocks
698 #clock-cells = <0>;
699 };
700 sdhi0_clk: sdhi0ck@e6150074 {
701 compatible = "renesas,
702 reg = <0xe6150074 4>;
703 clocks = <&pll1_div2_c
704 <&pll1_div13_
705 #clock-cells = <0>;
706 };
707 sdhi1_clk: sdhi1ck@e6150078 {
708 compatible = "renesas,
709 reg = <0xe6150078 4>;
710 clocks = <&pll1_div2_c
711 <&pll1_div13_
712 #clock-cells = <0>;
713 };
714 sdhi2_clk: sdhi2ck@e615007c {
715 compatible = "renesas,
716 reg = <0xe615007c 4>;
717 clocks = <&pll1_div2_c
718 <&pll1_div13_
719 #clock-cells = <0>;
720 };
721 fsia_clk: fsia@e6150018 {
722 compatible = "renesas,
723 reg = <0xe6150018 4>;
724 clocks = <&pll1_div2_c
725 <&fsiack_clk>
726 #clock-cells = <0>;
727 };
728 fsib_clk: fsib@e6150090 {
729 compatible = "renesas,
730 reg = <0xe6150090 4>;
731 clocks = <&pll1_div2_c
732 <&fsibck_clk>
733 #clock-cells = <0>;
734 };
735 sub_clk: sub@e6150080 {
736 compatible = "renesas,
737 reg = <0xe6150080 4>;
738 clocks = <&pll1_div2_c
739 <&extal2_clk>
740 #clock-cells = <0>;
741 };
742 spua_clk: spua@e6150084 {
743 compatible = "renesas,
744 reg = <0xe6150084 4>;
745 clocks = <&pll1_div2_c
746 <&extal2_clk>
747 #clock-cells = <0>;
748 };
749 spuv_clk: spuv@e6150094 {
750 compatible = "renesas,
751 reg = <0xe6150094 4>;
752 clocks = <&pll1_div2_c
753 <&extal2_clk>
754 #clock-cells = <0>;
755 };
756 msu_clk: msu@e6150088 {
757 compatible = "renesas,
758 reg = <0xe6150088 4>;
759 clocks = <&pll1_div2_c
760 <&cpg_clocks
761 #clock-cells = <0>;
762 };
763 hsi_clk: hsi@e615008c {
764 compatible = "renesas,
765 reg = <0xe615008c 4>;
766 clocks = <&pll1_div2_c
767 <&pll1_div7_c
768 #clock-cells = <0>;
769 };
770 mfg1_clk: mfg1@e6150098 {
771 compatible = "renesas,
772 reg = <0xe6150098 4>;
773 clocks = <&pll1_div2_c
774 <&cpg_clocks
775 #clock-cells = <0>;
776 };
777 mfg2_clk: mfg2@e615009c {
778 compatible = "renesas,
779 reg = <0xe615009c 4>;
780 clocks = <&pll1_div2_c
781 <&cpg_clocks
782 #clock-cells = <0>;
783 };
784 dsit_clk: dsit@e6150060 {
785 compatible = "renesas,
786 reg = <0xe6150060 4>;
787 clocks = <&pll1_div2_c
788 <&cpg_clocks
789 #clock-cells = <0>;
790 };
791 dsi0p_clk: dsi0pck@e6150064 {
792 compatible = "renesas,
793 reg = <0xe6150064 4>;
794 clocks = <&pll1_div2_c
795 <&cpg_clocks
796 <&extcki_clk>
797 #clock-cells = <0>;
798 };
799
800 /* Fixed factor clocks */
801 main_div2_clk: main_div2 {
802 compatible = "fixed-fa
803 clocks = <&cpg_clocks
804 #clock-cells = <0>;
805 clock-div = <2>;
806 clock-mult = <1>;
807 };
808 pll1_div2_clk: pll1_div2 {
809 compatible = "fixed-fa
810 clocks = <&cpg_clocks
811 #clock-cells = <0>;
812 clock-div = <2>;
813 clock-mult = <1>;
814 };
815 pll1_div7_clk: pll1_div7 {
816 compatible = "fixed-fa
817 clocks = <&cpg_clocks
818 #clock-cells = <0>;
819 clock-div = <7>;
820 clock-mult = <1>;
821 };
822 pll1_div13_clk: pll1_div13 {
823 compatible = "fixed-fa
824 clocks = <&cpg_clocks
825 #clock-cells = <0>;
826 clock-div = <13>;
827 clock-mult = <1>;
828 };
829 periph_clk: periph {
830 compatible = "fixed-fa
831 clocks = <&cpg_clocks
832 #clock-cells = <0>;
833 clock-div = <4>;
834 clock-mult = <1>;
835 };
836
837 /* Gate clocks */
838 mstp0_clks: mstp0_clks@e615013
839 compatible = "renesas,
840 reg = <0xe6150130 4>,
841 clocks = <&cpg_clocks
842 #clock-cells = <1>;
843 clock-indices = <
844 SH73A0_CLK_IIC
845 >;
846 clock-output-names =
847 "iic2", "msiof
848 };
849 mstp1_clks: mstp1_clks@e615013
850 compatible = "renesas,
851 reg = <0xe6150134 4>,
852 clocks = <&cpg_clocks
853 <&cpg_clocks
854 <&cpg_clocks
855 <&cpg_clocks
856 <&sub_clk>, <
857 <&cpg_clocks
858 <&cpg_clocks
859 <&cpg_clocks
860 #clock-cells = <1>;
861 clock-indices = <
862 SH73A0_CLK_CEU
863 SH73A0_CLK_CEU
864 SH73A0_CLK_TMU
865 SH73A0_CLK_IIC
866 SH73A0_CLK_LCD
867 >;
868 clock-output-names =
869 "ceu1", "csi2_
870 "tmu0", "dsitx
871 };
872 mstp2_clks: mstp2_clks@e615013
873 compatible = "renesas,
874 reg = <0xe6150138 4>,
875 clocks = <&sub_clk>, <
876 <&cpg_clocks
877 <&sub_clk>, <
878 <&sub_clk>, <
879 <&sub_clk>, <
880 #clock-cells = <1>;
881 clock-indices = <
882 SH73A0_CLK_SCI
883 SH73A0_CLK_MP_
884 SH73A0_CLK_MSI
885 SH73A0_CLK_SCI
886 SH73A0_CLK_SCI
887 SH73A0_CLK_SCI
888 SH73A0_CLK_SCI
889 >;
890 clock-output-names =
891 "scifa7", "sy_
892 "msiof1", "sci
893 "scifa0", "sci
894 "scifa4";
895 };
896 mstp3_clks: mstp3_clks@e615013
897 compatible = "renesas,
898 reg = <0xe615013c 4>,
899 clocks = <&sub_clk>, <
900 <&cpg_clocks
901 <&cpg_clocks
902 <&cpg_clocks
903 <&sdhi0_clk>,
904 <&cpg_clocks
905 <&main_div2_c
906 <&main_div2_c
907 <&main_div2_c
908 #clock-cells = <1>;
909 clock-indices = <
910 SH73A0_CLK_SCI
911 SH73A0_CLK_FSI
912 SH73A0_CLK_IIC
913 SH73A0_CLK_SDH
914 SH73A0_CLK_MMC
915 SH73A0_CLK_TPU
916 SH73A0_CLK_TPU
917 SH73A0_CLK_TPU
918 >;
919 clock-output-names =
920 "scifa6", "cmt
921 "usb", "flctl"
922 "tpu0", "tpu1"
923 };
924 mstp4_clks: mstp4_clks@e615014
925 compatible = "renesas,
926 reg = <0xe6150140 4>,
927 clocks = <&cpg_clocks
928 <&cpg_clocks
929 #clock-cells = <1>;
930 clock-indices = <
931 SH73A0_CLK_IIC
932 SH73A0_CLK_KEY
933 >;
934 clock-output-names =
935 "iic3", "iic4"
936 };
937 mstp5_clks: mstp5_clks@e615014
938 compatible = "renesas,
939 reg = <0xe6150144 4>,
940 clocks = <&cpg_clocks
941 #clock-cells = <1>;
942 clock-indices = <
943 SH73A0_CLK_INT
944 >;
945 clock-output-names =
946 "intca0";
947 };
948 };
949 };
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