1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 2
3 #include <dt-bindings/gpio/gpio.h> 3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq 4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h> 6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h> 7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h 8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h> 9 #include <dt-bindings/power/rk3036-power.h>
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 14
15 compatible = "rockchip,rk3036"; 15 compatible = "rockchip,rk3036";
16 16
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases { 19 aliases {
20 gpio0 = &gpio0; <<
21 gpio1 = &gpio1; <<
22 gpio2 = &gpio2; <<
23 i2c0 = &i2c0; 20 i2c0 = &i2c0;
24 i2c1 = &i2c1; 21 i2c1 = &i2c1;
25 i2c2 = &i2c2; 22 i2c2 = &i2c2;
26 mshc0 = &emmc; 23 mshc0 = &emmc;
27 mshc1 = &sdmmc; 24 mshc1 = &sdmmc;
28 mshc2 = &sdio; 25 mshc2 = &sdio;
29 serial0 = &uart0; 26 serial0 = &uart0;
30 serial1 = &uart1; 27 serial1 = &uart1;
31 serial2 = &uart2; 28 serial2 = &uart2;
32 spi = &spi; 29 spi = &spi;
33 }; 30 };
34 31
35 cpus { 32 cpus {
36 #address-cells = <1>; 33 #address-cells = <1>;
37 #size-cells = <0>; 34 #size-cells = <0>;
38 enable-method = "rockchip,rk30 35 enable-method = "rockchip,rk3036-smp";
39 36
40 cpu0: cpu@f00 { 37 cpu0: cpu@f00 {
41 device_type = "cpu"; 38 device_type = "cpu";
42 compatible = "arm,cort 39 compatible = "arm,cortex-a7";
43 reg = <0xf00>; 40 reg = <0xf00>;
44 resets = <&cru SRST_CO 41 resets = <&cru SRST_CORE0>;
45 operating-points = < 42 operating-points = <
46 /* KHz uV * 43 /* KHz uV */
47 816000 100000 44 816000 1000000
48 >; 45 >;
49 clock-latency = <40000 46 clock-latency = <40000>;
50 clocks = <&cru ARMCLK> 47 clocks = <&cru ARMCLK>;
51 }; 48 };
52 49
53 cpu1: cpu@f01 { 50 cpu1: cpu@f01 {
54 device_type = "cpu"; 51 device_type = "cpu";
55 compatible = "arm,cort 52 compatible = "arm,cortex-a7";
56 reg = <0xf01>; 53 reg = <0xf01>;
57 resets = <&cru SRST_CO 54 resets = <&cru SRST_CORE1>;
58 }; 55 };
59 }; 56 };
60 57
61 arm-pmu { 58 arm-pmu {
62 compatible = "arm,cortex-a7-pm 59 compatible = "arm,cortex-a7-pmu";
63 interrupts = <GIC_SPI 76 IRQ_T 60 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 77 IRQ_T 61 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&cpu0>, 62 interrupt-affinity = <&cpu0>, <&cpu1>;
66 }; 63 };
67 64
68 display-subsystem { 65 display-subsystem {
69 compatible = "rockchip,display 66 compatible = "rockchip,display-subsystem";
70 ports = <&vop_out>; 67 ports = <&vop_out>;
71 }; 68 };
72 69
73 timer { 70 timer {
74 compatible = "arm,armv7-timer" 71 compatible = "arm,armv7-timer";
75 arm,cpu-registers-not-fw-confi 72 arm,cpu-registers-not-fw-configured;
76 interrupts = <GIC_PPI 13 (GIC_ 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 14 (GIC_ 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
78 <GIC_PPI 11 (GIC_ 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
79 <GIC_PPI 10 (GIC_ 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
80 clock-frequency = <24000000>; 77 clock-frequency = <24000000>;
81 }; 78 };
82 79
83 xin24m: oscillator { 80 xin24m: oscillator {
84 compatible = "fixed-clock"; 81 compatible = "fixed-clock";
85 clock-frequency = <24000000>; 82 clock-frequency = <24000000>;
86 clock-output-names = "xin24m"; 83 clock-output-names = "xin24m";
87 #clock-cells = <0>; 84 #clock-cells = <0>;
88 }; 85 };
89 86
90 bus_intmem: sram@10080000 { 87 bus_intmem: sram@10080000 {
91 compatible = "mmio-sram"; 88 compatible = "mmio-sram";
92 reg = <0x10080000 0x2000>; 89 reg = <0x10080000 0x2000>;
93 #address-cells = <1>; 90 #address-cells = <1>;
94 #size-cells = <1>; 91 #size-cells = <1>;
95 ranges = <0 0x10080000 0x2000> 92 ranges = <0 0x10080000 0x2000>;
96 93
97 smp-sram@0 { 94 smp-sram@0 {
98 compatible = "rockchip 95 compatible = "rockchip,rk3066-smp-sram";
99 reg = <0x00 0x10>; 96 reg = <0x00 0x10>;
100 }; 97 };
101 }; 98 };
102 99
103 gpu: gpu@10090000 { 100 gpu: gpu@10090000 {
104 compatible = "rockchip,rk3036- 101 compatible = "rockchip,rk3036-mali", "arm,mali-400";
105 reg = <0x10090000 0x10000>; 102 reg = <0x10090000 0x10000>;
106 interrupts = <GIC_SPI 3 IRQ_TY 103 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 4 IRQ_TY 104 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 5 IRQ_TY 105 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 4 IRQ_TY 106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "gp", 107 interrupt-names = "gp",
111 "gpmmu", 108 "gpmmu",
112 "pp0", 109 "pp0",
113 "ppmmu0"; 110 "ppmmu0";
114 assigned-clocks = <&cru SCLK_G 111 assigned-clocks = <&cru SCLK_GPU>;
115 assigned-clock-rates = <100000 112 assigned-clock-rates = <100000000>;
116 clocks = <&cru SCLK_GPU>, <&cr 113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
117 clock-names = "bus", "core"; 114 clock-names = "bus", "core";
118 power-domains = <&power RK3036 115 power-domains = <&power RK3036_PD_GPU>;
119 resets = <&cru SRST_GPU>; 116 resets = <&cru SRST_GPU>;
120 status = "disabled"; 117 status = "disabled";
121 }; 118 };
122 119
123 vpu: video-codec@10108000 { 120 vpu: video-codec@10108000 {
124 compatible = "rockchip,rk3036- 121 compatible = "rockchip,rk3036-vpu";
125 reg = <0x10108000 0x800>; 122 reg = <0x10108000 0x800>;
126 interrupts = <GIC_SPI 7 IRQ_TY 123 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-names = "vdpu"; 124 interrupt-names = "vdpu";
128 clocks = <&cru ACLK_VCODEC>, < 125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
129 clock-names = "aclk", "hclk"; 126 clock-names = "aclk", "hclk";
130 iommus = <&vpu_mmu>; 127 iommus = <&vpu_mmu>;
131 power-domains = <&power RK3036 128 power-domains = <&power RK3036_PD_VPU>;
132 }; 129 };
133 130
134 vpu_mmu: iommu@10108800 { 131 vpu_mmu: iommu@10108800 {
135 compatible = "rockchip,iommu"; 132 compatible = "rockchip,iommu";
136 reg = <0x10108800 0x100>; 133 reg = <0x10108800 0x100>;
137 interrupts = <GIC_SPI 55 IRQ_T 134 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cru ACLK_VCODEC>, < 135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
139 clock-names = "aclk", "iface"; 136 clock-names = "aclk", "iface";
140 power-domains = <&power RK3036 137 power-domains = <&power RK3036_PD_VPU>;
141 #iommu-cells = <0>; 138 #iommu-cells = <0>;
142 }; 139 };
143 140
144 vop: vop@10118000 { 141 vop: vop@10118000 {
145 compatible = "rockchip,rk3036- 142 compatible = "rockchip,rk3036-vop";
146 reg = <0x10118000 0x19c>; 143 reg = <0x10118000 0x19c>;
147 interrupts = <GIC_SPI 43 IRQ_T 144 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cru ACLK_LCDC>, <&c 145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
149 clock-names = "aclk_vop", "dcl 146 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
150 resets = <&cru SRST_LCDC1_A>, 147 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
151 reset-names = "axi", "ahb", "d 148 reset-names = "axi", "ahb", "dclk";
152 iommus = <&vop_mmu>; 149 iommus = <&vop_mmu>;
153 power-domains = <&power RK3036 150 power-domains = <&power RK3036_PD_VIO>;
154 status = "disabled"; 151 status = "disabled";
155 152
156 vop_out: port { 153 vop_out: port {
157 #address-cells = <1>; 154 #address-cells = <1>;
158 #size-cells = <0>; 155 #size-cells = <0>;
159 vop_out_hdmi: endpoint 156 vop_out_hdmi: endpoint@0 {
160 reg = <0>; 157 reg = <0>;
161 remote-endpoin 158 remote-endpoint = <&hdmi_in_vop>;
162 }; 159 };
163 }; 160 };
164 }; 161 };
165 162
166 vop_mmu: iommu@10118300 { 163 vop_mmu: iommu@10118300 {
167 compatible = "rockchip,iommu"; 164 compatible = "rockchip,iommu";
168 reg = <0x10118300 0x100>; 165 reg = <0x10118300 0x100>;
169 interrupts = <GIC_SPI 43 IRQ_T 166 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru ACLK_LCDC>, <&c 167 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
171 clock-names = "aclk", "iface"; 168 clock-names = "aclk", "iface";
172 power-domains = <&power RK3036 169 power-domains = <&power RK3036_PD_VIO>;
173 #iommu-cells = <0>; 170 #iommu-cells = <0>;
174 status = "disabled"; 171 status = "disabled";
175 }; 172 };
176 173
177 qos_gpu: qos@1012d000 { 174 qos_gpu: qos@1012d000 {
178 compatible = "rockchip,rk3036- 175 compatible = "rockchip,rk3036-qos", "syscon";
179 reg = <0x1012d000 0x20>; 176 reg = <0x1012d000 0x20>;
180 }; 177 };
181 178
182 qos_vpu: qos@1012e000 { 179 qos_vpu: qos@1012e000 {
183 compatible = "rockchip,rk3036- 180 compatible = "rockchip,rk3036-qos", "syscon";
184 reg = <0x1012e000 0x20>; 181 reg = <0x1012e000 0x20>;
185 }; 182 };
186 183
187 qos_vio: qos@1012f000 { 184 qos_vio: qos@1012f000 {
188 compatible = "rockchip,rk3036- 185 compatible = "rockchip,rk3036-qos", "syscon";
189 reg = <0x1012f000 0x20>; 186 reg = <0x1012f000 0x20>;
190 }; 187 };
191 188
192 gic: interrupt-controller@10139000 { 189 gic: interrupt-controller@10139000 {
193 compatible = "arm,gic-400"; 190 compatible = "arm,gic-400";
194 interrupt-controller; 191 interrupt-controller;
195 #interrupt-cells = <3>; 192 #interrupt-cells = <3>;
196 #address-cells = <0>; 193 #address-cells = <0>;
197 194
198 reg = <0x10139000 0x1000>, 195 reg = <0x10139000 0x1000>,
199 <0x1013a000 0x2000>, 196 <0x1013a000 0x2000>,
200 <0x1013c000 0x2000>, 197 <0x1013c000 0x2000>,
201 <0x1013e000 0x2000>; 198 <0x1013e000 0x2000>;
202 interrupts = <GIC_PPI 9 (GIC_C 199 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
203 }; 200 };
204 201
205 usb_otg: usb@10180000 { 202 usb_otg: usb@10180000 {
206 compatible = "rockchip,rk3036- 203 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
207 "snps,dwc2"; 204 "snps,dwc2";
208 reg = <0x10180000 0x40000>; 205 reg = <0x10180000 0x40000>;
209 interrupts = <GIC_SPI 10 IRQ_T 206 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cru HCLK_OTG0>; 207 clocks = <&cru HCLK_OTG0>;
211 clock-names = "otg"; 208 clock-names = "otg";
212 dr_mode = "otg"; 209 dr_mode = "otg";
213 g-np-tx-fifo-size = <16>; 210 g-np-tx-fifo-size = <16>;
214 g-rx-fifo-size = <275>; 211 g-rx-fifo-size = <275>;
215 g-tx-fifo-size = <256 128 128 212 g-tx-fifo-size = <256 128 128 64 64 32>;
216 status = "disabled"; 213 status = "disabled";
217 }; 214 };
218 215
219 usb_host: usb@101c0000 { 216 usb_host: usb@101c0000 {
220 compatible = "rockchip,rk3036- 217 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
221 "snps,dwc2"; 218 "snps,dwc2";
222 reg = <0x101c0000 0x40000>; 219 reg = <0x101c0000 0x40000>;
223 interrupts = <GIC_SPI 11 IRQ_T 220 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru HCLK_OTG1>; 221 clocks = <&cru HCLK_OTG1>;
225 clock-names = "otg"; 222 clock-names = "otg";
226 dr_mode = "host"; 223 dr_mode = "host";
227 status = "disabled"; 224 status = "disabled";
228 }; 225 };
229 226
230 emac: ethernet@10200000 { 227 emac: ethernet@10200000 {
231 compatible = "rockchip,rk3036- 228 compatible = "rockchip,rk3036-emac";
232 reg = <0x10200000 0x4000>; 229 reg = <0x10200000 0x4000>;
233 interrupts = <GIC_SPI 8 IRQ_TY 230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
234 rockchip,grf = <&grf>; 231 rockchip,grf = <&grf>;
235 clocks = <&cru HCLK_MAC>, <&cr 232 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
236 clock-names = "hclk", "macref" 233 clock-names = "hclk", "macref", "macclk";
237 /* 234 /*
238 * Fix the emac parent clock i 235 * Fix the emac parent clock is DPLL instead of APLL.
239 * since that will cause some 236 * since that will cause some unstable things if the cpufreq
240 * is working. (e.g: the accur 237 * is working. (e.g: the accurate 50MHz what mac_ref need)
241 */ 238 */
242 assigned-clocks = <&cru SCLK_M 239 assigned-clocks = <&cru SCLK_MACPLL>;
243 assigned-clock-parents = <&cru 240 assigned-clock-parents = <&cru PLL_DPLL>;
244 max-speed = <100>; 241 max-speed = <100>;
245 phy-mode = "rmii"; 242 phy-mode = "rmii";
246 status = "disabled"; 243 status = "disabled";
247 }; 244 };
248 245
249 sdmmc: mmc@10214000 { 246 sdmmc: mmc@10214000 {
250 compatible = "rockchip,rk3036- 247 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
251 reg = <0x10214000 0x4000>; 248 reg = <0x10214000 0x4000>;
252 clock-frequency = <37500000>; 249 clock-frequency = <37500000>;
253 max-frequency = <37500000>; 250 max-frequency = <37500000>;
254 clocks = <&cru HCLK_SDMMC>, <& 251 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
255 clock-names = "biu", "ciu"; 252 clock-names = "biu", "ciu";
256 fifo-depth = <0x100>; 253 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 14 IRQ_T 254 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
258 resets = <&cru SRST_MMC0>; 255 resets = <&cru SRST_MMC0>;
259 reset-names = "reset"; 256 reset-names = "reset";
260 status = "disabled"; 257 status = "disabled";
261 }; 258 };
262 259
263 sdio: mmc@10218000 { 260 sdio: mmc@10218000 {
264 compatible = "rockchip,rk3036- 261 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
265 reg = <0x10218000 0x4000>; 262 reg = <0x10218000 0x4000>;
266 max-frequency = <37500000>; 263 max-frequency = <37500000>;
267 clocks = <&cru HCLK_SDIO>, <&c 264 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
268 <&cru SCLK_SDIO_DRV>, 265 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
269 clock-names = "biu", "ciu", "c 266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 fifo-depth = <0x100>; 267 fifo-depth = <0x100>;
271 interrupts = <GIC_SPI 15 IRQ_T 268 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
272 resets = <&cru SRST_SDIO>; 269 resets = <&cru SRST_SDIO>;
273 reset-names = "reset"; 270 reset-names = "reset";
274 status = "disabled"; 271 status = "disabled";
275 }; 272 };
276 273
277 emmc: mmc@1021c000 { 274 emmc: mmc@1021c000 {
278 compatible = "rockchip,rk3036- 275 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
279 reg = <0x1021c000 0x4000>; 276 reg = <0x1021c000 0x4000>;
280 interrupts = <GIC_SPI 16 IRQ_T 277 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
281 bus-width = <8>; 278 bus-width = <8>;
282 cap-mmc-highspeed; 279 cap-mmc-highspeed;
283 clock-frequency = <37500000>; 280 clock-frequency = <37500000>;
284 max-frequency = <37500000>; 281 max-frequency = <37500000>;
285 clocks = <&cru HCLK_EMMC>, <&c 282 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
286 <&cru SCLK_EMMC_DRV>, 283 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
287 clock-names = "biu", "ciu", "c 284 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
>> 285 rockchip,default-sample-phase = <158>;
288 disable-wp; 286 disable-wp;
289 dmas = <&pdma 12>; 287 dmas = <&pdma 12>;
290 dma-names = "rx-tx"; 288 dma-names = "rx-tx";
291 fifo-depth = <0x100>; 289 fifo-depth = <0x100>;
292 mmc-ddr-1_8v; 290 mmc-ddr-1_8v;
293 non-removable; 291 non-removable;
294 pinctrl-names = "default"; 292 pinctrl-names = "default";
295 pinctrl-0 = <&emmc_clk &emmc_c 293 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
296 resets = <&cru SRST_EMMC>; 294 resets = <&cru SRST_EMMC>;
297 reset-names = "reset"; 295 reset-names = "reset";
298 status = "disabled"; 296 status = "disabled";
299 }; 297 };
300 298
301 i2s: i2s@10220000 { 299 i2s: i2s@10220000 {
302 compatible = "rockchip,rk3036- 300 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
303 reg = <0x10220000 0x4000>; 301 reg = <0x10220000 0x4000>;
304 interrupts = <GIC_SPI 51 IRQ_T 302 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
305 clock-names = "i2s_clk", "i2s_ 303 clock-names = "i2s_clk", "i2s_hclk";
306 clocks = <&cru SCLK_I2S>, <&cr 304 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
307 dmas = <&pdma 0>, <&pdma 1>; 305 dmas = <&pdma 0>, <&pdma 1>;
308 dma-names = "tx", "rx"; 306 dma-names = "tx", "rx";
309 pinctrl-names = "default"; 307 pinctrl-names = "default";
310 pinctrl-0 = <&i2s_bus>; 308 pinctrl-0 = <&i2s_bus>;
311 #sound-dai-cells = <0>; 309 #sound-dai-cells = <0>;
312 status = "disabled"; 310 status = "disabled";
313 }; 311 };
314 312
315 nfc: nand-controller@10500000 { 313 nfc: nand-controller@10500000 {
316 compatible = "rockchip,rk3036- 314 compatible = "rockchip,rk3036-nfc",
317 "rockchip,rk2928- 315 "rockchip,rk2928-nfc";
318 reg = <0x10500000 0x4000>; 316 reg = <0x10500000 0x4000>;
319 interrupts = <GIC_SPI 18 IRQ_T 317 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&cru HCLK_NANDC>, <& 318 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
321 clock-names = "ahb", "nfc"; 319 clock-names = "ahb", "nfc";
322 assigned-clocks = <&cru SCLK_N 320 assigned-clocks = <&cru SCLK_NANDC>;
323 assigned-clock-rates = <150000 321 assigned-clock-rates = <150000000>;
324 pinctrl-0 = <&flash_ale &flash 322 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
325 &flash_rdn &flash 323 &flash_rdn &flash_rdy &flash_wrn>;
326 pinctrl-names = "default"; 324 pinctrl-names = "default";
327 status = "disabled"; 325 status = "disabled";
328 }; 326 };
329 327
330 cru: clock-controller@20000000 { 328 cru: clock-controller@20000000 {
331 compatible = "rockchip,rk3036- 329 compatible = "rockchip,rk3036-cru";
332 reg = <0x20000000 0x1000>; 330 reg = <0x20000000 0x1000>;
333 clocks = <&xin24m>; 331 clocks = <&xin24m>;
334 clock-names = "xin24m"; 332 clock-names = "xin24m";
335 rockchip,grf = <&grf>; 333 rockchip,grf = <&grf>;
336 #clock-cells = <1>; 334 #clock-cells = <1>;
337 #reset-cells = <1>; 335 #reset-cells = <1>;
338 assigned-clocks = <&cru PLL_GP 336 assigned-clocks = <&cru PLL_GPLL>;
339 assigned-clock-rates = <594000 337 assigned-clock-rates = <594000000>;
340 }; 338 };
341 339
342 grf: syscon@20008000 { 340 grf: syscon@20008000 {
343 compatible = "rockchip,rk3036- 341 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
344 reg = <0x20008000 0x1000>; 342 reg = <0x20008000 0x1000>;
345 343
346 power: power-controller { 344 power: power-controller {
347 compatible = "rockchip 345 compatible = "rockchip,rk3036-power-controller";
348 #power-domain-cells = 346 #power-domain-cells = <1>;
349 #address-cells = <1>; 347 #address-cells = <1>;
350 #size-cells = <0>; 348 #size-cells = <0>;
351 349
352 power-domain@RK3036_PD 350 power-domain@RK3036_PD_VIO {
353 reg = <RK3036_ 351 reg = <RK3036_PD_VIO>;
354 clocks = <&cru 352 clocks = <&cru ACLK_LCDC>,
355 <&cru 353 <&cru HCLK_LCDC>,
356 <&cru 354 <&cru SCLK_LCDC>;
357 pm_qos = <&qos 355 pm_qos = <&qos_vio>;
358 #power-domain- 356 #power-domain-cells = <0>;
359 }; 357 };
360 358
361 power-domain@RK3036_PD 359 power-domain@RK3036_PD_VPU {
362 reg = <RK3036_ 360 reg = <RK3036_PD_VPU>;
363 clocks = <&cru 361 clocks = <&cru ACLK_VCODEC>,
364 <&cru 362 <&cru HCLK_VCODEC>;
365 pm_qos = <&qos 363 pm_qos = <&qos_vpu>;
366 #power-domain- 364 #power-domain-cells = <0>;
367 }; 365 };
368 366
369 power-domain@RK3036_PD 367 power-domain@RK3036_PD_GPU {
370 reg = <RK3036_ 368 reg = <RK3036_PD_GPU>;
371 clocks = <&cru 369 clocks = <&cru SCLK_GPU>;
372 pm_qos = <&qos 370 pm_qos = <&qos_gpu>;
373 #power-domain- 371 #power-domain-cells = <0>;
374 }; 372 };
375 }; 373 };
376 374
377 reboot-mode { 375 reboot-mode {
378 compatible = "syscon-r 376 compatible = "syscon-reboot-mode";
379 offset = <0x1d8>; 377 offset = <0x1d8>;
380 mode-normal = <BOOT_NO 378 mode-normal = <BOOT_NORMAL>;
381 mode-recovery = <BOOT_ 379 mode-recovery = <BOOT_RECOVERY>;
382 mode-bootloader = <BOO 380 mode-bootloader = <BOOT_FASTBOOT>;
383 mode-loader = <BOOT_BL 381 mode-loader = <BOOT_BL_DOWNLOAD>;
384 }; 382 };
385 }; 383 };
386 384
387 acodec: audio-codec@20030000 { !! 385 acodec: acodec-ana@20030000 {
388 compatible = "rockchip,rk3036- !! 386 compatible = "rk3036-codec";
389 reg = <0x20030000 0x4000>; 387 reg = <0x20030000 0x4000>;
>> 388 rockchip,grf = <&grf>;
390 clock-names = "acodec_pclk"; 389 clock-names = "acodec_pclk";
391 clocks = <&cru PCLK_ACODEC>; 390 clocks = <&cru PCLK_ACODEC>;
392 rockchip,grf = <&grf>; <<
393 #sound-dai-cells = <0>; <<
394 status = "disabled"; 391 status = "disabled";
395 }; 392 };
396 393
397 hdmi: hdmi@20034000 { 394 hdmi: hdmi@20034000 {
398 compatible = "rockchip,rk3036- 395 compatible = "rockchip,rk3036-inno-hdmi";
399 reg = <0x20034000 0x4000>; 396 reg = <0x20034000 0x4000>;
400 interrupts = <GIC_SPI 45 IRQ_T 397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru PCLK_HDMI>; 398 clocks = <&cru PCLK_HDMI>;
402 clock-names = "pclk"; 399 clock-names = "pclk";
>> 400 rockchip,grf = <&grf>;
403 pinctrl-names = "default"; 401 pinctrl-names = "default";
404 pinctrl-0 = <&hdmi_ctl>; 402 pinctrl-0 = <&hdmi_ctl>;
405 #sound-dai-cells = <0>; <<
406 status = "disabled"; 403 status = "disabled";
407 404
408 ports { !! 405 hdmi_in: port {
409 #address-cells = <1>; 406 #address-cells = <1>;
410 #size-cells = <0>; 407 #size-cells = <0>;
411 !! 408 hdmi_in_vop: endpoint@0 {
412 hdmi_in: port@0 { <<
413 reg = <0>; 409 reg = <0>;
414 !! 410 remote-endpoint = <&vop_out_hdmi>;
415 hdmi_in_vop: e <<
416 remote <<
417 }; <<
418 }; <<
419 <<
420 hdmi_out: port@1 { <<
421 reg = <1>; <<
422 }; 411 };
423 }; 412 };
424 }; 413 };
425 414
426 timer: timer@20044000 { 415 timer: timer@20044000 {
427 compatible = "rockchip,rk3036- 416 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
428 reg = <0x20044000 0x20>; 417 reg = <0x20044000 0x20>;
429 interrupts = <GIC_SPI 28 IRQ_T 418 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cru PCLK_TIMER>, <& 419 clocks = <&cru PCLK_TIMER>, <&xin24m>;
431 clock-names = "pclk", "timer"; 420 clock-names = "pclk", "timer";
432 }; 421 };
433 422
434 pwm0: pwm@20050000 { 423 pwm0: pwm@20050000 {
435 compatible = "rockchip,rk3036- 424 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
436 reg = <0x20050000 0x10>; 425 reg = <0x20050000 0x10>;
437 #pwm-cells = <3>; 426 #pwm-cells = <3>;
438 clocks = <&cru PCLK_PWM>; 427 clocks = <&cru PCLK_PWM>;
439 pinctrl-names = "default"; 428 pinctrl-names = "default";
440 pinctrl-0 = <&pwm0_pin>; 429 pinctrl-0 = <&pwm0_pin>;
441 status = "disabled"; 430 status = "disabled";
442 }; 431 };
443 432
444 pwm1: pwm@20050010 { 433 pwm1: pwm@20050010 {
445 compatible = "rockchip,rk3036- 434 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
446 reg = <0x20050010 0x10>; 435 reg = <0x20050010 0x10>;
447 #pwm-cells = <3>; 436 #pwm-cells = <3>;
448 clocks = <&cru PCLK_PWM>; 437 clocks = <&cru PCLK_PWM>;
449 pinctrl-names = "default"; 438 pinctrl-names = "default";
450 pinctrl-0 = <&pwm1_pin>; 439 pinctrl-0 = <&pwm1_pin>;
451 status = "disabled"; 440 status = "disabled";
452 }; 441 };
453 442
454 pwm2: pwm@20050020 { 443 pwm2: pwm@20050020 {
455 compatible = "rockchip,rk3036- 444 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
456 reg = <0x20050020 0x10>; 445 reg = <0x20050020 0x10>;
457 #pwm-cells = <3>; 446 #pwm-cells = <3>;
458 clocks = <&cru PCLK_PWM>; 447 clocks = <&cru PCLK_PWM>;
459 pinctrl-names = "default"; 448 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>; 449 pinctrl-0 = <&pwm2_pin>;
461 status = "disabled"; 450 status = "disabled";
462 }; 451 };
463 452
464 pwm3: pwm@20050030 { 453 pwm3: pwm@20050030 {
465 compatible = "rockchip,rk3036- 454 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
466 reg = <0x20050030 0x10>; 455 reg = <0x20050030 0x10>;
467 #pwm-cells = <2>; 456 #pwm-cells = <2>;
468 clocks = <&cru PCLK_PWM>; 457 clocks = <&cru PCLK_PWM>;
469 pinctrl-names = "default"; 458 pinctrl-names = "default";
470 pinctrl-0 = <&pwm3_pin>; 459 pinctrl-0 = <&pwm3_pin>;
471 status = "disabled"; 460 status = "disabled";
472 }; 461 };
473 462
474 i2c1: i2c@20056000 { 463 i2c1: i2c@20056000 {
475 compatible = "rockchip,rk3036- 464 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
476 reg = <0x20056000 0x1000>; 465 reg = <0x20056000 0x1000>;
477 interrupts = <GIC_SPI 25 IRQ_T 466 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>; 467 #address-cells = <1>;
479 #size-cells = <0>; 468 #size-cells = <0>;
480 clock-names = "i2c"; 469 clock-names = "i2c";
481 clocks = <&cru PCLK_I2C1>; 470 clocks = <&cru PCLK_I2C1>;
482 pinctrl-names = "default"; 471 pinctrl-names = "default";
483 pinctrl-0 = <&i2c1_xfer>; 472 pinctrl-0 = <&i2c1_xfer>;
484 status = "disabled"; 473 status = "disabled";
485 }; 474 };
486 475
487 i2c2: i2c@2005a000 { 476 i2c2: i2c@2005a000 {
488 compatible = "rockchip,rk3036- 477 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
489 reg = <0x2005a000 0x1000>; 478 reg = <0x2005a000 0x1000>;
490 interrupts = <GIC_SPI 26 IRQ_T 479 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>; 480 #address-cells = <1>;
492 #size-cells = <0>; 481 #size-cells = <0>;
493 clock-names = "i2c"; 482 clock-names = "i2c";
494 clocks = <&cru PCLK_I2C2>; 483 clocks = <&cru PCLK_I2C2>;
495 pinctrl-names = "default"; 484 pinctrl-names = "default";
496 pinctrl-0 = <&i2c2_xfer>; 485 pinctrl-0 = <&i2c2_xfer>;
497 status = "disabled"; 486 status = "disabled";
498 }; 487 };
499 488
500 uart0: serial@20060000 { 489 uart0: serial@20060000 {
501 compatible = "rockchip,rk3036- 490 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
502 reg = <0x20060000 0x100>; 491 reg = <0x20060000 0x100>;
503 interrupts = <GIC_SPI 20 IRQ_T 492 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
504 reg-shift = <2>; 493 reg-shift = <2>;
505 reg-io-width = <4>; 494 reg-io-width = <4>;
506 clock-frequency = <24000000>; 495 clock-frequency = <24000000>;
507 clocks = <&cru SCLK_UART0>, <& 496 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
508 clock-names = "baudclk", "apb_ 497 clock-names = "baudclk", "apb_pclk";
509 pinctrl-names = "default"; 498 pinctrl-names = "default";
510 pinctrl-0 = <&uart0_xfer &uart 499 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
511 status = "disabled"; 500 status = "disabled";
512 }; 501 };
513 502
514 uart1: serial@20064000 { 503 uart1: serial@20064000 {
515 compatible = "rockchip,rk3036- 504 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
516 reg = <0x20064000 0x100>; 505 reg = <0x20064000 0x100>;
517 interrupts = <GIC_SPI 21 IRQ_T 506 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
518 reg-shift = <2>; 507 reg-shift = <2>;
519 reg-io-width = <4>; 508 reg-io-width = <4>;
520 clock-frequency = <24000000>; 509 clock-frequency = <24000000>;
521 clocks = <&cru SCLK_UART1>, <& 510 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
522 clock-names = "baudclk", "apb_ 511 clock-names = "baudclk", "apb_pclk";
523 pinctrl-names = "default"; 512 pinctrl-names = "default";
524 pinctrl-0 = <&uart1_xfer>; 513 pinctrl-0 = <&uart1_xfer>;
525 status = "disabled"; 514 status = "disabled";
526 }; 515 };
527 516
528 uart2: serial@20068000 { 517 uart2: serial@20068000 {
529 compatible = "rockchip,rk3036- 518 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
530 reg = <0x20068000 0x100>; 519 reg = <0x20068000 0x100>;
531 interrupts = <GIC_SPI 22 IRQ_T 520 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
532 reg-shift = <2>; 521 reg-shift = <2>;
533 reg-io-width = <4>; 522 reg-io-width = <4>;
534 clock-frequency = <24000000>; 523 clock-frequency = <24000000>;
535 clocks = <&cru SCLK_UART2>, <& 524 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
536 clock-names = "baudclk", "apb_ 525 clock-names = "baudclk", "apb_pclk";
537 pinctrl-names = "default"; 526 pinctrl-names = "default";
538 pinctrl-0 = <&uart2_xfer>; 527 pinctrl-0 = <&uart2_xfer>;
539 status = "disabled"; 528 status = "disabled";
540 }; 529 };
541 530
542 i2c0: i2c@20072000 { 531 i2c0: i2c@20072000 {
543 compatible = "rockchip,rk3036- 532 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
544 reg = <0x20072000 0x1000>; 533 reg = <0x20072000 0x1000>;
545 interrupts = <GIC_SPI 24 IRQ_T 534 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>; 535 #address-cells = <1>;
547 #size-cells = <0>; 536 #size-cells = <0>;
548 clock-names = "i2c"; 537 clock-names = "i2c";
549 clocks = <&cru PCLK_I2C0>; 538 clocks = <&cru PCLK_I2C0>;
550 pinctrl-names = "default"; 539 pinctrl-names = "default";
551 pinctrl-0 = <&i2c0_xfer>; 540 pinctrl-0 = <&i2c0_xfer>;
552 status = "disabled"; 541 status = "disabled";
553 }; 542 };
554 543
555 spi: spi@20074000 { 544 spi: spi@20074000 {
556 compatible = "rockchip,rk3036- !! 545 compatible = "rockchip,rockchip-spi";
557 reg = <0x20074000 0x1000>; 546 reg = <0x20074000 0x1000>;
558 interrupts = <GIC_SPI 23 IRQ_T 547 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cru SCLK_SPI>, <&cr !! 548 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
560 clock-names = "spiclk", "apb_p !! 549 clock-names = "apb-pclk","spi_pclk";
561 dmas = <&pdma 8>, <&pdma 9>; 550 dmas = <&pdma 8>, <&pdma 9>;
562 dma-names = "tx", "rx"; 551 dma-names = "tx", "rx";
563 pinctrl-names = "default"; 552 pinctrl-names = "default";
564 pinctrl-0 = <&spi_txd &spi_rxd 553 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
565 #address-cells = <1>; 554 #address-cells = <1>;
566 #size-cells = <0>; 555 #size-cells = <0>;
567 status = "disabled"; 556 status = "disabled";
568 }; 557 };
569 558
570 pdma: dma-controller@20078000 { 559 pdma: dma-controller@20078000 {
571 compatible = "arm,pl330", "arm 560 compatible = "arm,pl330", "arm,primecell";
572 reg = <0x20078000 0x4000>; 561 reg = <0x20078000 0x4000>;
573 interrupts = <GIC_SPI 0 IRQ_TY 562 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 1 IRQ_TY 563 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
575 #dma-cells = <1>; 564 #dma-cells = <1>;
576 arm,pl330-broken-no-flushp; 565 arm,pl330-broken-no-flushp;
577 arm,pl330-periph-burst; 566 arm,pl330-periph-burst;
578 clocks = <&cru ACLK_DMAC2>; 567 clocks = <&cru ACLK_DMAC2>;
579 clock-names = "apb_pclk"; 568 clock-names = "apb_pclk";
580 }; 569 };
581 570
582 pinctrl: pinctrl { 571 pinctrl: pinctrl {
583 compatible = "rockchip,rk3036- 572 compatible = "rockchip,rk3036-pinctrl";
584 rockchip,grf = <&grf>; 573 rockchip,grf = <&grf>;
585 #address-cells = <1>; 574 #address-cells = <1>;
586 #size-cells = <1>; 575 #size-cells = <1>;
587 ranges; 576 ranges;
588 577
589 gpio0: gpio@2007c000 { 578 gpio0: gpio@2007c000 {
590 compatible = "rockchip 579 compatible = "rockchip,gpio-bank";
591 reg = <0x2007c000 0x10 580 reg = <0x2007c000 0x100>;
592 interrupts = <GIC_SPI 581 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cru PCLK_GP 582 clocks = <&cru PCLK_GPIO0>;
594 583
595 gpio-controller; 584 gpio-controller;
596 #gpio-cells = <2>; 585 #gpio-cells = <2>;
597 586
598 interrupt-controller; 587 interrupt-controller;
599 #interrupt-cells = <2> 588 #interrupt-cells = <2>;
600 }; 589 };
601 590
602 gpio1: gpio@20080000 { 591 gpio1: gpio@20080000 {
603 compatible = "rockchip 592 compatible = "rockchip,gpio-bank";
604 reg = <0x20080000 0x10 593 reg = <0x20080000 0x100>;
605 interrupts = <GIC_SPI 594 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cru PCLK_GP 595 clocks = <&cru PCLK_GPIO1>;
607 596
608 gpio-controller; 597 gpio-controller;
609 #gpio-cells = <2>; 598 #gpio-cells = <2>;
610 599
611 interrupt-controller; 600 interrupt-controller;
612 #interrupt-cells = <2> 601 #interrupt-cells = <2>;
613 }; 602 };
614 603
615 gpio2: gpio@20084000 { 604 gpio2: gpio@20084000 {
616 compatible = "rockchip 605 compatible = "rockchip,gpio-bank";
617 reg = <0x20084000 0x10 606 reg = <0x20084000 0x100>;
618 interrupts = <GIC_SPI 607 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru PCLK_GP 608 clocks = <&cru PCLK_GPIO2>;
620 609
621 gpio-controller; 610 gpio-controller;
622 #gpio-cells = <2>; 611 #gpio-cells = <2>;
623 612
624 interrupt-controller; 613 interrupt-controller;
625 #interrupt-cells = <2> 614 #interrupt-cells = <2>;
626 }; 615 };
627 616
628 pcfg_pull_default: pcfg-pull-d 617 pcfg_pull_default: pcfg-pull-default {
629 bias-pull-pin-default; 618 bias-pull-pin-default;
630 }; 619 };
631 620
632 pcfg_pull_none: pcfg-pull-none 621 pcfg_pull_none: pcfg-pull-none {
633 bias-disable; 622 bias-disable;
634 }; 623 };
635 624
636 pwm0 { 625 pwm0 {
637 pwm0_pin: pwm0-pin { 626 pwm0_pin: pwm0-pin {
638 rockchip,pins 627 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
639 }; 628 };
640 }; 629 };
641 630
642 pwm1 { 631 pwm1 {
643 pwm1_pin: pwm1-pin { 632 pwm1_pin: pwm1-pin {
644 rockchip,pins 633 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
645 }; 634 };
646 }; 635 };
647 636
648 pwm2 { 637 pwm2 {
649 pwm2_pin: pwm2-pin { 638 pwm2_pin: pwm2-pin {
650 rockchip,pins 639 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
651 }; 640 };
652 }; 641 };
653 642
654 pwm3 { 643 pwm3 {
655 pwm3_pin: pwm3-pin { 644 pwm3_pin: pwm3-pin {
656 rockchip,pins 645 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
657 }; 646 };
658 }; 647 };
659 648
660 sdmmc { 649 sdmmc {
661 sdmmc_clk: sdmmc-clk { 650 sdmmc_clk: sdmmc-clk {
662 rockchip,pins 651 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
663 }; 652 };
664 653
665 sdmmc_cmd: sdmmc-cmd { 654 sdmmc_cmd: sdmmc-cmd {
666 rockchip,pins 655 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
667 }; 656 };
668 657
669 sdmmc_cd: sdmmc-cd { 658 sdmmc_cd: sdmmc-cd {
670 rockchip,pins 659 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
671 }; 660 };
672 661
673 sdmmc_bus1: sdmmc-bus1 662 sdmmc_bus1: sdmmc-bus1 {
674 rockchip,pins 663 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
675 }; 664 };
676 665
677 sdmmc_bus4: sdmmc-bus4 666 sdmmc_bus4: sdmmc-bus4 {
678 rockchip,pins 667 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
679 668 <1 RK_PC3 1 &pcfg_pull_default>,
680 669 <1 RK_PC4 1 &pcfg_pull_default>,
681 670 <1 RK_PC5 1 &pcfg_pull_default>;
682 }; 671 };
683 }; 672 };
684 673
685 sdio { 674 sdio {
686 sdio_bus1: sdio-bus1 { 675 sdio_bus1: sdio-bus1 {
687 rockchip,pins 676 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
688 }; 677 };
689 678
690 sdio_bus4: sdio-bus4 { 679 sdio_bus4: sdio-bus4 {
691 rockchip,pins 680 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
692 681 <0 RK_PB4 1 &pcfg_pull_default>,
693 682 <0 RK_PB5 1 &pcfg_pull_default>,
694 683 <0 RK_PB6 1 &pcfg_pull_default>;
695 }; 684 };
696 685
697 sdio_cmd: sdio-cmd { 686 sdio_cmd: sdio-cmd {
698 rockchip,pins 687 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
699 }; 688 };
700 689
701 sdio_clk: sdio-clk { 690 sdio_clk: sdio-clk {
702 rockchip,pins 691 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
703 }; 692 };
704 }; 693 };
705 694
706 emmc { 695 emmc {
707 /* 696 /*
708 * We run eMMC at max 697 * We run eMMC at max speed; bump up drive strength.
709 * We also have extern 698 * We also have external pulls, so disable the internal ones.
710 */ 699 */
711 emmc_clk: emmc-clk { 700 emmc_clk: emmc-clk {
712 rockchip,pins 701 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
713 }; 702 };
714 703
715 emmc_cmd: emmc-cmd { 704 emmc_cmd: emmc-cmd {
716 rockchip,pins 705 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
717 }; 706 };
718 707
719 emmc_bus8: emmc-bus8 { 708 emmc_bus8: emmc-bus8 {
720 rockchip,pins 709 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
721 710 <1 RK_PD1 2 &pcfg_pull_default>,
722 711 <1 RK_PD2 2 &pcfg_pull_default>,
723 712 <1 RK_PD3 2 &pcfg_pull_default>,
724 713 <1 RK_PD4 2 &pcfg_pull_default>,
725 714 <1 RK_PD5 2 &pcfg_pull_default>,
726 715 <1 RK_PD6 2 &pcfg_pull_default>,
727 716 <1 RK_PD7 2 &pcfg_pull_default>;
728 }; 717 };
729 }; 718 };
730 719
731 nfc { 720 nfc {
732 flash_ale: flash-ale { 721 flash_ale: flash-ale {
733 rockchip,pins 722 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
734 }; 723 };
735 724
736 flash_bus8: flash-bus8 725 flash_bus8: flash-bus8 {
737 rockchip,pins 726 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
738 727 <1 RK_PD1 1 &pcfg_pull_default>,
739 728 <1 RK_PD2 1 &pcfg_pull_default>,
740 729 <1 RK_PD3 1 &pcfg_pull_default>,
741 730 <1 RK_PD4 1 &pcfg_pull_default>,
742 731 <1 RK_PD5 1 &pcfg_pull_default>,
743 732 <1 RK_PD6 1 &pcfg_pull_default>,
744 733 <1 RK_PD7 1 &pcfg_pull_default>;
745 }; 734 };
746 735
747 flash_cle: flash-cle { 736 flash_cle: flash-cle {
748 rockchip,pins 737 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
749 }; 738 };
750 739
751 flash_csn0: flash-csn0 740 flash_csn0: flash-csn0 {
752 rockchip,pins 741 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
753 }; 742 };
754 743
755 flash_rdn: flash-rdn { 744 flash_rdn: flash-rdn {
756 rockchip,pins 745 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
757 }; 746 };
758 747
759 flash_rdy: flash-rdy { 748 flash_rdy: flash-rdy {
760 rockchip,pins 749 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
761 }; 750 };
762 751
763 flash_wrn: flash-wrn { 752 flash_wrn: flash-wrn {
764 rockchip,pins 753 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
765 }; 754 };
766 }; 755 };
767 756
768 emac { 757 emac {
769 emac_xfer: emac-xfer { 758 emac_xfer: emac-xfer {
770 rockchip,pins 759 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
771 760 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
772 761 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
773 762 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
774 763 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
775 764 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
776 765 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
777 766 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
778 }; 767 };
779 768
780 emac_mdio: emac-mdio { 769 emac_mdio: emac-mdio {
781 rockchip,pins 770 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
782 771 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
783 }; 772 };
784 }; 773 };
785 774
786 i2c0 { 775 i2c0 {
787 i2c0_xfer: i2c0-xfer { 776 i2c0_xfer: i2c0-xfer {
788 rockchip,pins 777 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
789 778 <0 RK_PA1 1 &pcfg_pull_none>;
790 }; 779 };
791 }; 780 };
792 781
793 i2c1 { 782 i2c1 {
794 i2c1_xfer: i2c1-xfer { 783 i2c1_xfer: i2c1-xfer {
795 rockchip,pins 784 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
796 785 <0 RK_PA3 1 &pcfg_pull_none>;
797 }; 786 };
798 }; 787 };
799 788
800 i2c2 { 789 i2c2 {
801 i2c2_xfer: i2c2-xfer { 790 i2c2_xfer: i2c2-xfer {
802 rockchip,pins 791 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
803 792 <2 RK_PC5 1 &pcfg_pull_none>;
804 }; 793 };
805 }; 794 };
806 795
807 i2s { 796 i2s {
808 i2s_bus: i2s-bus { 797 i2s_bus: i2s-bus {
809 rockchip,pins 798 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
810 799 <1 RK_PA1 1 &pcfg_pull_default>,
811 800 <1 RK_PA2 1 &pcfg_pull_default>,
812 801 <1 RK_PA3 1 &pcfg_pull_default>,
813 802 <1 RK_PA4 1 &pcfg_pull_default>,
814 803 <1 RK_PA5 1 &pcfg_pull_default>;
815 }; 804 };
816 }; 805 };
817 806
818 hdmi { 807 hdmi {
819 hdmi_ctl: hdmi-ctl { 808 hdmi_ctl: hdmi-ctl {
820 rockchip,pins 809 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
821 810 <1 RK_PB1 1 &pcfg_pull_none>,
822 811 <1 RK_PB2 1 &pcfg_pull_none>,
823 812 <1 RK_PB3 1 &pcfg_pull_none>;
824 }; 813 };
825 }; 814 };
826 815
827 uart0 { 816 uart0 {
828 uart0_xfer: uart0-xfer 817 uart0_xfer: uart0-xfer {
829 rockchip,pins 818 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
830 819 <0 RK_PC1 1 &pcfg_pull_none>;
831 }; 820 };
832 821
833 uart0_cts: uart0-cts { 822 uart0_cts: uart0-cts {
834 rockchip,pins 823 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
835 }; 824 };
836 825
837 uart0_rts: uart0-rts { 826 uart0_rts: uart0-rts {
838 rockchip,pins 827 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
839 }; 828 };
840 }; 829 };
841 830
842 uart1 { 831 uart1 {
843 uart1_xfer: uart1-xfer 832 uart1_xfer: uart1-xfer {
844 rockchip,pins 833 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
845 834 <2 RK_PC7 1 &pcfg_pull_none>;
846 }; 835 };
847 /* no rts / cts for ua 836 /* no rts / cts for uart1 */
848 }; 837 };
849 838
850 uart2 { 839 uart2 {
851 uart2_xfer: uart2-xfer 840 uart2_xfer: uart2-xfer {
852 rockchip,pins 841 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
853 842 <1 RK_PC3 2 &pcfg_pull_none>;
854 }; 843 };
855 /* no rts / cts for ua 844 /* no rts / cts for uart2 */
856 }; 845 };
857 846
858 spi-pins { 847 spi-pins {
859 spi_txd:spi-txd { 848 spi_txd:spi-txd {
860 rockchip,pins 849 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
861 }; 850 };
862 851
863 spi_rxd:spi-rxd { 852 spi_rxd:spi-rxd {
864 rockchip,pins 853 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
865 }; 854 };
866 855
867 spi_clk:spi-clk { 856 spi_clk:spi-clk {
868 rockchip,pins 857 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
869 }; 858 };
870 859
871 spi_cs0:spi-cs0 { 860 spi_cs0:spi-cs0 {
872 rockchip,pins 861 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
873 862
874 }; 863 };
875 864
876 spi_cs1:spi-cs1 { 865 spi_cs1:spi-cs1 {
877 rockchip,pins 866 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
878 867
879 }; 868 };
880 }; 869 };
881 }; 870 };
882 }; 871 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.