1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 2
3 #include <dt-bindings/gpio/gpio.h> 3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq 4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h> 6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h> 7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h 8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h> 9 #include <dt-bindings/power/rk3036-power.h>
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 14
15 compatible = "rockchip,rk3036"; 15 compatible = "rockchip,rk3036";
16 16
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases { 19 aliases {
20 gpio0 = &gpio0; 20 gpio0 = &gpio0;
21 gpio1 = &gpio1; 21 gpio1 = &gpio1;
22 gpio2 = &gpio2; 22 gpio2 = &gpio2;
23 i2c0 = &i2c0; 23 i2c0 = &i2c0;
24 i2c1 = &i2c1; 24 i2c1 = &i2c1;
25 i2c2 = &i2c2; 25 i2c2 = &i2c2;
26 mshc0 = &emmc; 26 mshc0 = &emmc;
27 mshc1 = &sdmmc; 27 mshc1 = &sdmmc;
28 mshc2 = &sdio; 28 mshc2 = &sdio;
29 serial0 = &uart0; 29 serial0 = &uart0;
30 serial1 = &uart1; 30 serial1 = &uart1;
31 serial2 = &uart2; 31 serial2 = &uart2;
32 spi = &spi; 32 spi = &spi;
33 }; 33 };
34 34
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 enable-method = "rockchip,rk30 38 enable-method = "rockchip,rk3036-smp";
39 39
40 cpu0: cpu@f00 { 40 cpu0: cpu@f00 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "arm,cort 42 compatible = "arm,cortex-a7";
43 reg = <0xf00>; 43 reg = <0xf00>;
44 resets = <&cru SRST_CO 44 resets = <&cru SRST_CORE0>;
45 operating-points = < 45 operating-points = <
46 /* KHz uV * 46 /* KHz uV */
47 816000 100000 47 816000 1000000
48 >; 48 >;
49 clock-latency = <40000 49 clock-latency = <40000>;
50 clocks = <&cru ARMCLK> 50 clocks = <&cru ARMCLK>;
51 }; 51 };
52 52
53 cpu1: cpu@f01 { 53 cpu1: cpu@f01 {
54 device_type = "cpu"; 54 device_type = "cpu";
55 compatible = "arm,cort 55 compatible = "arm,cortex-a7";
56 reg = <0xf01>; 56 reg = <0xf01>;
57 resets = <&cru SRST_CO 57 resets = <&cru SRST_CORE1>;
58 }; 58 };
59 }; 59 };
60 60
61 arm-pmu { 61 arm-pmu {
62 compatible = "arm,cortex-a7-pm 62 compatible = "arm,cortex-a7-pmu";
63 interrupts = <GIC_SPI 76 IRQ_T 63 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 77 IRQ_T 64 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&cpu0>, 65 interrupt-affinity = <&cpu0>, <&cpu1>;
66 }; 66 };
67 67
68 display-subsystem { 68 display-subsystem {
69 compatible = "rockchip,display 69 compatible = "rockchip,display-subsystem";
70 ports = <&vop_out>; 70 ports = <&vop_out>;
71 }; 71 };
72 72
73 timer { 73 timer {
74 compatible = "arm,armv7-timer" 74 compatible = "arm,armv7-timer";
75 arm,cpu-registers-not-fw-confi 75 arm,cpu-registers-not-fw-configured;
76 interrupts = <GIC_PPI 13 (GIC_ 76 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 14 (GIC_ 77 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
78 <GIC_PPI 11 (GIC_ 78 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
79 <GIC_PPI 10 (GIC_ 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
80 clock-frequency = <24000000>; 80 clock-frequency = <24000000>;
81 }; 81 };
82 82
83 xin24m: oscillator { 83 xin24m: oscillator {
84 compatible = "fixed-clock"; 84 compatible = "fixed-clock";
85 clock-frequency = <24000000>; 85 clock-frequency = <24000000>;
86 clock-output-names = "xin24m"; 86 clock-output-names = "xin24m";
87 #clock-cells = <0>; 87 #clock-cells = <0>;
88 }; 88 };
89 89
90 bus_intmem: sram@10080000 { 90 bus_intmem: sram@10080000 {
91 compatible = "mmio-sram"; 91 compatible = "mmio-sram";
92 reg = <0x10080000 0x2000>; 92 reg = <0x10080000 0x2000>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <1>; 94 #size-cells = <1>;
95 ranges = <0 0x10080000 0x2000> 95 ranges = <0 0x10080000 0x2000>;
96 96
97 smp-sram@0 { 97 smp-sram@0 {
98 compatible = "rockchip 98 compatible = "rockchip,rk3066-smp-sram";
99 reg = <0x00 0x10>; 99 reg = <0x00 0x10>;
100 }; 100 };
101 }; 101 };
102 102
103 gpu: gpu@10090000 { 103 gpu: gpu@10090000 {
104 compatible = "rockchip,rk3036- 104 compatible = "rockchip,rk3036-mali", "arm,mali-400";
105 reg = <0x10090000 0x10000>; 105 reg = <0x10090000 0x10000>;
106 interrupts = <GIC_SPI 3 IRQ_TY 106 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 4 IRQ_TY 107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 5 IRQ_TY 108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 4 IRQ_TY 109 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "gp", 110 interrupt-names = "gp",
111 "gpmmu", 111 "gpmmu",
112 "pp0", 112 "pp0",
113 "ppmmu0"; 113 "ppmmu0";
114 assigned-clocks = <&cru SCLK_G 114 assigned-clocks = <&cru SCLK_GPU>;
115 assigned-clock-rates = <100000 115 assigned-clock-rates = <100000000>;
116 clocks = <&cru SCLK_GPU>, <&cr 116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
117 clock-names = "bus", "core"; 117 clock-names = "bus", "core";
118 power-domains = <&power RK3036 118 power-domains = <&power RK3036_PD_GPU>;
119 resets = <&cru SRST_GPU>; 119 resets = <&cru SRST_GPU>;
120 status = "disabled"; 120 status = "disabled";
121 }; 121 };
122 122
123 vpu: video-codec@10108000 { 123 vpu: video-codec@10108000 {
124 compatible = "rockchip,rk3036- 124 compatible = "rockchip,rk3036-vpu";
125 reg = <0x10108000 0x800>; 125 reg = <0x10108000 0x800>;
126 interrupts = <GIC_SPI 7 IRQ_TY 126 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-names = "vdpu"; 127 interrupt-names = "vdpu";
128 clocks = <&cru ACLK_VCODEC>, < 128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
129 clock-names = "aclk", "hclk"; 129 clock-names = "aclk", "hclk";
130 iommus = <&vpu_mmu>; 130 iommus = <&vpu_mmu>;
131 power-domains = <&power RK3036 131 power-domains = <&power RK3036_PD_VPU>;
132 }; 132 };
133 133
134 vpu_mmu: iommu@10108800 { 134 vpu_mmu: iommu@10108800 {
135 compatible = "rockchip,iommu"; 135 compatible = "rockchip,iommu";
136 reg = <0x10108800 0x100>; 136 reg = <0x10108800 0x100>;
137 interrupts = <GIC_SPI 55 IRQ_T 137 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cru ACLK_VCODEC>, < 138 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
139 clock-names = "aclk", "iface"; 139 clock-names = "aclk", "iface";
140 power-domains = <&power RK3036 140 power-domains = <&power RK3036_PD_VPU>;
141 #iommu-cells = <0>; 141 #iommu-cells = <0>;
142 }; 142 };
143 143
144 vop: vop@10118000 { 144 vop: vop@10118000 {
145 compatible = "rockchip,rk3036- 145 compatible = "rockchip,rk3036-vop";
146 reg = <0x10118000 0x19c>; 146 reg = <0x10118000 0x19c>;
147 interrupts = <GIC_SPI 43 IRQ_T 147 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cru ACLK_LCDC>, <&c 148 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
149 clock-names = "aclk_vop", "dcl 149 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
150 resets = <&cru SRST_LCDC1_A>, 150 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
151 reset-names = "axi", "ahb", "d 151 reset-names = "axi", "ahb", "dclk";
152 iommus = <&vop_mmu>; 152 iommus = <&vop_mmu>;
153 power-domains = <&power RK3036 153 power-domains = <&power RK3036_PD_VIO>;
154 status = "disabled"; 154 status = "disabled";
155 155
156 vop_out: port { 156 vop_out: port {
157 #address-cells = <1>; 157 #address-cells = <1>;
158 #size-cells = <0>; 158 #size-cells = <0>;
159 vop_out_hdmi: endpoint 159 vop_out_hdmi: endpoint@0 {
160 reg = <0>; 160 reg = <0>;
161 remote-endpoin 161 remote-endpoint = <&hdmi_in_vop>;
162 }; 162 };
163 }; 163 };
164 }; 164 };
165 165
166 vop_mmu: iommu@10118300 { 166 vop_mmu: iommu@10118300 {
167 compatible = "rockchip,iommu"; 167 compatible = "rockchip,iommu";
168 reg = <0x10118300 0x100>; 168 reg = <0x10118300 0x100>;
169 interrupts = <GIC_SPI 43 IRQ_T 169 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru ACLK_LCDC>, <&c 170 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
171 clock-names = "aclk", "iface"; 171 clock-names = "aclk", "iface";
172 power-domains = <&power RK3036 172 power-domains = <&power RK3036_PD_VIO>;
173 #iommu-cells = <0>; 173 #iommu-cells = <0>;
174 status = "disabled"; 174 status = "disabled";
175 }; 175 };
176 176
177 qos_gpu: qos@1012d000 { 177 qos_gpu: qos@1012d000 {
178 compatible = "rockchip,rk3036- 178 compatible = "rockchip,rk3036-qos", "syscon";
179 reg = <0x1012d000 0x20>; 179 reg = <0x1012d000 0x20>;
180 }; 180 };
181 181
182 qos_vpu: qos@1012e000 { 182 qos_vpu: qos@1012e000 {
183 compatible = "rockchip,rk3036- 183 compatible = "rockchip,rk3036-qos", "syscon";
184 reg = <0x1012e000 0x20>; 184 reg = <0x1012e000 0x20>;
185 }; 185 };
186 186
187 qos_vio: qos@1012f000 { 187 qos_vio: qos@1012f000 {
188 compatible = "rockchip,rk3036- 188 compatible = "rockchip,rk3036-qos", "syscon";
189 reg = <0x1012f000 0x20>; 189 reg = <0x1012f000 0x20>;
190 }; 190 };
191 191
192 gic: interrupt-controller@10139000 { 192 gic: interrupt-controller@10139000 {
193 compatible = "arm,gic-400"; 193 compatible = "arm,gic-400";
194 interrupt-controller; 194 interrupt-controller;
195 #interrupt-cells = <3>; 195 #interrupt-cells = <3>;
196 #address-cells = <0>; 196 #address-cells = <0>;
197 197
198 reg = <0x10139000 0x1000>, 198 reg = <0x10139000 0x1000>,
199 <0x1013a000 0x2000>, 199 <0x1013a000 0x2000>,
200 <0x1013c000 0x2000>, 200 <0x1013c000 0x2000>,
201 <0x1013e000 0x2000>; 201 <0x1013e000 0x2000>;
202 interrupts = <GIC_PPI 9 (GIC_C 202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
203 }; 203 };
204 204
205 usb_otg: usb@10180000 { 205 usb_otg: usb@10180000 {
206 compatible = "rockchip,rk3036- 206 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
207 "snps,dwc2"; 207 "snps,dwc2";
208 reg = <0x10180000 0x40000>; 208 reg = <0x10180000 0x40000>;
209 interrupts = <GIC_SPI 10 IRQ_T 209 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cru HCLK_OTG0>; 210 clocks = <&cru HCLK_OTG0>;
211 clock-names = "otg"; 211 clock-names = "otg";
212 dr_mode = "otg"; 212 dr_mode = "otg";
213 g-np-tx-fifo-size = <16>; 213 g-np-tx-fifo-size = <16>;
214 g-rx-fifo-size = <275>; 214 g-rx-fifo-size = <275>;
215 g-tx-fifo-size = <256 128 128 215 g-tx-fifo-size = <256 128 128 64 64 32>;
216 status = "disabled"; 216 status = "disabled";
217 }; 217 };
218 218
219 usb_host: usb@101c0000 { 219 usb_host: usb@101c0000 {
220 compatible = "rockchip,rk3036- 220 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
221 "snps,dwc2"; 221 "snps,dwc2";
222 reg = <0x101c0000 0x40000>; 222 reg = <0x101c0000 0x40000>;
223 interrupts = <GIC_SPI 11 IRQ_T 223 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru HCLK_OTG1>; 224 clocks = <&cru HCLK_OTG1>;
225 clock-names = "otg"; 225 clock-names = "otg";
226 dr_mode = "host"; 226 dr_mode = "host";
227 status = "disabled"; 227 status = "disabled";
228 }; 228 };
229 229
230 emac: ethernet@10200000 { 230 emac: ethernet@10200000 {
231 compatible = "rockchip,rk3036- 231 compatible = "rockchip,rk3036-emac";
232 reg = <0x10200000 0x4000>; 232 reg = <0x10200000 0x4000>;
233 interrupts = <GIC_SPI 8 IRQ_TY 233 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
234 rockchip,grf = <&grf>; 234 rockchip,grf = <&grf>;
235 clocks = <&cru HCLK_MAC>, <&cr 235 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
236 clock-names = "hclk", "macref" 236 clock-names = "hclk", "macref", "macclk";
237 /* 237 /*
238 * Fix the emac parent clock i 238 * Fix the emac parent clock is DPLL instead of APLL.
239 * since that will cause some 239 * since that will cause some unstable things if the cpufreq
240 * is working. (e.g: the accur 240 * is working. (e.g: the accurate 50MHz what mac_ref need)
241 */ 241 */
242 assigned-clocks = <&cru SCLK_M 242 assigned-clocks = <&cru SCLK_MACPLL>;
243 assigned-clock-parents = <&cru 243 assigned-clock-parents = <&cru PLL_DPLL>;
244 max-speed = <100>; 244 max-speed = <100>;
245 phy-mode = "rmii"; 245 phy-mode = "rmii";
246 status = "disabled"; 246 status = "disabled";
247 }; 247 };
248 248
249 sdmmc: mmc@10214000 { 249 sdmmc: mmc@10214000 {
250 compatible = "rockchip,rk3036- 250 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
251 reg = <0x10214000 0x4000>; 251 reg = <0x10214000 0x4000>;
252 clock-frequency = <37500000>; 252 clock-frequency = <37500000>;
253 max-frequency = <37500000>; 253 max-frequency = <37500000>;
254 clocks = <&cru HCLK_SDMMC>, <& 254 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
255 clock-names = "biu", "ciu"; 255 clock-names = "biu", "ciu";
256 fifo-depth = <0x100>; 256 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 14 IRQ_T 257 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
258 resets = <&cru SRST_MMC0>; 258 resets = <&cru SRST_MMC0>;
259 reset-names = "reset"; 259 reset-names = "reset";
260 status = "disabled"; 260 status = "disabled";
261 }; 261 };
262 262
263 sdio: mmc@10218000 { 263 sdio: mmc@10218000 {
264 compatible = "rockchip,rk3036- 264 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
265 reg = <0x10218000 0x4000>; 265 reg = <0x10218000 0x4000>;
266 max-frequency = <37500000>; 266 max-frequency = <37500000>;
267 clocks = <&cru HCLK_SDIO>, <&c 267 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
268 <&cru SCLK_SDIO_DRV>, 268 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
269 clock-names = "biu", "ciu", "c 269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 fifo-depth = <0x100>; 270 fifo-depth = <0x100>;
271 interrupts = <GIC_SPI 15 IRQ_T 271 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
272 resets = <&cru SRST_SDIO>; 272 resets = <&cru SRST_SDIO>;
273 reset-names = "reset"; 273 reset-names = "reset";
274 status = "disabled"; 274 status = "disabled";
275 }; 275 };
276 276
277 emmc: mmc@1021c000 { 277 emmc: mmc@1021c000 {
278 compatible = "rockchip,rk3036- 278 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
279 reg = <0x1021c000 0x4000>; 279 reg = <0x1021c000 0x4000>;
280 interrupts = <GIC_SPI 16 IRQ_T 280 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
281 bus-width = <8>; 281 bus-width = <8>;
282 cap-mmc-highspeed; 282 cap-mmc-highspeed;
283 clock-frequency = <37500000>; 283 clock-frequency = <37500000>;
284 max-frequency = <37500000>; 284 max-frequency = <37500000>;
285 clocks = <&cru HCLK_EMMC>, <&c 285 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
286 <&cru SCLK_EMMC_DRV>, 286 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
287 clock-names = "biu", "ciu", "c 287 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
288 disable-wp; 288 disable-wp;
289 dmas = <&pdma 12>; 289 dmas = <&pdma 12>;
290 dma-names = "rx-tx"; 290 dma-names = "rx-tx";
291 fifo-depth = <0x100>; 291 fifo-depth = <0x100>;
292 mmc-ddr-1_8v; 292 mmc-ddr-1_8v;
293 non-removable; 293 non-removable;
294 pinctrl-names = "default"; 294 pinctrl-names = "default";
295 pinctrl-0 = <&emmc_clk &emmc_c 295 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
296 resets = <&cru SRST_EMMC>; 296 resets = <&cru SRST_EMMC>;
297 reset-names = "reset"; 297 reset-names = "reset";
298 status = "disabled"; 298 status = "disabled";
299 }; 299 };
300 300
301 i2s: i2s@10220000 { 301 i2s: i2s@10220000 {
302 compatible = "rockchip,rk3036- 302 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
303 reg = <0x10220000 0x4000>; 303 reg = <0x10220000 0x4000>;
304 interrupts = <GIC_SPI 51 IRQ_T 304 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
305 clock-names = "i2s_clk", "i2s_ 305 clock-names = "i2s_clk", "i2s_hclk";
306 clocks = <&cru SCLK_I2S>, <&cr 306 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
307 dmas = <&pdma 0>, <&pdma 1>; 307 dmas = <&pdma 0>, <&pdma 1>;
308 dma-names = "tx", "rx"; 308 dma-names = "tx", "rx";
309 pinctrl-names = "default"; 309 pinctrl-names = "default";
310 pinctrl-0 = <&i2s_bus>; 310 pinctrl-0 = <&i2s_bus>;
311 #sound-dai-cells = <0>; 311 #sound-dai-cells = <0>;
312 status = "disabled"; 312 status = "disabled";
313 }; 313 };
314 314
315 nfc: nand-controller@10500000 { 315 nfc: nand-controller@10500000 {
316 compatible = "rockchip,rk3036- 316 compatible = "rockchip,rk3036-nfc",
317 "rockchip,rk2928- 317 "rockchip,rk2928-nfc";
318 reg = <0x10500000 0x4000>; 318 reg = <0x10500000 0x4000>;
319 interrupts = <GIC_SPI 18 IRQ_T 319 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&cru HCLK_NANDC>, <& 320 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
321 clock-names = "ahb", "nfc"; 321 clock-names = "ahb", "nfc";
322 assigned-clocks = <&cru SCLK_N 322 assigned-clocks = <&cru SCLK_NANDC>;
323 assigned-clock-rates = <150000 323 assigned-clock-rates = <150000000>;
324 pinctrl-0 = <&flash_ale &flash 324 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
325 &flash_rdn &flash 325 &flash_rdn &flash_rdy &flash_wrn>;
326 pinctrl-names = "default"; 326 pinctrl-names = "default";
327 status = "disabled"; 327 status = "disabled";
328 }; 328 };
329 329
330 cru: clock-controller@20000000 { 330 cru: clock-controller@20000000 {
331 compatible = "rockchip,rk3036- 331 compatible = "rockchip,rk3036-cru";
332 reg = <0x20000000 0x1000>; 332 reg = <0x20000000 0x1000>;
333 clocks = <&xin24m>; 333 clocks = <&xin24m>;
334 clock-names = "xin24m"; 334 clock-names = "xin24m";
335 rockchip,grf = <&grf>; 335 rockchip,grf = <&grf>;
336 #clock-cells = <1>; 336 #clock-cells = <1>;
337 #reset-cells = <1>; 337 #reset-cells = <1>;
338 assigned-clocks = <&cru PLL_GP 338 assigned-clocks = <&cru PLL_GPLL>;
339 assigned-clock-rates = <594000 339 assigned-clock-rates = <594000000>;
340 }; 340 };
341 341
342 grf: syscon@20008000 { 342 grf: syscon@20008000 {
343 compatible = "rockchip,rk3036- 343 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
344 reg = <0x20008000 0x1000>; 344 reg = <0x20008000 0x1000>;
345 345
346 power: power-controller { 346 power: power-controller {
347 compatible = "rockchip 347 compatible = "rockchip,rk3036-power-controller";
348 #power-domain-cells = 348 #power-domain-cells = <1>;
349 #address-cells = <1>; 349 #address-cells = <1>;
350 #size-cells = <0>; 350 #size-cells = <0>;
351 351
352 power-domain@RK3036_PD 352 power-domain@RK3036_PD_VIO {
353 reg = <RK3036_ 353 reg = <RK3036_PD_VIO>;
354 clocks = <&cru 354 clocks = <&cru ACLK_LCDC>,
355 <&cru 355 <&cru HCLK_LCDC>,
356 <&cru 356 <&cru SCLK_LCDC>;
357 pm_qos = <&qos 357 pm_qos = <&qos_vio>;
358 #power-domain- 358 #power-domain-cells = <0>;
359 }; 359 };
360 360
361 power-domain@RK3036_PD 361 power-domain@RK3036_PD_VPU {
362 reg = <RK3036_ 362 reg = <RK3036_PD_VPU>;
363 clocks = <&cru 363 clocks = <&cru ACLK_VCODEC>,
364 <&cru 364 <&cru HCLK_VCODEC>;
365 pm_qos = <&qos 365 pm_qos = <&qos_vpu>;
366 #power-domain- 366 #power-domain-cells = <0>;
367 }; 367 };
368 368
369 power-domain@RK3036_PD 369 power-domain@RK3036_PD_GPU {
370 reg = <RK3036_ 370 reg = <RK3036_PD_GPU>;
371 clocks = <&cru 371 clocks = <&cru SCLK_GPU>;
372 pm_qos = <&qos 372 pm_qos = <&qos_gpu>;
373 #power-domain- 373 #power-domain-cells = <0>;
374 }; 374 };
375 }; 375 };
376 376
377 reboot-mode { 377 reboot-mode {
378 compatible = "syscon-r 378 compatible = "syscon-reboot-mode";
379 offset = <0x1d8>; 379 offset = <0x1d8>;
380 mode-normal = <BOOT_NO 380 mode-normal = <BOOT_NORMAL>;
381 mode-recovery = <BOOT_ 381 mode-recovery = <BOOT_RECOVERY>;
382 mode-bootloader = <BOO 382 mode-bootloader = <BOOT_FASTBOOT>;
383 mode-loader = <BOOT_BL 383 mode-loader = <BOOT_BL_DOWNLOAD>;
384 }; 384 };
385 }; 385 };
386 386
387 acodec: audio-codec@20030000 { 387 acodec: audio-codec@20030000 {
388 compatible = "rockchip,rk3036- 388 compatible = "rockchip,rk3036-codec";
389 reg = <0x20030000 0x4000>; 389 reg = <0x20030000 0x4000>;
390 clock-names = "acodec_pclk"; 390 clock-names = "acodec_pclk";
391 clocks = <&cru PCLK_ACODEC>; 391 clocks = <&cru PCLK_ACODEC>;
392 rockchip,grf = <&grf>; 392 rockchip,grf = <&grf>;
393 #sound-dai-cells = <0>; 393 #sound-dai-cells = <0>;
394 status = "disabled"; 394 status = "disabled";
395 }; 395 };
396 396
397 hdmi: hdmi@20034000 { 397 hdmi: hdmi@20034000 {
398 compatible = "rockchip,rk3036- 398 compatible = "rockchip,rk3036-inno-hdmi";
399 reg = <0x20034000 0x4000>; 399 reg = <0x20034000 0x4000>;
400 interrupts = <GIC_SPI 45 IRQ_T 400 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru PCLK_HDMI>; 401 clocks = <&cru PCLK_HDMI>;
402 clock-names = "pclk"; 402 clock-names = "pclk";
403 pinctrl-names = "default"; 403 pinctrl-names = "default";
404 pinctrl-0 = <&hdmi_ctl>; 404 pinctrl-0 = <&hdmi_ctl>;
405 #sound-dai-cells = <0>; 405 #sound-dai-cells = <0>;
406 status = "disabled"; 406 status = "disabled";
407 407
408 ports { 408 ports {
409 #address-cells = <1>; 409 #address-cells = <1>;
410 #size-cells = <0>; 410 #size-cells = <0>;
411 411
412 hdmi_in: port@0 { 412 hdmi_in: port@0 {
413 reg = <0>; 413 reg = <0>;
414 414
415 hdmi_in_vop: e 415 hdmi_in_vop: endpoint {
416 remote 416 remote-endpoint = <&vop_out_hdmi>;
417 }; 417 };
418 }; 418 };
419 419
420 hdmi_out: port@1 { 420 hdmi_out: port@1 {
421 reg = <1>; 421 reg = <1>;
422 }; 422 };
423 }; 423 };
424 }; 424 };
425 425
426 timer: timer@20044000 { 426 timer: timer@20044000 {
427 compatible = "rockchip,rk3036- 427 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
428 reg = <0x20044000 0x20>; 428 reg = <0x20044000 0x20>;
429 interrupts = <GIC_SPI 28 IRQ_T 429 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cru PCLK_TIMER>, <& 430 clocks = <&cru PCLK_TIMER>, <&xin24m>;
431 clock-names = "pclk", "timer"; 431 clock-names = "pclk", "timer";
432 }; 432 };
433 433
434 pwm0: pwm@20050000 { 434 pwm0: pwm@20050000 {
435 compatible = "rockchip,rk3036- 435 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
436 reg = <0x20050000 0x10>; 436 reg = <0x20050000 0x10>;
437 #pwm-cells = <3>; 437 #pwm-cells = <3>;
438 clocks = <&cru PCLK_PWM>; 438 clocks = <&cru PCLK_PWM>;
439 pinctrl-names = "default"; 439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm0_pin>; 440 pinctrl-0 = <&pwm0_pin>;
441 status = "disabled"; 441 status = "disabled";
442 }; 442 };
443 443
444 pwm1: pwm@20050010 { 444 pwm1: pwm@20050010 {
445 compatible = "rockchip,rk3036- 445 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
446 reg = <0x20050010 0x10>; 446 reg = <0x20050010 0x10>;
447 #pwm-cells = <3>; 447 #pwm-cells = <3>;
448 clocks = <&cru PCLK_PWM>; 448 clocks = <&cru PCLK_PWM>;
449 pinctrl-names = "default"; 449 pinctrl-names = "default";
450 pinctrl-0 = <&pwm1_pin>; 450 pinctrl-0 = <&pwm1_pin>;
451 status = "disabled"; 451 status = "disabled";
452 }; 452 };
453 453
454 pwm2: pwm@20050020 { 454 pwm2: pwm@20050020 {
455 compatible = "rockchip,rk3036- 455 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
456 reg = <0x20050020 0x10>; 456 reg = <0x20050020 0x10>;
457 #pwm-cells = <3>; 457 #pwm-cells = <3>;
458 clocks = <&cru PCLK_PWM>; 458 clocks = <&cru PCLK_PWM>;
459 pinctrl-names = "default"; 459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>; 460 pinctrl-0 = <&pwm2_pin>;
461 status = "disabled"; 461 status = "disabled";
462 }; 462 };
463 463
464 pwm3: pwm@20050030 { 464 pwm3: pwm@20050030 {
465 compatible = "rockchip,rk3036- 465 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
466 reg = <0x20050030 0x10>; 466 reg = <0x20050030 0x10>;
467 #pwm-cells = <2>; 467 #pwm-cells = <2>;
468 clocks = <&cru PCLK_PWM>; 468 clocks = <&cru PCLK_PWM>;
469 pinctrl-names = "default"; 469 pinctrl-names = "default";
470 pinctrl-0 = <&pwm3_pin>; 470 pinctrl-0 = <&pwm3_pin>;
471 status = "disabled"; 471 status = "disabled";
472 }; 472 };
473 473
474 i2c1: i2c@20056000 { 474 i2c1: i2c@20056000 {
475 compatible = "rockchip,rk3036- 475 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
476 reg = <0x20056000 0x1000>; 476 reg = <0x20056000 0x1000>;
477 interrupts = <GIC_SPI 25 IRQ_T 477 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>; 478 #address-cells = <1>;
479 #size-cells = <0>; 479 #size-cells = <0>;
480 clock-names = "i2c"; 480 clock-names = "i2c";
481 clocks = <&cru PCLK_I2C1>; 481 clocks = <&cru PCLK_I2C1>;
482 pinctrl-names = "default"; 482 pinctrl-names = "default";
483 pinctrl-0 = <&i2c1_xfer>; 483 pinctrl-0 = <&i2c1_xfer>;
484 status = "disabled"; 484 status = "disabled";
485 }; 485 };
486 486
487 i2c2: i2c@2005a000 { 487 i2c2: i2c@2005a000 {
488 compatible = "rockchip,rk3036- 488 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
489 reg = <0x2005a000 0x1000>; 489 reg = <0x2005a000 0x1000>;
490 interrupts = <GIC_SPI 26 IRQ_T 490 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>; 491 #address-cells = <1>;
492 #size-cells = <0>; 492 #size-cells = <0>;
493 clock-names = "i2c"; 493 clock-names = "i2c";
494 clocks = <&cru PCLK_I2C2>; 494 clocks = <&cru PCLK_I2C2>;
495 pinctrl-names = "default"; 495 pinctrl-names = "default";
496 pinctrl-0 = <&i2c2_xfer>; 496 pinctrl-0 = <&i2c2_xfer>;
497 status = "disabled"; 497 status = "disabled";
498 }; 498 };
499 499
500 uart0: serial@20060000 { 500 uart0: serial@20060000 {
501 compatible = "rockchip,rk3036- 501 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
502 reg = <0x20060000 0x100>; 502 reg = <0x20060000 0x100>;
503 interrupts = <GIC_SPI 20 IRQ_T 503 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
504 reg-shift = <2>; 504 reg-shift = <2>;
505 reg-io-width = <4>; 505 reg-io-width = <4>;
506 clock-frequency = <24000000>; 506 clock-frequency = <24000000>;
507 clocks = <&cru SCLK_UART0>, <& 507 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
508 clock-names = "baudclk", "apb_ 508 clock-names = "baudclk", "apb_pclk";
509 pinctrl-names = "default"; 509 pinctrl-names = "default";
510 pinctrl-0 = <&uart0_xfer &uart 510 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
511 status = "disabled"; 511 status = "disabled";
512 }; 512 };
513 513
514 uart1: serial@20064000 { 514 uart1: serial@20064000 {
515 compatible = "rockchip,rk3036- 515 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
516 reg = <0x20064000 0x100>; 516 reg = <0x20064000 0x100>;
517 interrupts = <GIC_SPI 21 IRQ_T 517 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
518 reg-shift = <2>; 518 reg-shift = <2>;
519 reg-io-width = <4>; 519 reg-io-width = <4>;
520 clock-frequency = <24000000>; 520 clock-frequency = <24000000>;
521 clocks = <&cru SCLK_UART1>, <& 521 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
522 clock-names = "baudclk", "apb_ 522 clock-names = "baudclk", "apb_pclk";
523 pinctrl-names = "default"; 523 pinctrl-names = "default";
524 pinctrl-0 = <&uart1_xfer>; 524 pinctrl-0 = <&uart1_xfer>;
525 status = "disabled"; 525 status = "disabled";
526 }; 526 };
527 527
528 uart2: serial@20068000 { 528 uart2: serial@20068000 {
529 compatible = "rockchip,rk3036- 529 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
530 reg = <0x20068000 0x100>; 530 reg = <0x20068000 0x100>;
531 interrupts = <GIC_SPI 22 IRQ_T 531 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
532 reg-shift = <2>; 532 reg-shift = <2>;
533 reg-io-width = <4>; 533 reg-io-width = <4>;
534 clock-frequency = <24000000>; 534 clock-frequency = <24000000>;
535 clocks = <&cru SCLK_UART2>, <& 535 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
536 clock-names = "baudclk", "apb_ 536 clock-names = "baudclk", "apb_pclk";
537 pinctrl-names = "default"; 537 pinctrl-names = "default";
538 pinctrl-0 = <&uart2_xfer>; 538 pinctrl-0 = <&uart2_xfer>;
539 status = "disabled"; 539 status = "disabled";
540 }; 540 };
541 541
542 i2c0: i2c@20072000 { 542 i2c0: i2c@20072000 {
543 compatible = "rockchip,rk3036- 543 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
544 reg = <0x20072000 0x1000>; 544 reg = <0x20072000 0x1000>;
545 interrupts = <GIC_SPI 24 IRQ_T 545 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>; 546 #address-cells = <1>;
547 #size-cells = <0>; 547 #size-cells = <0>;
548 clock-names = "i2c"; 548 clock-names = "i2c";
549 clocks = <&cru PCLK_I2C0>; 549 clocks = <&cru PCLK_I2C0>;
550 pinctrl-names = "default"; 550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c0_xfer>; 551 pinctrl-0 = <&i2c0_xfer>;
552 status = "disabled"; 552 status = "disabled";
553 }; 553 };
554 554
555 spi: spi@20074000 { 555 spi: spi@20074000 {
556 compatible = "rockchip,rk3036- 556 compatible = "rockchip,rk3036-spi";
557 reg = <0x20074000 0x1000>; 557 reg = <0x20074000 0x1000>;
558 interrupts = <GIC_SPI 23 IRQ_T 558 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cru SCLK_SPI>, <&cr 559 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
560 clock-names = "spiclk", "apb_p 560 clock-names = "spiclk", "apb_pclk";
561 dmas = <&pdma 8>, <&pdma 9>; 561 dmas = <&pdma 8>, <&pdma 9>;
562 dma-names = "tx", "rx"; 562 dma-names = "tx", "rx";
563 pinctrl-names = "default"; 563 pinctrl-names = "default";
564 pinctrl-0 = <&spi_txd &spi_rxd 564 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
565 #address-cells = <1>; 565 #address-cells = <1>;
566 #size-cells = <0>; 566 #size-cells = <0>;
567 status = "disabled"; 567 status = "disabled";
568 }; 568 };
569 569
570 pdma: dma-controller@20078000 { 570 pdma: dma-controller@20078000 {
571 compatible = "arm,pl330", "arm 571 compatible = "arm,pl330", "arm,primecell";
572 reg = <0x20078000 0x4000>; 572 reg = <0x20078000 0x4000>;
573 interrupts = <GIC_SPI 0 IRQ_TY 573 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 1 IRQ_TY 574 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
575 #dma-cells = <1>; 575 #dma-cells = <1>;
576 arm,pl330-broken-no-flushp; 576 arm,pl330-broken-no-flushp;
577 arm,pl330-periph-burst; 577 arm,pl330-periph-burst;
578 clocks = <&cru ACLK_DMAC2>; 578 clocks = <&cru ACLK_DMAC2>;
579 clock-names = "apb_pclk"; 579 clock-names = "apb_pclk";
580 }; 580 };
581 581
582 pinctrl: pinctrl { 582 pinctrl: pinctrl {
583 compatible = "rockchip,rk3036- 583 compatible = "rockchip,rk3036-pinctrl";
584 rockchip,grf = <&grf>; 584 rockchip,grf = <&grf>;
585 #address-cells = <1>; 585 #address-cells = <1>;
586 #size-cells = <1>; 586 #size-cells = <1>;
587 ranges; 587 ranges;
588 588
589 gpio0: gpio@2007c000 { 589 gpio0: gpio@2007c000 {
590 compatible = "rockchip 590 compatible = "rockchip,gpio-bank";
591 reg = <0x2007c000 0x10 591 reg = <0x2007c000 0x100>;
592 interrupts = <GIC_SPI 592 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cru PCLK_GP 593 clocks = <&cru PCLK_GPIO0>;
594 594
595 gpio-controller; 595 gpio-controller;
596 #gpio-cells = <2>; 596 #gpio-cells = <2>;
597 597
598 interrupt-controller; 598 interrupt-controller;
599 #interrupt-cells = <2> 599 #interrupt-cells = <2>;
600 }; 600 };
601 601
602 gpio1: gpio@20080000 { 602 gpio1: gpio@20080000 {
603 compatible = "rockchip 603 compatible = "rockchip,gpio-bank";
604 reg = <0x20080000 0x10 604 reg = <0x20080000 0x100>;
605 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cru PCLK_GP 606 clocks = <&cru PCLK_GPIO1>;
607 607
608 gpio-controller; 608 gpio-controller;
609 #gpio-cells = <2>; 609 #gpio-cells = <2>;
610 610
611 interrupt-controller; 611 interrupt-controller;
612 #interrupt-cells = <2> 612 #interrupt-cells = <2>;
613 }; 613 };
614 614
615 gpio2: gpio@20084000 { 615 gpio2: gpio@20084000 {
616 compatible = "rockchip 616 compatible = "rockchip,gpio-bank";
617 reg = <0x20084000 0x10 617 reg = <0x20084000 0x100>;
618 interrupts = <GIC_SPI 618 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru PCLK_GP 619 clocks = <&cru PCLK_GPIO2>;
620 620
621 gpio-controller; 621 gpio-controller;
622 #gpio-cells = <2>; 622 #gpio-cells = <2>;
623 623
624 interrupt-controller; 624 interrupt-controller;
625 #interrupt-cells = <2> 625 #interrupt-cells = <2>;
626 }; 626 };
627 627
628 pcfg_pull_default: pcfg-pull-d 628 pcfg_pull_default: pcfg-pull-default {
629 bias-pull-pin-default; 629 bias-pull-pin-default;
630 }; 630 };
631 631
632 pcfg_pull_none: pcfg-pull-none 632 pcfg_pull_none: pcfg-pull-none {
633 bias-disable; 633 bias-disable;
634 }; 634 };
635 635
636 pwm0 { 636 pwm0 {
637 pwm0_pin: pwm0-pin { 637 pwm0_pin: pwm0-pin {
638 rockchip,pins 638 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
639 }; 639 };
640 }; 640 };
641 641
642 pwm1 { 642 pwm1 {
643 pwm1_pin: pwm1-pin { 643 pwm1_pin: pwm1-pin {
644 rockchip,pins 644 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
645 }; 645 };
646 }; 646 };
647 647
648 pwm2 { 648 pwm2 {
649 pwm2_pin: pwm2-pin { 649 pwm2_pin: pwm2-pin {
650 rockchip,pins 650 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
651 }; 651 };
652 }; 652 };
653 653
654 pwm3 { 654 pwm3 {
655 pwm3_pin: pwm3-pin { 655 pwm3_pin: pwm3-pin {
656 rockchip,pins 656 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
657 }; 657 };
658 }; 658 };
659 659
660 sdmmc { 660 sdmmc {
661 sdmmc_clk: sdmmc-clk { 661 sdmmc_clk: sdmmc-clk {
662 rockchip,pins 662 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
663 }; 663 };
664 664
665 sdmmc_cmd: sdmmc-cmd { 665 sdmmc_cmd: sdmmc-cmd {
666 rockchip,pins 666 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
667 }; 667 };
668 668
669 sdmmc_cd: sdmmc-cd { 669 sdmmc_cd: sdmmc-cd {
670 rockchip,pins 670 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
671 }; 671 };
672 672
673 sdmmc_bus1: sdmmc-bus1 673 sdmmc_bus1: sdmmc-bus1 {
674 rockchip,pins 674 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
675 }; 675 };
676 676
677 sdmmc_bus4: sdmmc-bus4 677 sdmmc_bus4: sdmmc-bus4 {
678 rockchip,pins 678 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
679 679 <1 RK_PC3 1 &pcfg_pull_default>,
680 680 <1 RK_PC4 1 &pcfg_pull_default>,
681 681 <1 RK_PC5 1 &pcfg_pull_default>;
682 }; 682 };
683 }; 683 };
684 684
685 sdio { 685 sdio {
686 sdio_bus1: sdio-bus1 { 686 sdio_bus1: sdio-bus1 {
687 rockchip,pins 687 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
688 }; 688 };
689 689
690 sdio_bus4: sdio-bus4 { 690 sdio_bus4: sdio-bus4 {
691 rockchip,pins 691 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
692 692 <0 RK_PB4 1 &pcfg_pull_default>,
693 693 <0 RK_PB5 1 &pcfg_pull_default>,
694 694 <0 RK_PB6 1 &pcfg_pull_default>;
695 }; 695 };
696 696
697 sdio_cmd: sdio-cmd { 697 sdio_cmd: sdio-cmd {
698 rockchip,pins 698 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
699 }; 699 };
700 700
701 sdio_clk: sdio-clk { 701 sdio_clk: sdio-clk {
702 rockchip,pins 702 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
703 }; 703 };
704 }; 704 };
705 705
706 emmc { 706 emmc {
707 /* 707 /*
708 * We run eMMC at max 708 * We run eMMC at max speed; bump up drive strength.
709 * We also have extern 709 * We also have external pulls, so disable the internal ones.
710 */ 710 */
711 emmc_clk: emmc-clk { 711 emmc_clk: emmc-clk {
712 rockchip,pins 712 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
713 }; 713 };
714 714
715 emmc_cmd: emmc-cmd { 715 emmc_cmd: emmc-cmd {
716 rockchip,pins 716 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
717 }; 717 };
718 718
719 emmc_bus8: emmc-bus8 { 719 emmc_bus8: emmc-bus8 {
720 rockchip,pins 720 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
721 721 <1 RK_PD1 2 &pcfg_pull_default>,
722 722 <1 RK_PD2 2 &pcfg_pull_default>,
723 723 <1 RK_PD3 2 &pcfg_pull_default>,
724 724 <1 RK_PD4 2 &pcfg_pull_default>,
725 725 <1 RK_PD5 2 &pcfg_pull_default>,
726 726 <1 RK_PD6 2 &pcfg_pull_default>,
727 727 <1 RK_PD7 2 &pcfg_pull_default>;
728 }; 728 };
729 }; 729 };
730 730
731 nfc { 731 nfc {
732 flash_ale: flash-ale { 732 flash_ale: flash-ale {
733 rockchip,pins 733 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
734 }; 734 };
735 735
736 flash_bus8: flash-bus8 736 flash_bus8: flash-bus8 {
737 rockchip,pins 737 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
738 738 <1 RK_PD1 1 &pcfg_pull_default>,
739 739 <1 RK_PD2 1 &pcfg_pull_default>,
740 740 <1 RK_PD3 1 &pcfg_pull_default>,
741 741 <1 RK_PD4 1 &pcfg_pull_default>,
742 742 <1 RK_PD5 1 &pcfg_pull_default>,
743 743 <1 RK_PD6 1 &pcfg_pull_default>,
744 744 <1 RK_PD7 1 &pcfg_pull_default>;
745 }; 745 };
746 746
747 flash_cle: flash-cle { 747 flash_cle: flash-cle {
748 rockchip,pins 748 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
749 }; 749 };
750 750
751 flash_csn0: flash-csn0 751 flash_csn0: flash-csn0 {
752 rockchip,pins 752 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
753 }; 753 };
754 754
755 flash_rdn: flash-rdn { 755 flash_rdn: flash-rdn {
756 rockchip,pins 756 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
757 }; 757 };
758 758
759 flash_rdy: flash-rdy { 759 flash_rdy: flash-rdy {
760 rockchip,pins 760 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
761 }; 761 };
762 762
763 flash_wrn: flash-wrn { 763 flash_wrn: flash-wrn {
764 rockchip,pins 764 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
765 }; 765 };
766 }; 766 };
767 767
768 emac { 768 emac {
769 emac_xfer: emac-xfer { 769 emac_xfer: emac-xfer {
770 rockchip,pins 770 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
771 771 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
772 772 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
773 773 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
774 774 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
775 775 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
776 776 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
777 777 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
778 }; 778 };
779 779
780 emac_mdio: emac-mdio { 780 emac_mdio: emac-mdio {
781 rockchip,pins 781 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
782 782 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
783 }; 783 };
784 }; 784 };
785 785
786 i2c0 { 786 i2c0 {
787 i2c0_xfer: i2c0-xfer { 787 i2c0_xfer: i2c0-xfer {
788 rockchip,pins 788 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
789 789 <0 RK_PA1 1 &pcfg_pull_none>;
790 }; 790 };
791 }; 791 };
792 792
793 i2c1 { 793 i2c1 {
794 i2c1_xfer: i2c1-xfer { 794 i2c1_xfer: i2c1-xfer {
795 rockchip,pins 795 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
796 796 <0 RK_PA3 1 &pcfg_pull_none>;
797 }; 797 };
798 }; 798 };
799 799
800 i2c2 { 800 i2c2 {
801 i2c2_xfer: i2c2-xfer { 801 i2c2_xfer: i2c2-xfer {
802 rockchip,pins 802 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
803 803 <2 RK_PC5 1 &pcfg_pull_none>;
804 }; 804 };
805 }; 805 };
806 806
807 i2s { 807 i2s {
808 i2s_bus: i2s-bus { 808 i2s_bus: i2s-bus {
809 rockchip,pins 809 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
810 810 <1 RK_PA1 1 &pcfg_pull_default>,
811 811 <1 RK_PA2 1 &pcfg_pull_default>,
812 812 <1 RK_PA3 1 &pcfg_pull_default>,
813 813 <1 RK_PA4 1 &pcfg_pull_default>,
814 814 <1 RK_PA5 1 &pcfg_pull_default>;
815 }; 815 };
816 }; 816 };
817 817
818 hdmi { 818 hdmi {
819 hdmi_ctl: hdmi-ctl { 819 hdmi_ctl: hdmi-ctl {
820 rockchip,pins 820 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
821 821 <1 RK_PB1 1 &pcfg_pull_none>,
822 822 <1 RK_PB2 1 &pcfg_pull_none>,
823 823 <1 RK_PB3 1 &pcfg_pull_none>;
824 }; 824 };
825 }; 825 };
826 826
827 uart0 { 827 uart0 {
828 uart0_xfer: uart0-xfer 828 uart0_xfer: uart0-xfer {
829 rockchip,pins 829 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
830 830 <0 RK_PC1 1 &pcfg_pull_none>;
831 }; 831 };
832 832
833 uart0_cts: uart0-cts { 833 uart0_cts: uart0-cts {
834 rockchip,pins 834 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
835 }; 835 };
836 836
837 uart0_rts: uart0-rts { 837 uart0_rts: uart0-rts {
838 rockchip,pins 838 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
839 }; 839 };
840 }; 840 };
841 841
842 uart1 { 842 uart1 {
843 uart1_xfer: uart1-xfer 843 uart1_xfer: uart1-xfer {
844 rockchip,pins 844 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
845 845 <2 RK_PC7 1 &pcfg_pull_none>;
846 }; 846 };
847 /* no rts / cts for ua 847 /* no rts / cts for uart1 */
848 }; 848 };
849 849
850 uart2 { 850 uart2 {
851 uart2_xfer: uart2-xfer 851 uart2_xfer: uart2-xfer {
852 rockchip,pins 852 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
853 853 <1 RK_PC3 2 &pcfg_pull_none>;
854 }; 854 };
855 /* no rts / cts for ua 855 /* no rts / cts for uart2 */
856 }; 856 };
857 857
858 spi-pins { 858 spi-pins {
859 spi_txd:spi-txd { 859 spi_txd:spi-txd {
860 rockchip,pins 860 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
861 }; 861 };
862 862
863 spi_rxd:spi-rxd { 863 spi_rxd:spi-rxd {
864 rockchip,pins 864 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
865 }; 865 };
866 866
867 spi_clk:spi-clk { 867 spi_clk:spi-clk {
868 rockchip,pins 868 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
869 }; 869 };
870 870
871 spi_cs0:spi-cs0 { 871 spi_cs0:spi-cs0 {
872 rockchip,pins 872 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
873 873
874 }; 874 };
875 875
876 spi_cs1:spi-cs1 { 876 spi_cs1:spi-cs1 {
877 rockchip,pins 877 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
878 878
879 }; 879 };
880 }; 880 };
881 }; 881 };
882 }; 882 };
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