1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co. 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3128-cru.h> 6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h> 11 #include <dt-bindings/power/rk3128-power.h>
12 12
13 / { 13 / {
14 compatible = "rockchip,rk3128"; 14 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 18
19 aliases { 19 aliases {
20 gpio0 = &gpio0; 20 gpio0 = &gpio0;
21 gpio1 = &gpio1; 21 gpio1 = &gpio1;
22 gpio2 = &gpio2; 22 gpio2 = &gpio2;
23 gpio3 = &gpio3; 23 gpio3 = &gpio3;
24 i2c0 = &i2c0; 24 i2c0 = &i2c0;
25 i2c1 = &i2c1; 25 i2c1 = &i2c1;
26 i2c2 = &i2c2; 26 i2c2 = &i2c2;
27 i2c3 = &i2c3; 27 i2c3 = &i2c3;
28 serial0 = &uart0; 28 serial0 = &uart0;
29 serial1 = &uart1; 29 serial1 = &uart1;
30 serial2 = &uart2; 30 serial2 = &uart2;
31 }; 31 };
32 32
33 arm-pmu { 33 arm-pmu {
34 compatible = "arm,cortex-a7-pm 34 compatible = "arm,cortex-a7-pmu";
35 interrupts = <GIC_SPI 76 IRQ_T 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 77 IRQ_T 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 78 IRQ_T 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 79 IRQ_T 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
39 interrupt-affinity = <&cpu0>, 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <1>; 43 #address-cells = <1>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 enable-method = "rockchip,rk30 45 enable-method = "rockchip,rk3036-smp";
46 46
47 cpu0: cpu@f00 { 47 cpu0: cpu@f00 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "arm,cort 49 compatible = "arm,cortex-a7";
50 reg = <0xf00>; 50 reg = <0xf00>;
51 clock-latency = <40000 51 clock-latency = <40000>;
52 clocks = <&cru ARMCLK> 52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CO 53 resets = <&cru SRST_CORE0>;
54 operating-points-v2 = 54 operating-points-v2 = <&cpu_opp_table>;
55 #cooling-cells = <2>; 55 #cooling-cells = <2>; /* min followed by max */
56 }; 56 };
57 57
58 cpu1: cpu@f01 { 58 cpu1: cpu@f01 {
59 device_type = "cpu"; 59 device_type = "cpu";
60 compatible = "arm,cort 60 compatible = "arm,cortex-a7";
61 reg = <0xf01>; 61 reg = <0xf01>;
62 resets = <&cru SRST_CO 62 resets = <&cru SRST_CORE1>;
63 operating-points-v2 = 63 operating-points-v2 = <&cpu_opp_table>;
64 }; 64 };
65 65
66 cpu2: cpu@f02 { 66 cpu2: cpu@f02 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cort 68 compatible = "arm,cortex-a7";
69 reg = <0xf02>; 69 reg = <0xf02>;
70 resets = <&cru SRST_CO 70 resets = <&cru SRST_CORE2>;
71 operating-points-v2 = 71 operating-points-v2 = <&cpu_opp_table>;
72 }; 72 };
73 73
74 cpu3: cpu@f03 { 74 cpu3: cpu@f03 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 compatible = "arm,cort 76 compatible = "arm,cortex-a7";
77 reg = <0xf03>; 77 reg = <0xf03>;
78 resets = <&cru SRST_CO 78 resets = <&cru SRST_CORE3>;
79 operating-points-v2 = 79 operating-points-v2 = <&cpu_opp_table>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu_opp_table: opp-table-0 { 83 cpu_opp_table: opp-table-0 {
84 compatible = "operating-points 84 compatible = "operating-points-v2";
85 opp-shared; 85 opp-shared;
86 86
87 opp-216000000 { 87 opp-216000000 {
88 opp-hz = /bits/ 64 <21 88 opp-hz = /bits/ 64 <216000000>;
89 opp-microvolt = <95000 89 opp-microvolt = <950000 950000 1325000>;
90 }; 90 };
91 opp-408000000 { 91 opp-408000000 {
92 opp-hz = /bits/ 64 <40 92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <95000 93 opp-microvolt = <950000 950000 1325000>;
94 }; 94 };
95 opp-600000000 { 95 opp-600000000 {
96 opp-hz = /bits/ 64 <60 96 opp-hz = /bits/ 64 <600000000>;
97 opp-microvolt = <95000 97 opp-microvolt = <950000 950000 1325000>;
98 }; 98 };
99 opp-696000000 { 99 opp-696000000 {
100 opp-hz = /bits/ 64 <69 100 opp-hz = /bits/ 64 <696000000>;
101 opp-microvolt = <97500 101 opp-microvolt = <975000 975000 1325000>;
102 }; 102 };
103 opp-816000000 { 103 opp-816000000 {
104 opp-hz = /bits/ 64 <81 104 opp-hz = /bits/ 64 <816000000>;
105 opp-microvolt = <10750 105 opp-microvolt = <1075000 1075000 1325000>;
106 opp-suspend; 106 opp-suspend;
107 }; 107 };
108 opp-1008000000 { 108 opp-1008000000 {
109 opp-hz = /bits/ 64 <10 109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <12000 110 opp-microvolt = <1200000 1200000 1325000>;
111 }; 111 };
112 opp-1200000000 { 112 opp-1200000000 {
113 opp-hz = /bits/ 64 <12 113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <13250 114 opp-microvolt = <1325000 1325000 1325000>;
115 }; 115 };
116 }; 116 };
117 117
118 display_subsystem: display-subsystem { 118 display_subsystem: display-subsystem {
119 compatible = "rockchip,display 119 compatible = "rockchip,display-subsystem";
120 ports = <&vop_out>; 120 ports = <&vop_out>;
121 status = "disabled"; 121 status = "disabled";
122 }; 122 };
123 123
124 gpu_opp_table: opp-table-1 { 124 gpu_opp_table: opp-table-1 {
125 compatible = "operating-points 125 compatible = "operating-points-v2";
126 126
127 opp-200000000 { 127 opp-200000000 {
128 opp-hz = /bits/ 64 <20 128 opp-hz = /bits/ 64 <200000000>;
129 opp-microvolt = <97500 129 opp-microvolt = <975000 975000 1250000>;
130 }; 130 };
131 opp-300000000 { 131 opp-300000000 {
132 opp-hz = /bits/ 64 <30 132 opp-hz = /bits/ 64 <300000000>;
133 opp-microvolt = <10500 133 opp-microvolt = <1050000 1050000 1250000>;
134 }; 134 };
135 opp-400000000 { 135 opp-400000000 {
136 opp-hz = /bits/ 64 <40 136 opp-hz = /bits/ 64 <400000000>;
137 opp-microvolt = <11500 137 opp-microvolt = <1150000 1150000 1250000>;
138 }; 138 };
139 opp-480000000 { 139 opp-480000000 {
140 opp-hz = /bits/ 64 <48 140 opp-hz = /bits/ 64 <480000000>;
141 opp-microvolt = <12500 141 opp-microvolt = <1250000 1250000 1250000>;
142 }; 142 };
143 }; 143 };
144 144
145 timer { 145 timer {
146 compatible = "arm,armv7-timer" 146 compatible = "arm,armv7-timer";
147 interrupts = <GIC_PPI 13 (GIC_ 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 14 (GIC_ 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
149 <GIC_PPI 11 (GIC_ 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
150 <GIC_PPI 10 (GIC_ 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151 arm,cpu-registers-not-fw-confi 151 arm,cpu-registers-not-fw-configured;
152 clock-frequency = <24000000>; 152 clock-frequency = <24000000>;
153 }; 153 };
154 154
155 xin24m: oscillator { 155 xin24m: oscillator {
156 compatible = "fixed-clock"; 156 compatible = "fixed-clock";
157 clock-frequency = <24000000>; 157 clock-frequency = <24000000>;
158 clock-output-names = "xin24m"; 158 clock-output-names = "xin24m";
159 #clock-cells = <0>; 159 #clock-cells = <0>;
160 }; 160 };
161 161
162 imem: sram@10080000 { 162 imem: sram@10080000 {
163 compatible = "mmio-sram"; 163 compatible = "mmio-sram";
164 reg = <0x10080000 0x2000>; 164 reg = <0x10080000 0x2000>;
165 #address-cells = <1>; 165 #address-cells = <1>;
166 #size-cells = <1>; 166 #size-cells = <1>;
167 ranges = <0 0x10080000 0x2000> 167 ranges = <0 0x10080000 0x2000>;
168 168
169 smp-sram@0 { 169 smp-sram@0 {
170 compatible = "rockchip 170 compatible = "rockchip,rk3066-smp-sram";
171 reg = <0x00 0x10>; 171 reg = <0x00 0x10>;
172 }; 172 };
173 }; 173 };
174 174
175 gpu: gpu@10090000 { 175 gpu: gpu@10090000 {
176 compatible = "rockchip,rk3128- 176 compatible = "rockchip,rk3128-mali", "arm,mali-400";
177 reg = <0x10090000 0x10000>; 177 reg = <0x10090000 0x10000>;
178 interrupts = <GIC_SPI 3 IRQ_TY 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 4 IRQ_TY 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 5 IRQ_TY 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 4 IRQ_TY 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 5 IRQ_TY 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 4 IRQ_TY 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "gp", 184 interrupt-names = "gp",
185 "gpmmu", 185 "gpmmu",
186 "pp0", 186 "pp0",
187 "ppmmu0", 187 "ppmmu0",
188 "pp1", 188 "pp1",
189 "ppmmu1"; 189 "ppmmu1";
190 clocks = <&cru ACLK_GPU>, <&cr 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
191 clock-names = "bus", "core"; 191 clock-names = "bus", "core";
192 operating-points-v2 = <&gpu_op 192 operating-points-v2 = <&gpu_opp_table>;
193 resets = <&cru SRST_GPU>; 193 resets = <&cru SRST_GPU>;
194 power-domains = <&power RK3128 194 power-domains = <&power RK3128_PD_GPU>;
195 status = "disabled"; 195 status = "disabled";
196 }; 196 };
197 197
198 pmu: syscon@100a0000 { 198 pmu: syscon@100a0000 {
199 compatible = "rockchip,rk3128- 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
200 reg = <0x100a0000 0x1000>; 200 reg = <0x100a0000 0x1000>;
201 201
202 power: power-controller { 202 power: power-controller {
203 compatible = "rockchip 203 compatible = "rockchip,rk3128-power-controller";
204 #power-domain-cells = 204 #power-domain-cells = <1>;
205 #address-cells = <1>; 205 #address-cells = <1>;
206 #size-cells = <0>; 206 #size-cells = <0>;
207 207
208 power-domain@RK3128_PD 208 power-domain@RK3128_PD_VIO {
209 reg = <RK3128_ 209 reg = <RK3128_PD_VIO>;
210 clocks = <&cru 210 clocks = <&cru ACLK_CIF>,
211 <&cru 211 <&cru HCLK_CIF>,
212 <&cru 212 <&cru DCLK_EBC>,
213 <&cru 213 <&cru HCLK_EBC>,
214 <&cru 214 <&cru ACLK_IEP>,
215 <&cru 215 <&cru HCLK_IEP>,
216 <&cru 216 <&cru ACLK_LCDC0>,
217 <&cru 217 <&cru HCLK_LCDC0>,
218 <&cru 218 <&cru PCLK_MIPI>,
219 <&cru <<
220 <&cru <<
221 <&cru 219 <&cru ACLK_RGA>,
222 <&cru 220 <&cru HCLK_RGA>,
223 <&cru 221 <&cru ACLK_VIO0>,
224 <&cru 222 <&cru ACLK_VIO1>,
225 <&cru 223 <&cru HCLK_VIO>,
226 <&cru 224 <&cru HCLK_VIO_H2P>,
227 <&cru 225 <&cru DCLK_VOP>,
228 <&cru 226 <&cru SCLK_VOP>;
229 pm_qos = <&qos 227 pm_qos = <&qos_ebc>,
230 <&qos 228 <&qos_iep>,
231 <&qos 229 <&qos_lcdc>,
232 <&qos 230 <&qos_rga>,
233 <&qos 231 <&qos_vip>;
234 #power-domain- 232 #power-domain-cells = <0>;
235 }; 233 };
236 234
237 power-domain@RK3128_PD 235 power-domain@RK3128_PD_VIDEO {
238 reg = <RK3128_ 236 reg = <RK3128_PD_VIDEO>;
239 clocks = <&cru 237 clocks = <&cru ACLK_VDPU>,
240 <&cru 238 <&cru HCLK_VDPU>,
241 <&cru 239 <&cru ACLK_VEPU>,
242 <&cru 240 <&cru HCLK_VEPU>,
243 <&cru 241 <&cru SCLK_HEVC_CORE>;
244 pm_qos = <&qos 242 pm_qos = <&qos_vpu>;
245 #power-domain- 243 #power-domain-cells = <0>;
246 }; 244 };
247 245
248 power-domain@RK3128_PD 246 power-domain@RK3128_PD_GPU {
249 reg = <RK3128_ 247 reg = <RK3128_PD_GPU>;
250 clocks = <&cru 248 clocks = <&cru ACLK_GPU>;
251 pm_qos = <&qos 249 pm_qos = <&qos_gpu>;
252 #power-domain- 250 #power-domain-cells = <0>;
253 }; 251 };
254 }; 252 };
255 }; 253 };
256 254
257 vpu: video-codec@10106000 { <<
258 compatible = "rockchip,rk3128- <<
259 reg = <0x10106000 0x800>; <<
260 interrupts = <GIC_SPI 6 IRQ_TY <<
261 <GIC_SPI 7 IRQ_TY <<
262 interrupt-names = "vepu", "vdp <<
263 clocks = <&cru ACLK_VDPU>, <&c <<
264 <&cru ACLK_VEPU>, <&c <<
265 clock-names = "aclk_vdpu", "hc <<
266 "aclk_vepu", "hc <<
267 iommus = <&vpu_mmu>; <<
268 power-domains = <&power RK3128 <<
269 }; <<
270 <<
271 vpu_mmu: iommu@10106800 { <<
272 compatible = "rockchip,iommu"; <<
273 reg = <0x10106800 0x100>; <<
274 interrupts = <GIC_SPI 67 IRQ_T <<
275 clocks = <&cru ACLK_VEPU>, <&c <<
276 clock-names = "aclk", "iface"; <<
277 power-domains = <&power RK3128 <<
278 #iommu-cells = <0>; <<
279 }; <<
280 <<
281 vop: vop@1010e000 { 255 vop: vop@1010e000 {
282 compatible = "rockchip,rk3126- 256 compatible = "rockchip,rk3126-vop";
283 reg = <0x1010e000 0x300>; 257 reg = <0x1010e000 0x300>;
284 interrupts = <GIC_SPI 9 IRQ_TY 258 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru ACLK_LCDC0>, <& 259 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
286 <&cru HCLK_LCDC0>; 260 <&cru HCLK_LCDC0>;
287 clock-names = "aclk_vop", "dcl 261 clock-names = "aclk_vop", "dclk_vop",
288 "hclk_vop"; 262 "hclk_vop";
289 resets = <&cru SRST_VOP_A>, <& 263 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>,
290 <&cru SRST_VOP_D>; 264 <&cru SRST_VOP_D>;
291 reset-names = "axi", "ahb", 265 reset-names = "axi", "ahb",
292 "dclk"; 266 "dclk";
293 power-domains = <&power RK3128 267 power-domains = <&power RK3128_PD_VIO>;
294 status = "disabled"; 268 status = "disabled";
295 269
296 vop_out: port { 270 vop_out: port {
297 #address-cells = <1>; 271 #address-cells = <1>;
298 #size-cells = <0>; 272 #size-cells = <0>;
299 273
300 vop_out_hdmi: endpoint 274 vop_out_hdmi: endpoint@0 {
301 reg = <0>; 275 reg = <0>;
302 remote-endpoin 276 remote-endpoint = <&hdmi_in_vop>;
303 }; 277 };
304 <<
305 vop_out_dsi: endpoint@ <<
306 reg = <1>; <<
307 remote-endpoin <<
308 }; <<
309 }; <<
310 }; <<
311 <<
312 dsi: dsi@10110000 { <<
313 compatible = "rockchip,rk3128- <<
314 reg = <0x10110000 0x4000>; <<
315 interrupts = <GIC_SPI 33 IRQ_T <<
316 clocks = <&cru PCLK_MIPI>; <<
317 clock-names = "pclk"; <<
318 phys = <&dphy>; <<
319 phy-names = "dphy"; <<
320 power-domains = <&power RK3128 <<
321 resets = <&cru SRST_VIO_MIPI_D <<
322 reset-names = "apb"; <<
323 rockchip,grf = <&grf>; <<
324 status = "disabled"; <<
325 <<
326 ports { <<
327 #address-cells = <1>; <<
328 #size-cells = <0>; <<
329 <<
330 dsi_in: port@0 { <<
331 reg = <0>; <<
332 <<
333 dsi_in_vop: en <<
334 remote <<
335 }; <<
336 }; <<
337 <<
338 dsi_out: port@1 { <<
339 reg = <1>; <<
340 }; <<
341 }; 278 };
342 }; 279 };
343 280
344 qos_gpu: qos@1012d000 { 281 qos_gpu: qos@1012d000 {
345 compatible = "rockchip,rk3128- 282 compatible = "rockchip,rk3128-qos", "syscon";
346 reg = <0x1012d000 0x20>; 283 reg = <0x1012d000 0x20>;
347 }; 284 };
348 285
349 qos_vpu: qos@1012e000 { 286 qos_vpu: qos@1012e000 {
350 compatible = "rockchip,rk3128- 287 compatible = "rockchip,rk3128-qos", "syscon";
351 reg = <0x1012e000 0x20>; 288 reg = <0x1012e000 0x20>;
352 }; 289 };
353 290
354 qos_rga: qos@1012f000 { 291 qos_rga: qos@1012f000 {
355 compatible = "rockchip,rk3128- 292 compatible = "rockchip,rk3128-qos", "syscon";
356 reg = <0x1012f000 0x20>; 293 reg = <0x1012f000 0x20>;
357 }; 294 };
358 295
359 qos_ebc: qos@1012f080 { 296 qos_ebc: qos@1012f080 {
360 compatible = "rockchip,rk3128- 297 compatible = "rockchip,rk3128-qos", "syscon";
361 reg = <0x1012f080 0x20>; 298 reg = <0x1012f080 0x20>;
362 }; 299 };
363 300
364 qos_iep: qos@1012f100 { 301 qos_iep: qos@1012f100 {
365 compatible = "rockchip,rk3128- 302 compatible = "rockchip,rk3128-qos", "syscon";
366 reg = <0x1012f100 0x20>; 303 reg = <0x1012f100 0x20>;
367 }; 304 };
368 305
369 qos_lcdc: qos@1012f180 { 306 qos_lcdc: qos@1012f180 {
370 compatible = "rockchip,rk3128- 307 compatible = "rockchip,rk3128-qos", "syscon";
371 reg = <0x1012f180 0x20>; 308 reg = <0x1012f180 0x20>;
372 }; 309 };
373 310
374 qos_vip: qos@1012f200 { 311 qos_vip: qos@1012f200 {
375 compatible = "rockchip,rk3128- 312 compatible = "rockchip,rk3128-qos", "syscon";
376 reg = <0x1012f200 0x20>; 313 reg = <0x1012f200 0x20>;
377 }; 314 };
378 315
379 gic: interrupt-controller@10139000 { 316 gic: interrupt-controller@10139000 {
380 compatible = "arm,cortex-a7-gi 317 compatible = "arm,cortex-a7-gic";
381 reg = <0x10139000 0x1000>, 318 reg = <0x10139000 0x1000>,
382 <0x1013a000 0x1000>, 319 <0x1013a000 0x1000>,
383 <0x1013c000 0x2000>, 320 <0x1013c000 0x2000>,
384 <0x1013e000 0x2000>; 321 <0x1013e000 0x2000>;
385 interrupts = <GIC_PPI 9 (GIC_C 322 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
386 interrupt-controller; 323 interrupt-controller;
387 #interrupt-cells = <3>; 324 #interrupt-cells = <3>;
388 #address-cells = <0>; 325 #address-cells = <0>;
389 }; 326 };
390 327
391 usb_otg: usb@10180000 { 328 usb_otg: usb@10180000 {
392 compatible = "rockchip,rk3128- 329 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
393 reg = <0x10180000 0x40000>; 330 reg = <0x10180000 0x40000>;
394 interrupts = <GIC_SPI 10 IRQ_T 331 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru HCLK_OTG>; 332 clocks = <&cru HCLK_OTG>;
396 clock-names = "otg"; 333 clock-names = "otg";
397 dr_mode = "otg"; 334 dr_mode = "otg";
398 g-np-tx-fifo-size = <16>; 335 g-np-tx-fifo-size = <16>;
399 g-rx-fifo-size = <280>; 336 g-rx-fifo-size = <280>;
400 g-tx-fifo-size = <256 128 128 337 g-tx-fifo-size = <256 128 128 64 32 16>;
401 phys = <&usb2phy_otg>; 338 phys = <&usb2phy_otg>;
402 phy-names = "usb2-phy"; 339 phy-names = "usb2-phy";
403 status = "disabled"; 340 status = "disabled";
404 }; 341 };
405 342
406 usb_host_ehci: usb@101c0000 { 343 usb_host_ehci: usb@101c0000 {
407 compatible = "generic-ehci"; 344 compatible = "generic-ehci";
408 reg = <0x101c0000 0x20000>; 345 reg = <0x101c0000 0x20000>;
409 interrupts = <GIC_SPI 11 IRQ_T 346 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cru HCLK_HOST2>; 347 clocks = <&cru HCLK_HOST2>;
411 phys = <&usb2phy_host>; 348 phys = <&usb2phy_host>;
412 phy-names = "usb"; 349 phy-names = "usb";
413 status = "disabled"; 350 status = "disabled";
414 }; 351 };
415 352
416 usb_host_ohci: usb@101e0000 { 353 usb_host_ohci: usb@101e0000 {
417 compatible = "generic-ohci"; 354 compatible = "generic-ohci";
418 reg = <0x101e0000 0x20000>; 355 reg = <0x101e0000 0x20000>;
419 interrupts = <GIC_SPI 32 IRQ_T 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru HCLK_HOST2>; 357 clocks = <&cru HCLK_HOST2>;
421 phys = <&usb2phy_host>; 358 phys = <&usb2phy_host>;
422 phy-names = "usb"; 359 phy-names = "usb";
423 status = "disabled"; 360 status = "disabled";
424 }; 361 };
425 362
426 i2s_8ch: i2s@10200000 { <<
427 compatible = "rockchip,rk3128- <<
428 reg = <0x10200000 0x1000>; <<
429 interrupts = <GIC_SPI 68 IRQ_T <<
430 clocks = <&cru SCLK_I2S0>, <&c <<
431 clock-names = "i2s_clk", "i2s_ <<
432 dmas = <&pdma 14>, <&pdma 15>; <<
433 dma-names = "tx", "rx"; <<
434 #sound-dai-cells = <0>; <<
435 status = "disabled"; <<
436 }; <<
437 <<
438 spdif: spdif@10204000 { <<
439 compatible = "rockchip,rk3128- <<
440 reg = <0x10204000 0x1000>; <<
441 interrupts = <GIC_SPI 55 IRQ_T <<
442 clocks = <&cru SCLK_SPDIF>, <& <<
443 clock-names = "mclk", "hclk"; <<
444 dmas = <&pdma 13>; <<
445 dma-names = "tx"; <<
446 pinctrl-names = "default"; <<
447 pinctrl-0 = <&spdif_tx>; <<
448 #sound-dai-cells = <0>; <<
449 status = "disabled"; <<
450 }; <<
451 <<
452 sfc: spi@1020c000 { <<
453 compatible = "rockchip,sfc"; <<
454 reg = <0x1020c000 0x8000>; <<
455 interrupts = <GIC_SPI 50 IRQ_T <<
456 clocks = <&cru SCLK_SFC>, <&cr <<
457 clock-names = "clk_sfc", "hclk <<
458 status = "disabled"; <<
459 }; <<
460 <<
461 sdmmc: mmc@10214000 { 363 sdmmc: mmc@10214000 {
462 compatible = "rockchip,rk3128- 364 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
463 reg = <0x10214000 0x4000>; 365 reg = <0x10214000 0x4000>;
464 interrupts = <GIC_SPI 14 IRQ_T 366 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_SDMMC>, <& 367 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
466 <&cru SCLK_SDMMC_DRV> 368 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
467 clock-names = "biu", "ciu", "c 369 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
468 dmas = <&pdma 10>; 370 dmas = <&pdma 10>;
469 dma-names = "rx-tx"; 371 dma-names = "rx-tx";
470 fifo-depth = <256>; 372 fifo-depth = <256>;
471 max-frequency = <150000000>; 373 max-frequency = <150000000>;
472 resets = <&cru SRST_SDMMC>; 374 resets = <&cru SRST_SDMMC>;
473 reset-names = "reset"; 375 reset-names = "reset";
474 status = "disabled"; 376 status = "disabled";
475 }; 377 };
476 378
477 sdio: mmc@10218000 { 379 sdio: mmc@10218000 {
478 compatible = "rockchip,rk3128- 380 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
479 reg = <0x10218000 0x4000>; 381 reg = <0x10218000 0x4000>;
480 interrupts = <GIC_SPI 15 IRQ_T 382 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_SDIO>, <&c 383 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
482 <&cru SCLK_SDIO_DRV>, 384 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
483 clock-names = "biu", "ciu", "c 385 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
484 dmas = <&pdma 11>; 386 dmas = <&pdma 11>;
485 dma-names = "rx-tx"; 387 dma-names = "rx-tx";
486 fifo-depth = <256>; 388 fifo-depth = <256>;
487 max-frequency = <150000000>; 389 max-frequency = <150000000>;
488 resets = <&cru SRST_SDIO>; 390 resets = <&cru SRST_SDIO>;
489 reset-names = "reset"; 391 reset-names = "reset";
490 status = "disabled"; 392 status = "disabled";
491 }; 393 };
492 394
493 emmc: mmc@1021c000 { 395 emmc: mmc@1021c000 {
494 compatible = "rockchip,rk3128- 396 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
495 reg = <0x1021c000 0x4000>; 397 reg = <0x1021c000 0x4000>;
496 interrupts = <GIC_SPI 16 IRQ_T 398 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru HCLK_EMMC>, <&c 399 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
498 <&cru SCLK_EMMC_DRV>, 400 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
499 clock-names = "biu", "ciu", "c 401 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
500 dmas = <&pdma 12>; 402 dmas = <&pdma 12>;
501 dma-names = "rx-tx"; 403 dma-names = "rx-tx";
502 fifo-depth = <256>; 404 fifo-depth = <256>;
503 max-frequency = <150000000>; 405 max-frequency = <150000000>;
504 resets = <&cru SRST_EMMC>; 406 resets = <&cru SRST_EMMC>;
505 reset-names = "reset"; 407 reset-names = "reset";
506 status = "disabled"; 408 status = "disabled";
507 }; 409 };
508 410
509 i2s_2ch: i2s@10220000 { <<
510 compatible = "rockchip,rk3128- <<
511 reg = <0x10220000 0x1000>; <<
512 interrupts = <GIC_SPI 19 IRQ_T <<
513 clocks = <&cru SCLK_I2S1>, <&c <<
514 clock-names = "i2s_clk", "i2s_ <<
515 dmas = <&pdma 0>, <&pdma 1>; <<
516 dma-names = "tx", "rx"; <<
517 rockchip,playback-channels = < <<
518 pinctrl-names = "default"; <<
519 pinctrl-0 = <&i2s_bus>; <<
520 #sound-dai-cells = <0>; <<
521 status = "disabled"; <<
522 }; <<
523 <<
524 nfc: nand-controller@10500000 { 411 nfc: nand-controller@10500000 {
525 compatible = "rockchip,rk3128- 412 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
526 reg = <0x10500000 0x4000>; 413 reg = <0x10500000 0x4000>;
527 interrupts = <GIC_SPI 18 IRQ_T 414 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cru HCLK_NANDC>, <& 415 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
529 clock-names = "ahb", "nfc"; 416 clock-names = "ahb", "nfc";
530 pinctrl-names = "default"; 417 pinctrl-names = "default";
531 pinctrl-0 = <&flash_ale &flash 418 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
532 &flash_dqs &flash 419 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
533 status = "disabled"; 420 status = "disabled";
534 }; 421 };
535 422
536 cru: clock-controller@20000000 { 423 cru: clock-controller@20000000 {
537 compatible = "rockchip,rk3128- 424 compatible = "rockchip,rk3128-cru";
538 reg = <0x20000000 0x1000>; 425 reg = <0x20000000 0x1000>;
539 clocks = <&xin24m>; 426 clocks = <&xin24m>;
540 clock-names = "xin24m"; 427 clock-names = "xin24m";
541 rockchip,grf = <&grf>; 428 rockchip,grf = <&grf>;
542 #clock-cells = <1>; 429 #clock-cells = <1>;
543 #reset-cells = <1>; 430 #reset-cells = <1>;
544 assigned-clocks = <&cru PLL_GP 431 assigned-clocks = <&cru PLL_GPLL>;
545 assigned-clock-rates = <594000 432 assigned-clock-rates = <594000000>;
546 }; 433 };
547 434
548 grf: syscon@20008000 { 435 grf: syscon@20008000 {
549 compatible = "rockchip,rk3128- 436 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
550 reg = <0x20008000 0x1000>; 437 reg = <0x20008000 0x1000>;
551 #address-cells = <1>; 438 #address-cells = <1>;
552 #size-cells = <1>; 439 #size-cells = <1>;
553 440
554 usb2phy: usb2phy@17c { 441 usb2phy: usb2phy@17c {
555 compatible = "rockchip 442 compatible = "rockchip,rk3128-usb2phy";
556 reg = <0x017c 0x0c>; 443 reg = <0x017c 0x0c>;
557 clocks = <&cru SCLK_OT 444 clocks = <&cru SCLK_OTGPHY0>;
558 clock-names = "phyclk" 445 clock-names = "phyclk";
559 clock-output-names = " 446 clock-output-names = "usb480m_phy";
560 assigned-clocks = <&cr 447 assigned-clocks = <&cru SCLK_USB480M>;
561 assigned-clock-parents 448 assigned-clock-parents = <&usb2phy>;
562 #clock-cells = <0>; 449 #clock-cells = <0>;
563 status = "disabled"; 450 status = "disabled";
564 451
565 usb2phy_host: host-por 452 usb2phy_host: host-port {
566 interrupts = < 453 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-name 454 interrupt-names = "linestate";
568 #phy-cells = < 455 #phy-cells = <0>;
569 status = "disa 456 status = "disabled";
570 }; 457 };
571 458
572 usb2phy_otg: otg-port 459 usb2phy_otg: otg-port {
573 interrupts = < 460 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
574 < 461 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
575 < 462 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-name 463 interrupt-names = "otg-bvalid", "otg-id",
577 464 "linestate";
578 #phy-cells = < 465 #phy-cells = <0>;
579 status = "disa 466 status = "disabled";
580 }; 467 };
581 }; 468 };
582 }; 469 };
583 470
584 hdmi: hdmi@20034000 { 471 hdmi: hdmi@20034000 {
585 compatible = "rockchip,rk3128- 472 compatible = "rockchip,rk3128-inno-hdmi";
586 reg = <0x20034000 0x4000>; 473 reg = <0x20034000 0x4000>;
587 interrupts = <GIC_SPI 45 IRQ_T 474 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cru PCLK_HDMI>, <&c 475 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
589 clock-names = "pclk", "ref"; 476 clock-names = "pclk", "ref";
590 pinctrl-names = "default"; 477 pinctrl-names = "default";
591 pinctrl-0 = <&hdmii2c_xfer &hd 478 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
592 power-domains = <&power RK3128 479 power-domains = <&power RK3128_PD_VIO>;
593 #sound-dai-cells = <0>; <<
594 status = "disabled"; 480 status = "disabled";
595 481
596 ports { 482 ports {
597 #address-cells = <1>; 483 #address-cells = <1>;
598 #size-cells = <0>; 484 #size-cells = <0>;
599 485
600 hdmi_in: port@0 { 486 hdmi_in: port@0 {
601 reg = <0>; 487 reg = <0>;
602 hdmi_in_vop: e 488 hdmi_in_vop: endpoint {
603 remote 489 remote-endpoint = <&vop_out_hdmi>;
604 }; 490 };
605 }; 491 };
606 492
607 hdmi_out: port@1 { 493 hdmi_out: port@1 {
608 reg = <1>; 494 reg = <1>;
609 }; 495 };
610 }; 496 };
611 }; 497 };
612 498
613 dphy: phy@20038000 { <<
614 compatible = "rockchip,rk3128- <<
615 reg = <0x20038000 0x4000>; <<
616 clocks = <&cru SCLK_MIPI_24M>, <<
617 clock-names = "ref", "pclk"; <<
618 #phy-cells = <0>; <<
619 power-domains = <&power RK3128 <<
620 resets = <&cru SRST_MIPIPHY_P> <<
621 reset-names = "apb"; <<
622 status = "disabled"; <<
623 }; <<
624 <<
625 timer0: timer@20044000 { 499 timer0: timer@20044000 {
626 compatible = "rockchip,rk3128- 500 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
627 reg = <0x20044000 0x20>; 501 reg = <0x20044000 0x20>;
628 interrupts = <GIC_SPI 28 IRQ_T 502 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru PCLK_TIMER>, <& 503 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
630 clock-names = "pclk", "timer"; 504 clock-names = "pclk", "timer";
631 }; 505 };
632 506
633 timer1: timer@20044020 { 507 timer1: timer@20044020 {
634 compatible = "rockchip,rk3128- 508 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
635 reg = <0x20044020 0x20>; 509 reg = <0x20044020 0x20>;
636 interrupts = <GIC_SPI 29 IRQ_T 510 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru PCLK_TIMER>, <& 511 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
638 clock-names = "pclk", "timer"; 512 clock-names = "pclk", "timer";
639 }; 513 };
640 514
641 timer2: timer@20044040 { 515 timer2: timer@20044040 {
642 compatible = "rockchip,rk3128- 516 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
643 reg = <0x20044040 0x20>; 517 reg = <0x20044040 0x20>;
644 interrupts = <GIC_SPI 59 IRQ_T 518 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru PCLK_TIMER>, <& 519 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
646 clock-names = "pclk", "timer"; 520 clock-names = "pclk", "timer";
647 }; 521 };
648 522
649 timer3: timer@20044060 { 523 timer3: timer@20044060 {
650 compatible = "rockchip,rk3128- 524 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
651 reg = <0x20044060 0x20>; 525 reg = <0x20044060 0x20>;
652 interrupts = <GIC_SPI 60 IRQ_T 526 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru PCLK_TIMER>, <& 527 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
654 clock-names = "pclk", "timer"; 528 clock-names = "pclk", "timer";
655 }; 529 };
656 530
657 timer4: timer@20044080 { 531 timer4: timer@20044080 {
658 compatible = "rockchip,rk3128- 532 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
659 reg = <0x20044080 0x20>; 533 reg = <0x20044080 0x20>;
660 interrupts = <GIC_SPI 61 IRQ_T 534 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cru PCLK_TIMER>, <& 535 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
662 clock-names = "pclk", "timer"; 536 clock-names = "pclk", "timer";
663 }; 537 };
664 538
665 timer5: timer@200440a0 { 539 timer5: timer@200440a0 {
666 compatible = "rockchip,rk3128- 540 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
667 reg = <0x200440a0 0x20>; 541 reg = <0x200440a0 0x20>;
668 interrupts = <GIC_SPI 62 IRQ_T 542 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru PCLK_TIMER>, <& 543 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
670 clock-names = "pclk", "timer"; 544 clock-names = "pclk", "timer";
671 }; 545 };
672 546
673 watchdog: watchdog@2004c000 { 547 watchdog: watchdog@2004c000 {
674 compatible = "rockchip,rk3128- 548 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
675 reg = <0x2004c000 0x100>; 549 reg = <0x2004c000 0x100>;
676 interrupts = <GIC_SPI 34 IRQ_T 550 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cru PCLK_WDT>; 551 clocks = <&cru PCLK_WDT>;
678 status = "disabled"; 552 status = "disabled";
679 }; 553 };
680 554
681 pwm0: pwm@20050000 { 555 pwm0: pwm@20050000 {
682 compatible = "rockchip,rk3128- 556 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
683 reg = <0x20050000 0x10>; 557 reg = <0x20050000 0x10>;
684 clocks = <&cru PCLK_PWM>; 558 clocks = <&cru PCLK_PWM>;
685 pinctrl-names = "default"; 559 pinctrl-names = "default";
686 pinctrl-0 = <&pwm0_pin>; 560 pinctrl-0 = <&pwm0_pin>;
687 #pwm-cells = <3>; 561 #pwm-cells = <3>;
688 status = "disabled"; 562 status = "disabled";
689 }; 563 };
690 564
691 pwm1: pwm@20050010 { 565 pwm1: pwm@20050010 {
692 compatible = "rockchip,rk3128- 566 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
693 reg = <0x20050010 0x10>; 567 reg = <0x20050010 0x10>;
694 clocks = <&cru PCLK_PWM>; 568 clocks = <&cru PCLK_PWM>;
695 pinctrl-names = "default"; 569 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>; 570 pinctrl-0 = <&pwm1_pin>;
697 #pwm-cells = <3>; 571 #pwm-cells = <3>;
698 status = "disabled"; 572 status = "disabled";
699 }; 573 };
700 574
701 pwm2: pwm@20050020 { 575 pwm2: pwm@20050020 {
702 compatible = "rockchip,rk3128- 576 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
703 reg = <0x20050020 0x10>; 577 reg = <0x20050020 0x10>;
704 clocks = <&cru PCLK_PWM>; 578 clocks = <&cru PCLK_PWM>;
705 pinctrl-names = "default"; 579 pinctrl-names = "default";
706 pinctrl-0 = <&pwm2_pin>; 580 pinctrl-0 = <&pwm2_pin>;
707 #pwm-cells = <3>; 581 #pwm-cells = <3>;
708 status = "disabled"; 582 status = "disabled";
709 }; 583 };
710 584
711 pwm3: pwm@20050030 { 585 pwm3: pwm@20050030 {
712 compatible = "rockchip,rk3128- 586 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
713 reg = <0x20050030 0x10>; 587 reg = <0x20050030 0x10>;
714 clocks = <&cru PCLK_PWM>; 588 clocks = <&cru PCLK_PWM>;
715 pinctrl-names = "default"; 589 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3_pin>; 590 pinctrl-0 = <&pwm3_pin>;
717 #pwm-cells = <3>; 591 #pwm-cells = <3>;
718 status = "disabled"; 592 status = "disabled";
719 }; 593 };
720 594
721 i2c1: i2c@20056000 { 595 i2c1: i2c@20056000 {
722 compatible = "rockchip,rk3128- 596 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
723 reg = <0x20056000 0x1000>; 597 reg = <0x20056000 0x1000>;
724 interrupts = <GIC_SPI 25 IRQ_T 598 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
725 clock-names = "i2c"; 599 clock-names = "i2c";
726 clocks = <&cru PCLK_I2C1>; 600 clocks = <&cru PCLK_I2C1>;
727 pinctrl-names = "default"; 601 pinctrl-names = "default";
728 pinctrl-0 = <&i2c1_xfer>; 602 pinctrl-0 = <&i2c1_xfer>;
729 #address-cells = <1>; 603 #address-cells = <1>;
730 #size-cells = <0>; 604 #size-cells = <0>;
731 status = "disabled"; 605 status = "disabled";
732 }; 606 };
733 607
734 i2c2: i2c@2005a000 { 608 i2c2: i2c@2005a000 {
735 compatible = "rockchip,rk3128- 609 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
736 reg = <0x2005a000 0x1000>; 610 reg = <0x2005a000 0x1000>;
737 interrupts = <GIC_SPI 26 IRQ_T 611 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
738 clock-names = "i2c"; 612 clock-names = "i2c";
739 clocks = <&cru PCLK_I2C2>; 613 clocks = <&cru PCLK_I2C2>;
740 pinctrl-names = "default"; 614 pinctrl-names = "default";
741 pinctrl-0 = <&i2c2_xfer>; 615 pinctrl-0 = <&i2c2_xfer>;
742 #address-cells = <1>; 616 #address-cells = <1>;
743 #size-cells = <0>; 617 #size-cells = <0>;
744 status = "disabled"; 618 status = "disabled";
745 }; 619 };
746 620
747 i2c3: i2c@2005e000 { 621 i2c3: i2c@2005e000 {
748 compatible = "rockchip,rk3128- 622 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
749 reg = <0x2005e000 0x1000>; 623 reg = <0x2005e000 0x1000>;
750 interrupts = <GIC_SPI 27 IRQ_T 624 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
751 clock-names = "i2c"; 625 clock-names = "i2c";
752 clocks = <&cru PCLK_I2C3>; 626 clocks = <&cru PCLK_I2C3>;
753 pinctrl-names = "default"; 627 pinctrl-names = "default";
754 pinctrl-0 = <&i2c3_xfer>; 628 pinctrl-0 = <&i2c3_xfer>;
755 #address-cells = <1>; 629 #address-cells = <1>;
756 #size-cells = <0>; 630 #size-cells = <0>;
757 status = "disabled"; 631 status = "disabled";
758 }; 632 };
759 633
760 uart0: serial@20060000 { 634 uart0: serial@20060000 {
761 compatible = "rockchip,rk3128- 635 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
762 reg = <0x20060000 0x100>; 636 reg = <0x20060000 0x100>;
763 interrupts = <GIC_SPI 20 IRQ_T 637 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
764 clock-frequency = <24000000>; 638 clock-frequency = <24000000>;
765 clocks = <&cru SCLK_UART0>, <& 639 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
766 clock-names = "baudclk", "apb_ 640 clock-names = "baudclk", "apb_pclk";
767 dmas = <&pdma 2>, <&pdma 3>; 641 dmas = <&pdma 2>, <&pdma 3>;
768 dma-names = "tx", "rx"; 642 dma-names = "tx", "rx";
769 pinctrl-names = "default"; 643 pinctrl-names = "default";
770 pinctrl-0 = <&uart0_xfer &uart 644 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
771 reg-io-width = <4>; 645 reg-io-width = <4>;
772 reg-shift = <2>; 646 reg-shift = <2>;
773 status = "disabled"; 647 status = "disabled";
774 }; 648 };
775 649
776 uart1: serial@20064000 { 650 uart1: serial@20064000 {
777 compatible = "rockchip,rk3128- 651 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
778 reg = <0x20064000 0x100>; 652 reg = <0x20064000 0x100>;
779 interrupts = <GIC_SPI 21 IRQ_T 653 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
780 clock-frequency = <24000000>; 654 clock-frequency = <24000000>;
781 clocks = <&cru SCLK_UART1>, <& 655 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
782 clock-names = "baudclk", "apb_ 656 clock-names = "baudclk", "apb_pclk";
783 dmas = <&pdma 4>, <&pdma 5>; 657 dmas = <&pdma 4>, <&pdma 5>;
784 dma-names = "tx", "rx"; 658 dma-names = "tx", "rx";
785 pinctrl-names = "default"; 659 pinctrl-names = "default";
786 pinctrl-0 = <&uart1_xfer>; 660 pinctrl-0 = <&uart1_xfer>;
787 reg-io-width = <4>; 661 reg-io-width = <4>;
788 reg-shift = <2>; 662 reg-shift = <2>;
789 status = "disabled"; 663 status = "disabled";
790 }; 664 };
791 665
792 uart2: serial@20068000 { 666 uart2: serial@20068000 {
793 compatible = "rockchip,rk3128- 667 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
794 reg = <0x20068000 0x100>; 668 reg = <0x20068000 0x100>;
795 interrupts = <GIC_SPI 22 IRQ_T 669 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
796 clock-frequency = <24000000>; 670 clock-frequency = <24000000>;
797 clocks = <&cru SCLK_UART2>, <& 671 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
798 clock-names = "baudclk", "apb_ 672 clock-names = "baudclk", "apb_pclk";
799 dmas = <&pdma 6>, <&pdma 7>; 673 dmas = <&pdma 6>, <&pdma 7>;
800 dma-names = "tx", "rx"; 674 dma-names = "tx", "rx";
801 pinctrl-names = "default"; 675 pinctrl-names = "default";
802 pinctrl-0 = <&uart2_xfer>; 676 pinctrl-0 = <&uart2_xfer>;
803 reg-io-width = <4>; 677 reg-io-width = <4>;
804 reg-shift = <2>; 678 reg-shift = <2>;
805 status = "disabled"; 679 status = "disabled";
806 }; 680 };
807 681
808 saradc: saradc@2006c000 { 682 saradc: saradc@2006c000 {
809 compatible = "rockchip,saradc" 683 compatible = "rockchip,saradc";
810 reg = <0x2006c000 0x100>; 684 reg = <0x2006c000 0x100>;
811 interrupts = <GIC_SPI 17 IRQ_T 685 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cru SCLK_SARADC>, < 686 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
813 clock-names = "saradc", "apb_p 687 clock-names = "saradc", "apb_pclk";
814 resets = <&cru SRST_SARADC>; 688 resets = <&cru SRST_SARADC>;
815 reset-names = "saradc-apb"; 689 reset-names = "saradc-apb";
816 #io-channel-cells = <1>; 690 #io-channel-cells = <1>;
817 status = "disabled"; 691 status = "disabled";
818 }; 692 };
819 693
820 i2c0: i2c@20072000 { 694 i2c0: i2c@20072000 {
821 compatible = "rockchip,rk3128- 695 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
822 reg = <0x20072000 0x1000>; 696 reg = <0x20072000 0x1000>;
823 interrupts = <GIC_SPI 24 IRQ_T 697 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
824 clock-names = "i2c"; 698 clock-names = "i2c";
825 clocks = <&cru PCLK_I2C0>; 699 clocks = <&cru PCLK_I2C0>;
826 pinctrl-names = "default"; 700 pinctrl-names = "default";
827 pinctrl-0 = <&i2c0_xfer>; 701 pinctrl-0 = <&i2c0_xfer>;
828 #address-cells = <1>; 702 #address-cells = <1>;
829 #size-cells = <0>; 703 #size-cells = <0>;
830 status = "disabled"; 704 status = "disabled";
831 }; 705 };
832 706
833 spi0: spi@20074000 { 707 spi0: spi@20074000 {
834 compatible = "rockchip,rk3128- 708 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
835 reg = <0x20074000 0x1000>; 709 reg = <0x20074000 0x1000>;
836 interrupts = <GIC_SPI 23 IRQ_T 710 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&cru SCLK_SPI0>, <&c 711 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
838 clock-names = "spiclk", "apb_p 712 clock-names = "spiclk", "apb_pclk";
839 dmas = <&pdma 8>, <&pdma 9>; 713 dmas = <&pdma 8>, <&pdma 9>;
840 dma-names = "tx", "rx"; 714 dma-names = "tx", "rx";
841 pinctrl-names = "default"; 715 pinctrl-names = "default";
842 pinctrl-0 = <&spi0_tx &spi0_rx 716 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
843 #address-cells = <1>; 717 #address-cells = <1>;
844 #size-cells = <0>; 718 #size-cells = <0>;
845 status = "disabled"; 719 status = "disabled";
846 }; 720 };
847 721
848 pdma: dma-controller@20078000 { 722 pdma: dma-controller@20078000 {
849 compatible = "arm,pl330", "arm 723 compatible = "arm,pl330", "arm,primecell";
850 reg = <0x20078000 0x4000>; 724 reg = <0x20078000 0x4000>;
851 interrupts = <GIC_SPI 0 IRQ_TY 725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 1 IRQ_TY 726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
853 arm,pl330-broken-no-flushp; 727 arm,pl330-broken-no-flushp;
854 arm,pl330-periph-burst; 728 arm,pl330-periph-burst;
855 clocks = <&cru ACLK_DMAC>; 729 clocks = <&cru ACLK_DMAC>;
856 clock-names = "apb_pclk"; 730 clock-names = "apb_pclk";
857 #dma-cells = <1>; 731 #dma-cells = <1>;
858 }; 732 };
859 733
860 gmac: ethernet@2008c000 { 734 gmac: ethernet@2008c000 {
861 compatible = "rockchip,rk3128- 735 compatible = "rockchip,rk3128-gmac";
862 reg = <0x2008c000 0x4000>; 736 reg = <0x2008c000 0x4000>;
863 interrupts = <GIC_SPI 56 IRQ_T 737 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 57 IRQ_T 738 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
865 interrupt-names = "macirq", "e 739 interrupt-names = "macirq", "eth_wake_irq";
866 clocks = <&cru SCLK_MAC>, 740 clocks = <&cru SCLK_MAC>,
867 <&cru SCLK_MAC_RX>, < 741 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
868 <&cru SCLK_MAC_REF>, 742 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
869 <&cru ACLK_GMAC>, <&c 743 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
870 clock-names = "stmmaceth", 744 clock-names = "stmmaceth",
871 "mac_clk_rx", "m 745 "mac_clk_rx", "mac_clk_tx",
872 "clk_mac_ref", " 746 "clk_mac_ref", "clk_mac_refout",
873 "aclk_mac", "pcl 747 "aclk_mac", "pclk_mac";
874 resets = <&cru SRST_GMAC>; 748 resets = <&cru SRST_GMAC>;
875 reset-names = "stmmaceth"; 749 reset-names = "stmmaceth";
876 rockchip,grf = <&grf>; 750 rockchip,grf = <&grf>;
877 rx-fifo-depth = <4096>; 751 rx-fifo-depth = <4096>;
878 tx-fifo-depth = <2048>; 752 tx-fifo-depth = <2048>;
879 status = "disabled"; 753 status = "disabled";
880 754
881 mdio: mdio { 755 mdio: mdio {
882 compatible = "snps,dwm 756 compatible = "snps,dwmac-mdio";
883 #address-cells = <0x1> 757 #address-cells = <0x1>;
884 #size-cells = <0x0>; 758 #size-cells = <0x0>;
885 }; 759 };
886 }; 760 };
887 761
888 pinctrl: pinctrl { 762 pinctrl: pinctrl {
889 compatible = "rockchip,rk3128- 763 compatible = "rockchip,rk3128-pinctrl";
890 rockchip,grf = <&grf>; 764 rockchip,grf = <&grf>;
891 #address-cells = <1>; 765 #address-cells = <1>;
892 #size-cells = <1>; 766 #size-cells = <1>;
893 ranges; 767 ranges;
894 768
895 gpio0: gpio@2007c000 { 769 gpio0: gpio@2007c000 {
896 compatible = "rockchip 770 compatible = "rockchip,gpio-bank";
897 reg = <0x2007c000 0x10 771 reg = <0x2007c000 0x100>;
898 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cru PCLK_GP 773 clocks = <&cru PCLK_GPIO0>;
900 gpio-controller; 774 gpio-controller;
901 #gpio-cells = <2>; 775 #gpio-cells = <2>;
902 interrupt-controller; 776 interrupt-controller;
903 #interrupt-cells = <2> 777 #interrupt-cells = <2>;
904 }; 778 };
905 779
906 gpio1: gpio@20080000 { 780 gpio1: gpio@20080000 {
907 compatible = "rockchip 781 compatible = "rockchip,gpio-bank";
908 reg = <0x20080000 0x10 782 reg = <0x20080000 0x100>;
909 interrupts = <GIC_SPI 783 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&cru PCLK_GP 784 clocks = <&cru PCLK_GPIO1>;
911 gpio-controller; 785 gpio-controller;
912 #gpio-cells = <2>; 786 #gpio-cells = <2>;
913 interrupt-controller; 787 interrupt-controller;
914 #interrupt-cells = <2> 788 #interrupt-cells = <2>;
915 }; 789 };
916 790
917 gpio2: gpio@20084000 { 791 gpio2: gpio@20084000 {
918 compatible = "rockchip 792 compatible = "rockchip,gpio-bank";
919 reg = <0x20084000 0x10 793 reg = <0x20084000 0x100>;
920 interrupts = <GIC_SPI 794 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cru PCLK_GP 795 clocks = <&cru PCLK_GPIO2>;
922 gpio-controller; 796 gpio-controller;
923 #gpio-cells = <2>; 797 #gpio-cells = <2>;
924 interrupt-controller; 798 interrupt-controller;
925 #interrupt-cells = <2> 799 #interrupt-cells = <2>;
926 }; 800 };
927 801
928 gpio3: gpio@20088000 { 802 gpio3: gpio@20088000 {
929 compatible = "rockchip 803 compatible = "rockchip,gpio-bank";
930 reg = <0x20088000 0x10 804 reg = <0x20088000 0x100>;
931 interrupts = <GIC_SPI 805 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&cru PCLK_GP 806 clocks = <&cru PCLK_GPIO3>;
933 gpio-controller; 807 gpio-controller;
934 #gpio-cells = <2>; 808 #gpio-cells = <2>;
935 interrupt-controller; 809 interrupt-controller;
936 #interrupt-cells = <2> 810 #interrupt-cells = <2>;
937 }; 811 };
938 812
939 pcfg_pull_default: pcfg-pull-d 813 pcfg_pull_default: pcfg-pull-default {
940 bias-pull-pin-default; 814 bias-pull-pin-default;
941 }; 815 };
942 816
943 pcfg_pull_none: pcfg-pull-none 817 pcfg_pull_none: pcfg-pull-none {
944 bias-disable; 818 bias-disable;
945 }; 819 };
946 820
947 emmc { 821 emmc {
948 emmc_clk: emmc-clk { 822 emmc_clk: emmc-clk {
949 rockchip,pins 823 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
950 }; 824 };
951 825
952 emmc_cmd: emmc-cmd { 826 emmc_cmd: emmc-cmd {
953 rockchip,pins 827 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
954 }; 828 };
955 829
956 emmc_cmd1: emmc-cmd1 { 830 emmc_cmd1: emmc-cmd1 {
957 rockchip,pins 831 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
958 }; 832 };
959 833
960 emmc_pwr: emmc-pwr { 834 emmc_pwr: emmc-pwr {
961 rockchip,pins 835 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
962 }; 836 };
963 837
964 emmc_bus1: emmc-bus1 { 838 emmc_bus1: emmc-bus1 {
965 rockchip,pins 839 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
966 }; 840 };
967 841
968 emmc_bus4: emmc-bus4 { 842 emmc_bus4: emmc-bus4 {
969 rockchip,pins 843 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
970 844 <1 RK_PD1 2 &pcfg_pull_default>,
971 845 <1 RK_PD2 2 &pcfg_pull_default>,
972 846 <1 RK_PD3 2 &pcfg_pull_default>;
973 }; 847 };
974 848
975 emmc_bus8: emmc-bus8 { 849 emmc_bus8: emmc-bus8 {
976 rockchip,pins 850 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
977 851 <1 RK_PD1 2 &pcfg_pull_default>,
978 852 <1 RK_PD2 2 &pcfg_pull_default>,
979 853 <1 RK_PD3 2 &pcfg_pull_default>,
980 854 <1 RK_PD4 2 &pcfg_pull_default>,
981 855 <1 RK_PD5 2 &pcfg_pull_default>,
982 856 <1 RK_PD6 2 &pcfg_pull_default>,
983 857 <1 RK_PD7 2 &pcfg_pull_default>;
984 }; 858 };
985 }; 859 };
986 860
987 gmac { 861 gmac {
988 rgmii_pins: rgmii-pins 862 rgmii_pins: rgmii-pins {
989 rockchip,pins 863 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
990 864 <2 RK_PB1 3 &pcfg_pull_default>,
991 865 <2 RK_PB3 3 &pcfg_pull_default>,
992 866 <2 RK_PB4 3 &pcfg_pull_default>,
993 867 <2 RK_PB5 3 &pcfg_pull_default>,
994 868 <2 RK_PB6 3 &pcfg_pull_default>,
995 869 <2 RK_PC0 3 &pcfg_pull_default>,
996 870 <2 RK_PC1 3 &pcfg_pull_default>,
997 871 <2 RK_PC2 3 &pcfg_pull_default>,
998 872 <2 RK_PC3 3 &pcfg_pull_default>,
999 873 <2 RK_PD1 3 &pcfg_pull_default>,
1000 874 <2 RK_PC4 4 &pcfg_pull_default>,
1001 875 <2 RK_PC5 4 &pcfg_pull_default>,
1002 876 <2 RK_PC6 4 &pcfg_pull_default>,
1003 877 <2 RK_PC7 4 &pcfg_pull_default>;
1004 }; 878 };
1005 879
1006 rmii_pins: rmii-pins 880 rmii_pins: rmii-pins {
1007 rockchip,pins 881 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
1008 882 <2 RK_PB4 3 &pcfg_pull_default>,
1009 883 <2 RK_PB5 3 &pcfg_pull_default>,
1010 884 <2 RK_PB6 3 &pcfg_pull_default>,
1011 885 <2 RK_PB7 3 &pcfg_pull_default>,
1012 886 <2 RK_PC0 3 &pcfg_pull_default>,
1013 887 <2 RK_PC1 3 &pcfg_pull_default>,
1014 888 <2 RK_PC2 3 &pcfg_pull_default>,
1015 889 <2 RK_PC3 3 &pcfg_pull_default>,
1016 890 <2 RK_PD1 3 &pcfg_pull_default>;
1017 }; 891 };
1018 }; 892 };
1019 893
1020 hdmi { 894 hdmi {
1021 hdmii2c_xfer: hdmii2c 895 hdmii2c_xfer: hdmii2c-xfer {
1022 rockchip,pins 896 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1023 897 <0 RK_PA7 2 &pcfg_pull_none>;
1024 }; 898 };
1025 899
1026 hdmi_hpd: hdmi-hpd { 900 hdmi_hpd: hdmi-hpd {
1027 rockchip,pins 901 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1028 }; 902 };
1029 903
1030 hdmi_cec: hdmi-cec { 904 hdmi_cec: hdmi-cec {
1031 rockchip,pins 905 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1032 }; 906 };
1033 }; 907 };
1034 908
1035 i2c0 { 909 i2c0 {
1036 i2c0_xfer: i2c0-xfer 910 i2c0_xfer: i2c0-xfer {
1037 rockchip,pins 911 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1038 912 <0 RK_PA1 1 &pcfg_pull_none>;
1039 }; 913 };
1040 }; 914 };
1041 915
1042 i2c1 { 916 i2c1 {
1043 i2c1_xfer: i2c1-xfer 917 i2c1_xfer: i2c1-xfer {
1044 rockchip,pins 918 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1045 919 <0 RK_PA3 1 &pcfg_pull_none>;
1046 }; 920 };
1047 }; 921 };
1048 922
1049 i2c2 { 923 i2c2 {
1050 i2c2_xfer: i2c2-xfer 924 i2c2_xfer: i2c2-xfer {
1051 rockchip,pins 925 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
1052 926 <2 RK_PC5 3 &pcfg_pull_none>;
1053 }; 927 };
1054 }; 928 };
1055 929
1056 i2c3 { 930 i2c3 {
1057 i2c3_xfer: i2c3-xfer 931 i2c3_xfer: i2c3-xfer {
1058 rockchip,pins 932 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1059 933 <0 RK_PA7 1 &pcfg_pull_none>;
1060 }; 934 };
1061 }; 935 };
1062 936
1063 i2s { 937 i2s {
1064 i2s_bus: i2s-bus { 938 i2s_bus: i2s-bus {
1065 rockchip,pins 939 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1066 940 <0 RK_PB1 1 &pcfg_pull_none>,
1067 941 <0 RK_PB3 1 &pcfg_pull_none>,
1068 942 <0 RK_PB4 1 &pcfg_pull_none>,
1069 943 <0 RK_PB5 1 &pcfg_pull_none>,
1070 944 <0 RK_PB6 1 &pcfg_pull_none>;
1071 }; 945 };
1072 946
1073 i2s1_bus: i2s1-bus { 947 i2s1_bus: i2s1-bus {
1074 rockchip,pins 948 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
1075 949 <1 RK_PA1 1 &pcfg_pull_none>,
1076 950 <1 RK_PA2 1 &pcfg_pull_none>,
1077 951 <1 RK_PA3 1 &pcfg_pull_none>,
1078 952 <1 RK_PA4 1 &pcfg_pull_none>,
1079 953 <1 RK_PA5 1 &pcfg_pull_none>;
1080 }; 954 };
1081 }; 955 };
1082 956
1083 lcdc { 957 lcdc {
1084 lcdc_dclk: lcdc-dclk 958 lcdc_dclk: lcdc-dclk {
1085 rockchip,pins 959 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
1086 }; 960 };
1087 961
1088 lcdc_den: lcdc-den { 962 lcdc_den: lcdc-den {
1089 rockchip,pins 963 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
1090 }; 964 };
1091 965
1092 lcdc_hsync: lcdc-hsyn 966 lcdc_hsync: lcdc-hsync {
1093 rockchip,pins 967 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1094 }; 968 };
1095 969
1096 lcdc_vsync: lcdc-vsyn 970 lcdc_vsync: lcdc-vsync {
1097 rockchip,pins 971 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
1098 }; 972 };
1099 973
1100 lcdc_rgb24: lcdc-rgb2 974 lcdc_rgb24: lcdc-rgb24 {
1101 rockchip,pins 975 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1102 976 <2 RK_PB5 1 &pcfg_pull_none>,
1103 977 <2 RK_PB6 1 &pcfg_pull_none>,
1104 978 <2 RK_PB7 1 &pcfg_pull_none>,
1105 979 <2 RK_PC0 1 &pcfg_pull_none>,
1106 980 <2 RK_PC1 1 &pcfg_pull_none>,
1107 981 <2 RK_PC2 1 &pcfg_pull_none>,
1108 982 <2 RK_PC3 1 &pcfg_pull_none>,
1109 983 <2 RK_PC4 1 &pcfg_pull_none>,
1110 984 <2 RK_PC5 1 &pcfg_pull_none>,
1111 985 <2 RK_PC6 1 &pcfg_pull_none>,
1112 986 <2 RK_PC7 1 &pcfg_pull_none>,
1113 987 <2 RK_PD0 1 &pcfg_pull_none>,
1114 988 <2 RK_PD1 1 &pcfg_pull_none>;
1115 }; 989 };
1116 }; 990 };
1117 991
1118 nfc { 992 nfc {
1119 flash_ale: flash-ale 993 flash_ale: flash-ale {
1120 rockchip,pins 994 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
1121 }; 995 };
1122 996
1123 flash_cle: flash-cle 997 flash_cle: flash-cle {
1124 rockchip,pins 998 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
1125 }; 999 };
1126 1000
1127 flash_wrn: flash-wrn 1001 flash_wrn: flash-wrn {
1128 rockchip,pins 1002 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1129 }; 1003 };
1130 1004
1131 flash_rdn: flash-rdn 1005 flash_rdn: flash-rdn {
1132 rockchip,pins 1006 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
1133 }; 1007 };
1134 1008
1135 flash_rdy: flash-rdy 1009 flash_rdy: flash-rdy {
1136 rockchip,pins 1010 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1137 }; 1011 };
1138 1012
1139 flash_cs0: flash-cs0 1013 flash_cs0: flash-cs0 {
1140 rockchip,pins 1014 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1141 }; 1015 };
1142 1016
1143 flash_dqs: flash-dqs 1017 flash_dqs: flash-dqs {
1144 rockchip,pins 1018 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
1145 }; 1019 };
1146 1020
1147 flash_bus8: flash-bus 1021 flash_bus8: flash-bus8 {
1148 rockchip,pins 1022 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1149 1023 <1 RK_PD1 1 &pcfg_pull_none>,
1150 1024 <1 RK_PD2 1 &pcfg_pull_none>,
1151 1025 <1 RK_PD3 1 &pcfg_pull_none>,
1152 1026 <1 RK_PD4 1 &pcfg_pull_none>,
1153 1027 <1 RK_PD5 1 &pcfg_pull_none>,
1154 1028 <1 RK_PD6 1 &pcfg_pull_none>,
1155 1029 <1 RK_PD7 1 &pcfg_pull_none>;
1156 }; 1030 };
1157 }; 1031 };
1158 1032
1159 pwm0 { 1033 pwm0 {
1160 pwm0_pin: pwm0-pin { 1034 pwm0_pin: pwm0-pin {
1161 rockchip,pins 1035 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1162 }; 1036 };
1163 }; 1037 };
1164 1038
1165 pwm1 { 1039 pwm1 {
1166 pwm1_pin: pwm1-pin { 1040 pwm1_pin: pwm1-pin {
1167 rockchip,pins 1041 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1168 }; 1042 };
1169 }; 1043 };
1170 1044
1171 pwm2 { 1045 pwm2 {
1172 pwm2_pin: pwm2-pin { 1046 pwm2_pin: pwm2-pin {
1173 rockchip,pins 1047 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1174 }; 1048 };
1175 }; 1049 };
1176 1050
1177 pwm3 { 1051 pwm3 {
1178 pwm3_pin: pwm3-pin { 1052 pwm3_pin: pwm3-pin {
1179 rockchip,pins 1053 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
1180 }; 1054 };
1181 }; 1055 };
1182 1056
1183 sdio { 1057 sdio {
1184 sdio_clk: sdio-clk { 1058 sdio_clk: sdio-clk {
1185 rockchip,pins 1059 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1186 }; 1060 };
1187 1061
1188 sdio_cmd: sdio-cmd { 1062 sdio_cmd: sdio-cmd {
1189 rockchip,pins 1063 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1190 }; 1064 };
1191 1065
1192 sdio_pwren: sdio-pwre 1066 sdio_pwren: sdio-pwren {
1193 rockchip,pins 1067 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1194 }; 1068 };
1195 1069
1196 sdio_bus4: sdio-bus4 1070 sdio_bus4: sdio-bus4 {
1197 rockchip,pins 1071 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1198 1072 <1 RK_PA2 2 &pcfg_pull_default>,
1199 1073 <1 RK_PA4 2 &pcfg_pull_default>,
1200 1074 <1 RK_PA5 2 &pcfg_pull_default>;
1201 }; 1075 };
1202 }; 1076 };
1203 1077
1204 sdmmc { 1078 sdmmc {
1205 sdmmc_clk: sdmmc-clk 1079 sdmmc_clk: sdmmc-clk {
1206 rockchip,pins 1080 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1207 }; 1081 };
1208 1082
1209 sdmmc_cmd: sdmmc-cmd 1083 sdmmc_cmd: sdmmc-cmd {
1210 rockchip,pins 1084 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1211 }; 1085 };
1212 1086
1213 sdmmc_det: sdmmc-det 1087 sdmmc_det: sdmmc-det {
1214 rockchip,pins 1088 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
1215 }; 1089 };
1216 1090
1217 sdmmc_wp: sdmmc-wp { 1091 sdmmc_wp: sdmmc-wp {
1218 rockchip,pins 1092 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1219 }; 1093 };
1220 1094
1221 sdmmc_pwren: sdmmc-pw 1095 sdmmc_pwren: sdmmc-pwren {
1222 rockchip,pins 1096 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
1223 }; 1097 };
1224 1098
1225 sdmmc_bus4: sdmmc-bus 1099 sdmmc_bus4: sdmmc-bus4 {
1226 rockchip,pins 1100 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1227 1101 <1 RK_PC3 1 &pcfg_pull_default>,
1228 1102 <1 RK_PC4 1 &pcfg_pull_default>,
1229 1103 <1 RK_PC5 1 &pcfg_pull_default>;
1230 }; <<
1231 }; <<
1232 <<
1233 sfc { <<
1234 sfc_bus2: sfc-bus2 { <<
1235 rockchip,pins <<
1236 <<
1237 }; <<
1238 <<
1239 sfc_bus4: sfc-bus4 { <<
1240 rockchip,pins <<
1241 <<
1242 <<
1243 <<
1244 }; <<
1245 <<
1246 sfc_clk: sfc-clk { <<
1247 rockchip,pins <<
1248 }; <<
1249 <<
1250 sfc_cs0: sfc-cs0 { <<
1251 rockchip,pins <<
1252 }; <<
1253 <<
1254 sfc_cs1: sfc-cs1 { <<
1255 rockchip,pins <<
1256 }; 1104 };
1257 }; 1105 };
1258 1106
1259 spdif { 1107 spdif {
1260 spdif_tx: spdif-tx { 1108 spdif_tx: spdif-tx {
1261 rockchip,pins 1109 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1262 }; 1110 };
1263 }; 1111 };
1264 1112
1265 spi0 { 1113 spi0 {
1266 spi0_clk: spi0-clk { 1114 spi0_clk: spi0-clk {
1267 rockchip,pins 1115 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1268 }; 1116 };
1269 1117
1270 spi0_cs0: spi0-cs0 { 1118 spi0_cs0: spi0-cs0 {
1271 rockchip,pins 1119 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1272 }; 1120 };
1273 1121
1274 spi0_tx: spi0-tx { 1122 spi0_tx: spi0-tx {
1275 rockchip,pins 1123 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1276 }; 1124 };
1277 1125
1278 spi0_rx: spi0-rx { 1126 spi0_rx: spi0-rx {
1279 rockchip,pins 1127 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1280 }; 1128 };
1281 1129
1282 spi0_cs1: spi0-cs1 { 1130 spi0_cs1: spi0-cs1 {
1283 rockchip,pins 1131 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1284 }; 1132 };
1285 1133
1286 spi1_clk: spi1-clk { 1134 spi1_clk: spi1-clk {
1287 rockchip,pins 1135 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1288 }; 1136 };
1289 1137
1290 spi1_cs0: spi1-cs0 { 1138 spi1_cs0: spi1-cs0 {
1291 rockchip,pins 1139 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1292 }; 1140 };
1293 1141
1294 spi1_tx: spi1-tx { 1142 spi1_tx: spi1-tx {
1295 rockchip,pins 1143 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1296 }; 1144 };
1297 1145
1298 spi1_rx: spi1-rx { 1146 spi1_rx: spi1-rx {
1299 rockchip,pins 1147 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1300 }; 1148 };
1301 1149
1302 spi1_cs1: spi1-cs1 { 1150 spi1_cs1: spi1-cs1 {
1303 rockchip,pins 1151 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1304 }; 1152 };
1305 1153
1306 spi2_clk: spi2-clk { 1154 spi2_clk: spi2-clk {
1307 rockchip,pins 1155 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1308 }; 1156 };
1309 1157
1310 spi2_cs0: spi2-cs0 { 1158 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 1159 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1312 }; 1160 };
1313 1161
1314 spi2_tx: spi2-tx { 1162 spi2_tx: spi2-tx {
1315 rockchip,pins 1163 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1316 }; 1164 };
1317 1165
1318 spi2_rx: spi2-rx { 1166 spi2_rx: spi2-rx {
1319 rockchip,pins 1167 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1320 }; 1168 };
1321 }; 1169 };
1322 1170
1323 uart0 { 1171 uart0 {
1324 uart0_xfer: uart0-xfe 1172 uart0_xfer: uart0-xfer {
1325 rockchip,pins 1173 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1326 1174 <2 RK_PD3 2 &pcfg_pull_none>;
1327 }; 1175 };
1328 1176
1329 uart0_cts: uart0-cts 1177 uart0_cts: uart0-cts {
1330 rockchip,pins 1178 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1331 }; 1179 };
1332 1180
1333 uart0_rts: uart0-rts 1181 uart0_rts: uart0-rts {
1334 rockchip,pins 1182 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1335 }; 1183 };
1336 }; 1184 };
1337 1185
1338 uart1 { 1186 uart1 {
1339 uart1_xfer: uart1-xfe 1187 uart1_xfer: uart1-xfer {
1340 rockchip,pins 1188 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1341 1189 <1 RK_PB2 2 &pcfg_pull_default>;
1342 }; 1190 };
1343 1191
1344 uart1_cts: uart1-cts 1192 uart1_cts: uart1-cts {
1345 rockchip,pins 1193 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1346 }; 1194 };
1347 1195
1348 uart1_rts: uart1-rts 1196 uart1_rts: uart1-rts {
1349 rockchip,pins 1197 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1350 }; 1198 };
1351 }; 1199 };
1352 1200
1353 uart2 { 1201 uart2 {
1354 uart2_xfer: uart2-xfe 1202 uart2_xfer: uart2-xfer {
1355 rockchip,pins 1203 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1356 1204 <1 RK_PC3 2 &pcfg_pull_none>;
1357 }; 1205 };
1358 1206
1359 uart2_cts: uart2-cts 1207 uart2_cts: uart2-cts {
1360 rockchip,pins 1208 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1361 }; 1209 };
1362 1210
1363 uart2_rts: uart2-rts 1211 uart2_rts: uart2-rts {
1364 rockchip,pins 1212 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1365 }; 1213 };
1366 }; 1214 };
1367 }; 1215 };
1368 }; 1216 };
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