1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co. 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3128-cru.h> 6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h> <<
12 11
13 / { 12 / {
14 compatible = "rockchip,rk3128"; 13 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
16 #address-cells = <1>; 15 #address-cells = <1>;
17 #size-cells = <1>; 16 #size-cells = <1>;
18 17
19 aliases { <<
20 gpio0 = &gpio0; <<
21 gpio1 = &gpio1; <<
22 gpio2 = &gpio2; <<
23 gpio3 = &gpio3; <<
24 i2c0 = &i2c0; <<
25 i2c1 = &i2c1; <<
26 i2c2 = &i2c2; <<
27 i2c3 = &i2c3; <<
28 serial0 = &uart0; <<
29 serial1 = &uart1; <<
30 serial2 = &uart2; <<
31 }; <<
32 <<
33 arm-pmu { 18 arm-pmu {
34 compatible = "arm,cortex-a7-pm 19 compatible = "arm,cortex-a7-pmu";
35 interrupts = <GIC_SPI 76 IRQ_T 20 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 77 IRQ_T 21 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 78 IRQ_T 22 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 79 IRQ_T 23 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
39 interrupt-affinity = <&cpu0>, 24 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
40 }; 25 };
41 26
42 cpus { 27 cpus {
43 #address-cells = <1>; 28 #address-cells = <1>;
44 #size-cells = <0>; 29 #size-cells = <0>;
45 enable-method = "rockchip,rk30 <<
46 30
47 cpu0: cpu@f00 { 31 cpu0: cpu@f00 {
48 device_type = "cpu"; 32 device_type = "cpu";
49 compatible = "arm,cort 33 compatible = "arm,cortex-a7";
50 reg = <0xf00>; 34 reg = <0xf00>;
51 clock-latency = <40000 35 clock-latency = <40000>;
52 clocks = <&cru ARMCLK> 36 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CO !! 37 operating-points = <
54 operating-points-v2 = !! 38 /* KHz uV */
>> 39 816000 1000000
>> 40 >;
55 #cooling-cells = <2>; 41 #cooling-cells = <2>; /* min followed by max */
56 }; 42 };
57 43
58 cpu1: cpu@f01 { 44 cpu1: cpu@f01 {
59 device_type = "cpu"; 45 device_type = "cpu";
60 compatible = "arm,cort 46 compatible = "arm,cortex-a7";
61 reg = <0xf01>; 47 reg = <0xf01>;
62 resets = <&cru SRST_CO <<
63 operating-points-v2 = <<
64 }; 48 };
65 49
66 cpu2: cpu@f02 { 50 cpu2: cpu@f02 {
67 device_type = "cpu"; 51 device_type = "cpu";
68 compatible = "arm,cort 52 compatible = "arm,cortex-a7";
69 reg = <0xf02>; 53 reg = <0xf02>;
70 resets = <&cru SRST_CO <<
71 operating-points-v2 = <<
72 }; 54 };
73 55
74 cpu3: cpu@f03 { 56 cpu3: cpu@f03 {
75 device_type = "cpu"; 57 device_type = "cpu";
76 compatible = "arm,cort 58 compatible = "arm,cortex-a7";
77 reg = <0xf03>; 59 reg = <0xf03>;
78 resets = <&cru SRST_CO <<
79 operating-points-v2 = <<
80 }; <<
81 }; <<
82 <<
83 cpu_opp_table: opp-table-0 { <<
84 compatible = "operating-points <<
85 opp-shared; <<
86 <<
87 opp-216000000 { <<
88 opp-hz = /bits/ 64 <21 <<
89 opp-microvolt = <95000 <<
90 }; <<
91 opp-408000000 { <<
92 opp-hz = /bits/ 64 <40 <<
93 opp-microvolt = <95000 <<
94 }; <<
95 opp-600000000 { <<
96 opp-hz = /bits/ 64 <60 <<
97 opp-microvolt = <95000 <<
98 }; <<
99 opp-696000000 { <<
100 opp-hz = /bits/ 64 <69 <<
101 opp-microvolt = <97500 <<
102 }; <<
103 opp-816000000 { <<
104 opp-hz = /bits/ 64 <81 <<
105 opp-microvolt = <10750 <<
106 opp-suspend; <<
107 }; <<
108 opp-1008000000 { <<
109 opp-hz = /bits/ 64 <10 <<
110 opp-microvolt = <12000 <<
111 }; <<
112 opp-1200000000 { <<
113 opp-hz = /bits/ 64 <12 <<
114 opp-microvolt = <13250 <<
115 }; <<
116 }; <<
117 <<
118 display_subsystem: display-subsystem { <<
119 compatible = "rockchip,display <<
120 ports = <&vop_out>; <<
121 status = "disabled"; <<
122 }; <<
123 <<
124 gpu_opp_table: opp-table-1 { <<
125 compatible = "operating-points <<
126 <<
127 opp-200000000 { <<
128 opp-hz = /bits/ 64 <20 <<
129 opp-microvolt = <97500 <<
130 }; <<
131 opp-300000000 { <<
132 opp-hz = /bits/ 64 <30 <<
133 opp-microvolt = <10500 <<
134 }; <<
135 opp-400000000 { <<
136 opp-hz = /bits/ 64 <40 <<
137 opp-microvolt = <11500 <<
138 }; <<
139 opp-480000000 { <<
140 opp-hz = /bits/ 64 <48 <<
141 opp-microvolt = <12500 <<
142 }; 60 };
143 }; 61 };
144 62
145 timer { 63 timer {
146 compatible = "arm,armv7-timer" 64 compatible = "arm,armv7-timer";
147 interrupts = <GIC_PPI 13 (GIC_ 65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 14 (GIC_ 66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
149 <GIC_PPI 11 (GIC_ 67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
150 <GIC_PPI 10 (GIC_ 68 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151 arm,cpu-registers-not-fw-confi 69 arm,cpu-registers-not-fw-configured;
152 clock-frequency = <24000000>; 70 clock-frequency = <24000000>;
153 }; 71 };
154 72
155 xin24m: oscillator { 73 xin24m: oscillator {
156 compatible = "fixed-clock"; 74 compatible = "fixed-clock";
157 clock-frequency = <24000000>; 75 clock-frequency = <24000000>;
158 clock-output-names = "xin24m"; 76 clock-output-names = "xin24m";
159 #clock-cells = <0>; 77 #clock-cells = <0>;
160 }; 78 };
161 79
162 imem: sram@10080000 { <<
163 compatible = "mmio-sram"; <<
164 reg = <0x10080000 0x2000>; <<
165 #address-cells = <1>; <<
166 #size-cells = <1>; <<
167 ranges = <0 0x10080000 0x2000> <<
168 <<
169 smp-sram@0 { <<
170 compatible = "rockchip <<
171 reg = <0x00 0x10>; <<
172 }; <<
173 }; <<
174 <<
175 gpu: gpu@10090000 { <<
176 compatible = "rockchip,rk3128- <<
177 reg = <0x10090000 0x10000>; <<
178 interrupts = <GIC_SPI 3 IRQ_TY <<
179 <GIC_SPI 4 IRQ_TY <<
180 <GIC_SPI 5 IRQ_TY <<
181 <GIC_SPI 4 IRQ_TY <<
182 <GIC_SPI 5 IRQ_TY <<
183 <GIC_SPI 4 IRQ_TY <<
184 interrupt-names = "gp", <<
185 "gpmmu", <<
186 "pp0", <<
187 "ppmmu0", <<
188 "pp1", <<
189 "ppmmu1"; <<
190 clocks = <&cru ACLK_GPU>, <&cr <<
191 clock-names = "bus", "core"; <<
192 operating-points-v2 = <&gpu_op <<
193 resets = <&cru SRST_GPU>; <<
194 power-domains = <&power RK3128 <<
195 status = "disabled"; <<
196 }; <<
197 <<
198 pmu: syscon@100a0000 { 80 pmu: syscon@100a0000 {
199 compatible = "rockchip,rk3128- 81 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
200 reg = <0x100a0000 0x1000>; 82 reg = <0x100a0000 0x1000>;
201 <<
202 power: power-controller { <<
203 compatible = "rockchip <<
204 #power-domain-cells = <<
205 #address-cells = <1>; <<
206 #size-cells = <0>; <<
207 <<
208 power-domain@RK3128_PD <<
209 reg = <RK3128_ <<
210 clocks = <&cru <<
211 <&cru <<
212 <&cru <<
213 <&cru <<
214 <&cru <<
215 <&cru <<
216 <&cru <<
217 <&cru <<
218 <&cru <<
219 <&cru <<
220 <&cru <<
221 <&cru <<
222 <&cru <<
223 <&cru <<
224 <&cru <<
225 <&cru <<
226 <&cru <<
227 <&cru <<
228 <&cru <<
229 pm_qos = <&qos <<
230 <&qos <<
231 <&qos <<
232 <&qos <<
233 <&qos <<
234 #power-domain- <<
235 }; <<
236 <<
237 power-domain@RK3128_PD <<
238 reg = <RK3128_ <<
239 clocks = <&cru <<
240 <&cru <<
241 <&cru <<
242 <&cru <<
243 <&cru <<
244 pm_qos = <&qos <<
245 #power-domain- <<
246 }; <<
247 <<
248 power-domain@RK3128_PD <<
249 reg = <RK3128_ <<
250 clocks = <&cru <<
251 pm_qos = <&qos <<
252 #power-domain- <<
253 }; <<
254 }; <<
255 }; <<
256 <<
257 vpu: video-codec@10106000 { <<
258 compatible = "rockchip,rk3128- <<
259 reg = <0x10106000 0x800>; <<
260 interrupts = <GIC_SPI 6 IRQ_TY <<
261 <GIC_SPI 7 IRQ_TY <<
262 interrupt-names = "vepu", "vdp <<
263 clocks = <&cru ACLK_VDPU>, <&c <<
264 <&cru ACLK_VEPU>, <&c <<
265 clock-names = "aclk_vdpu", "hc <<
266 "aclk_vepu", "hc <<
267 iommus = <&vpu_mmu>; <<
268 power-domains = <&power RK3128 <<
269 }; <<
270 <<
271 vpu_mmu: iommu@10106800 { <<
272 compatible = "rockchip,iommu"; <<
273 reg = <0x10106800 0x100>; <<
274 interrupts = <GIC_SPI 67 IRQ_T <<
275 clocks = <&cru ACLK_VEPU>, <&c <<
276 clock-names = "aclk", "iface"; <<
277 power-domains = <&power RK3128 <<
278 #iommu-cells = <0>; <<
279 }; <<
280 <<
281 vop: vop@1010e000 { <<
282 compatible = "rockchip,rk3126- <<
283 reg = <0x1010e000 0x300>; <<
284 interrupts = <GIC_SPI 9 IRQ_TY <<
285 clocks = <&cru ACLK_LCDC0>, <& <<
286 <&cru HCLK_LCDC0>; <<
287 clock-names = "aclk_vop", "dcl <<
288 "hclk_vop"; <<
289 resets = <&cru SRST_VOP_A>, <& <<
290 <&cru SRST_VOP_D>; <<
291 reset-names = "axi", "ahb", <<
292 "dclk"; <<
293 power-domains = <&power RK3128 <<
294 status = "disabled"; <<
295 <<
296 vop_out: port { <<
297 #address-cells = <1>; <<
298 #size-cells = <0>; <<
299 <<
300 vop_out_hdmi: endpoint <<
301 reg = <0>; <<
302 remote-endpoin <<
303 }; <<
304 <<
305 vop_out_dsi: endpoint@ <<
306 reg = <1>; <<
307 remote-endpoin <<
308 }; <<
309 }; <<
310 }; <<
311 <<
312 dsi: dsi@10110000 { <<
313 compatible = "rockchip,rk3128- <<
314 reg = <0x10110000 0x4000>; <<
315 interrupts = <GIC_SPI 33 IRQ_T <<
316 clocks = <&cru PCLK_MIPI>; <<
317 clock-names = "pclk"; <<
318 phys = <&dphy>; <<
319 phy-names = "dphy"; <<
320 power-domains = <&power RK3128 <<
321 resets = <&cru SRST_VIO_MIPI_D <<
322 reset-names = "apb"; <<
323 rockchip,grf = <&grf>; <<
324 status = "disabled"; <<
325 <<
326 ports { <<
327 #address-cells = <1>; <<
328 #size-cells = <0>; <<
329 <<
330 dsi_in: port@0 { <<
331 reg = <0>; <<
332 <<
333 dsi_in_vop: en <<
334 remote <<
335 }; <<
336 }; <<
337 <<
338 dsi_out: port@1 { <<
339 reg = <1>; <<
340 }; <<
341 }; <<
342 }; <<
343 <<
344 qos_gpu: qos@1012d000 { <<
345 compatible = "rockchip,rk3128- <<
346 reg = <0x1012d000 0x20>; <<
347 }; <<
348 <<
349 qos_vpu: qos@1012e000 { <<
350 compatible = "rockchip,rk3128- <<
351 reg = <0x1012e000 0x20>; <<
352 }; <<
353 <<
354 qos_rga: qos@1012f000 { <<
355 compatible = "rockchip,rk3128- <<
356 reg = <0x1012f000 0x20>; <<
357 }; <<
358 <<
359 qos_ebc: qos@1012f080 { <<
360 compatible = "rockchip,rk3128- <<
361 reg = <0x1012f080 0x20>; <<
362 }; <<
363 <<
364 qos_iep: qos@1012f100 { <<
365 compatible = "rockchip,rk3128- <<
366 reg = <0x1012f100 0x20>; <<
367 }; <<
368 <<
369 qos_lcdc: qos@1012f180 { <<
370 compatible = "rockchip,rk3128- <<
371 reg = <0x1012f180 0x20>; <<
372 }; <<
373 <<
374 qos_vip: qos@1012f200 { <<
375 compatible = "rockchip,rk3128- <<
376 reg = <0x1012f200 0x20>; <<
377 }; 83 };
378 84
379 gic: interrupt-controller@10139000 { 85 gic: interrupt-controller@10139000 {
380 compatible = "arm,cortex-a7-gi 86 compatible = "arm,cortex-a7-gic";
381 reg = <0x10139000 0x1000>, 87 reg = <0x10139000 0x1000>,
382 <0x1013a000 0x1000>, 88 <0x1013a000 0x1000>,
383 <0x1013c000 0x2000>, 89 <0x1013c000 0x2000>,
384 <0x1013e000 0x2000>; 90 <0x1013e000 0x2000>;
385 interrupts = <GIC_PPI 9 (GIC_C 91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
386 interrupt-controller; 92 interrupt-controller;
387 #interrupt-cells = <3>; 93 #interrupt-cells = <3>;
388 #address-cells = <0>; 94 #address-cells = <0>;
389 }; 95 };
390 96
391 usb_otg: usb@10180000 { 97 usb_otg: usb@10180000 {
392 compatible = "rockchip,rk3128- 98 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
393 reg = <0x10180000 0x40000>; 99 reg = <0x10180000 0x40000>;
394 interrupts = <GIC_SPI 10 IRQ_T 100 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru HCLK_OTG>; 101 clocks = <&cru HCLK_OTG>;
396 clock-names = "otg"; 102 clock-names = "otg";
397 dr_mode = "otg"; 103 dr_mode = "otg";
398 g-np-tx-fifo-size = <16>; <<
399 g-rx-fifo-size = <280>; <<
400 g-tx-fifo-size = <256 128 128 <<
401 phys = <&usb2phy_otg>; 104 phys = <&usb2phy_otg>;
402 phy-names = "usb2-phy"; 105 phy-names = "usb2-phy";
403 status = "disabled"; 106 status = "disabled";
404 }; 107 };
405 108
406 usb_host_ehci: usb@101c0000 { 109 usb_host_ehci: usb@101c0000 {
407 compatible = "generic-ehci"; 110 compatible = "generic-ehci";
408 reg = <0x101c0000 0x20000>; 111 reg = <0x101c0000 0x20000>;
409 interrupts = <GIC_SPI 11 IRQ_T 112 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cru HCLK_HOST2>; <<
411 phys = <&usb2phy_host>; 113 phys = <&usb2phy_host>;
412 phy-names = "usb"; 114 phy-names = "usb";
413 status = "disabled"; 115 status = "disabled";
414 }; 116 };
415 117
416 usb_host_ohci: usb@101e0000 { 118 usb_host_ohci: usb@101e0000 {
417 compatible = "generic-ohci"; 119 compatible = "generic-ohci";
418 reg = <0x101e0000 0x20000>; 120 reg = <0x101e0000 0x20000>;
419 interrupts = <GIC_SPI 32 IRQ_T 121 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru HCLK_HOST2>; <<
421 phys = <&usb2phy_host>; 122 phys = <&usb2phy_host>;
422 phy-names = "usb"; 123 phy-names = "usb";
423 status = "disabled"; 124 status = "disabled";
424 }; 125 };
425 126
426 i2s_8ch: i2s@10200000 { <<
427 compatible = "rockchip,rk3128- <<
428 reg = <0x10200000 0x1000>; <<
429 interrupts = <GIC_SPI 68 IRQ_T <<
430 clocks = <&cru SCLK_I2S0>, <&c <<
431 clock-names = "i2s_clk", "i2s_ <<
432 dmas = <&pdma 14>, <&pdma 15>; <<
433 dma-names = "tx", "rx"; <<
434 #sound-dai-cells = <0>; <<
435 status = "disabled"; <<
436 }; <<
437 <<
438 spdif: spdif@10204000 { <<
439 compatible = "rockchip,rk3128- <<
440 reg = <0x10204000 0x1000>; <<
441 interrupts = <GIC_SPI 55 IRQ_T <<
442 clocks = <&cru SCLK_SPDIF>, <& <<
443 clock-names = "mclk", "hclk"; <<
444 dmas = <&pdma 13>; <<
445 dma-names = "tx"; <<
446 pinctrl-names = "default"; <<
447 pinctrl-0 = <&spdif_tx>; <<
448 #sound-dai-cells = <0>; <<
449 status = "disabled"; <<
450 }; <<
451 <<
452 sfc: spi@1020c000 { <<
453 compatible = "rockchip,sfc"; <<
454 reg = <0x1020c000 0x8000>; <<
455 interrupts = <GIC_SPI 50 IRQ_T <<
456 clocks = <&cru SCLK_SFC>, <&cr <<
457 clock-names = "clk_sfc", "hclk <<
458 status = "disabled"; <<
459 }; <<
460 <<
461 sdmmc: mmc@10214000 { 127 sdmmc: mmc@10214000 {
462 compatible = "rockchip,rk3128- 128 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
463 reg = <0x10214000 0x4000>; 129 reg = <0x10214000 0x4000>;
464 interrupts = <GIC_SPI 14 IRQ_T 130 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_SDMMC>, <& 131 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
466 <&cru SCLK_SDMMC_DRV> 132 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
467 clock-names = "biu", "ciu", "c 133 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
468 dmas = <&pdma 10>; 134 dmas = <&pdma 10>;
469 dma-names = "rx-tx"; 135 dma-names = "rx-tx";
470 fifo-depth = <256>; 136 fifo-depth = <256>;
471 max-frequency = <150000000>; 137 max-frequency = <150000000>;
472 resets = <&cru SRST_SDMMC>; 138 resets = <&cru SRST_SDMMC>;
473 reset-names = "reset"; 139 reset-names = "reset";
474 status = "disabled"; 140 status = "disabled";
475 }; 141 };
476 142
477 sdio: mmc@10218000 { 143 sdio: mmc@10218000 {
478 compatible = "rockchip,rk3128- 144 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
479 reg = <0x10218000 0x4000>; 145 reg = <0x10218000 0x4000>;
480 interrupts = <GIC_SPI 15 IRQ_T 146 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_SDIO>, <&c 147 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
482 <&cru SCLK_SDIO_DRV>, 148 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
483 clock-names = "biu", "ciu", "c 149 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
484 dmas = <&pdma 11>; 150 dmas = <&pdma 11>;
485 dma-names = "rx-tx"; 151 dma-names = "rx-tx";
486 fifo-depth = <256>; 152 fifo-depth = <256>;
487 max-frequency = <150000000>; 153 max-frequency = <150000000>;
488 resets = <&cru SRST_SDIO>; 154 resets = <&cru SRST_SDIO>;
489 reset-names = "reset"; 155 reset-names = "reset";
490 status = "disabled"; 156 status = "disabled";
491 }; 157 };
492 158
493 emmc: mmc@1021c000 { 159 emmc: mmc@1021c000 {
494 compatible = "rockchip,rk3128- 160 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
495 reg = <0x1021c000 0x4000>; 161 reg = <0x1021c000 0x4000>;
496 interrupts = <GIC_SPI 16 IRQ_T 162 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru HCLK_EMMC>, <&c 163 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
498 <&cru SCLK_EMMC_DRV>, 164 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
499 clock-names = "biu", "ciu", "c 165 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
500 dmas = <&pdma 12>; 166 dmas = <&pdma 12>;
501 dma-names = "rx-tx"; 167 dma-names = "rx-tx";
502 fifo-depth = <256>; 168 fifo-depth = <256>;
503 max-frequency = <150000000>; 169 max-frequency = <150000000>;
504 resets = <&cru SRST_EMMC>; 170 resets = <&cru SRST_EMMC>;
505 reset-names = "reset"; 171 reset-names = "reset";
506 status = "disabled"; 172 status = "disabled";
507 }; 173 };
508 174
509 i2s_2ch: i2s@10220000 { <<
510 compatible = "rockchip,rk3128- <<
511 reg = <0x10220000 0x1000>; <<
512 interrupts = <GIC_SPI 19 IRQ_T <<
513 clocks = <&cru SCLK_I2S1>, <&c <<
514 clock-names = "i2s_clk", "i2s_ <<
515 dmas = <&pdma 0>, <&pdma 1>; <<
516 dma-names = "tx", "rx"; <<
517 rockchip,playback-channels = < <<
518 pinctrl-names = "default"; <<
519 pinctrl-0 = <&i2s_bus>; <<
520 #sound-dai-cells = <0>; <<
521 status = "disabled"; <<
522 }; <<
523 <<
524 nfc: nand-controller@10500000 { 175 nfc: nand-controller@10500000 {
525 compatible = "rockchip,rk3128- 176 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
526 reg = <0x10500000 0x4000>; 177 reg = <0x10500000 0x4000>;
527 interrupts = <GIC_SPI 18 IRQ_T 178 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cru HCLK_NANDC>, <& 179 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
529 clock-names = "ahb", "nfc"; 180 clock-names = "ahb", "nfc";
530 pinctrl-names = "default"; 181 pinctrl-names = "default";
531 pinctrl-0 = <&flash_ale &flash 182 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
532 &flash_dqs &flash 183 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
533 status = "disabled"; 184 status = "disabled";
534 }; 185 };
535 186
536 cru: clock-controller@20000000 { 187 cru: clock-controller@20000000 {
537 compatible = "rockchip,rk3128- 188 compatible = "rockchip,rk3128-cru";
538 reg = <0x20000000 0x1000>; 189 reg = <0x20000000 0x1000>;
539 clocks = <&xin24m>; 190 clocks = <&xin24m>;
540 clock-names = "xin24m"; 191 clock-names = "xin24m";
541 rockchip,grf = <&grf>; 192 rockchip,grf = <&grf>;
542 #clock-cells = <1>; 193 #clock-cells = <1>;
543 #reset-cells = <1>; 194 #reset-cells = <1>;
544 assigned-clocks = <&cru PLL_GP 195 assigned-clocks = <&cru PLL_GPLL>;
545 assigned-clock-rates = <594000 196 assigned-clock-rates = <594000000>;
546 }; 197 };
547 198
548 grf: syscon@20008000 { 199 grf: syscon@20008000 {
549 compatible = "rockchip,rk3128- 200 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
550 reg = <0x20008000 0x1000>; 201 reg = <0x20008000 0x1000>;
551 #address-cells = <1>; 202 #address-cells = <1>;
552 #size-cells = <1>; 203 #size-cells = <1>;
553 204
554 usb2phy: usb2phy@17c { 205 usb2phy: usb2phy@17c {
555 compatible = "rockchip 206 compatible = "rockchip,rk3128-usb2phy";
556 reg = <0x017c 0x0c>; 207 reg = <0x017c 0x0c>;
557 clocks = <&cru SCLK_OT 208 clocks = <&cru SCLK_OTGPHY0>;
558 clock-names = "phyclk" 209 clock-names = "phyclk";
559 clock-output-names = " 210 clock-output-names = "usb480m_phy";
560 assigned-clocks = <&cr <<
561 assigned-clock-parents <<
562 #clock-cells = <0>; 211 #clock-cells = <0>;
563 status = "disabled"; 212 status = "disabled";
564 213
565 usb2phy_host: host-por 214 usb2phy_host: host-port {
566 interrupts = < 215 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-name 216 interrupt-names = "linestate";
568 #phy-cells = < 217 #phy-cells = <0>;
569 status = "disa 218 status = "disabled";
570 }; 219 };
571 220
572 usb2phy_otg: otg-port 221 usb2phy_otg: otg-port {
573 interrupts = < 222 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
574 < 223 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
575 < 224 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-name 225 interrupt-names = "otg-bvalid", "otg-id",
577 226 "linestate";
578 #phy-cells = < 227 #phy-cells = <0>;
579 status = "disa 228 status = "disabled";
580 }; 229 };
581 }; 230 };
582 }; 231 };
583 232
584 hdmi: hdmi@20034000 { <<
585 compatible = "rockchip,rk3128- <<
586 reg = <0x20034000 0x4000>; <<
587 interrupts = <GIC_SPI 45 IRQ_T <<
588 clocks = <&cru PCLK_HDMI>, <&c <<
589 clock-names = "pclk", "ref"; <<
590 pinctrl-names = "default"; <<
591 pinctrl-0 = <&hdmii2c_xfer &hd <<
592 power-domains = <&power RK3128 <<
593 #sound-dai-cells = <0>; <<
594 status = "disabled"; <<
595 <<
596 ports { <<
597 #address-cells = <1>; <<
598 #size-cells = <0>; <<
599 <<
600 hdmi_in: port@0 { <<
601 reg = <0>; <<
602 hdmi_in_vop: e <<
603 remote <<
604 }; <<
605 }; <<
606 <<
607 hdmi_out: port@1 { <<
608 reg = <1>; <<
609 }; <<
610 }; <<
611 }; <<
612 <<
613 dphy: phy@20038000 { <<
614 compatible = "rockchip,rk3128- <<
615 reg = <0x20038000 0x4000>; <<
616 clocks = <&cru SCLK_MIPI_24M>, <<
617 clock-names = "ref", "pclk"; <<
618 #phy-cells = <0>; <<
619 power-domains = <&power RK3128 <<
620 resets = <&cru SRST_MIPIPHY_P> <<
621 reset-names = "apb"; <<
622 status = "disabled"; <<
623 }; <<
624 <<
625 timer0: timer@20044000 { 233 timer0: timer@20044000 {
626 compatible = "rockchip,rk3128- 234 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
627 reg = <0x20044000 0x20>; 235 reg = <0x20044000 0x20>;
628 interrupts = <GIC_SPI 28 IRQ_T 236 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru PCLK_TIMER>, <& 237 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
630 clock-names = "pclk", "timer"; 238 clock-names = "pclk", "timer";
631 }; 239 };
632 240
633 timer1: timer@20044020 { 241 timer1: timer@20044020 {
634 compatible = "rockchip,rk3128- 242 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
635 reg = <0x20044020 0x20>; 243 reg = <0x20044020 0x20>;
636 interrupts = <GIC_SPI 29 IRQ_T 244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru PCLK_TIMER>, <& 245 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
638 clock-names = "pclk", "timer"; 246 clock-names = "pclk", "timer";
639 }; 247 };
640 248
641 timer2: timer@20044040 { 249 timer2: timer@20044040 {
642 compatible = "rockchip,rk3128- 250 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
643 reg = <0x20044040 0x20>; 251 reg = <0x20044040 0x20>;
644 interrupts = <GIC_SPI 59 IRQ_T 252 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru PCLK_TIMER>, <& 253 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
646 clock-names = "pclk", "timer"; 254 clock-names = "pclk", "timer";
647 }; 255 };
648 256
649 timer3: timer@20044060 { 257 timer3: timer@20044060 {
650 compatible = "rockchip,rk3128- 258 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
651 reg = <0x20044060 0x20>; 259 reg = <0x20044060 0x20>;
652 interrupts = <GIC_SPI 60 IRQ_T 260 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru PCLK_TIMER>, <& 261 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
654 clock-names = "pclk", "timer"; 262 clock-names = "pclk", "timer";
655 }; 263 };
656 264
657 timer4: timer@20044080 { 265 timer4: timer@20044080 {
658 compatible = "rockchip,rk3128- 266 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
659 reg = <0x20044080 0x20>; 267 reg = <0x20044080 0x20>;
660 interrupts = <GIC_SPI 61 IRQ_T 268 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cru PCLK_TIMER>, <& 269 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
662 clock-names = "pclk", "timer"; 270 clock-names = "pclk", "timer";
663 }; 271 };
664 272
665 timer5: timer@200440a0 { 273 timer5: timer@200440a0 {
666 compatible = "rockchip,rk3128- 274 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
667 reg = <0x200440a0 0x20>; 275 reg = <0x200440a0 0x20>;
668 interrupts = <GIC_SPI 62 IRQ_T 276 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru PCLK_TIMER>, <& 277 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
670 clock-names = "pclk", "timer"; 278 clock-names = "pclk", "timer";
671 }; 279 };
672 280
673 watchdog: watchdog@2004c000 { 281 watchdog: watchdog@2004c000 {
674 compatible = "rockchip,rk3128- 282 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
675 reg = <0x2004c000 0x100>; 283 reg = <0x2004c000 0x100>;
676 interrupts = <GIC_SPI 34 IRQ_T 284 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cru PCLK_WDT>; 285 clocks = <&cru PCLK_WDT>;
678 status = "disabled"; 286 status = "disabled";
679 }; 287 };
680 288
681 pwm0: pwm@20050000 { 289 pwm0: pwm@20050000 {
682 compatible = "rockchip,rk3128- 290 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
683 reg = <0x20050000 0x10>; 291 reg = <0x20050000 0x10>;
684 clocks = <&cru PCLK_PWM>; 292 clocks = <&cru PCLK_PWM>;
685 pinctrl-names = "default"; 293 pinctrl-names = "default";
686 pinctrl-0 = <&pwm0_pin>; 294 pinctrl-0 = <&pwm0_pin>;
687 #pwm-cells = <3>; 295 #pwm-cells = <3>;
688 status = "disabled"; 296 status = "disabled";
689 }; 297 };
690 298
691 pwm1: pwm@20050010 { 299 pwm1: pwm@20050010 {
692 compatible = "rockchip,rk3128- 300 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
693 reg = <0x20050010 0x10>; 301 reg = <0x20050010 0x10>;
694 clocks = <&cru PCLK_PWM>; 302 clocks = <&cru PCLK_PWM>;
695 pinctrl-names = "default"; 303 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>; 304 pinctrl-0 = <&pwm1_pin>;
697 #pwm-cells = <3>; 305 #pwm-cells = <3>;
698 status = "disabled"; 306 status = "disabled";
699 }; 307 };
700 308
701 pwm2: pwm@20050020 { 309 pwm2: pwm@20050020 {
702 compatible = "rockchip,rk3128- 310 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
703 reg = <0x20050020 0x10>; 311 reg = <0x20050020 0x10>;
704 clocks = <&cru PCLK_PWM>; 312 clocks = <&cru PCLK_PWM>;
705 pinctrl-names = "default"; 313 pinctrl-names = "default";
706 pinctrl-0 = <&pwm2_pin>; 314 pinctrl-0 = <&pwm2_pin>;
707 #pwm-cells = <3>; 315 #pwm-cells = <3>;
708 status = "disabled"; 316 status = "disabled";
709 }; 317 };
710 318
711 pwm3: pwm@20050030 { 319 pwm3: pwm@20050030 {
712 compatible = "rockchip,rk3128- 320 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
713 reg = <0x20050030 0x10>; 321 reg = <0x20050030 0x10>;
714 clocks = <&cru PCLK_PWM>; 322 clocks = <&cru PCLK_PWM>;
715 pinctrl-names = "default"; 323 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3_pin>; 324 pinctrl-0 = <&pwm3_pin>;
717 #pwm-cells = <3>; 325 #pwm-cells = <3>;
718 status = "disabled"; 326 status = "disabled";
719 }; 327 };
720 328
721 i2c1: i2c@20056000 { 329 i2c1: i2c@20056000 {
722 compatible = "rockchip,rk3128- 330 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
723 reg = <0x20056000 0x1000>; 331 reg = <0x20056000 0x1000>;
724 interrupts = <GIC_SPI 25 IRQ_T 332 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
725 clock-names = "i2c"; 333 clock-names = "i2c";
726 clocks = <&cru PCLK_I2C1>; 334 clocks = <&cru PCLK_I2C1>;
727 pinctrl-names = "default"; 335 pinctrl-names = "default";
728 pinctrl-0 = <&i2c1_xfer>; 336 pinctrl-0 = <&i2c1_xfer>;
729 #address-cells = <1>; 337 #address-cells = <1>;
730 #size-cells = <0>; 338 #size-cells = <0>;
731 status = "disabled"; 339 status = "disabled";
732 }; 340 };
733 341
734 i2c2: i2c@2005a000 { 342 i2c2: i2c@2005a000 {
735 compatible = "rockchip,rk3128- 343 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
736 reg = <0x2005a000 0x1000>; 344 reg = <0x2005a000 0x1000>;
737 interrupts = <GIC_SPI 26 IRQ_T 345 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
738 clock-names = "i2c"; 346 clock-names = "i2c";
739 clocks = <&cru PCLK_I2C2>; 347 clocks = <&cru PCLK_I2C2>;
740 pinctrl-names = "default"; 348 pinctrl-names = "default";
741 pinctrl-0 = <&i2c2_xfer>; 349 pinctrl-0 = <&i2c2_xfer>;
742 #address-cells = <1>; 350 #address-cells = <1>;
743 #size-cells = <0>; 351 #size-cells = <0>;
744 status = "disabled"; 352 status = "disabled";
745 }; 353 };
746 354
747 i2c3: i2c@2005e000 { 355 i2c3: i2c@2005e000 {
748 compatible = "rockchip,rk3128- 356 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
749 reg = <0x2005e000 0x1000>; 357 reg = <0x2005e000 0x1000>;
750 interrupts = <GIC_SPI 27 IRQ_T 358 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
751 clock-names = "i2c"; 359 clock-names = "i2c";
752 clocks = <&cru PCLK_I2C3>; 360 clocks = <&cru PCLK_I2C3>;
753 pinctrl-names = "default"; 361 pinctrl-names = "default";
754 pinctrl-0 = <&i2c3_xfer>; 362 pinctrl-0 = <&i2c3_xfer>;
755 #address-cells = <1>; 363 #address-cells = <1>;
756 #size-cells = <0>; 364 #size-cells = <0>;
757 status = "disabled"; 365 status = "disabled";
758 }; 366 };
759 367
760 uart0: serial@20060000 { 368 uart0: serial@20060000 {
761 compatible = "rockchip,rk3128- 369 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
762 reg = <0x20060000 0x100>; 370 reg = <0x20060000 0x100>;
763 interrupts = <GIC_SPI 20 IRQ_T 371 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
764 clock-frequency = <24000000>; 372 clock-frequency = <24000000>;
765 clocks = <&cru SCLK_UART0>, <& 373 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
766 clock-names = "baudclk", "apb_ 374 clock-names = "baudclk", "apb_pclk";
767 dmas = <&pdma 2>, <&pdma 3>; 375 dmas = <&pdma 2>, <&pdma 3>;
768 dma-names = "tx", "rx"; 376 dma-names = "tx", "rx";
769 pinctrl-names = "default"; 377 pinctrl-names = "default";
770 pinctrl-0 = <&uart0_xfer &uart 378 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
771 reg-io-width = <4>; 379 reg-io-width = <4>;
772 reg-shift = <2>; 380 reg-shift = <2>;
773 status = "disabled"; 381 status = "disabled";
774 }; 382 };
775 383
776 uart1: serial@20064000 { 384 uart1: serial@20064000 {
777 compatible = "rockchip,rk3128- 385 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
778 reg = <0x20064000 0x100>; 386 reg = <0x20064000 0x100>;
779 interrupts = <GIC_SPI 21 IRQ_T 387 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
780 clock-frequency = <24000000>; 388 clock-frequency = <24000000>;
781 clocks = <&cru SCLK_UART1>, <& 389 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
782 clock-names = "baudclk", "apb_ 390 clock-names = "baudclk", "apb_pclk";
783 dmas = <&pdma 4>, <&pdma 5>; 391 dmas = <&pdma 4>, <&pdma 5>;
784 dma-names = "tx", "rx"; 392 dma-names = "tx", "rx";
785 pinctrl-names = "default"; 393 pinctrl-names = "default";
786 pinctrl-0 = <&uart1_xfer>; 394 pinctrl-0 = <&uart1_xfer>;
787 reg-io-width = <4>; 395 reg-io-width = <4>;
788 reg-shift = <2>; 396 reg-shift = <2>;
789 status = "disabled"; 397 status = "disabled";
790 }; 398 };
791 399
792 uart2: serial@20068000 { 400 uart2: serial@20068000 {
793 compatible = "rockchip,rk3128- 401 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
794 reg = <0x20068000 0x100>; 402 reg = <0x20068000 0x100>;
795 interrupts = <GIC_SPI 22 IRQ_T 403 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
796 clock-frequency = <24000000>; 404 clock-frequency = <24000000>;
797 clocks = <&cru SCLK_UART2>, <& 405 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
798 clock-names = "baudclk", "apb_ 406 clock-names = "baudclk", "apb_pclk";
799 dmas = <&pdma 6>, <&pdma 7>; 407 dmas = <&pdma 6>, <&pdma 7>;
800 dma-names = "tx", "rx"; 408 dma-names = "tx", "rx";
801 pinctrl-names = "default"; 409 pinctrl-names = "default";
802 pinctrl-0 = <&uart2_xfer>; 410 pinctrl-0 = <&uart2_xfer>;
803 reg-io-width = <4>; 411 reg-io-width = <4>;
804 reg-shift = <2>; 412 reg-shift = <2>;
805 status = "disabled"; 413 status = "disabled";
806 }; 414 };
807 415
808 saradc: saradc@2006c000 { 416 saradc: saradc@2006c000 {
809 compatible = "rockchip,saradc" 417 compatible = "rockchip,saradc";
810 reg = <0x2006c000 0x100>; 418 reg = <0x2006c000 0x100>;
811 interrupts = <GIC_SPI 17 IRQ_T 419 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cru SCLK_SARADC>, < 420 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
813 clock-names = "saradc", "apb_p 421 clock-names = "saradc", "apb_pclk";
814 resets = <&cru SRST_SARADC>; 422 resets = <&cru SRST_SARADC>;
815 reset-names = "saradc-apb"; 423 reset-names = "saradc-apb";
816 #io-channel-cells = <1>; 424 #io-channel-cells = <1>;
817 status = "disabled"; 425 status = "disabled";
818 }; 426 };
819 427
820 i2c0: i2c@20072000 { 428 i2c0: i2c@20072000 {
821 compatible = "rockchip,rk3128- 429 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
822 reg = <0x20072000 0x1000>; 430 reg = <0x20072000 0x1000>;
823 interrupts = <GIC_SPI 24 IRQ_T 431 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
824 clock-names = "i2c"; 432 clock-names = "i2c";
825 clocks = <&cru PCLK_I2C0>; 433 clocks = <&cru PCLK_I2C0>;
826 pinctrl-names = "default"; 434 pinctrl-names = "default";
827 pinctrl-0 = <&i2c0_xfer>; 435 pinctrl-0 = <&i2c0_xfer>;
828 #address-cells = <1>; 436 #address-cells = <1>;
829 #size-cells = <0>; 437 #size-cells = <0>;
830 status = "disabled"; 438 status = "disabled";
831 }; 439 };
832 440
833 spi0: spi@20074000 { 441 spi0: spi@20074000 {
834 compatible = "rockchip,rk3128- 442 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
835 reg = <0x20074000 0x1000>; 443 reg = <0x20074000 0x1000>;
836 interrupts = <GIC_SPI 23 IRQ_T 444 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&cru SCLK_SPI0>, <&c 445 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
838 clock-names = "spiclk", "apb_p 446 clock-names = "spiclk", "apb_pclk";
839 dmas = <&pdma 8>, <&pdma 9>; 447 dmas = <&pdma 8>, <&pdma 9>;
840 dma-names = "tx", "rx"; 448 dma-names = "tx", "rx";
841 pinctrl-names = "default"; 449 pinctrl-names = "default";
842 pinctrl-0 = <&spi0_tx &spi0_rx 450 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
843 #address-cells = <1>; 451 #address-cells = <1>;
844 #size-cells = <0>; 452 #size-cells = <0>;
845 status = "disabled"; 453 status = "disabled";
846 }; 454 };
847 455
848 pdma: dma-controller@20078000 { 456 pdma: dma-controller@20078000 {
849 compatible = "arm,pl330", "arm 457 compatible = "arm,pl330", "arm,primecell";
850 reg = <0x20078000 0x4000>; 458 reg = <0x20078000 0x4000>;
851 interrupts = <GIC_SPI 0 IRQ_TY 459 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 1 IRQ_TY 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
853 arm,pl330-broken-no-flushp; 461 arm,pl330-broken-no-flushp;
854 arm,pl330-periph-burst; 462 arm,pl330-periph-burst;
855 clocks = <&cru ACLK_DMAC>; 463 clocks = <&cru ACLK_DMAC>;
856 clock-names = "apb_pclk"; 464 clock-names = "apb_pclk";
857 #dma-cells = <1>; 465 #dma-cells = <1>;
858 }; 466 };
859 467
860 gmac: ethernet@2008c000 { <<
861 compatible = "rockchip,rk3128- <<
862 reg = <0x2008c000 0x4000>; <<
863 interrupts = <GIC_SPI 56 IRQ_T <<
864 <GIC_SPI 57 IRQ_T <<
865 interrupt-names = "macirq", "e <<
866 clocks = <&cru SCLK_MAC>, <<
867 <&cru SCLK_MAC_RX>, < <<
868 <&cru SCLK_MAC_REF>, <<
869 <&cru ACLK_GMAC>, <&c <<
870 clock-names = "stmmaceth", <<
871 "mac_clk_rx", "m <<
872 "clk_mac_ref", " <<
873 "aclk_mac", "pcl <<
874 resets = <&cru SRST_GMAC>; <<
875 reset-names = "stmmaceth"; <<
876 rockchip,grf = <&grf>; <<
877 rx-fifo-depth = <4096>; <<
878 tx-fifo-depth = <2048>; <<
879 status = "disabled"; <<
880 <<
881 mdio: mdio { <<
882 compatible = "snps,dwm <<
883 #address-cells = <0x1> <<
884 #size-cells = <0x0>; <<
885 }; <<
886 }; <<
887 <<
888 pinctrl: pinctrl { 468 pinctrl: pinctrl {
889 compatible = "rockchip,rk3128- 469 compatible = "rockchip,rk3128-pinctrl";
890 rockchip,grf = <&grf>; 470 rockchip,grf = <&grf>;
891 #address-cells = <1>; 471 #address-cells = <1>;
892 #size-cells = <1>; 472 #size-cells = <1>;
893 ranges; 473 ranges;
894 474
895 gpio0: gpio@2007c000 { 475 gpio0: gpio@2007c000 {
896 compatible = "rockchip 476 compatible = "rockchip,gpio-bank";
897 reg = <0x2007c000 0x10 477 reg = <0x2007c000 0x100>;
898 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cru PCLK_GP 479 clocks = <&cru PCLK_GPIO0>;
900 gpio-controller; 480 gpio-controller;
901 #gpio-cells = <2>; 481 #gpio-cells = <2>;
902 interrupt-controller; 482 interrupt-controller;
903 #interrupt-cells = <2> 483 #interrupt-cells = <2>;
904 }; 484 };
905 485
906 gpio1: gpio@20080000 { 486 gpio1: gpio@20080000 {
907 compatible = "rockchip 487 compatible = "rockchip,gpio-bank";
908 reg = <0x20080000 0x10 488 reg = <0x20080000 0x100>;
909 interrupts = <GIC_SPI 489 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&cru PCLK_GP 490 clocks = <&cru PCLK_GPIO1>;
911 gpio-controller; 491 gpio-controller;
912 #gpio-cells = <2>; 492 #gpio-cells = <2>;
913 interrupt-controller; 493 interrupt-controller;
914 #interrupt-cells = <2> 494 #interrupt-cells = <2>;
915 }; 495 };
916 496
917 gpio2: gpio@20084000 { 497 gpio2: gpio@20084000 {
918 compatible = "rockchip 498 compatible = "rockchip,gpio-bank";
919 reg = <0x20084000 0x10 499 reg = <0x20084000 0x100>;
920 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cru PCLK_GP 501 clocks = <&cru PCLK_GPIO2>;
922 gpio-controller; 502 gpio-controller;
923 #gpio-cells = <2>; 503 #gpio-cells = <2>;
924 interrupt-controller; 504 interrupt-controller;
925 #interrupt-cells = <2> 505 #interrupt-cells = <2>;
926 }; 506 };
927 507
928 gpio3: gpio@20088000 { 508 gpio3: gpio@20088000 {
929 compatible = "rockchip 509 compatible = "rockchip,gpio-bank";
930 reg = <0x20088000 0x10 510 reg = <0x20088000 0x100>;
931 interrupts = <GIC_SPI 511 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&cru PCLK_GP 512 clocks = <&cru PCLK_GPIO3>;
933 gpio-controller; 513 gpio-controller;
934 #gpio-cells = <2>; 514 #gpio-cells = <2>;
935 interrupt-controller; 515 interrupt-controller;
936 #interrupt-cells = <2> 516 #interrupt-cells = <2>;
937 }; 517 };
938 518
939 pcfg_pull_default: pcfg-pull-d 519 pcfg_pull_default: pcfg-pull-default {
940 bias-pull-pin-default; 520 bias-pull-pin-default;
941 }; 521 };
942 522
943 pcfg_pull_none: pcfg-pull-none 523 pcfg_pull_none: pcfg-pull-none {
944 bias-disable; 524 bias-disable;
945 }; 525 };
946 526
947 emmc { 527 emmc {
948 emmc_clk: emmc-clk { 528 emmc_clk: emmc-clk {
949 rockchip,pins 529 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
950 }; 530 };
951 531
952 emmc_cmd: emmc-cmd { 532 emmc_cmd: emmc-cmd {
953 rockchip,pins 533 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
954 }; 534 };
955 535
956 emmc_cmd1: emmc-cmd1 { 536 emmc_cmd1: emmc-cmd1 {
957 rockchip,pins 537 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
958 }; 538 };
959 539
960 emmc_pwr: emmc-pwr { 540 emmc_pwr: emmc-pwr {
961 rockchip,pins 541 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
962 }; 542 };
963 543
964 emmc_bus1: emmc-bus1 { 544 emmc_bus1: emmc-bus1 {
965 rockchip,pins 545 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
966 }; 546 };
967 547
968 emmc_bus4: emmc-bus4 { 548 emmc_bus4: emmc-bus4 {
969 rockchip,pins 549 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
970 550 <1 RK_PD1 2 &pcfg_pull_default>,
971 551 <1 RK_PD2 2 &pcfg_pull_default>,
972 552 <1 RK_PD3 2 &pcfg_pull_default>;
973 }; 553 };
974 554
975 emmc_bus8: emmc-bus8 { 555 emmc_bus8: emmc-bus8 {
976 rockchip,pins 556 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
977 557 <1 RK_PD1 2 &pcfg_pull_default>,
978 558 <1 RK_PD2 2 &pcfg_pull_default>,
979 559 <1 RK_PD3 2 &pcfg_pull_default>,
980 560 <1 RK_PD4 2 &pcfg_pull_default>,
981 561 <1 RK_PD5 2 &pcfg_pull_default>,
982 562 <1 RK_PD6 2 &pcfg_pull_default>,
983 563 <1 RK_PD7 2 &pcfg_pull_default>;
984 }; 564 };
985 }; 565 };
986 566
987 gmac { 567 gmac {
988 rgmii_pins: rgmii-pins 568 rgmii_pins: rgmii-pins {
989 rockchip,pins 569 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
990 570 <2 RK_PB1 3 &pcfg_pull_default>,
991 571 <2 RK_PB3 3 &pcfg_pull_default>,
992 572 <2 RK_PB4 3 &pcfg_pull_default>,
993 573 <2 RK_PB5 3 &pcfg_pull_default>,
994 574 <2 RK_PB6 3 &pcfg_pull_default>,
995 575 <2 RK_PC0 3 &pcfg_pull_default>,
996 576 <2 RK_PC1 3 &pcfg_pull_default>,
997 577 <2 RK_PC2 3 &pcfg_pull_default>,
998 578 <2 RK_PC3 3 &pcfg_pull_default>,
999 579 <2 RK_PD1 3 &pcfg_pull_default>,
1000 580 <2 RK_PC4 4 &pcfg_pull_default>,
1001 581 <2 RK_PC5 4 &pcfg_pull_default>,
1002 582 <2 RK_PC6 4 &pcfg_pull_default>,
1003 583 <2 RK_PC7 4 &pcfg_pull_default>;
1004 }; 584 };
1005 585
1006 rmii_pins: rmii-pins 586 rmii_pins: rmii-pins {
1007 rockchip,pins 587 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
1008 588 <2 RK_PB4 3 &pcfg_pull_default>,
1009 589 <2 RK_PB5 3 &pcfg_pull_default>,
1010 590 <2 RK_PB6 3 &pcfg_pull_default>,
1011 591 <2 RK_PB7 3 &pcfg_pull_default>,
1012 592 <2 RK_PC0 3 &pcfg_pull_default>,
1013 593 <2 RK_PC1 3 &pcfg_pull_default>,
1014 594 <2 RK_PC2 3 &pcfg_pull_default>,
1015 595 <2 RK_PC3 3 &pcfg_pull_default>,
1016 596 <2 RK_PD1 3 &pcfg_pull_default>;
1017 }; 597 };
1018 }; 598 };
1019 599
1020 hdmi { 600 hdmi {
1021 hdmii2c_xfer: hdmii2c 601 hdmii2c_xfer: hdmii2c-xfer {
1022 rockchip,pins 602 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1023 603 <0 RK_PA7 2 &pcfg_pull_none>;
1024 }; 604 };
1025 605
1026 hdmi_hpd: hdmi-hpd { 606 hdmi_hpd: hdmi-hpd {
1027 rockchip,pins 607 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1028 }; 608 };
1029 609
1030 hdmi_cec: hdmi-cec { 610 hdmi_cec: hdmi-cec {
1031 rockchip,pins 611 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1032 }; 612 };
1033 }; 613 };
1034 614
1035 i2c0 { 615 i2c0 {
1036 i2c0_xfer: i2c0-xfer 616 i2c0_xfer: i2c0-xfer {
1037 rockchip,pins 617 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1038 618 <0 RK_PA1 1 &pcfg_pull_none>;
1039 }; 619 };
1040 }; 620 };
1041 621
1042 i2c1 { 622 i2c1 {
1043 i2c1_xfer: i2c1-xfer 623 i2c1_xfer: i2c1-xfer {
1044 rockchip,pins 624 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1045 625 <0 RK_PA3 1 &pcfg_pull_none>;
1046 }; 626 };
1047 }; 627 };
1048 628
1049 i2c2 { 629 i2c2 {
1050 i2c2_xfer: i2c2-xfer 630 i2c2_xfer: i2c2-xfer {
1051 rockchip,pins 631 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
1052 632 <2 RK_PC5 3 &pcfg_pull_none>;
1053 }; 633 };
1054 }; 634 };
1055 635
1056 i2c3 { 636 i2c3 {
1057 i2c3_xfer: i2c3-xfer 637 i2c3_xfer: i2c3-xfer {
1058 rockchip,pins 638 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1059 639 <0 RK_PA7 1 &pcfg_pull_none>;
1060 }; 640 };
1061 }; 641 };
1062 642
1063 i2s { 643 i2s {
1064 i2s_bus: i2s-bus { 644 i2s_bus: i2s-bus {
1065 rockchip,pins 645 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1066 646 <0 RK_PB1 1 &pcfg_pull_none>,
1067 647 <0 RK_PB3 1 &pcfg_pull_none>,
1068 648 <0 RK_PB4 1 &pcfg_pull_none>,
1069 649 <0 RK_PB5 1 &pcfg_pull_none>,
1070 650 <0 RK_PB6 1 &pcfg_pull_none>;
1071 }; 651 };
1072 652
1073 i2s1_bus: i2s1-bus { 653 i2s1_bus: i2s1-bus {
1074 rockchip,pins 654 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
1075 655 <1 RK_PA1 1 &pcfg_pull_none>,
1076 656 <1 RK_PA2 1 &pcfg_pull_none>,
1077 657 <1 RK_PA3 1 &pcfg_pull_none>,
1078 658 <1 RK_PA4 1 &pcfg_pull_none>,
1079 659 <1 RK_PA5 1 &pcfg_pull_none>;
1080 }; 660 };
1081 }; 661 };
1082 662
1083 lcdc { 663 lcdc {
1084 lcdc_dclk: lcdc-dclk 664 lcdc_dclk: lcdc-dclk {
1085 rockchip,pins 665 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
1086 }; 666 };
1087 667
1088 lcdc_den: lcdc-den { 668 lcdc_den: lcdc-den {
1089 rockchip,pins 669 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
1090 }; 670 };
1091 671
1092 lcdc_hsync: lcdc-hsyn 672 lcdc_hsync: lcdc-hsync {
1093 rockchip,pins 673 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1094 }; 674 };
1095 675
1096 lcdc_vsync: lcdc-vsyn 676 lcdc_vsync: lcdc-vsync {
1097 rockchip,pins 677 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
1098 }; 678 };
1099 679
1100 lcdc_rgb24: lcdc-rgb2 680 lcdc_rgb24: lcdc-rgb24 {
1101 rockchip,pins 681 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1102 682 <2 RK_PB5 1 &pcfg_pull_none>,
1103 683 <2 RK_PB6 1 &pcfg_pull_none>,
1104 684 <2 RK_PB7 1 &pcfg_pull_none>,
1105 685 <2 RK_PC0 1 &pcfg_pull_none>,
1106 686 <2 RK_PC1 1 &pcfg_pull_none>,
1107 687 <2 RK_PC2 1 &pcfg_pull_none>,
1108 688 <2 RK_PC3 1 &pcfg_pull_none>,
1109 689 <2 RK_PC4 1 &pcfg_pull_none>,
1110 690 <2 RK_PC5 1 &pcfg_pull_none>,
1111 691 <2 RK_PC6 1 &pcfg_pull_none>,
1112 692 <2 RK_PC7 1 &pcfg_pull_none>,
1113 693 <2 RK_PD0 1 &pcfg_pull_none>,
1114 694 <2 RK_PD1 1 &pcfg_pull_none>;
1115 }; 695 };
1116 }; 696 };
1117 697
1118 nfc { 698 nfc {
1119 flash_ale: flash-ale 699 flash_ale: flash-ale {
1120 rockchip,pins 700 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
1121 }; 701 };
1122 702
1123 flash_cle: flash-cle 703 flash_cle: flash-cle {
1124 rockchip,pins 704 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
1125 }; 705 };
1126 706
1127 flash_wrn: flash-wrn 707 flash_wrn: flash-wrn {
1128 rockchip,pins 708 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1129 }; 709 };
1130 710
1131 flash_rdn: flash-rdn 711 flash_rdn: flash-rdn {
1132 rockchip,pins 712 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
1133 }; 713 };
1134 714
1135 flash_rdy: flash-rdy 715 flash_rdy: flash-rdy {
1136 rockchip,pins 716 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1137 }; 717 };
1138 718
1139 flash_cs0: flash-cs0 719 flash_cs0: flash-cs0 {
1140 rockchip,pins 720 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1141 }; 721 };
1142 722
1143 flash_dqs: flash-dqs 723 flash_dqs: flash-dqs {
1144 rockchip,pins 724 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
1145 }; 725 };
1146 726
1147 flash_bus8: flash-bus 727 flash_bus8: flash-bus8 {
1148 rockchip,pins 728 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1149 729 <1 RK_PD1 1 &pcfg_pull_none>,
1150 730 <1 RK_PD2 1 &pcfg_pull_none>,
1151 731 <1 RK_PD3 1 &pcfg_pull_none>,
1152 732 <1 RK_PD4 1 &pcfg_pull_none>,
1153 733 <1 RK_PD5 1 &pcfg_pull_none>,
1154 734 <1 RK_PD6 1 &pcfg_pull_none>,
1155 735 <1 RK_PD7 1 &pcfg_pull_none>;
1156 }; 736 };
1157 }; 737 };
1158 738
1159 pwm0 { 739 pwm0 {
1160 pwm0_pin: pwm0-pin { 740 pwm0_pin: pwm0-pin {
1161 rockchip,pins 741 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1162 }; 742 };
1163 }; 743 };
1164 744
1165 pwm1 { 745 pwm1 {
1166 pwm1_pin: pwm1-pin { 746 pwm1_pin: pwm1-pin {
1167 rockchip,pins 747 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1168 }; 748 };
1169 }; 749 };
1170 750
1171 pwm2 { 751 pwm2 {
1172 pwm2_pin: pwm2-pin { 752 pwm2_pin: pwm2-pin {
1173 rockchip,pins 753 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1174 }; 754 };
1175 }; 755 };
1176 756
1177 pwm3 { 757 pwm3 {
1178 pwm3_pin: pwm3-pin { 758 pwm3_pin: pwm3-pin {
1179 rockchip,pins 759 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
1180 }; 760 };
1181 }; 761 };
1182 762
1183 sdio { 763 sdio {
1184 sdio_clk: sdio-clk { 764 sdio_clk: sdio-clk {
1185 rockchip,pins 765 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1186 }; 766 };
1187 767
1188 sdio_cmd: sdio-cmd { 768 sdio_cmd: sdio-cmd {
1189 rockchip,pins 769 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1190 }; 770 };
1191 771
1192 sdio_pwren: sdio-pwre 772 sdio_pwren: sdio-pwren {
1193 rockchip,pins 773 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1194 }; 774 };
1195 775
1196 sdio_bus4: sdio-bus4 776 sdio_bus4: sdio-bus4 {
1197 rockchip,pins 777 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1198 778 <1 RK_PA2 2 &pcfg_pull_default>,
1199 779 <1 RK_PA4 2 &pcfg_pull_default>,
1200 780 <1 RK_PA5 2 &pcfg_pull_default>;
1201 }; 781 };
1202 }; 782 };
1203 783
1204 sdmmc { 784 sdmmc {
1205 sdmmc_clk: sdmmc-clk 785 sdmmc_clk: sdmmc-clk {
1206 rockchip,pins 786 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1207 }; 787 };
1208 788
1209 sdmmc_cmd: sdmmc-cmd 789 sdmmc_cmd: sdmmc-cmd {
1210 rockchip,pins 790 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1211 }; 791 };
1212 792
1213 sdmmc_det: sdmmc-det <<
1214 rockchip,pins <<
1215 }; <<
1216 <<
1217 sdmmc_wp: sdmmc-wp { 793 sdmmc_wp: sdmmc-wp {
1218 rockchip,pins 794 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1219 }; 795 };
1220 796
1221 sdmmc_pwren: sdmmc-pw 797 sdmmc_pwren: sdmmc-pwren {
1222 rockchip,pins !! 798 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
1223 }; 799 };
1224 800
1225 sdmmc_bus4: sdmmc-bus 801 sdmmc_bus4: sdmmc-bus4 {
1226 rockchip,pins 802 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1227 803 <1 RK_PC3 1 &pcfg_pull_default>,
1228 804 <1 RK_PC4 1 &pcfg_pull_default>,
1229 805 <1 RK_PC5 1 &pcfg_pull_default>;
1230 }; <<
1231 }; <<
1232 <<
1233 sfc { <<
1234 sfc_bus2: sfc-bus2 { <<
1235 rockchip,pins <<
1236 <<
1237 }; <<
1238 <<
1239 sfc_bus4: sfc-bus4 { <<
1240 rockchip,pins <<
1241 <<
1242 <<
1243 <<
1244 }; <<
1245 <<
1246 sfc_clk: sfc-clk { <<
1247 rockchip,pins <<
1248 }; <<
1249 <<
1250 sfc_cs0: sfc-cs0 { <<
1251 rockchip,pins <<
1252 }; <<
1253 <<
1254 sfc_cs1: sfc-cs1 { <<
1255 rockchip,pins <<
1256 }; 806 };
1257 }; 807 };
1258 808
1259 spdif { 809 spdif {
1260 spdif_tx: spdif-tx { 810 spdif_tx: spdif-tx {
1261 rockchip,pins 811 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1262 }; 812 };
1263 }; 813 };
1264 814
1265 spi0 { 815 spi0 {
1266 spi0_clk: spi0-clk { 816 spi0_clk: spi0-clk {
1267 rockchip,pins 817 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1268 }; 818 };
1269 819
1270 spi0_cs0: spi0-cs0 { 820 spi0_cs0: spi0-cs0 {
1271 rockchip,pins 821 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1272 }; 822 };
1273 823
1274 spi0_tx: spi0-tx { 824 spi0_tx: spi0-tx {
1275 rockchip,pins 825 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1276 }; 826 };
1277 827
1278 spi0_rx: spi0-rx { 828 spi0_rx: spi0-rx {
1279 rockchip,pins 829 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1280 }; 830 };
1281 831
1282 spi0_cs1: spi0-cs1 { 832 spi0_cs1: spi0-cs1 {
1283 rockchip,pins 833 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1284 }; 834 };
1285 835
1286 spi1_clk: spi1-clk { 836 spi1_clk: spi1-clk {
1287 rockchip,pins 837 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1288 }; 838 };
1289 839
1290 spi1_cs0: spi1-cs0 { 840 spi1_cs0: spi1-cs0 {
1291 rockchip,pins 841 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1292 }; 842 };
1293 843
1294 spi1_tx: spi1-tx { 844 spi1_tx: spi1-tx {
1295 rockchip,pins 845 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1296 }; 846 };
1297 847
1298 spi1_rx: spi1-rx { 848 spi1_rx: spi1-rx {
1299 rockchip,pins 849 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1300 }; 850 };
1301 851
1302 spi1_cs1: spi1-cs1 { 852 spi1_cs1: spi1-cs1 {
1303 rockchip,pins 853 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1304 }; 854 };
1305 855
1306 spi2_clk: spi2-clk { 856 spi2_clk: spi2-clk {
1307 rockchip,pins 857 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1308 }; 858 };
1309 859
1310 spi2_cs0: spi2-cs0 { 860 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 861 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1312 }; 862 };
1313 863
1314 spi2_tx: spi2-tx { 864 spi2_tx: spi2-tx {
1315 rockchip,pins 865 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1316 }; 866 };
1317 867
1318 spi2_rx: spi2-rx { 868 spi2_rx: spi2-rx {
1319 rockchip,pins 869 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1320 }; 870 };
1321 }; 871 };
1322 872
1323 uart0 { 873 uart0 {
1324 uart0_xfer: uart0-xfe 874 uart0_xfer: uart0-xfer {
1325 rockchip,pins 875 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1326 876 <2 RK_PD3 2 &pcfg_pull_none>;
1327 }; 877 };
1328 878
1329 uart0_cts: uart0-cts 879 uart0_cts: uart0-cts {
1330 rockchip,pins 880 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1331 }; 881 };
1332 882
1333 uart0_rts: uart0-rts 883 uart0_rts: uart0-rts {
1334 rockchip,pins 884 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1335 }; 885 };
1336 }; 886 };
1337 887
1338 uart1 { 888 uart1 {
1339 uart1_xfer: uart1-xfe 889 uart1_xfer: uart1-xfer {
1340 rockchip,pins 890 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1341 891 <1 RK_PB2 2 &pcfg_pull_default>;
1342 }; 892 };
1343 893
1344 uart1_cts: uart1-cts 894 uart1_cts: uart1-cts {
1345 rockchip,pins 895 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1346 }; 896 };
1347 897
1348 uart1_rts: uart1-rts 898 uart1_rts: uart1-rts {
1349 rockchip,pins 899 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1350 }; 900 };
1351 }; 901 };
1352 902
1353 uart2 { 903 uart2 {
1354 uart2_xfer: uart2-xfe 904 uart2_xfer: uart2-xfer {
1355 rockchip,pins 905 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1356 906 <1 RK_PC3 2 &pcfg_pull_none>;
1357 }; 907 };
1358 908
1359 uart2_cts: uart2-cts 909 uart2_cts: uart2-cts {
1360 rockchip,pins 910 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1361 }; 911 };
1362 912
1363 uart2_rts: uart2-rts 913 uart2_rts: uart2-rts {
1364 rockchip,pins 914 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1365 }; 915 };
1366 }; 916 };
1367 }; 917 };
1368 }; 918 };
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