1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co. 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3128-cru.h> 6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h> 11 #include <dt-bindings/power/rk3128-power.h>
12 12
13 / { 13 / {
14 compatible = "rockchip,rk3128"; 14 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 18
19 aliases { 19 aliases {
20 gpio0 = &gpio0; 20 gpio0 = &gpio0;
21 gpio1 = &gpio1; 21 gpio1 = &gpio1;
22 gpio2 = &gpio2; 22 gpio2 = &gpio2;
23 gpio3 = &gpio3; 23 gpio3 = &gpio3;
24 i2c0 = &i2c0; 24 i2c0 = &i2c0;
25 i2c1 = &i2c1; 25 i2c1 = &i2c1;
26 i2c2 = &i2c2; 26 i2c2 = &i2c2;
27 i2c3 = &i2c3; 27 i2c3 = &i2c3;
28 serial0 = &uart0; 28 serial0 = &uart0;
29 serial1 = &uart1; 29 serial1 = &uart1;
30 serial2 = &uart2; 30 serial2 = &uart2;
31 }; 31 };
32 32
33 arm-pmu { 33 arm-pmu {
34 compatible = "arm,cortex-a7-pm 34 compatible = "arm,cortex-a7-pmu";
35 interrupts = <GIC_SPI 76 IRQ_T 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 77 IRQ_T 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 78 IRQ_T 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 79 IRQ_T 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
39 interrupt-affinity = <&cpu0>, 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <1>; 43 #address-cells = <1>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 enable-method = "rockchip,rk30 45 enable-method = "rockchip,rk3036-smp";
46 46
47 cpu0: cpu@f00 { 47 cpu0: cpu@f00 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "arm,cort 49 compatible = "arm,cortex-a7";
50 reg = <0xf00>; 50 reg = <0xf00>;
51 clock-latency = <40000 51 clock-latency = <40000>;
52 clocks = <&cru ARMCLK> 52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CO 53 resets = <&cru SRST_CORE0>;
54 operating-points-v2 = 54 operating-points-v2 = <&cpu_opp_table>;
55 #cooling-cells = <2>; 55 #cooling-cells = <2>; /* min followed by max */
56 }; 56 };
57 57
58 cpu1: cpu@f01 { 58 cpu1: cpu@f01 {
59 device_type = "cpu"; 59 device_type = "cpu";
60 compatible = "arm,cort 60 compatible = "arm,cortex-a7";
61 reg = <0xf01>; 61 reg = <0xf01>;
62 resets = <&cru SRST_CO 62 resets = <&cru SRST_CORE1>;
63 operating-points-v2 = 63 operating-points-v2 = <&cpu_opp_table>;
64 }; 64 };
65 65
66 cpu2: cpu@f02 { 66 cpu2: cpu@f02 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cort 68 compatible = "arm,cortex-a7";
69 reg = <0xf02>; 69 reg = <0xf02>;
70 resets = <&cru SRST_CO 70 resets = <&cru SRST_CORE2>;
71 operating-points-v2 = 71 operating-points-v2 = <&cpu_opp_table>;
72 }; 72 };
73 73
74 cpu3: cpu@f03 { 74 cpu3: cpu@f03 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 compatible = "arm,cort 76 compatible = "arm,cortex-a7";
77 reg = <0xf03>; 77 reg = <0xf03>;
78 resets = <&cru SRST_CO 78 resets = <&cru SRST_CORE3>;
79 operating-points-v2 = 79 operating-points-v2 = <&cpu_opp_table>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu_opp_table: opp-table-0 { 83 cpu_opp_table: opp-table-0 {
84 compatible = "operating-points 84 compatible = "operating-points-v2";
85 opp-shared; 85 opp-shared;
86 86
87 opp-216000000 { 87 opp-216000000 {
88 opp-hz = /bits/ 64 <21 88 opp-hz = /bits/ 64 <216000000>;
89 opp-microvolt = <95000 89 opp-microvolt = <950000 950000 1325000>;
90 }; 90 };
91 opp-408000000 { 91 opp-408000000 {
92 opp-hz = /bits/ 64 <40 92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <95000 93 opp-microvolt = <950000 950000 1325000>;
94 }; 94 };
95 opp-600000000 { 95 opp-600000000 {
96 opp-hz = /bits/ 64 <60 96 opp-hz = /bits/ 64 <600000000>;
97 opp-microvolt = <95000 97 opp-microvolt = <950000 950000 1325000>;
98 }; 98 };
99 opp-696000000 { 99 opp-696000000 {
100 opp-hz = /bits/ 64 <69 100 opp-hz = /bits/ 64 <696000000>;
101 opp-microvolt = <97500 101 opp-microvolt = <975000 975000 1325000>;
102 }; 102 };
103 opp-816000000 { 103 opp-816000000 {
104 opp-hz = /bits/ 64 <81 104 opp-hz = /bits/ 64 <816000000>;
105 opp-microvolt = <10750 105 opp-microvolt = <1075000 1075000 1325000>;
106 opp-suspend; 106 opp-suspend;
107 }; 107 };
108 opp-1008000000 { 108 opp-1008000000 {
109 opp-hz = /bits/ 64 <10 109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <12000 110 opp-microvolt = <1200000 1200000 1325000>;
111 }; 111 };
112 opp-1200000000 { 112 opp-1200000000 {
113 opp-hz = /bits/ 64 <12 113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <13250 114 opp-microvolt = <1325000 1325000 1325000>;
115 }; 115 };
116 }; 116 };
117 117
118 display_subsystem: display-subsystem { <<
119 compatible = "rockchip,display <<
120 ports = <&vop_out>; <<
121 status = "disabled"; <<
122 }; <<
123 <<
124 gpu_opp_table: opp-table-1 { 118 gpu_opp_table: opp-table-1 {
125 compatible = "operating-points 119 compatible = "operating-points-v2";
126 120
127 opp-200000000 { 121 opp-200000000 {
128 opp-hz = /bits/ 64 <20 122 opp-hz = /bits/ 64 <200000000>;
129 opp-microvolt = <97500 123 opp-microvolt = <975000 975000 1250000>;
130 }; 124 };
131 opp-300000000 { 125 opp-300000000 {
132 opp-hz = /bits/ 64 <30 126 opp-hz = /bits/ 64 <300000000>;
133 opp-microvolt = <10500 127 opp-microvolt = <1050000 1050000 1250000>;
134 }; 128 };
135 opp-400000000 { 129 opp-400000000 {
136 opp-hz = /bits/ 64 <40 130 opp-hz = /bits/ 64 <400000000>;
137 opp-microvolt = <11500 131 opp-microvolt = <1150000 1150000 1250000>;
138 }; 132 };
139 opp-480000000 { 133 opp-480000000 {
140 opp-hz = /bits/ 64 <48 134 opp-hz = /bits/ 64 <480000000>;
141 opp-microvolt = <12500 135 opp-microvolt = <1250000 1250000 1250000>;
142 }; 136 };
143 }; 137 };
144 138
145 timer { 139 timer {
146 compatible = "arm,armv7-timer" 140 compatible = "arm,armv7-timer";
147 interrupts = <GIC_PPI 13 (GIC_ 141 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 14 (GIC_ 142 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
149 <GIC_PPI 11 (GIC_ 143 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
150 <GIC_PPI 10 (GIC_ 144 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151 arm,cpu-registers-not-fw-confi 145 arm,cpu-registers-not-fw-configured;
152 clock-frequency = <24000000>; 146 clock-frequency = <24000000>;
153 }; 147 };
154 148
155 xin24m: oscillator { 149 xin24m: oscillator {
156 compatible = "fixed-clock"; 150 compatible = "fixed-clock";
157 clock-frequency = <24000000>; 151 clock-frequency = <24000000>;
158 clock-output-names = "xin24m"; 152 clock-output-names = "xin24m";
159 #clock-cells = <0>; 153 #clock-cells = <0>;
160 }; 154 };
161 155
162 imem: sram@10080000 { 156 imem: sram@10080000 {
163 compatible = "mmio-sram"; 157 compatible = "mmio-sram";
164 reg = <0x10080000 0x2000>; 158 reg = <0x10080000 0x2000>;
165 #address-cells = <1>; 159 #address-cells = <1>;
166 #size-cells = <1>; 160 #size-cells = <1>;
167 ranges = <0 0x10080000 0x2000> 161 ranges = <0 0x10080000 0x2000>;
168 162
169 smp-sram@0 { 163 smp-sram@0 {
170 compatible = "rockchip 164 compatible = "rockchip,rk3066-smp-sram";
171 reg = <0x00 0x10>; 165 reg = <0x00 0x10>;
172 }; 166 };
173 }; 167 };
174 168
175 gpu: gpu@10090000 { 169 gpu: gpu@10090000 {
176 compatible = "rockchip,rk3128- 170 compatible = "rockchip,rk3128-mali", "arm,mali-400";
177 reg = <0x10090000 0x10000>; 171 reg = <0x10090000 0x10000>;
178 interrupts = <GIC_SPI 3 IRQ_TY 172 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 4 IRQ_TY 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 5 IRQ_TY 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 4 IRQ_TY 175 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 5 IRQ_TY 176 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 4 IRQ_TY 177 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "gp", 178 interrupt-names = "gp",
185 "gpmmu", 179 "gpmmu",
186 "pp0", 180 "pp0",
187 "ppmmu0", 181 "ppmmu0",
188 "pp1", 182 "pp1",
189 "ppmmu1"; 183 "ppmmu1";
190 clocks = <&cru ACLK_GPU>, <&cr 184 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
191 clock-names = "bus", "core"; 185 clock-names = "bus", "core";
192 operating-points-v2 = <&gpu_op 186 operating-points-v2 = <&gpu_opp_table>;
193 resets = <&cru SRST_GPU>; 187 resets = <&cru SRST_GPU>;
194 power-domains = <&power RK3128 188 power-domains = <&power RK3128_PD_GPU>;
195 status = "disabled"; 189 status = "disabled";
196 }; 190 };
197 191
198 pmu: syscon@100a0000 { 192 pmu: syscon@100a0000 {
199 compatible = "rockchip,rk3128- 193 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
200 reg = <0x100a0000 0x1000>; 194 reg = <0x100a0000 0x1000>;
201 195
202 power: power-controller { 196 power: power-controller {
203 compatible = "rockchip 197 compatible = "rockchip,rk3128-power-controller";
204 #power-domain-cells = 198 #power-domain-cells = <1>;
205 #address-cells = <1>; 199 #address-cells = <1>;
206 #size-cells = <0>; 200 #size-cells = <0>;
207 201
208 power-domain@RK3128_PD 202 power-domain@RK3128_PD_VIO {
209 reg = <RK3128_ 203 reg = <RK3128_PD_VIO>;
210 clocks = <&cru 204 clocks = <&cru ACLK_CIF>,
211 <&cru 205 <&cru HCLK_CIF>,
212 <&cru 206 <&cru DCLK_EBC>,
213 <&cru 207 <&cru HCLK_EBC>,
214 <&cru 208 <&cru ACLK_IEP>,
215 <&cru 209 <&cru HCLK_IEP>,
216 <&cru 210 <&cru ACLK_LCDC0>,
217 <&cru 211 <&cru HCLK_LCDC0>,
218 <&cru 212 <&cru PCLK_MIPI>,
219 <&cru <<
220 <&cru <<
221 <&cru 213 <&cru ACLK_RGA>,
222 <&cru 214 <&cru HCLK_RGA>,
223 <&cru 215 <&cru ACLK_VIO0>,
224 <&cru 216 <&cru ACLK_VIO1>,
225 <&cru 217 <&cru HCLK_VIO>,
226 <&cru 218 <&cru HCLK_VIO_H2P>,
227 <&cru 219 <&cru DCLK_VOP>,
228 <&cru 220 <&cru SCLK_VOP>;
229 pm_qos = <&qos 221 pm_qos = <&qos_ebc>,
230 <&qos 222 <&qos_iep>,
231 <&qos 223 <&qos_lcdc>,
232 <&qos 224 <&qos_rga>,
233 <&qos 225 <&qos_vip>;
234 #power-domain- 226 #power-domain-cells = <0>;
235 }; 227 };
236 228
237 power-domain@RK3128_PD 229 power-domain@RK3128_PD_VIDEO {
238 reg = <RK3128_ 230 reg = <RK3128_PD_VIDEO>;
239 clocks = <&cru 231 clocks = <&cru ACLK_VDPU>,
240 <&cru 232 <&cru HCLK_VDPU>,
241 <&cru 233 <&cru ACLK_VEPU>,
242 <&cru 234 <&cru HCLK_VEPU>,
243 <&cru 235 <&cru SCLK_HEVC_CORE>;
244 pm_qos = <&qos 236 pm_qos = <&qos_vpu>;
245 #power-domain- 237 #power-domain-cells = <0>;
246 }; 238 };
247 239
248 power-domain@RK3128_PD 240 power-domain@RK3128_PD_GPU {
249 reg = <RK3128_ 241 reg = <RK3128_PD_GPU>;
250 clocks = <&cru 242 clocks = <&cru ACLK_GPU>;
251 pm_qos = <&qos 243 pm_qos = <&qos_gpu>;
252 #power-domain- 244 #power-domain-cells = <0>;
253 }; 245 };
254 }; 246 };
255 }; 247 };
256 248
257 vpu: video-codec@10106000 { <<
258 compatible = "rockchip,rk3128- <<
259 reg = <0x10106000 0x800>; <<
260 interrupts = <GIC_SPI 6 IRQ_TY <<
261 <GIC_SPI 7 IRQ_TY <<
262 interrupt-names = "vepu", "vdp <<
263 clocks = <&cru ACLK_VDPU>, <&c <<
264 <&cru ACLK_VEPU>, <&c <<
265 clock-names = "aclk_vdpu", "hc <<
266 "aclk_vepu", "hc <<
267 iommus = <&vpu_mmu>; <<
268 power-domains = <&power RK3128 <<
269 }; <<
270 <<
271 vpu_mmu: iommu@10106800 { <<
272 compatible = "rockchip,iommu"; <<
273 reg = <0x10106800 0x100>; <<
274 interrupts = <GIC_SPI 67 IRQ_T <<
275 clocks = <&cru ACLK_VEPU>, <&c <<
276 clock-names = "aclk", "iface"; <<
277 power-domains = <&power RK3128 <<
278 #iommu-cells = <0>; <<
279 }; <<
280 <<
281 vop: vop@1010e000 { <<
282 compatible = "rockchip,rk3126- <<
283 reg = <0x1010e000 0x300>; <<
284 interrupts = <GIC_SPI 9 IRQ_TY <<
285 clocks = <&cru ACLK_LCDC0>, <& <<
286 <&cru HCLK_LCDC0>; <<
287 clock-names = "aclk_vop", "dcl <<
288 "hclk_vop"; <<
289 resets = <&cru SRST_VOP_A>, <& <<
290 <&cru SRST_VOP_D>; <<
291 reset-names = "axi", "ahb", <<
292 "dclk"; <<
293 power-domains = <&power RK3128 <<
294 status = "disabled"; <<
295 <<
296 vop_out: port { <<
297 #address-cells = <1>; <<
298 #size-cells = <0>; <<
299 <<
300 vop_out_hdmi: endpoint <<
301 reg = <0>; <<
302 remote-endpoin <<
303 }; <<
304 <<
305 vop_out_dsi: endpoint@ <<
306 reg = <1>; <<
307 remote-endpoin <<
308 }; <<
309 }; <<
310 }; <<
311 <<
312 dsi: dsi@10110000 { <<
313 compatible = "rockchip,rk3128- <<
314 reg = <0x10110000 0x4000>; <<
315 interrupts = <GIC_SPI 33 IRQ_T <<
316 clocks = <&cru PCLK_MIPI>; <<
317 clock-names = "pclk"; <<
318 phys = <&dphy>; <<
319 phy-names = "dphy"; <<
320 power-domains = <&power RK3128 <<
321 resets = <&cru SRST_VIO_MIPI_D <<
322 reset-names = "apb"; <<
323 rockchip,grf = <&grf>; <<
324 status = "disabled"; <<
325 <<
326 ports { <<
327 #address-cells = <1>; <<
328 #size-cells = <0>; <<
329 <<
330 dsi_in: port@0 { <<
331 reg = <0>; <<
332 <<
333 dsi_in_vop: en <<
334 remote <<
335 }; <<
336 }; <<
337 <<
338 dsi_out: port@1 { <<
339 reg = <1>; <<
340 }; <<
341 }; <<
342 }; <<
343 <<
344 qos_gpu: qos@1012d000 { 249 qos_gpu: qos@1012d000 {
345 compatible = "rockchip,rk3128- 250 compatible = "rockchip,rk3128-qos", "syscon";
346 reg = <0x1012d000 0x20>; 251 reg = <0x1012d000 0x20>;
347 }; 252 };
348 253
349 qos_vpu: qos@1012e000 { 254 qos_vpu: qos@1012e000 {
350 compatible = "rockchip,rk3128- 255 compatible = "rockchip,rk3128-qos", "syscon";
351 reg = <0x1012e000 0x20>; 256 reg = <0x1012e000 0x20>;
352 }; 257 };
353 258
354 qos_rga: qos@1012f000 { 259 qos_rga: qos@1012f000 {
355 compatible = "rockchip,rk3128- 260 compatible = "rockchip,rk3128-qos", "syscon";
356 reg = <0x1012f000 0x20>; 261 reg = <0x1012f000 0x20>;
357 }; 262 };
358 263
359 qos_ebc: qos@1012f080 { 264 qos_ebc: qos@1012f080 {
360 compatible = "rockchip,rk3128- 265 compatible = "rockchip,rk3128-qos", "syscon";
361 reg = <0x1012f080 0x20>; 266 reg = <0x1012f080 0x20>;
362 }; 267 };
363 268
364 qos_iep: qos@1012f100 { 269 qos_iep: qos@1012f100 {
365 compatible = "rockchip,rk3128- 270 compatible = "rockchip,rk3128-qos", "syscon";
366 reg = <0x1012f100 0x20>; 271 reg = <0x1012f100 0x20>;
367 }; 272 };
368 273
369 qos_lcdc: qos@1012f180 { 274 qos_lcdc: qos@1012f180 {
370 compatible = "rockchip,rk3128- 275 compatible = "rockchip,rk3128-qos", "syscon";
371 reg = <0x1012f180 0x20>; 276 reg = <0x1012f180 0x20>;
372 }; 277 };
373 278
374 qos_vip: qos@1012f200 { 279 qos_vip: qos@1012f200 {
375 compatible = "rockchip,rk3128- 280 compatible = "rockchip,rk3128-qos", "syscon";
376 reg = <0x1012f200 0x20>; 281 reg = <0x1012f200 0x20>;
377 }; 282 };
378 283
379 gic: interrupt-controller@10139000 { 284 gic: interrupt-controller@10139000 {
380 compatible = "arm,cortex-a7-gi 285 compatible = "arm,cortex-a7-gic";
381 reg = <0x10139000 0x1000>, 286 reg = <0x10139000 0x1000>,
382 <0x1013a000 0x1000>, 287 <0x1013a000 0x1000>,
383 <0x1013c000 0x2000>, 288 <0x1013c000 0x2000>,
384 <0x1013e000 0x2000>; 289 <0x1013e000 0x2000>;
385 interrupts = <GIC_PPI 9 (GIC_C 290 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
386 interrupt-controller; 291 interrupt-controller;
387 #interrupt-cells = <3>; 292 #interrupt-cells = <3>;
388 #address-cells = <0>; 293 #address-cells = <0>;
389 }; 294 };
390 295
391 usb_otg: usb@10180000 { 296 usb_otg: usb@10180000 {
392 compatible = "rockchip,rk3128- 297 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
393 reg = <0x10180000 0x40000>; 298 reg = <0x10180000 0x40000>;
394 interrupts = <GIC_SPI 10 IRQ_T 299 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru HCLK_OTG>; 300 clocks = <&cru HCLK_OTG>;
396 clock-names = "otg"; 301 clock-names = "otg";
397 dr_mode = "otg"; 302 dr_mode = "otg";
398 g-np-tx-fifo-size = <16>; 303 g-np-tx-fifo-size = <16>;
399 g-rx-fifo-size = <280>; 304 g-rx-fifo-size = <280>;
400 g-tx-fifo-size = <256 128 128 305 g-tx-fifo-size = <256 128 128 64 32 16>;
401 phys = <&usb2phy_otg>; 306 phys = <&usb2phy_otg>;
402 phy-names = "usb2-phy"; 307 phy-names = "usb2-phy";
403 status = "disabled"; 308 status = "disabled";
404 }; 309 };
405 310
406 usb_host_ehci: usb@101c0000 { 311 usb_host_ehci: usb@101c0000 {
407 compatible = "generic-ehci"; 312 compatible = "generic-ehci";
408 reg = <0x101c0000 0x20000>; 313 reg = <0x101c0000 0x20000>;
409 interrupts = <GIC_SPI 11 IRQ_T 314 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cru HCLK_HOST2>; 315 clocks = <&cru HCLK_HOST2>;
411 phys = <&usb2phy_host>; 316 phys = <&usb2phy_host>;
412 phy-names = "usb"; 317 phy-names = "usb";
413 status = "disabled"; 318 status = "disabled";
414 }; 319 };
415 320
416 usb_host_ohci: usb@101e0000 { 321 usb_host_ohci: usb@101e0000 {
417 compatible = "generic-ohci"; 322 compatible = "generic-ohci";
418 reg = <0x101e0000 0x20000>; 323 reg = <0x101e0000 0x20000>;
419 interrupts = <GIC_SPI 32 IRQ_T 324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru HCLK_HOST2>; 325 clocks = <&cru HCLK_HOST2>;
421 phys = <&usb2phy_host>; 326 phys = <&usb2phy_host>;
422 phy-names = "usb"; 327 phy-names = "usb";
423 status = "disabled"; 328 status = "disabled";
424 }; 329 };
425 330
426 i2s_8ch: i2s@10200000 { <<
427 compatible = "rockchip,rk3128- <<
428 reg = <0x10200000 0x1000>; <<
429 interrupts = <GIC_SPI 68 IRQ_T <<
430 clocks = <&cru SCLK_I2S0>, <&c <<
431 clock-names = "i2s_clk", "i2s_ <<
432 dmas = <&pdma 14>, <&pdma 15>; <<
433 dma-names = "tx", "rx"; <<
434 #sound-dai-cells = <0>; <<
435 status = "disabled"; <<
436 }; <<
437 <<
438 spdif: spdif@10204000 { <<
439 compatible = "rockchip,rk3128- <<
440 reg = <0x10204000 0x1000>; <<
441 interrupts = <GIC_SPI 55 IRQ_T <<
442 clocks = <&cru SCLK_SPDIF>, <& <<
443 clock-names = "mclk", "hclk"; <<
444 dmas = <&pdma 13>; <<
445 dma-names = "tx"; <<
446 pinctrl-names = "default"; <<
447 pinctrl-0 = <&spdif_tx>; <<
448 #sound-dai-cells = <0>; <<
449 status = "disabled"; <<
450 }; <<
451 <<
452 sfc: spi@1020c000 { <<
453 compatible = "rockchip,sfc"; <<
454 reg = <0x1020c000 0x8000>; <<
455 interrupts = <GIC_SPI 50 IRQ_T <<
456 clocks = <&cru SCLK_SFC>, <&cr <<
457 clock-names = "clk_sfc", "hclk <<
458 status = "disabled"; <<
459 }; <<
460 <<
461 sdmmc: mmc@10214000 { 331 sdmmc: mmc@10214000 {
462 compatible = "rockchip,rk3128- 332 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
463 reg = <0x10214000 0x4000>; 333 reg = <0x10214000 0x4000>;
464 interrupts = <GIC_SPI 14 IRQ_T 334 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_SDMMC>, <& 335 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
466 <&cru SCLK_SDMMC_DRV> 336 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
467 clock-names = "biu", "ciu", "c 337 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
468 dmas = <&pdma 10>; 338 dmas = <&pdma 10>;
469 dma-names = "rx-tx"; 339 dma-names = "rx-tx";
470 fifo-depth = <256>; 340 fifo-depth = <256>;
471 max-frequency = <150000000>; 341 max-frequency = <150000000>;
472 resets = <&cru SRST_SDMMC>; 342 resets = <&cru SRST_SDMMC>;
473 reset-names = "reset"; 343 reset-names = "reset";
474 status = "disabled"; 344 status = "disabled";
475 }; 345 };
476 346
477 sdio: mmc@10218000 { 347 sdio: mmc@10218000 {
478 compatible = "rockchip,rk3128- 348 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
479 reg = <0x10218000 0x4000>; 349 reg = <0x10218000 0x4000>;
480 interrupts = <GIC_SPI 15 IRQ_T 350 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_SDIO>, <&c 351 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
482 <&cru SCLK_SDIO_DRV>, 352 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
483 clock-names = "biu", "ciu", "c 353 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
484 dmas = <&pdma 11>; 354 dmas = <&pdma 11>;
485 dma-names = "rx-tx"; 355 dma-names = "rx-tx";
486 fifo-depth = <256>; 356 fifo-depth = <256>;
487 max-frequency = <150000000>; 357 max-frequency = <150000000>;
488 resets = <&cru SRST_SDIO>; 358 resets = <&cru SRST_SDIO>;
489 reset-names = "reset"; 359 reset-names = "reset";
490 status = "disabled"; 360 status = "disabled";
491 }; 361 };
492 362
493 emmc: mmc@1021c000 { 363 emmc: mmc@1021c000 {
494 compatible = "rockchip,rk3128- 364 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
495 reg = <0x1021c000 0x4000>; 365 reg = <0x1021c000 0x4000>;
496 interrupts = <GIC_SPI 16 IRQ_T 366 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru HCLK_EMMC>, <&c 367 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
498 <&cru SCLK_EMMC_DRV>, 368 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
499 clock-names = "biu", "ciu", "c 369 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
500 dmas = <&pdma 12>; 370 dmas = <&pdma 12>;
501 dma-names = "rx-tx"; 371 dma-names = "rx-tx";
502 fifo-depth = <256>; 372 fifo-depth = <256>;
503 max-frequency = <150000000>; 373 max-frequency = <150000000>;
504 resets = <&cru SRST_EMMC>; 374 resets = <&cru SRST_EMMC>;
505 reset-names = "reset"; 375 reset-names = "reset";
506 status = "disabled"; 376 status = "disabled";
507 }; 377 };
508 378
509 i2s_2ch: i2s@10220000 { <<
510 compatible = "rockchip,rk3128- <<
511 reg = <0x10220000 0x1000>; <<
512 interrupts = <GIC_SPI 19 IRQ_T <<
513 clocks = <&cru SCLK_I2S1>, <&c <<
514 clock-names = "i2s_clk", "i2s_ <<
515 dmas = <&pdma 0>, <&pdma 1>; <<
516 dma-names = "tx", "rx"; <<
517 rockchip,playback-channels = < <<
518 pinctrl-names = "default"; <<
519 pinctrl-0 = <&i2s_bus>; <<
520 #sound-dai-cells = <0>; <<
521 status = "disabled"; <<
522 }; <<
523 <<
524 nfc: nand-controller@10500000 { 379 nfc: nand-controller@10500000 {
525 compatible = "rockchip,rk3128- 380 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
526 reg = <0x10500000 0x4000>; 381 reg = <0x10500000 0x4000>;
527 interrupts = <GIC_SPI 18 IRQ_T 382 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cru HCLK_NANDC>, <& 383 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
529 clock-names = "ahb", "nfc"; 384 clock-names = "ahb", "nfc";
530 pinctrl-names = "default"; 385 pinctrl-names = "default";
531 pinctrl-0 = <&flash_ale &flash 386 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
532 &flash_dqs &flash 387 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
533 status = "disabled"; 388 status = "disabled";
534 }; 389 };
535 390
536 cru: clock-controller@20000000 { 391 cru: clock-controller@20000000 {
537 compatible = "rockchip,rk3128- 392 compatible = "rockchip,rk3128-cru";
538 reg = <0x20000000 0x1000>; 393 reg = <0x20000000 0x1000>;
539 clocks = <&xin24m>; 394 clocks = <&xin24m>;
540 clock-names = "xin24m"; 395 clock-names = "xin24m";
541 rockchip,grf = <&grf>; 396 rockchip,grf = <&grf>;
542 #clock-cells = <1>; 397 #clock-cells = <1>;
543 #reset-cells = <1>; 398 #reset-cells = <1>;
544 assigned-clocks = <&cru PLL_GP 399 assigned-clocks = <&cru PLL_GPLL>;
545 assigned-clock-rates = <594000 400 assigned-clock-rates = <594000000>;
546 }; 401 };
547 402
548 grf: syscon@20008000 { 403 grf: syscon@20008000 {
549 compatible = "rockchip,rk3128- 404 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
550 reg = <0x20008000 0x1000>; 405 reg = <0x20008000 0x1000>;
551 #address-cells = <1>; 406 #address-cells = <1>;
552 #size-cells = <1>; 407 #size-cells = <1>;
553 408
554 usb2phy: usb2phy@17c { 409 usb2phy: usb2phy@17c {
555 compatible = "rockchip 410 compatible = "rockchip,rk3128-usb2phy";
556 reg = <0x017c 0x0c>; 411 reg = <0x017c 0x0c>;
557 clocks = <&cru SCLK_OT 412 clocks = <&cru SCLK_OTGPHY0>;
558 clock-names = "phyclk" 413 clock-names = "phyclk";
559 clock-output-names = " 414 clock-output-names = "usb480m_phy";
560 assigned-clocks = <&cr 415 assigned-clocks = <&cru SCLK_USB480M>;
561 assigned-clock-parents 416 assigned-clock-parents = <&usb2phy>;
562 #clock-cells = <0>; 417 #clock-cells = <0>;
563 status = "disabled"; 418 status = "disabled";
564 419
565 usb2phy_host: host-por 420 usb2phy_host: host-port {
566 interrupts = < 421 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-name 422 interrupt-names = "linestate";
568 #phy-cells = < 423 #phy-cells = <0>;
569 status = "disa 424 status = "disabled";
570 }; 425 };
571 426
572 usb2phy_otg: otg-port 427 usb2phy_otg: otg-port {
573 interrupts = < 428 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
574 < 429 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
575 < 430 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-name 431 interrupt-names = "otg-bvalid", "otg-id",
577 432 "linestate";
578 #phy-cells = < 433 #phy-cells = <0>;
579 status = "disa 434 status = "disabled";
580 }; 435 };
581 }; 436 };
582 }; 437 };
583 438
584 hdmi: hdmi@20034000 { <<
585 compatible = "rockchip,rk3128- <<
586 reg = <0x20034000 0x4000>; <<
587 interrupts = <GIC_SPI 45 IRQ_T <<
588 clocks = <&cru PCLK_HDMI>, <&c <<
589 clock-names = "pclk", "ref"; <<
590 pinctrl-names = "default"; <<
591 pinctrl-0 = <&hdmii2c_xfer &hd <<
592 power-domains = <&power RK3128 <<
593 #sound-dai-cells = <0>; <<
594 status = "disabled"; <<
595 <<
596 ports { <<
597 #address-cells = <1>; <<
598 #size-cells = <0>; <<
599 <<
600 hdmi_in: port@0 { <<
601 reg = <0>; <<
602 hdmi_in_vop: e <<
603 remote <<
604 }; <<
605 }; <<
606 <<
607 hdmi_out: port@1 { <<
608 reg = <1>; <<
609 }; <<
610 }; <<
611 }; <<
612 <<
613 dphy: phy@20038000 { <<
614 compatible = "rockchip,rk3128- <<
615 reg = <0x20038000 0x4000>; <<
616 clocks = <&cru SCLK_MIPI_24M>, <<
617 clock-names = "ref", "pclk"; <<
618 #phy-cells = <0>; <<
619 power-domains = <&power RK3128 <<
620 resets = <&cru SRST_MIPIPHY_P> <<
621 reset-names = "apb"; <<
622 status = "disabled"; <<
623 }; <<
624 <<
625 timer0: timer@20044000 { 439 timer0: timer@20044000 {
626 compatible = "rockchip,rk3128- 440 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
627 reg = <0x20044000 0x20>; 441 reg = <0x20044000 0x20>;
628 interrupts = <GIC_SPI 28 IRQ_T 442 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru PCLK_TIMER>, <& 443 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
630 clock-names = "pclk", "timer"; 444 clock-names = "pclk", "timer";
631 }; 445 };
632 446
633 timer1: timer@20044020 { 447 timer1: timer@20044020 {
634 compatible = "rockchip,rk3128- 448 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
635 reg = <0x20044020 0x20>; 449 reg = <0x20044020 0x20>;
636 interrupts = <GIC_SPI 29 IRQ_T 450 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru PCLK_TIMER>, <& 451 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
638 clock-names = "pclk", "timer"; 452 clock-names = "pclk", "timer";
639 }; 453 };
640 454
641 timer2: timer@20044040 { 455 timer2: timer@20044040 {
642 compatible = "rockchip,rk3128- 456 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
643 reg = <0x20044040 0x20>; 457 reg = <0x20044040 0x20>;
644 interrupts = <GIC_SPI 59 IRQ_T 458 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru PCLK_TIMER>, <& 459 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
646 clock-names = "pclk", "timer"; 460 clock-names = "pclk", "timer";
647 }; 461 };
648 462
649 timer3: timer@20044060 { 463 timer3: timer@20044060 {
650 compatible = "rockchip,rk3128- 464 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
651 reg = <0x20044060 0x20>; 465 reg = <0x20044060 0x20>;
652 interrupts = <GIC_SPI 60 IRQ_T 466 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru PCLK_TIMER>, <& 467 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
654 clock-names = "pclk", "timer"; 468 clock-names = "pclk", "timer";
655 }; 469 };
656 470
657 timer4: timer@20044080 { 471 timer4: timer@20044080 {
658 compatible = "rockchip,rk3128- 472 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
659 reg = <0x20044080 0x20>; 473 reg = <0x20044080 0x20>;
660 interrupts = <GIC_SPI 61 IRQ_T 474 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cru PCLK_TIMER>, <& 475 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
662 clock-names = "pclk", "timer"; 476 clock-names = "pclk", "timer";
663 }; 477 };
664 478
665 timer5: timer@200440a0 { 479 timer5: timer@200440a0 {
666 compatible = "rockchip,rk3128- 480 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
667 reg = <0x200440a0 0x20>; 481 reg = <0x200440a0 0x20>;
668 interrupts = <GIC_SPI 62 IRQ_T 482 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru PCLK_TIMER>, <& 483 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
670 clock-names = "pclk", "timer"; 484 clock-names = "pclk", "timer";
671 }; 485 };
672 486
673 watchdog: watchdog@2004c000 { 487 watchdog: watchdog@2004c000 {
674 compatible = "rockchip,rk3128- 488 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
675 reg = <0x2004c000 0x100>; 489 reg = <0x2004c000 0x100>;
676 interrupts = <GIC_SPI 34 IRQ_T 490 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cru PCLK_WDT>; 491 clocks = <&cru PCLK_WDT>;
678 status = "disabled"; 492 status = "disabled";
679 }; 493 };
680 494
681 pwm0: pwm@20050000 { 495 pwm0: pwm@20050000 {
682 compatible = "rockchip,rk3128- 496 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
683 reg = <0x20050000 0x10>; 497 reg = <0x20050000 0x10>;
684 clocks = <&cru PCLK_PWM>; 498 clocks = <&cru PCLK_PWM>;
685 pinctrl-names = "default"; 499 pinctrl-names = "default";
686 pinctrl-0 = <&pwm0_pin>; 500 pinctrl-0 = <&pwm0_pin>;
687 #pwm-cells = <3>; 501 #pwm-cells = <3>;
688 status = "disabled"; 502 status = "disabled";
689 }; 503 };
690 504
691 pwm1: pwm@20050010 { 505 pwm1: pwm@20050010 {
692 compatible = "rockchip,rk3128- 506 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
693 reg = <0x20050010 0x10>; 507 reg = <0x20050010 0x10>;
694 clocks = <&cru PCLK_PWM>; 508 clocks = <&cru PCLK_PWM>;
695 pinctrl-names = "default"; 509 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>; 510 pinctrl-0 = <&pwm1_pin>;
697 #pwm-cells = <3>; 511 #pwm-cells = <3>;
698 status = "disabled"; 512 status = "disabled";
699 }; 513 };
700 514
701 pwm2: pwm@20050020 { 515 pwm2: pwm@20050020 {
702 compatible = "rockchip,rk3128- 516 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
703 reg = <0x20050020 0x10>; 517 reg = <0x20050020 0x10>;
704 clocks = <&cru PCLK_PWM>; 518 clocks = <&cru PCLK_PWM>;
705 pinctrl-names = "default"; 519 pinctrl-names = "default";
706 pinctrl-0 = <&pwm2_pin>; 520 pinctrl-0 = <&pwm2_pin>;
707 #pwm-cells = <3>; 521 #pwm-cells = <3>;
708 status = "disabled"; 522 status = "disabled";
709 }; 523 };
710 524
711 pwm3: pwm@20050030 { 525 pwm3: pwm@20050030 {
712 compatible = "rockchip,rk3128- 526 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
713 reg = <0x20050030 0x10>; 527 reg = <0x20050030 0x10>;
714 clocks = <&cru PCLK_PWM>; 528 clocks = <&cru PCLK_PWM>;
715 pinctrl-names = "default"; 529 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3_pin>; 530 pinctrl-0 = <&pwm3_pin>;
717 #pwm-cells = <3>; 531 #pwm-cells = <3>;
718 status = "disabled"; 532 status = "disabled";
719 }; 533 };
720 534
721 i2c1: i2c@20056000 { 535 i2c1: i2c@20056000 {
722 compatible = "rockchip,rk3128- 536 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
723 reg = <0x20056000 0x1000>; 537 reg = <0x20056000 0x1000>;
724 interrupts = <GIC_SPI 25 IRQ_T 538 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
725 clock-names = "i2c"; 539 clock-names = "i2c";
726 clocks = <&cru PCLK_I2C1>; 540 clocks = <&cru PCLK_I2C1>;
727 pinctrl-names = "default"; 541 pinctrl-names = "default";
728 pinctrl-0 = <&i2c1_xfer>; 542 pinctrl-0 = <&i2c1_xfer>;
729 #address-cells = <1>; 543 #address-cells = <1>;
730 #size-cells = <0>; 544 #size-cells = <0>;
731 status = "disabled"; 545 status = "disabled";
732 }; 546 };
733 547
734 i2c2: i2c@2005a000 { 548 i2c2: i2c@2005a000 {
735 compatible = "rockchip,rk3128- 549 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
736 reg = <0x2005a000 0x1000>; 550 reg = <0x2005a000 0x1000>;
737 interrupts = <GIC_SPI 26 IRQ_T 551 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
738 clock-names = "i2c"; 552 clock-names = "i2c";
739 clocks = <&cru PCLK_I2C2>; 553 clocks = <&cru PCLK_I2C2>;
740 pinctrl-names = "default"; 554 pinctrl-names = "default";
741 pinctrl-0 = <&i2c2_xfer>; 555 pinctrl-0 = <&i2c2_xfer>;
742 #address-cells = <1>; 556 #address-cells = <1>;
743 #size-cells = <0>; 557 #size-cells = <0>;
744 status = "disabled"; 558 status = "disabled";
745 }; 559 };
746 560
747 i2c3: i2c@2005e000 { 561 i2c3: i2c@2005e000 {
748 compatible = "rockchip,rk3128- 562 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
749 reg = <0x2005e000 0x1000>; 563 reg = <0x2005e000 0x1000>;
750 interrupts = <GIC_SPI 27 IRQ_T 564 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
751 clock-names = "i2c"; 565 clock-names = "i2c";
752 clocks = <&cru PCLK_I2C3>; 566 clocks = <&cru PCLK_I2C3>;
753 pinctrl-names = "default"; 567 pinctrl-names = "default";
754 pinctrl-0 = <&i2c3_xfer>; 568 pinctrl-0 = <&i2c3_xfer>;
755 #address-cells = <1>; 569 #address-cells = <1>;
756 #size-cells = <0>; 570 #size-cells = <0>;
757 status = "disabled"; 571 status = "disabled";
758 }; 572 };
759 573
760 uart0: serial@20060000 { 574 uart0: serial@20060000 {
761 compatible = "rockchip,rk3128- 575 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
762 reg = <0x20060000 0x100>; 576 reg = <0x20060000 0x100>;
763 interrupts = <GIC_SPI 20 IRQ_T 577 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
764 clock-frequency = <24000000>; 578 clock-frequency = <24000000>;
765 clocks = <&cru SCLK_UART0>, <& 579 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
766 clock-names = "baudclk", "apb_ 580 clock-names = "baudclk", "apb_pclk";
767 dmas = <&pdma 2>, <&pdma 3>; 581 dmas = <&pdma 2>, <&pdma 3>;
768 dma-names = "tx", "rx"; 582 dma-names = "tx", "rx";
769 pinctrl-names = "default"; 583 pinctrl-names = "default";
770 pinctrl-0 = <&uart0_xfer &uart 584 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
771 reg-io-width = <4>; 585 reg-io-width = <4>;
772 reg-shift = <2>; 586 reg-shift = <2>;
773 status = "disabled"; 587 status = "disabled";
774 }; 588 };
775 589
776 uart1: serial@20064000 { 590 uart1: serial@20064000 {
777 compatible = "rockchip,rk3128- 591 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
778 reg = <0x20064000 0x100>; 592 reg = <0x20064000 0x100>;
779 interrupts = <GIC_SPI 21 IRQ_T 593 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
780 clock-frequency = <24000000>; 594 clock-frequency = <24000000>;
781 clocks = <&cru SCLK_UART1>, <& 595 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
782 clock-names = "baudclk", "apb_ 596 clock-names = "baudclk", "apb_pclk";
783 dmas = <&pdma 4>, <&pdma 5>; 597 dmas = <&pdma 4>, <&pdma 5>;
784 dma-names = "tx", "rx"; 598 dma-names = "tx", "rx";
785 pinctrl-names = "default"; 599 pinctrl-names = "default";
786 pinctrl-0 = <&uart1_xfer>; 600 pinctrl-0 = <&uart1_xfer>;
787 reg-io-width = <4>; 601 reg-io-width = <4>;
788 reg-shift = <2>; 602 reg-shift = <2>;
789 status = "disabled"; 603 status = "disabled";
790 }; 604 };
791 605
792 uart2: serial@20068000 { 606 uart2: serial@20068000 {
793 compatible = "rockchip,rk3128- 607 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
794 reg = <0x20068000 0x100>; 608 reg = <0x20068000 0x100>;
795 interrupts = <GIC_SPI 22 IRQ_T 609 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
796 clock-frequency = <24000000>; 610 clock-frequency = <24000000>;
797 clocks = <&cru SCLK_UART2>, <& 611 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
798 clock-names = "baudclk", "apb_ 612 clock-names = "baudclk", "apb_pclk";
799 dmas = <&pdma 6>, <&pdma 7>; 613 dmas = <&pdma 6>, <&pdma 7>;
800 dma-names = "tx", "rx"; 614 dma-names = "tx", "rx";
801 pinctrl-names = "default"; 615 pinctrl-names = "default";
802 pinctrl-0 = <&uart2_xfer>; 616 pinctrl-0 = <&uart2_xfer>;
803 reg-io-width = <4>; 617 reg-io-width = <4>;
804 reg-shift = <2>; 618 reg-shift = <2>;
805 status = "disabled"; 619 status = "disabled";
806 }; 620 };
807 621
808 saradc: saradc@2006c000 { 622 saradc: saradc@2006c000 {
809 compatible = "rockchip,saradc" 623 compatible = "rockchip,saradc";
810 reg = <0x2006c000 0x100>; 624 reg = <0x2006c000 0x100>;
811 interrupts = <GIC_SPI 17 IRQ_T 625 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cru SCLK_SARADC>, < 626 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
813 clock-names = "saradc", "apb_p 627 clock-names = "saradc", "apb_pclk";
814 resets = <&cru SRST_SARADC>; 628 resets = <&cru SRST_SARADC>;
815 reset-names = "saradc-apb"; 629 reset-names = "saradc-apb";
816 #io-channel-cells = <1>; 630 #io-channel-cells = <1>;
817 status = "disabled"; 631 status = "disabled";
818 }; 632 };
819 633
820 i2c0: i2c@20072000 { 634 i2c0: i2c@20072000 {
821 compatible = "rockchip,rk3128- 635 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
822 reg = <0x20072000 0x1000>; 636 reg = <0x20072000 0x1000>;
823 interrupts = <GIC_SPI 24 IRQ_T 637 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
824 clock-names = "i2c"; 638 clock-names = "i2c";
825 clocks = <&cru PCLK_I2C0>; 639 clocks = <&cru PCLK_I2C0>;
826 pinctrl-names = "default"; 640 pinctrl-names = "default";
827 pinctrl-0 = <&i2c0_xfer>; 641 pinctrl-0 = <&i2c0_xfer>;
828 #address-cells = <1>; 642 #address-cells = <1>;
829 #size-cells = <0>; 643 #size-cells = <0>;
830 status = "disabled"; 644 status = "disabled";
831 }; 645 };
832 646
833 spi0: spi@20074000 { 647 spi0: spi@20074000 {
834 compatible = "rockchip,rk3128- 648 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
835 reg = <0x20074000 0x1000>; 649 reg = <0x20074000 0x1000>;
836 interrupts = <GIC_SPI 23 IRQ_T 650 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&cru SCLK_SPI0>, <&c 651 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
838 clock-names = "spiclk", "apb_p 652 clock-names = "spiclk", "apb_pclk";
839 dmas = <&pdma 8>, <&pdma 9>; 653 dmas = <&pdma 8>, <&pdma 9>;
840 dma-names = "tx", "rx"; 654 dma-names = "tx", "rx";
841 pinctrl-names = "default"; 655 pinctrl-names = "default";
842 pinctrl-0 = <&spi0_tx &spi0_rx 656 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
843 #address-cells = <1>; 657 #address-cells = <1>;
844 #size-cells = <0>; 658 #size-cells = <0>;
845 status = "disabled"; 659 status = "disabled";
846 }; 660 };
847 661
848 pdma: dma-controller@20078000 { 662 pdma: dma-controller@20078000 {
849 compatible = "arm,pl330", "arm 663 compatible = "arm,pl330", "arm,primecell";
850 reg = <0x20078000 0x4000>; 664 reg = <0x20078000 0x4000>;
851 interrupts = <GIC_SPI 0 IRQ_TY 665 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 1 IRQ_TY 666 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
853 arm,pl330-broken-no-flushp; 667 arm,pl330-broken-no-flushp;
854 arm,pl330-periph-burst; 668 arm,pl330-periph-burst;
855 clocks = <&cru ACLK_DMAC>; 669 clocks = <&cru ACLK_DMAC>;
856 clock-names = "apb_pclk"; 670 clock-names = "apb_pclk";
857 #dma-cells = <1>; 671 #dma-cells = <1>;
858 }; 672 };
859 673
860 gmac: ethernet@2008c000 { 674 gmac: ethernet@2008c000 {
861 compatible = "rockchip,rk3128- 675 compatible = "rockchip,rk3128-gmac";
862 reg = <0x2008c000 0x4000>; 676 reg = <0x2008c000 0x4000>;
863 interrupts = <GIC_SPI 56 IRQ_T 677 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 57 IRQ_T 678 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
865 interrupt-names = "macirq", "e 679 interrupt-names = "macirq", "eth_wake_irq";
866 clocks = <&cru SCLK_MAC>, 680 clocks = <&cru SCLK_MAC>,
867 <&cru SCLK_MAC_RX>, < 681 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
868 <&cru SCLK_MAC_REF>, 682 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
869 <&cru ACLK_GMAC>, <&c 683 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
870 clock-names = "stmmaceth", 684 clock-names = "stmmaceth",
871 "mac_clk_rx", "m 685 "mac_clk_rx", "mac_clk_tx",
872 "clk_mac_ref", " 686 "clk_mac_ref", "clk_mac_refout",
873 "aclk_mac", "pcl 687 "aclk_mac", "pclk_mac";
874 resets = <&cru SRST_GMAC>; 688 resets = <&cru SRST_GMAC>;
875 reset-names = "stmmaceth"; 689 reset-names = "stmmaceth";
876 rockchip,grf = <&grf>; 690 rockchip,grf = <&grf>;
877 rx-fifo-depth = <4096>; 691 rx-fifo-depth = <4096>;
878 tx-fifo-depth = <2048>; 692 tx-fifo-depth = <2048>;
879 status = "disabled"; 693 status = "disabled";
880 694
881 mdio: mdio { 695 mdio: mdio {
882 compatible = "snps,dwm 696 compatible = "snps,dwmac-mdio";
883 #address-cells = <0x1> 697 #address-cells = <0x1>;
884 #size-cells = <0x0>; 698 #size-cells = <0x0>;
885 }; 699 };
886 }; 700 };
887 701
888 pinctrl: pinctrl { 702 pinctrl: pinctrl {
889 compatible = "rockchip,rk3128- 703 compatible = "rockchip,rk3128-pinctrl";
890 rockchip,grf = <&grf>; 704 rockchip,grf = <&grf>;
891 #address-cells = <1>; 705 #address-cells = <1>;
892 #size-cells = <1>; 706 #size-cells = <1>;
893 ranges; 707 ranges;
894 708
895 gpio0: gpio@2007c000 { 709 gpio0: gpio@2007c000 {
896 compatible = "rockchip 710 compatible = "rockchip,gpio-bank";
897 reg = <0x2007c000 0x10 711 reg = <0x2007c000 0x100>;
898 interrupts = <GIC_SPI 712 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cru PCLK_GP 713 clocks = <&cru PCLK_GPIO0>;
900 gpio-controller; 714 gpio-controller;
901 #gpio-cells = <2>; 715 #gpio-cells = <2>;
902 interrupt-controller; 716 interrupt-controller;
903 #interrupt-cells = <2> 717 #interrupt-cells = <2>;
904 }; 718 };
905 719
906 gpio1: gpio@20080000 { 720 gpio1: gpio@20080000 {
907 compatible = "rockchip 721 compatible = "rockchip,gpio-bank";
908 reg = <0x20080000 0x10 722 reg = <0x20080000 0x100>;
909 interrupts = <GIC_SPI 723 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&cru PCLK_GP 724 clocks = <&cru PCLK_GPIO1>;
911 gpio-controller; 725 gpio-controller;
912 #gpio-cells = <2>; 726 #gpio-cells = <2>;
913 interrupt-controller; 727 interrupt-controller;
914 #interrupt-cells = <2> 728 #interrupt-cells = <2>;
915 }; 729 };
916 730
917 gpio2: gpio@20084000 { 731 gpio2: gpio@20084000 {
918 compatible = "rockchip 732 compatible = "rockchip,gpio-bank";
919 reg = <0x20084000 0x10 733 reg = <0x20084000 0x100>;
920 interrupts = <GIC_SPI 734 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cru PCLK_GP 735 clocks = <&cru PCLK_GPIO2>;
922 gpio-controller; 736 gpio-controller;
923 #gpio-cells = <2>; 737 #gpio-cells = <2>;
924 interrupt-controller; 738 interrupt-controller;
925 #interrupt-cells = <2> 739 #interrupt-cells = <2>;
926 }; 740 };
927 741
928 gpio3: gpio@20088000 { 742 gpio3: gpio@20088000 {
929 compatible = "rockchip 743 compatible = "rockchip,gpio-bank";
930 reg = <0x20088000 0x10 744 reg = <0x20088000 0x100>;
931 interrupts = <GIC_SPI 745 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&cru PCLK_GP 746 clocks = <&cru PCLK_GPIO3>;
933 gpio-controller; 747 gpio-controller;
934 #gpio-cells = <2>; 748 #gpio-cells = <2>;
935 interrupt-controller; 749 interrupt-controller;
936 #interrupt-cells = <2> 750 #interrupt-cells = <2>;
937 }; 751 };
938 752
939 pcfg_pull_default: pcfg-pull-d 753 pcfg_pull_default: pcfg-pull-default {
940 bias-pull-pin-default; 754 bias-pull-pin-default;
941 }; 755 };
942 756
943 pcfg_pull_none: pcfg-pull-none 757 pcfg_pull_none: pcfg-pull-none {
944 bias-disable; 758 bias-disable;
945 }; 759 };
946 760
947 emmc { 761 emmc {
948 emmc_clk: emmc-clk { 762 emmc_clk: emmc-clk {
949 rockchip,pins 763 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
950 }; 764 };
951 765
952 emmc_cmd: emmc-cmd { 766 emmc_cmd: emmc-cmd {
953 rockchip,pins 767 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
954 }; 768 };
955 769
956 emmc_cmd1: emmc-cmd1 { 770 emmc_cmd1: emmc-cmd1 {
957 rockchip,pins 771 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
958 }; 772 };
959 773
960 emmc_pwr: emmc-pwr { 774 emmc_pwr: emmc-pwr {
961 rockchip,pins 775 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
962 }; 776 };
963 777
964 emmc_bus1: emmc-bus1 { 778 emmc_bus1: emmc-bus1 {
965 rockchip,pins 779 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
966 }; 780 };
967 781
968 emmc_bus4: emmc-bus4 { 782 emmc_bus4: emmc-bus4 {
969 rockchip,pins 783 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
970 784 <1 RK_PD1 2 &pcfg_pull_default>,
971 785 <1 RK_PD2 2 &pcfg_pull_default>,
972 786 <1 RK_PD3 2 &pcfg_pull_default>;
973 }; 787 };
974 788
975 emmc_bus8: emmc-bus8 { 789 emmc_bus8: emmc-bus8 {
976 rockchip,pins 790 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
977 791 <1 RK_PD1 2 &pcfg_pull_default>,
978 792 <1 RK_PD2 2 &pcfg_pull_default>,
979 793 <1 RK_PD3 2 &pcfg_pull_default>,
980 794 <1 RK_PD4 2 &pcfg_pull_default>,
981 795 <1 RK_PD5 2 &pcfg_pull_default>,
982 796 <1 RK_PD6 2 &pcfg_pull_default>,
983 797 <1 RK_PD7 2 &pcfg_pull_default>;
984 }; 798 };
985 }; 799 };
986 800
987 gmac { 801 gmac {
988 rgmii_pins: rgmii-pins 802 rgmii_pins: rgmii-pins {
989 rockchip,pins 803 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
990 804 <2 RK_PB1 3 &pcfg_pull_default>,
991 805 <2 RK_PB3 3 &pcfg_pull_default>,
992 806 <2 RK_PB4 3 &pcfg_pull_default>,
993 807 <2 RK_PB5 3 &pcfg_pull_default>,
994 808 <2 RK_PB6 3 &pcfg_pull_default>,
995 809 <2 RK_PC0 3 &pcfg_pull_default>,
996 810 <2 RK_PC1 3 &pcfg_pull_default>,
997 811 <2 RK_PC2 3 &pcfg_pull_default>,
998 812 <2 RK_PC3 3 &pcfg_pull_default>,
999 813 <2 RK_PD1 3 &pcfg_pull_default>,
1000 814 <2 RK_PC4 4 &pcfg_pull_default>,
1001 815 <2 RK_PC5 4 &pcfg_pull_default>,
1002 816 <2 RK_PC6 4 &pcfg_pull_default>,
1003 817 <2 RK_PC7 4 &pcfg_pull_default>;
1004 }; 818 };
1005 819
1006 rmii_pins: rmii-pins 820 rmii_pins: rmii-pins {
1007 rockchip,pins 821 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
1008 822 <2 RK_PB4 3 &pcfg_pull_default>,
1009 823 <2 RK_PB5 3 &pcfg_pull_default>,
1010 824 <2 RK_PB6 3 &pcfg_pull_default>,
1011 825 <2 RK_PB7 3 &pcfg_pull_default>,
1012 826 <2 RK_PC0 3 &pcfg_pull_default>,
1013 827 <2 RK_PC1 3 &pcfg_pull_default>,
1014 828 <2 RK_PC2 3 &pcfg_pull_default>,
1015 829 <2 RK_PC3 3 &pcfg_pull_default>,
1016 830 <2 RK_PD1 3 &pcfg_pull_default>;
1017 }; 831 };
1018 }; 832 };
1019 833
1020 hdmi { 834 hdmi {
1021 hdmii2c_xfer: hdmii2c 835 hdmii2c_xfer: hdmii2c-xfer {
1022 rockchip,pins 836 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1023 837 <0 RK_PA7 2 &pcfg_pull_none>;
1024 }; 838 };
1025 839
1026 hdmi_hpd: hdmi-hpd { 840 hdmi_hpd: hdmi-hpd {
1027 rockchip,pins 841 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1028 }; 842 };
1029 843
1030 hdmi_cec: hdmi-cec { 844 hdmi_cec: hdmi-cec {
1031 rockchip,pins 845 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1032 }; 846 };
1033 }; 847 };
1034 848
1035 i2c0 { 849 i2c0 {
1036 i2c0_xfer: i2c0-xfer 850 i2c0_xfer: i2c0-xfer {
1037 rockchip,pins 851 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1038 852 <0 RK_PA1 1 &pcfg_pull_none>;
1039 }; 853 };
1040 }; 854 };
1041 855
1042 i2c1 { 856 i2c1 {
1043 i2c1_xfer: i2c1-xfer 857 i2c1_xfer: i2c1-xfer {
1044 rockchip,pins 858 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1045 859 <0 RK_PA3 1 &pcfg_pull_none>;
1046 }; 860 };
1047 }; 861 };
1048 862
1049 i2c2 { 863 i2c2 {
1050 i2c2_xfer: i2c2-xfer 864 i2c2_xfer: i2c2-xfer {
1051 rockchip,pins 865 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
1052 866 <2 RK_PC5 3 &pcfg_pull_none>;
1053 }; 867 };
1054 }; 868 };
1055 869
1056 i2c3 { 870 i2c3 {
1057 i2c3_xfer: i2c3-xfer 871 i2c3_xfer: i2c3-xfer {
1058 rockchip,pins 872 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1059 873 <0 RK_PA7 1 &pcfg_pull_none>;
1060 }; 874 };
1061 }; 875 };
1062 876
1063 i2s { 877 i2s {
1064 i2s_bus: i2s-bus { 878 i2s_bus: i2s-bus {
1065 rockchip,pins 879 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1066 880 <0 RK_PB1 1 &pcfg_pull_none>,
1067 881 <0 RK_PB3 1 &pcfg_pull_none>,
1068 882 <0 RK_PB4 1 &pcfg_pull_none>,
1069 883 <0 RK_PB5 1 &pcfg_pull_none>,
1070 884 <0 RK_PB6 1 &pcfg_pull_none>;
1071 }; 885 };
1072 886
1073 i2s1_bus: i2s1-bus { 887 i2s1_bus: i2s1-bus {
1074 rockchip,pins 888 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
1075 889 <1 RK_PA1 1 &pcfg_pull_none>,
1076 890 <1 RK_PA2 1 &pcfg_pull_none>,
1077 891 <1 RK_PA3 1 &pcfg_pull_none>,
1078 892 <1 RK_PA4 1 &pcfg_pull_none>,
1079 893 <1 RK_PA5 1 &pcfg_pull_none>;
1080 }; 894 };
1081 }; 895 };
1082 896
1083 lcdc { 897 lcdc {
1084 lcdc_dclk: lcdc-dclk 898 lcdc_dclk: lcdc-dclk {
1085 rockchip,pins 899 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
1086 }; 900 };
1087 901
1088 lcdc_den: lcdc-den { 902 lcdc_den: lcdc-den {
1089 rockchip,pins 903 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
1090 }; 904 };
1091 905
1092 lcdc_hsync: lcdc-hsyn 906 lcdc_hsync: lcdc-hsync {
1093 rockchip,pins 907 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1094 }; 908 };
1095 909
1096 lcdc_vsync: lcdc-vsyn 910 lcdc_vsync: lcdc-vsync {
1097 rockchip,pins 911 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
1098 }; 912 };
1099 913
1100 lcdc_rgb24: lcdc-rgb2 914 lcdc_rgb24: lcdc-rgb24 {
1101 rockchip,pins 915 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1102 916 <2 RK_PB5 1 &pcfg_pull_none>,
1103 917 <2 RK_PB6 1 &pcfg_pull_none>,
1104 918 <2 RK_PB7 1 &pcfg_pull_none>,
1105 919 <2 RK_PC0 1 &pcfg_pull_none>,
1106 920 <2 RK_PC1 1 &pcfg_pull_none>,
1107 921 <2 RK_PC2 1 &pcfg_pull_none>,
1108 922 <2 RK_PC3 1 &pcfg_pull_none>,
1109 923 <2 RK_PC4 1 &pcfg_pull_none>,
1110 924 <2 RK_PC5 1 &pcfg_pull_none>,
1111 925 <2 RK_PC6 1 &pcfg_pull_none>,
1112 926 <2 RK_PC7 1 &pcfg_pull_none>,
1113 927 <2 RK_PD0 1 &pcfg_pull_none>,
1114 928 <2 RK_PD1 1 &pcfg_pull_none>;
1115 }; 929 };
1116 }; 930 };
1117 931
1118 nfc { 932 nfc {
1119 flash_ale: flash-ale 933 flash_ale: flash-ale {
1120 rockchip,pins 934 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
1121 }; 935 };
1122 936
1123 flash_cle: flash-cle 937 flash_cle: flash-cle {
1124 rockchip,pins 938 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
1125 }; 939 };
1126 940
1127 flash_wrn: flash-wrn 941 flash_wrn: flash-wrn {
1128 rockchip,pins 942 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1129 }; 943 };
1130 944
1131 flash_rdn: flash-rdn 945 flash_rdn: flash-rdn {
1132 rockchip,pins 946 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
1133 }; 947 };
1134 948
1135 flash_rdy: flash-rdy 949 flash_rdy: flash-rdy {
1136 rockchip,pins 950 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1137 }; 951 };
1138 952
1139 flash_cs0: flash-cs0 953 flash_cs0: flash-cs0 {
1140 rockchip,pins 954 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1141 }; 955 };
1142 956
1143 flash_dqs: flash-dqs 957 flash_dqs: flash-dqs {
1144 rockchip,pins 958 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
1145 }; 959 };
1146 960
1147 flash_bus8: flash-bus 961 flash_bus8: flash-bus8 {
1148 rockchip,pins 962 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1149 963 <1 RK_PD1 1 &pcfg_pull_none>,
1150 964 <1 RK_PD2 1 &pcfg_pull_none>,
1151 965 <1 RK_PD3 1 &pcfg_pull_none>,
1152 966 <1 RK_PD4 1 &pcfg_pull_none>,
1153 967 <1 RK_PD5 1 &pcfg_pull_none>,
1154 968 <1 RK_PD6 1 &pcfg_pull_none>,
1155 969 <1 RK_PD7 1 &pcfg_pull_none>;
1156 }; 970 };
1157 }; 971 };
1158 972
1159 pwm0 { 973 pwm0 {
1160 pwm0_pin: pwm0-pin { 974 pwm0_pin: pwm0-pin {
1161 rockchip,pins 975 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1162 }; 976 };
1163 }; 977 };
1164 978
1165 pwm1 { 979 pwm1 {
1166 pwm1_pin: pwm1-pin { 980 pwm1_pin: pwm1-pin {
1167 rockchip,pins 981 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1168 }; 982 };
1169 }; 983 };
1170 984
1171 pwm2 { 985 pwm2 {
1172 pwm2_pin: pwm2-pin { 986 pwm2_pin: pwm2-pin {
1173 rockchip,pins 987 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1174 }; 988 };
1175 }; 989 };
1176 990
1177 pwm3 { 991 pwm3 {
1178 pwm3_pin: pwm3-pin { 992 pwm3_pin: pwm3-pin {
1179 rockchip,pins 993 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
1180 }; 994 };
1181 }; 995 };
1182 996
1183 sdio { 997 sdio {
1184 sdio_clk: sdio-clk { 998 sdio_clk: sdio-clk {
1185 rockchip,pins 999 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1186 }; 1000 };
1187 1001
1188 sdio_cmd: sdio-cmd { 1002 sdio_cmd: sdio-cmd {
1189 rockchip,pins 1003 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1190 }; 1004 };
1191 1005
1192 sdio_pwren: sdio-pwre 1006 sdio_pwren: sdio-pwren {
1193 rockchip,pins 1007 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1194 }; 1008 };
1195 1009
1196 sdio_bus4: sdio-bus4 1010 sdio_bus4: sdio-bus4 {
1197 rockchip,pins 1011 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1198 1012 <1 RK_PA2 2 &pcfg_pull_default>,
1199 1013 <1 RK_PA4 2 &pcfg_pull_default>,
1200 1014 <1 RK_PA5 2 &pcfg_pull_default>;
1201 }; 1015 };
1202 }; 1016 };
1203 1017
1204 sdmmc { 1018 sdmmc {
1205 sdmmc_clk: sdmmc-clk 1019 sdmmc_clk: sdmmc-clk {
1206 rockchip,pins 1020 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1207 }; 1021 };
1208 1022
1209 sdmmc_cmd: sdmmc-cmd 1023 sdmmc_cmd: sdmmc-cmd {
1210 rockchip,pins 1024 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1211 }; 1025 };
1212 1026
1213 sdmmc_det: sdmmc-det 1027 sdmmc_det: sdmmc-det {
1214 rockchip,pins 1028 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
1215 }; 1029 };
1216 1030
1217 sdmmc_wp: sdmmc-wp { 1031 sdmmc_wp: sdmmc-wp {
1218 rockchip,pins 1032 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1219 }; 1033 };
1220 1034
1221 sdmmc_pwren: sdmmc-pw 1035 sdmmc_pwren: sdmmc-pwren {
1222 rockchip,pins 1036 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
1223 }; 1037 };
1224 1038
1225 sdmmc_bus4: sdmmc-bus 1039 sdmmc_bus4: sdmmc-bus4 {
1226 rockchip,pins 1040 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1227 1041 <1 RK_PC3 1 &pcfg_pull_default>,
1228 1042 <1 RK_PC4 1 &pcfg_pull_default>,
1229 1043 <1 RK_PC5 1 &pcfg_pull_default>;
1230 }; <<
1231 }; <<
1232 <<
1233 sfc { <<
1234 sfc_bus2: sfc-bus2 { <<
1235 rockchip,pins <<
1236 <<
1237 }; <<
1238 <<
1239 sfc_bus4: sfc-bus4 { <<
1240 rockchip,pins <<
1241 <<
1242 <<
1243 <<
1244 }; <<
1245 <<
1246 sfc_clk: sfc-clk { <<
1247 rockchip,pins <<
1248 }; <<
1249 <<
1250 sfc_cs0: sfc-cs0 { <<
1251 rockchip,pins <<
1252 }; <<
1253 <<
1254 sfc_cs1: sfc-cs1 { <<
1255 rockchip,pins <<
1256 }; 1044 };
1257 }; 1045 };
1258 1046
1259 spdif { 1047 spdif {
1260 spdif_tx: spdif-tx { 1048 spdif_tx: spdif-tx {
1261 rockchip,pins 1049 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1262 }; 1050 };
1263 }; 1051 };
1264 1052
1265 spi0 { 1053 spi0 {
1266 spi0_clk: spi0-clk { 1054 spi0_clk: spi0-clk {
1267 rockchip,pins 1055 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1268 }; 1056 };
1269 1057
1270 spi0_cs0: spi0-cs0 { 1058 spi0_cs0: spi0-cs0 {
1271 rockchip,pins 1059 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1272 }; 1060 };
1273 1061
1274 spi0_tx: spi0-tx { 1062 spi0_tx: spi0-tx {
1275 rockchip,pins 1063 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1276 }; 1064 };
1277 1065
1278 spi0_rx: spi0-rx { 1066 spi0_rx: spi0-rx {
1279 rockchip,pins 1067 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1280 }; 1068 };
1281 1069
1282 spi0_cs1: spi0-cs1 { 1070 spi0_cs1: spi0-cs1 {
1283 rockchip,pins 1071 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1284 }; 1072 };
1285 1073
1286 spi1_clk: spi1-clk { 1074 spi1_clk: spi1-clk {
1287 rockchip,pins 1075 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1288 }; 1076 };
1289 1077
1290 spi1_cs0: spi1-cs0 { 1078 spi1_cs0: spi1-cs0 {
1291 rockchip,pins 1079 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1292 }; 1080 };
1293 1081
1294 spi1_tx: spi1-tx { 1082 spi1_tx: spi1-tx {
1295 rockchip,pins 1083 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1296 }; 1084 };
1297 1085
1298 spi1_rx: spi1-rx { 1086 spi1_rx: spi1-rx {
1299 rockchip,pins 1087 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1300 }; 1088 };
1301 1089
1302 spi1_cs1: spi1-cs1 { 1090 spi1_cs1: spi1-cs1 {
1303 rockchip,pins 1091 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1304 }; 1092 };
1305 1093
1306 spi2_clk: spi2-clk { 1094 spi2_clk: spi2-clk {
1307 rockchip,pins 1095 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1308 }; 1096 };
1309 1097
1310 spi2_cs0: spi2-cs0 { 1098 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 1099 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1312 }; 1100 };
1313 1101
1314 spi2_tx: spi2-tx { 1102 spi2_tx: spi2-tx {
1315 rockchip,pins 1103 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1316 }; 1104 };
1317 1105
1318 spi2_rx: spi2-rx { 1106 spi2_rx: spi2-rx {
1319 rockchip,pins 1107 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1320 }; 1108 };
1321 }; 1109 };
1322 1110
1323 uart0 { 1111 uart0 {
1324 uart0_xfer: uart0-xfe 1112 uart0_xfer: uart0-xfer {
1325 rockchip,pins 1113 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1326 1114 <2 RK_PD3 2 &pcfg_pull_none>;
1327 }; 1115 };
1328 1116
1329 uart0_cts: uart0-cts 1117 uart0_cts: uart0-cts {
1330 rockchip,pins 1118 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1331 }; 1119 };
1332 1120
1333 uart0_rts: uart0-rts 1121 uart0_rts: uart0-rts {
1334 rockchip,pins 1122 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1335 }; 1123 };
1336 }; 1124 };
1337 1125
1338 uart1 { 1126 uart1 {
1339 uart1_xfer: uart1-xfe 1127 uart1_xfer: uart1-xfer {
1340 rockchip,pins 1128 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1341 1129 <1 RK_PB2 2 &pcfg_pull_default>;
1342 }; 1130 };
1343 1131
1344 uart1_cts: uart1-cts 1132 uart1_cts: uart1-cts {
1345 rockchip,pins 1133 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1346 }; 1134 };
1347 1135
1348 uart1_rts: uart1-rts 1136 uart1_rts: uart1-rts {
1349 rockchip,pins 1137 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1350 }; 1138 };
1351 }; 1139 };
1352 1140
1353 uart2 { 1141 uart2 {
1354 uart2_xfer: uart2-xfe 1142 uart2_xfer: uart2-xfer {
1355 rockchip,pins 1143 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1356 1144 <1 RK_PC3 2 &pcfg_pull_none>;
1357 }; 1145 };
1358 1146
1359 uart2_cts: uart2-cts 1147 uart2_cts: uart2-cts {
1360 rockchip,pins 1148 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1361 }; 1149 };
1362 1150
1363 uart2_rts: uart2-rts 1151 uart2_rts: uart2-rts {
1364 rockchip,pins 1152 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1365 }; 1153 };
1366 }; 1154 };
1367 }; 1155 };
1368 }; 1156 };
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