1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co. 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3128-cru.h> 6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h> 11 #include <dt-bindings/power/rk3128-power.h>
12 12
13 / { 13 / {
14 compatible = "rockchip,rk3128"; 14 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 18
19 aliases { 19 aliases {
20 gpio0 = &gpio0; 20 gpio0 = &gpio0;
21 gpio1 = &gpio1; 21 gpio1 = &gpio1;
22 gpio2 = &gpio2; 22 gpio2 = &gpio2;
23 gpio3 = &gpio3; 23 gpio3 = &gpio3;
24 i2c0 = &i2c0; 24 i2c0 = &i2c0;
25 i2c1 = &i2c1; 25 i2c1 = &i2c1;
26 i2c2 = &i2c2; 26 i2c2 = &i2c2;
27 i2c3 = &i2c3; 27 i2c3 = &i2c3;
28 serial0 = &uart0; 28 serial0 = &uart0;
29 serial1 = &uart1; 29 serial1 = &uart1;
30 serial2 = &uart2; 30 serial2 = &uart2;
31 }; 31 };
32 32
33 arm-pmu { 33 arm-pmu {
34 compatible = "arm,cortex-a7-pm 34 compatible = "arm,cortex-a7-pmu";
35 interrupts = <GIC_SPI 76 IRQ_T 35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 77 IRQ_T 36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 78 IRQ_T 37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 79 IRQ_T 38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
39 interrupt-affinity = <&cpu0>, 39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <1>; 43 #address-cells = <1>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 enable-method = "rockchip,rk30 45 enable-method = "rockchip,rk3036-smp";
46 46
47 cpu0: cpu@f00 { 47 cpu0: cpu@f00 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "arm,cort 49 compatible = "arm,cortex-a7";
50 reg = <0xf00>; 50 reg = <0xf00>;
51 clock-latency = <40000 51 clock-latency = <40000>;
52 clocks = <&cru ARMCLK> 52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CO 53 resets = <&cru SRST_CORE0>;
54 operating-points-v2 = 54 operating-points-v2 = <&cpu_opp_table>;
55 #cooling-cells = <2>; 55 #cooling-cells = <2>; /* min followed by max */
56 }; 56 };
57 57
58 cpu1: cpu@f01 { 58 cpu1: cpu@f01 {
59 device_type = "cpu"; 59 device_type = "cpu";
60 compatible = "arm,cort 60 compatible = "arm,cortex-a7";
61 reg = <0xf01>; 61 reg = <0xf01>;
62 resets = <&cru SRST_CO 62 resets = <&cru SRST_CORE1>;
63 operating-points-v2 = 63 operating-points-v2 = <&cpu_opp_table>;
64 }; 64 };
65 65
66 cpu2: cpu@f02 { 66 cpu2: cpu@f02 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cort 68 compatible = "arm,cortex-a7";
69 reg = <0xf02>; 69 reg = <0xf02>;
70 resets = <&cru SRST_CO 70 resets = <&cru SRST_CORE2>;
71 operating-points-v2 = 71 operating-points-v2 = <&cpu_opp_table>;
72 }; 72 };
73 73
74 cpu3: cpu@f03 { 74 cpu3: cpu@f03 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 compatible = "arm,cort 76 compatible = "arm,cortex-a7";
77 reg = <0xf03>; 77 reg = <0xf03>;
78 resets = <&cru SRST_CO 78 resets = <&cru SRST_CORE3>;
79 operating-points-v2 = 79 operating-points-v2 = <&cpu_opp_table>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu_opp_table: opp-table-0 { 83 cpu_opp_table: opp-table-0 {
84 compatible = "operating-points 84 compatible = "operating-points-v2";
85 opp-shared; 85 opp-shared;
86 86
87 opp-216000000 { 87 opp-216000000 {
88 opp-hz = /bits/ 64 <21 88 opp-hz = /bits/ 64 <216000000>;
89 opp-microvolt = <95000 89 opp-microvolt = <950000 950000 1325000>;
90 }; 90 };
91 opp-408000000 { 91 opp-408000000 {
92 opp-hz = /bits/ 64 <40 92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <95000 93 opp-microvolt = <950000 950000 1325000>;
94 }; 94 };
95 opp-600000000 { 95 opp-600000000 {
96 opp-hz = /bits/ 64 <60 96 opp-hz = /bits/ 64 <600000000>;
97 opp-microvolt = <95000 97 opp-microvolt = <950000 950000 1325000>;
98 }; 98 };
99 opp-696000000 { 99 opp-696000000 {
100 opp-hz = /bits/ 64 <69 100 opp-hz = /bits/ 64 <696000000>;
101 opp-microvolt = <97500 101 opp-microvolt = <975000 975000 1325000>;
102 }; 102 };
103 opp-816000000 { 103 opp-816000000 {
104 opp-hz = /bits/ 64 <81 104 opp-hz = /bits/ 64 <816000000>;
105 opp-microvolt = <10750 105 opp-microvolt = <1075000 1075000 1325000>;
106 opp-suspend; 106 opp-suspend;
107 }; 107 };
108 opp-1008000000 { 108 opp-1008000000 {
109 opp-hz = /bits/ 64 <10 109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <12000 110 opp-microvolt = <1200000 1200000 1325000>;
111 }; 111 };
112 opp-1200000000 { 112 opp-1200000000 {
113 opp-hz = /bits/ 64 <12 113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <13250 114 opp-microvolt = <1325000 1325000 1325000>;
115 }; 115 };
116 }; 116 };
117 117
118 display_subsystem: display-subsystem { 118 display_subsystem: display-subsystem {
119 compatible = "rockchip,display 119 compatible = "rockchip,display-subsystem";
120 ports = <&vop_out>; 120 ports = <&vop_out>;
121 status = "disabled"; 121 status = "disabled";
122 }; 122 };
123 123
124 gpu_opp_table: opp-table-1 { 124 gpu_opp_table: opp-table-1 {
125 compatible = "operating-points 125 compatible = "operating-points-v2";
126 126
127 opp-200000000 { 127 opp-200000000 {
128 opp-hz = /bits/ 64 <20 128 opp-hz = /bits/ 64 <200000000>;
129 opp-microvolt = <97500 129 opp-microvolt = <975000 975000 1250000>;
130 }; 130 };
131 opp-300000000 { 131 opp-300000000 {
132 opp-hz = /bits/ 64 <30 132 opp-hz = /bits/ 64 <300000000>;
133 opp-microvolt = <10500 133 opp-microvolt = <1050000 1050000 1250000>;
134 }; 134 };
135 opp-400000000 { 135 opp-400000000 {
136 opp-hz = /bits/ 64 <40 136 opp-hz = /bits/ 64 <400000000>;
137 opp-microvolt = <11500 137 opp-microvolt = <1150000 1150000 1250000>;
138 }; 138 };
139 opp-480000000 { 139 opp-480000000 {
140 opp-hz = /bits/ 64 <48 140 opp-hz = /bits/ 64 <480000000>;
141 opp-microvolt = <12500 141 opp-microvolt = <1250000 1250000 1250000>;
142 }; 142 };
143 }; 143 };
144 144
145 timer { 145 timer {
146 compatible = "arm,armv7-timer" 146 compatible = "arm,armv7-timer";
147 interrupts = <GIC_PPI 13 (GIC_ 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 14 (GIC_ 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
149 <GIC_PPI 11 (GIC_ 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
150 <GIC_PPI 10 (GIC_ 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151 arm,cpu-registers-not-fw-confi 151 arm,cpu-registers-not-fw-configured;
152 clock-frequency = <24000000>; 152 clock-frequency = <24000000>;
153 }; 153 };
154 154
155 xin24m: oscillator { 155 xin24m: oscillator {
156 compatible = "fixed-clock"; 156 compatible = "fixed-clock";
157 clock-frequency = <24000000>; 157 clock-frequency = <24000000>;
158 clock-output-names = "xin24m"; 158 clock-output-names = "xin24m";
159 #clock-cells = <0>; 159 #clock-cells = <0>;
160 }; 160 };
161 161
162 imem: sram@10080000 { 162 imem: sram@10080000 {
163 compatible = "mmio-sram"; 163 compatible = "mmio-sram";
164 reg = <0x10080000 0x2000>; 164 reg = <0x10080000 0x2000>;
165 #address-cells = <1>; 165 #address-cells = <1>;
166 #size-cells = <1>; 166 #size-cells = <1>;
167 ranges = <0 0x10080000 0x2000> 167 ranges = <0 0x10080000 0x2000>;
168 168
169 smp-sram@0 { 169 smp-sram@0 {
170 compatible = "rockchip 170 compatible = "rockchip,rk3066-smp-sram";
171 reg = <0x00 0x10>; 171 reg = <0x00 0x10>;
172 }; 172 };
173 }; 173 };
174 174
175 gpu: gpu@10090000 { 175 gpu: gpu@10090000 {
176 compatible = "rockchip,rk3128- 176 compatible = "rockchip,rk3128-mali", "arm,mali-400";
177 reg = <0x10090000 0x10000>; 177 reg = <0x10090000 0x10000>;
178 interrupts = <GIC_SPI 3 IRQ_TY 178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 4 IRQ_TY 179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 5 IRQ_TY 180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 4 IRQ_TY 181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 5 IRQ_TY 182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 4 IRQ_TY 183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "gp", 184 interrupt-names = "gp",
185 "gpmmu", 185 "gpmmu",
186 "pp0", 186 "pp0",
187 "ppmmu0", 187 "ppmmu0",
188 "pp1", 188 "pp1",
189 "ppmmu1"; 189 "ppmmu1";
190 clocks = <&cru ACLK_GPU>, <&cr 190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
191 clock-names = "bus", "core"; 191 clock-names = "bus", "core";
192 operating-points-v2 = <&gpu_op 192 operating-points-v2 = <&gpu_opp_table>;
193 resets = <&cru SRST_GPU>; 193 resets = <&cru SRST_GPU>;
194 power-domains = <&power RK3128 194 power-domains = <&power RK3128_PD_GPU>;
195 status = "disabled"; 195 status = "disabled";
196 }; 196 };
197 197
198 pmu: syscon@100a0000 { 198 pmu: syscon@100a0000 {
199 compatible = "rockchip,rk3128- 199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
200 reg = <0x100a0000 0x1000>; 200 reg = <0x100a0000 0x1000>;
201 201
202 power: power-controller { 202 power: power-controller {
203 compatible = "rockchip 203 compatible = "rockchip,rk3128-power-controller";
204 #power-domain-cells = 204 #power-domain-cells = <1>;
205 #address-cells = <1>; 205 #address-cells = <1>;
206 #size-cells = <0>; 206 #size-cells = <0>;
207 207
208 power-domain@RK3128_PD 208 power-domain@RK3128_PD_VIO {
209 reg = <RK3128_ 209 reg = <RK3128_PD_VIO>;
210 clocks = <&cru 210 clocks = <&cru ACLK_CIF>,
211 <&cru 211 <&cru HCLK_CIF>,
212 <&cru 212 <&cru DCLK_EBC>,
213 <&cru 213 <&cru HCLK_EBC>,
214 <&cru 214 <&cru ACLK_IEP>,
215 <&cru 215 <&cru HCLK_IEP>,
216 <&cru 216 <&cru ACLK_LCDC0>,
217 <&cru 217 <&cru HCLK_LCDC0>,
218 <&cru 218 <&cru PCLK_MIPI>,
219 <&cru 219 <&cru PCLK_MIPIPHY>,
220 <&cru 220 <&cru SCLK_MIPI_24M>,
221 <&cru 221 <&cru ACLK_RGA>,
222 <&cru 222 <&cru HCLK_RGA>,
223 <&cru 223 <&cru ACLK_VIO0>,
224 <&cru 224 <&cru ACLK_VIO1>,
225 <&cru 225 <&cru HCLK_VIO>,
226 <&cru 226 <&cru HCLK_VIO_H2P>,
227 <&cru 227 <&cru DCLK_VOP>,
228 <&cru 228 <&cru SCLK_VOP>;
229 pm_qos = <&qos 229 pm_qos = <&qos_ebc>,
230 <&qos 230 <&qos_iep>,
231 <&qos 231 <&qos_lcdc>,
232 <&qos 232 <&qos_rga>,
233 <&qos 233 <&qos_vip>;
234 #power-domain- 234 #power-domain-cells = <0>;
235 }; 235 };
236 236
237 power-domain@RK3128_PD 237 power-domain@RK3128_PD_VIDEO {
238 reg = <RK3128_ 238 reg = <RK3128_PD_VIDEO>;
239 clocks = <&cru 239 clocks = <&cru ACLK_VDPU>,
240 <&cru 240 <&cru HCLK_VDPU>,
241 <&cru 241 <&cru ACLK_VEPU>,
242 <&cru 242 <&cru HCLK_VEPU>,
243 <&cru 243 <&cru SCLK_HEVC_CORE>;
244 pm_qos = <&qos 244 pm_qos = <&qos_vpu>;
245 #power-domain- 245 #power-domain-cells = <0>;
246 }; 246 };
247 247
248 power-domain@RK3128_PD 248 power-domain@RK3128_PD_GPU {
249 reg = <RK3128_ 249 reg = <RK3128_PD_GPU>;
250 clocks = <&cru 250 clocks = <&cru ACLK_GPU>;
251 pm_qos = <&qos 251 pm_qos = <&qos_gpu>;
252 #power-domain- 252 #power-domain-cells = <0>;
253 }; 253 };
254 }; 254 };
255 }; 255 };
256 256
257 vpu: video-codec@10106000 { 257 vpu: video-codec@10106000 {
258 compatible = "rockchip,rk3128- 258 compatible = "rockchip,rk3128-vpu", "rockchip,rk3066-vpu";
259 reg = <0x10106000 0x800>; 259 reg = <0x10106000 0x800>;
260 interrupts = <GIC_SPI 6 IRQ_TY 260 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 7 IRQ_TY 261 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-names = "vepu", "vdp 262 interrupt-names = "vepu", "vdpu";
263 clocks = <&cru ACLK_VDPU>, <&c 263 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
264 <&cru ACLK_VEPU>, <&c 264 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
265 clock-names = "aclk_vdpu", "hc 265 clock-names = "aclk_vdpu", "hclk_vdpu",
266 "aclk_vepu", "hc 266 "aclk_vepu", "hclk_vepu";
267 iommus = <&vpu_mmu>; 267 iommus = <&vpu_mmu>;
268 power-domains = <&power RK3128 268 power-domains = <&power RK3128_PD_VIDEO>;
269 }; 269 };
270 270
271 vpu_mmu: iommu@10106800 { 271 vpu_mmu: iommu@10106800 {
272 compatible = "rockchip,iommu"; 272 compatible = "rockchip,iommu";
273 reg = <0x10106800 0x100>; 273 reg = <0x10106800 0x100>;
274 interrupts = <GIC_SPI 67 IRQ_T 274 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&cru ACLK_VEPU>, <&c 275 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VDPU>;
276 clock-names = "aclk", "iface"; 276 clock-names = "aclk", "iface";
277 power-domains = <&power RK3128 277 power-domains = <&power RK3128_PD_VIDEO>;
278 #iommu-cells = <0>; 278 #iommu-cells = <0>;
279 }; 279 };
280 280
281 vop: vop@1010e000 { 281 vop: vop@1010e000 {
282 compatible = "rockchip,rk3126- 282 compatible = "rockchip,rk3126-vop";
283 reg = <0x1010e000 0x300>; 283 reg = <0x1010e000 0x300>;
284 interrupts = <GIC_SPI 9 IRQ_TY 284 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru ACLK_LCDC0>, <& 285 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
286 <&cru HCLK_LCDC0>; 286 <&cru HCLK_LCDC0>;
287 clock-names = "aclk_vop", "dcl 287 clock-names = "aclk_vop", "dclk_vop",
288 "hclk_vop"; 288 "hclk_vop";
289 resets = <&cru SRST_VOP_A>, <& 289 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>,
290 <&cru SRST_VOP_D>; 290 <&cru SRST_VOP_D>;
291 reset-names = "axi", "ahb", 291 reset-names = "axi", "ahb",
292 "dclk"; 292 "dclk";
293 power-domains = <&power RK3128 293 power-domains = <&power RK3128_PD_VIO>;
294 status = "disabled"; 294 status = "disabled";
295 295
296 vop_out: port { 296 vop_out: port {
297 #address-cells = <1>; 297 #address-cells = <1>;
298 #size-cells = <0>; 298 #size-cells = <0>;
299 299
300 vop_out_hdmi: endpoint 300 vop_out_hdmi: endpoint@0 {
301 reg = <0>; 301 reg = <0>;
302 remote-endpoin 302 remote-endpoint = <&hdmi_in_vop>;
303 }; 303 };
304 304
305 vop_out_dsi: endpoint@ 305 vop_out_dsi: endpoint@1 {
306 reg = <1>; 306 reg = <1>;
307 remote-endpoin 307 remote-endpoint = <&dsi_in_vop>;
308 }; 308 };
309 }; 309 };
310 }; 310 };
311 311
312 dsi: dsi@10110000 { 312 dsi: dsi@10110000 {
313 compatible = "rockchip,rk3128- 313 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
314 reg = <0x10110000 0x4000>; 314 reg = <0x10110000 0x4000>;
315 interrupts = <GIC_SPI 33 IRQ_T 315 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&cru PCLK_MIPI>; 316 clocks = <&cru PCLK_MIPI>;
317 clock-names = "pclk"; 317 clock-names = "pclk";
318 phys = <&dphy>; 318 phys = <&dphy>;
319 phy-names = "dphy"; 319 phy-names = "dphy";
320 power-domains = <&power RK3128 320 power-domains = <&power RK3128_PD_VIO>;
321 resets = <&cru SRST_VIO_MIPI_D 321 resets = <&cru SRST_VIO_MIPI_DSI>;
322 reset-names = "apb"; 322 reset-names = "apb";
323 rockchip,grf = <&grf>; 323 rockchip,grf = <&grf>;
324 status = "disabled"; 324 status = "disabled";
325 325
326 ports { 326 ports {
327 #address-cells = <1>; 327 #address-cells = <1>;
328 #size-cells = <0>; 328 #size-cells = <0>;
329 329
330 dsi_in: port@0 { 330 dsi_in: port@0 {
331 reg = <0>; 331 reg = <0>;
332 332
333 dsi_in_vop: en 333 dsi_in_vop: endpoint {
334 remote 334 remote-endpoint = <&vop_out_dsi>;
335 }; 335 };
336 }; 336 };
337 337
338 dsi_out: port@1 { 338 dsi_out: port@1 {
339 reg = <1>; 339 reg = <1>;
340 }; 340 };
341 }; 341 };
342 }; 342 };
343 343
344 qos_gpu: qos@1012d000 { 344 qos_gpu: qos@1012d000 {
345 compatible = "rockchip,rk3128- 345 compatible = "rockchip,rk3128-qos", "syscon";
346 reg = <0x1012d000 0x20>; 346 reg = <0x1012d000 0x20>;
347 }; 347 };
348 348
349 qos_vpu: qos@1012e000 { 349 qos_vpu: qos@1012e000 {
350 compatible = "rockchip,rk3128- 350 compatible = "rockchip,rk3128-qos", "syscon";
351 reg = <0x1012e000 0x20>; 351 reg = <0x1012e000 0x20>;
352 }; 352 };
353 353
354 qos_rga: qos@1012f000 { 354 qos_rga: qos@1012f000 {
355 compatible = "rockchip,rk3128- 355 compatible = "rockchip,rk3128-qos", "syscon";
356 reg = <0x1012f000 0x20>; 356 reg = <0x1012f000 0x20>;
357 }; 357 };
358 358
359 qos_ebc: qos@1012f080 { 359 qos_ebc: qos@1012f080 {
360 compatible = "rockchip,rk3128- 360 compatible = "rockchip,rk3128-qos", "syscon";
361 reg = <0x1012f080 0x20>; 361 reg = <0x1012f080 0x20>;
362 }; 362 };
363 363
364 qos_iep: qos@1012f100 { 364 qos_iep: qos@1012f100 {
365 compatible = "rockchip,rk3128- 365 compatible = "rockchip,rk3128-qos", "syscon";
366 reg = <0x1012f100 0x20>; 366 reg = <0x1012f100 0x20>;
367 }; 367 };
368 368
369 qos_lcdc: qos@1012f180 { 369 qos_lcdc: qos@1012f180 {
370 compatible = "rockchip,rk3128- 370 compatible = "rockchip,rk3128-qos", "syscon";
371 reg = <0x1012f180 0x20>; 371 reg = <0x1012f180 0x20>;
372 }; 372 };
373 373
374 qos_vip: qos@1012f200 { 374 qos_vip: qos@1012f200 {
375 compatible = "rockchip,rk3128- 375 compatible = "rockchip,rk3128-qos", "syscon";
376 reg = <0x1012f200 0x20>; 376 reg = <0x1012f200 0x20>;
377 }; 377 };
378 378
379 gic: interrupt-controller@10139000 { 379 gic: interrupt-controller@10139000 {
380 compatible = "arm,cortex-a7-gi 380 compatible = "arm,cortex-a7-gic";
381 reg = <0x10139000 0x1000>, 381 reg = <0x10139000 0x1000>,
382 <0x1013a000 0x1000>, 382 <0x1013a000 0x1000>,
383 <0x1013c000 0x2000>, 383 <0x1013c000 0x2000>,
384 <0x1013e000 0x2000>; 384 <0x1013e000 0x2000>;
385 interrupts = <GIC_PPI 9 (GIC_C 385 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
386 interrupt-controller; 386 interrupt-controller;
387 #interrupt-cells = <3>; 387 #interrupt-cells = <3>;
388 #address-cells = <0>; 388 #address-cells = <0>;
389 }; 389 };
390 390
391 usb_otg: usb@10180000 { 391 usb_otg: usb@10180000 {
392 compatible = "rockchip,rk3128- 392 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
393 reg = <0x10180000 0x40000>; 393 reg = <0x10180000 0x40000>;
394 interrupts = <GIC_SPI 10 IRQ_T 394 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru HCLK_OTG>; 395 clocks = <&cru HCLK_OTG>;
396 clock-names = "otg"; 396 clock-names = "otg";
397 dr_mode = "otg"; 397 dr_mode = "otg";
398 g-np-tx-fifo-size = <16>; 398 g-np-tx-fifo-size = <16>;
399 g-rx-fifo-size = <280>; 399 g-rx-fifo-size = <280>;
400 g-tx-fifo-size = <256 128 128 400 g-tx-fifo-size = <256 128 128 64 32 16>;
401 phys = <&usb2phy_otg>; 401 phys = <&usb2phy_otg>;
402 phy-names = "usb2-phy"; 402 phy-names = "usb2-phy";
403 status = "disabled"; 403 status = "disabled";
404 }; 404 };
405 405
406 usb_host_ehci: usb@101c0000 { 406 usb_host_ehci: usb@101c0000 {
407 compatible = "generic-ehci"; 407 compatible = "generic-ehci";
408 reg = <0x101c0000 0x20000>; 408 reg = <0x101c0000 0x20000>;
409 interrupts = <GIC_SPI 11 IRQ_T 409 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cru HCLK_HOST2>; 410 clocks = <&cru HCLK_HOST2>;
411 phys = <&usb2phy_host>; 411 phys = <&usb2phy_host>;
412 phy-names = "usb"; 412 phy-names = "usb";
413 status = "disabled"; 413 status = "disabled";
414 }; 414 };
415 415
416 usb_host_ohci: usb@101e0000 { 416 usb_host_ohci: usb@101e0000 {
417 compatible = "generic-ohci"; 417 compatible = "generic-ohci";
418 reg = <0x101e0000 0x20000>; 418 reg = <0x101e0000 0x20000>;
419 interrupts = <GIC_SPI 32 IRQ_T 419 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru HCLK_HOST2>; 420 clocks = <&cru HCLK_HOST2>;
421 phys = <&usb2phy_host>; 421 phys = <&usb2phy_host>;
422 phy-names = "usb"; 422 phy-names = "usb";
423 status = "disabled"; 423 status = "disabled";
424 }; 424 };
425 425
426 i2s_8ch: i2s@10200000 { 426 i2s_8ch: i2s@10200000 {
427 compatible = "rockchip,rk3128- 427 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
428 reg = <0x10200000 0x1000>; 428 reg = <0x10200000 0x1000>;
429 interrupts = <GIC_SPI 68 IRQ_T 429 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cru SCLK_I2S0>, <&c 430 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>;
431 clock-names = "i2s_clk", "i2s_ 431 clock-names = "i2s_clk", "i2s_hclk";
432 dmas = <&pdma 14>, <&pdma 15>; 432 dmas = <&pdma 14>, <&pdma 15>;
433 dma-names = "tx", "rx"; 433 dma-names = "tx", "rx";
434 #sound-dai-cells = <0>; 434 #sound-dai-cells = <0>;
435 status = "disabled"; 435 status = "disabled";
436 }; 436 };
437 437
438 spdif: spdif@10204000 { 438 spdif: spdif@10204000 {
439 compatible = "rockchip,rk3128- 439 compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif";
440 reg = <0x10204000 0x1000>; 440 reg = <0x10204000 0x1000>;
441 interrupts = <GIC_SPI 55 IRQ_T 441 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru SCLK_SPDIF>, <& 442 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
443 clock-names = "mclk", "hclk"; 443 clock-names = "mclk", "hclk";
444 dmas = <&pdma 13>; 444 dmas = <&pdma 13>;
445 dma-names = "tx"; 445 dma-names = "tx";
446 pinctrl-names = "default"; 446 pinctrl-names = "default";
447 pinctrl-0 = <&spdif_tx>; 447 pinctrl-0 = <&spdif_tx>;
448 #sound-dai-cells = <0>; 448 #sound-dai-cells = <0>;
449 status = "disabled"; 449 status = "disabled";
450 }; 450 };
451 451
452 sfc: spi@1020c000 { 452 sfc: spi@1020c000 {
453 compatible = "rockchip,sfc"; 453 compatible = "rockchip,sfc";
454 reg = <0x1020c000 0x8000>; 454 reg = <0x1020c000 0x8000>;
455 interrupts = <GIC_SPI 50 IRQ_T 455 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cru SCLK_SFC>, <&cr 456 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
457 clock-names = "clk_sfc", "hclk 457 clock-names = "clk_sfc", "hclk_sfc";
458 status = "disabled"; 458 status = "disabled";
459 }; 459 };
460 460
461 sdmmc: mmc@10214000 { 461 sdmmc: mmc@10214000 {
462 compatible = "rockchip,rk3128- 462 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
463 reg = <0x10214000 0x4000>; 463 reg = <0x10214000 0x4000>;
464 interrupts = <GIC_SPI 14 IRQ_T 464 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_SDMMC>, <& 465 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
466 <&cru SCLK_SDMMC_DRV> 466 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
467 clock-names = "biu", "ciu", "c 467 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
468 dmas = <&pdma 10>; 468 dmas = <&pdma 10>;
469 dma-names = "rx-tx"; 469 dma-names = "rx-tx";
470 fifo-depth = <256>; 470 fifo-depth = <256>;
471 max-frequency = <150000000>; 471 max-frequency = <150000000>;
472 resets = <&cru SRST_SDMMC>; 472 resets = <&cru SRST_SDMMC>;
473 reset-names = "reset"; 473 reset-names = "reset";
474 status = "disabled"; 474 status = "disabled";
475 }; 475 };
476 476
477 sdio: mmc@10218000 { 477 sdio: mmc@10218000 {
478 compatible = "rockchip,rk3128- 478 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
479 reg = <0x10218000 0x4000>; 479 reg = <0x10218000 0x4000>;
480 interrupts = <GIC_SPI 15 IRQ_T 480 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_SDIO>, <&c 481 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
482 <&cru SCLK_SDIO_DRV>, 482 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
483 clock-names = "biu", "ciu", "c 483 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
484 dmas = <&pdma 11>; 484 dmas = <&pdma 11>;
485 dma-names = "rx-tx"; 485 dma-names = "rx-tx";
486 fifo-depth = <256>; 486 fifo-depth = <256>;
487 max-frequency = <150000000>; 487 max-frequency = <150000000>;
488 resets = <&cru SRST_SDIO>; 488 resets = <&cru SRST_SDIO>;
489 reset-names = "reset"; 489 reset-names = "reset";
490 status = "disabled"; 490 status = "disabled";
491 }; 491 };
492 492
493 emmc: mmc@1021c000 { 493 emmc: mmc@1021c000 {
494 compatible = "rockchip,rk3128- 494 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
495 reg = <0x1021c000 0x4000>; 495 reg = <0x1021c000 0x4000>;
496 interrupts = <GIC_SPI 16 IRQ_T 496 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru HCLK_EMMC>, <&c 497 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
498 <&cru SCLK_EMMC_DRV>, 498 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
499 clock-names = "biu", "ciu", "c 499 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
500 dmas = <&pdma 12>; 500 dmas = <&pdma 12>;
501 dma-names = "rx-tx"; 501 dma-names = "rx-tx";
502 fifo-depth = <256>; 502 fifo-depth = <256>;
503 max-frequency = <150000000>; 503 max-frequency = <150000000>;
504 resets = <&cru SRST_EMMC>; 504 resets = <&cru SRST_EMMC>;
505 reset-names = "reset"; 505 reset-names = "reset";
506 status = "disabled"; 506 status = "disabled";
507 }; 507 };
508 508
509 i2s_2ch: i2s@10220000 { 509 i2s_2ch: i2s@10220000 {
510 compatible = "rockchip,rk3128- 510 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
511 reg = <0x10220000 0x1000>; 511 reg = <0x10220000 0x1000>;
512 interrupts = <GIC_SPI 19 IRQ_T 512 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cru SCLK_I2S1>, <&c 513 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>;
514 clock-names = "i2s_clk", "i2s_ 514 clock-names = "i2s_clk", "i2s_hclk";
515 dmas = <&pdma 0>, <&pdma 1>; 515 dmas = <&pdma 0>, <&pdma 1>;
516 dma-names = "tx", "rx"; 516 dma-names = "tx", "rx";
517 rockchip,playback-channels = < 517 rockchip,playback-channels = <2>;
518 pinctrl-names = "default"; 518 pinctrl-names = "default";
519 pinctrl-0 = <&i2s_bus>; 519 pinctrl-0 = <&i2s_bus>;
520 #sound-dai-cells = <0>; 520 #sound-dai-cells = <0>;
521 status = "disabled"; 521 status = "disabled";
522 }; 522 };
523 523
524 nfc: nand-controller@10500000 { 524 nfc: nand-controller@10500000 {
525 compatible = "rockchip,rk3128- 525 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
526 reg = <0x10500000 0x4000>; 526 reg = <0x10500000 0x4000>;
527 interrupts = <GIC_SPI 18 IRQ_T 527 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&cru HCLK_NANDC>, <& 528 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
529 clock-names = "ahb", "nfc"; 529 clock-names = "ahb", "nfc";
530 pinctrl-names = "default"; 530 pinctrl-names = "default";
531 pinctrl-0 = <&flash_ale &flash 531 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
532 &flash_dqs &flash 532 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
533 status = "disabled"; 533 status = "disabled";
534 }; 534 };
535 535
536 cru: clock-controller@20000000 { 536 cru: clock-controller@20000000 {
537 compatible = "rockchip,rk3128- 537 compatible = "rockchip,rk3128-cru";
538 reg = <0x20000000 0x1000>; 538 reg = <0x20000000 0x1000>;
539 clocks = <&xin24m>; 539 clocks = <&xin24m>;
540 clock-names = "xin24m"; 540 clock-names = "xin24m";
541 rockchip,grf = <&grf>; 541 rockchip,grf = <&grf>;
542 #clock-cells = <1>; 542 #clock-cells = <1>;
543 #reset-cells = <1>; 543 #reset-cells = <1>;
544 assigned-clocks = <&cru PLL_GP 544 assigned-clocks = <&cru PLL_GPLL>;
545 assigned-clock-rates = <594000 545 assigned-clock-rates = <594000000>;
546 }; 546 };
547 547
548 grf: syscon@20008000 { 548 grf: syscon@20008000 {
549 compatible = "rockchip,rk3128- 549 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
550 reg = <0x20008000 0x1000>; 550 reg = <0x20008000 0x1000>;
551 #address-cells = <1>; 551 #address-cells = <1>;
552 #size-cells = <1>; 552 #size-cells = <1>;
553 553
554 usb2phy: usb2phy@17c { 554 usb2phy: usb2phy@17c {
555 compatible = "rockchip 555 compatible = "rockchip,rk3128-usb2phy";
556 reg = <0x017c 0x0c>; 556 reg = <0x017c 0x0c>;
557 clocks = <&cru SCLK_OT 557 clocks = <&cru SCLK_OTGPHY0>;
558 clock-names = "phyclk" 558 clock-names = "phyclk";
559 clock-output-names = " 559 clock-output-names = "usb480m_phy";
560 assigned-clocks = <&cr 560 assigned-clocks = <&cru SCLK_USB480M>;
561 assigned-clock-parents 561 assigned-clock-parents = <&usb2phy>;
562 #clock-cells = <0>; 562 #clock-cells = <0>;
563 status = "disabled"; 563 status = "disabled";
564 564
565 usb2phy_host: host-por 565 usb2phy_host: host-port {
566 interrupts = < 566 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-name 567 interrupt-names = "linestate";
568 #phy-cells = < 568 #phy-cells = <0>;
569 status = "disa 569 status = "disabled";
570 }; 570 };
571 571
572 usb2phy_otg: otg-port 572 usb2phy_otg: otg-port {
573 interrupts = < 573 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
574 < 574 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
575 < 575 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-name 576 interrupt-names = "otg-bvalid", "otg-id",
577 577 "linestate";
578 #phy-cells = < 578 #phy-cells = <0>;
579 status = "disa 579 status = "disabled";
580 }; 580 };
581 }; 581 };
582 }; 582 };
583 583
584 hdmi: hdmi@20034000 { 584 hdmi: hdmi@20034000 {
585 compatible = "rockchip,rk3128- 585 compatible = "rockchip,rk3128-inno-hdmi";
586 reg = <0x20034000 0x4000>; 586 reg = <0x20034000 0x4000>;
587 interrupts = <GIC_SPI 45 IRQ_T 587 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cru PCLK_HDMI>, <&c 588 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
589 clock-names = "pclk", "ref"; 589 clock-names = "pclk", "ref";
590 pinctrl-names = "default"; 590 pinctrl-names = "default";
591 pinctrl-0 = <&hdmii2c_xfer &hd 591 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
592 power-domains = <&power RK3128 592 power-domains = <&power RK3128_PD_VIO>;
593 #sound-dai-cells = <0>; 593 #sound-dai-cells = <0>;
594 status = "disabled"; 594 status = "disabled";
595 595
596 ports { 596 ports {
597 #address-cells = <1>; 597 #address-cells = <1>;
598 #size-cells = <0>; 598 #size-cells = <0>;
599 599
600 hdmi_in: port@0 { 600 hdmi_in: port@0 {
601 reg = <0>; 601 reg = <0>;
602 hdmi_in_vop: e 602 hdmi_in_vop: endpoint {
603 remote 603 remote-endpoint = <&vop_out_hdmi>;
604 }; 604 };
605 }; 605 };
606 606
607 hdmi_out: port@1 { 607 hdmi_out: port@1 {
608 reg = <1>; 608 reg = <1>;
609 }; 609 };
610 }; 610 };
611 }; 611 };
612 612
613 dphy: phy@20038000 { 613 dphy: phy@20038000 {
614 compatible = "rockchip,rk3128- 614 compatible = "rockchip,rk3128-dsi-dphy";
615 reg = <0x20038000 0x4000>; 615 reg = <0x20038000 0x4000>;
616 clocks = <&cru SCLK_MIPI_24M>, 616 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
617 clock-names = "ref", "pclk"; 617 clock-names = "ref", "pclk";
618 #phy-cells = <0>; 618 #phy-cells = <0>;
619 power-domains = <&power RK3128 619 power-domains = <&power RK3128_PD_VIO>;
620 resets = <&cru SRST_MIPIPHY_P> 620 resets = <&cru SRST_MIPIPHY_P>;
621 reset-names = "apb"; 621 reset-names = "apb";
622 status = "disabled"; 622 status = "disabled";
623 }; 623 };
624 624
625 timer0: timer@20044000 { 625 timer0: timer@20044000 {
626 compatible = "rockchip,rk3128- 626 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
627 reg = <0x20044000 0x20>; 627 reg = <0x20044000 0x20>;
628 interrupts = <GIC_SPI 28 IRQ_T 628 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru PCLK_TIMER>, <& 629 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
630 clock-names = "pclk", "timer"; 630 clock-names = "pclk", "timer";
631 }; 631 };
632 632
633 timer1: timer@20044020 { 633 timer1: timer@20044020 {
634 compatible = "rockchip,rk3128- 634 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
635 reg = <0x20044020 0x20>; 635 reg = <0x20044020 0x20>;
636 interrupts = <GIC_SPI 29 IRQ_T 636 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru PCLK_TIMER>, <& 637 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
638 clock-names = "pclk", "timer"; 638 clock-names = "pclk", "timer";
639 }; 639 };
640 640
641 timer2: timer@20044040 { 641 timer2: timer@20044040 {
642 compatible = "rockchip,rk3128- 642 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
643 reg = <0x20044040 0x20>; 643 reg = <0x20044040 0x20>;
644 interrupts = <GIC_SPI 59 IRQ_T 644 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru PCLK_TIMER>, <& 645 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
646 clock-names = "pclk", "timer"; 646 clock-names = "pclk", "timer";
647 }; 647 };
648 648
649 timer3: timer@20044060 { 649 timer3: timer@20044060 {
650 compatible = "rockchip,rk3128- 650 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
651 reg = <0x20044060 0x20>; 651 reg = <0x20044060 0x20>;
652 interrupts = <GIC_SPI 60 IRQ_T 652 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru PCLK_TIMER>, <& 653 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
654 clock-names = "pclk", "timer"; 654 clock-names = "pclk", "timer";
655 }; 655 };
656 656
657 timer4: timer@20044080 { 657 timer4: timer@20044080 {
658 compatible = "rockchip,rk3128- 658 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
659 reg = <0x20044080 0x20>; 659 reg = <0x20044080 0x20>;
660 interrupts = <GIC_SPI 61 IRQ_T 660 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cru PCLK_TIMER>, <& 661 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
662 clock-names = "pclk", "timer"; 662 clock-names = "pclk", "timer";
663 }; 663 };
664 664
665 timer5: timer@200440a0 { 665 timer5: timer@200440a0 {
666 compatible = "rockchip,rk3128- 666 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
667 reg = <0x200440a0 0x20>; 667 reg = <0x200440a0 0x20>;
668 interrupts = <GIC_SPI 62 IRQ_T 668 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru PCLK_TIMER>, <& 669 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
670 clock-names = "pclk", "timer"; 670 clock-names = "pclk", "timer";
671 }; 671 };
672 672
673 watchdog: watchdog@2004c000 { 673 watchdog: watchdog@2004c000 {
674 compatible = "rockchip,rk3128- 674 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
675 reg = <0x2004c000 0x100>; 675 reg = <0x2004c000 0x100>;
676 interrupts = <GIC_SPI 34 IRQ_T 676 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cru PCLK_WDT>; 677 clocks = <&cru PCLK_WDT>;
678 status = "disabled"; 678 status = "disabled";
679 }; 679 };
680 680
681 pwm0: pwm@20050000 { 681 pwm0: pwm@20050000 {
682 compatible = "rockchip,rk3128- 682 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
683 reg = <0x20050000 0x10>; 683 reg = <0x20050000 0x10>;
684 clocks = <&cru PCLK_PWM>; 684 clocks = <&cru PCLK_PWM>;
685 pinctrl-names = "default"; 685 pinctrl-names = "default";
686 pinctrl-0 = <&pwm0_pin>; 686 pinctrl-0 = <&pwm0_pin>;
687 #pwm-cells = <3>; 687 #pwm-cells = <3>;
688 status = "disabled"; 688 status = "disabled";
689 }; 689 };
690 690
691 pwm1: pwm@20050010 { 691 pwm1: pwm@20050010 {
692 compatible = "rockchip,rk3128- 692 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
693 reg = <0x20050010 0x10>; 693 reg = <0x20050010 0x10>;
694 clocks = <&cru PCLK_PWM>; 694 clocks = <&cru PCLK_PWM>;
695 pinctrl-names = "default"; 695 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>; 696 pinctrl-0 = <&pwm1_pin>;
697 #pwm-cells = <3>; 697 #pwm-cells = <3>;
698 status = "disabled"; 698 status = "disabled";
699 }; 699 };
700 700
701 pwm2: pwm@20050020 { 701 pwm2: pwm@20050020 {
702 compatible = "rockchip,rk3128- 702 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
703 reg = <0x20050020 0x10>; 703 reg = <0x20050020 0x10>;
704 clocks = <&cru PCLK_PWM>; 704 clocks = <&cru PCLK_PWM>;
705 pinctrl-names = "default"; 705 pinctrl-names = "default";
706 pinctrl-0 = <&pwm2_pin>; 706 pinctrl-0 = <&pwm2_pin>;
707 #pwm-cells = <3>; 707 #pwm-cells = <3>;
708 status = "disabled"; 708 status = "disabled";
709 }; 709 };
710 710
711 pwm3: pwm@20050030 { 711 pwm3: pwm@20050030 {
712 compatible = "rockchip,rk3128- 712 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
713 reg = <0x20050030 0x10>; 713 reg = <0x20050030 0x10>;
714 clocks = <&cru PCLK_PWM>; 714 clocks = <&cru PCLK_PWM>;
715 pinctrl-names = "default"; 715 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3_pin>; 716 pinctrl-0 = <&pwm3_pin>;
717 #pwm-cells = <3>; 717 #pwm-cells = <3>;
718 status = "disabled"; 718 status = "disabled";
719 }; 719 };
720 720
721 i2c1: i2c@20056000 { 721 i2c1: i2c@20056000 {
722 compatible = "rockchip,rk3128- 722 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
723 reg = <0x20056000 0x1000>; 723 reg = <0x20056000 0x1000>;
724 interrupts = <GIC_SPI 25 IRQ_T 724 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
725 clock-names = "i2c"; 725 clock-names = "i2c";
726 clocks = <&cru PCLK_I2C1>; 726 clocks = <&cru PCLK_I2C1>;
727 pinctrl-names = "default"; 727 pinctrl-names = "default";
728 pinctrl-0 = <&i2c1_xfer>; 728 pinctrl-0 = <&i2c1_xfer>;
729 #address-cells = <1>; 729 #address-cells = <1>;
730 #size-cells = <0>; 730 #size-cells = <0>;
731 status = "disabled"; 731 status = "disabled";
732 }; 732 };
733 733
734 i2c2: i2c@2005a000 { 734 i2c2: i2c@2005a000 {
735 compatible = "rockchip,rk3128- 735 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
736 reg = <0x2005a000 0x1000>; 736 reg = <0x2005a000 0x1000>;
737 interrupts = <GIC_SPI 26 IRQ_T 737 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
738 clock-names = "i2c"; 738 clock-names = "i2c";
739 clocks = <&cru PCLK_I2C2>; 739 clocks = <&cru PCLK_I2C2>;
740 pinctrl-names = "default"; 740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c2_xfer>; 741 pinctrl-0 = <&i2c2_xfer>;
742 #address-cells = <1>; 742 #address-cells = <1>;
743 #size-cells = <0>; 743 #size-cells = <0>;
744 status = "disabled"; 744 status = "disabled";
745 }; 745 };
746 746
747 i2c3: i2c@2005e000 { 747 i2c3: i2c@2005e000 {
748 compatible = "rockchip,rk3128- 748 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
749 reg = <0x2005e000 0x1000>; 749 reg = <0x2005e000 0x1000>;
750 interrupts = <GIC_SPI 27 IRQ_T 750 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
751 clock-names = "i2c"; 751 clock-names = "i2c";
752 clocks = <&cru PCLK_I2C3>; 752 clocks = <&cru PCLK_I2C3>;
753 pinctrl-names = "default"; 753 pinctrl-names = "default";
754 pinctrl-0 = <&i2c3_xfer>; 754 pinctrl-0 = <&i2c3_xfer>;
755 #address-cells = <1>; 755 #address-cells = <1>;
756 #size-cells = <0>; 756 #size-cells = <0>;
757 status = "disabled"; 757 status = "disabled";
758 }; 758 };
759 759
760 uart0: serial@20060000 { 760 uart0: serial@20060000 {
761 compatible = "rockchip,rk3128- 761 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
762 reg = <0x20060000 0x100>; 762 reg = <0x20060000 0x100>;
763 interrupts = <GIC_SPI 20 IRQ_T 763 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
764 clock-frequency = <24000000>; 764 clock-frequency = <24000000>;
765 clocks = <&cru SCLK_UART0>, <& 765 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
766 clock-names = "baudclk", "apb_ 766 clock-names = "baudclk", "apb_pclk";
767 dmas = <&pdma 2>, <&pdma 3>; 767 dmas = <&pdma 2>, <&pdma 3>;
768 dma-names = "tx", "rx"; 768 dma-names = "tx", "rx";
769 pinctrl-names = "default"; 769 pinctrl-names = "default";
770 pinctrl-0 = <&uart0_xfer &uart 770 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
771 reg-io-width = <4>; 771 reg-io-width = <4>;
772 reg-shift = <2>; 772 reg-shift = <2>;
773 status = "disabled"; 773 status = "disabled";
774 }; 774 };
775 775
776 uart1: serial@20064000 { 776 uart1: serial@20064000 {
777 compatible = "rockchip,rk3128- 777 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
778 reg = <0x20064000 0x100>; 778 reg = <0x20064000 0x100>;
779 interrupts = <GIC_SPI 21 IRQ_T 779 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
780 clock-frequency = <24000000>; 780 clock-frequency = <24000000>;
781 clocks = <&cru SCLK_UART1>, <& 781 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
782 clock-names = "baudclk", "apb_ 782 clock-names = "baudclk", "apb_pclk";
783 dmas = <&pdma 4>, <&pdma 5>; 783 dmas = <&pdma 4>, <&pdma 5>;
784 dma-names = "tx", "rx"; 784 dma-names = "tx", "rx";
785 pinctrl-names = "default"; 785 pinctrl-names = "default";
786 pinctrl-0 = <&uart1_xfer>; 786 pinctrl-0 = <&uart1_xfer>;
787 reg-io-width = <4>; 787 reg-io-width = <4>;
788 reg-shift = <2>; 788 reg-shift = <2>;
789 status = "disabled"; 789 status = "disabled";
790 }; 790 };
791 791
792 uart2: serial@20068000 { 792 uart2: serial@20068000 {
793 compatible = "rockchip,rk3128- 793 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
794 reg = <0x20068000 0x100>; 794 reg = <0x20068000 0x100>;
795 interrupts = <GIC_SPI 22 IRQ_T 795 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
796 clock-frequency = <24000000>; 796 clock-frequency = <24000000>;
797 clocks = <&cru SCLK_UART2>, <& 797 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
798 clock-names = "baudclk", "apb_ 798 clock-names = "baudclk", "apb_pclk";
799 dmas = <&pdma 6>, <&pdma 7>; 799 dmas = <&pdma 6>, <&pdma 7>;
800 dma-names = "tx", "rx"; 800 dma-names = "tx", "rx";
801 pinctrl-names = "default"; 801 pinctrl-names = "default";
802 pinctrl-0 = <&uart2_xfer>; 802 pinctrl-0 = <&uart2_xfer>;
803 reg-io-width = <4>; 803 reg-io-width = <4>;
804 reg-shift = <2>; 804 reg-shift = <2>;
805 status = "disabled"; 805 status = "disabled";
806 }; 806 };
807 807
808 saradc: saradc@2006c000 { 808 saradc: saradc@2006c000 {
809 compatible = "rockchip,saradc" 809 compatible = "rockchip,saradc";
810 reg = <0x2006c000 0x100>; 810 reg = <0x2006c000 0x100>;
811 interrupts = <GIC_SPI 17 IRQ_T 811 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cru SCLK_SARADC>, < 812 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
813 clock-names = "saradc", "apb_p 813 clock-names = "saradc", "apb_pclk";
814 resets = <&cru SRST_SARADC>; 814 resets = <&cru SRST_SARADC>;
815 reset-names = "saradc-apb"; 815 reset-names = "saradc-apb";
816 #io-channel-cells = <1>; 816 #io-channel-cells = <1>;
817 status = "disabled"; 817 status = "disabled";
818 }; 818 };
819 819
820 i2c0: i2c@20072000 { 820 i2c0: i2c@20072000 {
821 compatible = "rockchip,rk3128- 821 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
822 reg = <0x20072000 0x1000>; 822 reg = <0x20072000 0x1000>;
823 interrupts = <GIC_SPI 24 IRQ_T 823 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
824 clock-names = "i2c"; 824 clock-names = "i2c";
825 clocks = <&cru PCLK_I2C0>; 825 clocks = <&cru PCLK_I2C0>;
826 pinctrl-names = "default"; 826 pinctrl-names = "default";
827 pinctrl-0 = <&i2c0_xfer>; 827 pinctrl-0 = <&i2c0_xfer>;
828 #address-cells = <1>; 828 #address-cells = <1>;
829 #size-cells = <0>; 829 #size-cells = <0>;
830 status = "disabled"; 830 status = "disabled";
831 }; 831 };
832 832
833 spi0: spi@20074000 { 833 spi0: spi@20074000 {
834 compatible = "rockchip,rk3128- 834 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
835 reg = <0x20074000 0x1000>; 835 reg = <0x20074000 0x1000>;
836 interrupts = <GIC_SPI 23 IRQ_T 836 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&cru SCLK_SPI0>, <&c 837 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
838 clock-names = "spiclk", "apb_p 838 clock-names = "spiclk", "apb_pclk";
839 dmas = <&pdma 8>, <&pdma 9>; 839 dmas = <&pdma 8>, <&pdma 9>;
840 dma-names = "tx", "rx"; 840 dma-names = "tx", "rx";
841 pinctrl-names = "default"; 841 pinctrl-names = "default";
842 pinctrl-0 = <&spi0_tx &spi0_rx 842 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
843 #address-cells = <1>; 843 #address-cells = <1>;
844 #size-cells = <0>; 844 #size-cells = <0>;
845 status = "disabled"; 845 status = "disabled";
846 }; 846 };
847 847
848 pdma: dma-controller@20078000 { 848 pdma: dma-controller@20078000 {
849 compatible = "arm,pl330", "arm 849 compatible = "arm,pl330", "arm,primecell";
850 reg = <0x20078000 0x4000>; 850 reg = <0x20078000 0x4000>;
851 interrupts = <GIC_SPI 0 IRQ_TY 851 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 1 IRQ_TY 852 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
853 arm,pl330-broken-no-flushp; 853 arm,pl330-broken-no-flushp;
854 arm,pl330-periph-burst; 854 arm,pl330-periph-burst;
855 clocks = <&cru ACLK_DMAC>; 855 clocks = <&cru ACLK_DMAC>;
856 clock-names = "apb_pclk"; 856 clock-names = "apb_pclk";
857 #dma-cells = <1>; 857 #dma-cells = <1>;
858 }; 858 };
859 859
860 gmac: ethernet@2008c000 { 860 gmac: ethernet@2008c000 {
861 compatible = "rockchip,rk3128- 861 compatible = "rockchip,rk3128-gmac";
862 reg = <0x2008c000 0x4000>; 862 reg = <0x2008c000 0x4000>;
863 interrupts = <GIC_SPI 56 IRQ_T 863 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 57 IRQ_T 864 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
865 interrupt-names = "macirq", "e 865 interrupt-names = "macirq", "eth_wake_irq";
866 clocks = <&cru SCLK_MAC>, 866 clocks = <&cru SCLK_MAC>,
867 <&cru SCLK_MAC_RX>, < 867 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
868 <&cru SCLK_MAC_REF>, 868 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
869 <&cru ACLK_GMAC>, <&c 869 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
870 clock-names = "stmmaceth", 870 clock-names = "stmmaceth",
871 "mac_clk_rx", "m 871 "mac_clk_rx", "mac_clk_tx",
872 "clk_mac_ref", " 872 "clk_mac_ref", "clk_mac_refout",
873 "aclk_mac", "pcl 873 "aclk_mac", "pclk_mac";
874 resets = <&cru SRST_GMAC>; 874 resets = <&cru SRST_GMAC>;
875 reset-names = "stmmaceth"; 875 reset-names = "stmmaceth";
876 rockchip,grf = <&grf>; 876 rockchip,grf = <&grf>;
877 rx-fifo-depth = <4096>; 877 rx-fifo-depth = <4096>;
878 tx-fifo-depth = <2048>; 878 tx-fifo-depth = <2048>;
879 status = "disabled"; 879 status = "disabled";
880 880
881 mdio: mdio { 881 mdio: mdio {
882 compatible = "snps,dwm 882 compatible = "snps,dwmac-mdio";
883 #address-cells = <0x1> 883 #address-cells = <0x1>;
884 #size-cells = <0x0>; 884 #size-cells = <0x0>;
885 }; 885 };
886 }; 886 };
887 887
888 pinctrl: pinctrl { 888 pinctrl: pinctrl {
889 compatible = "rockchip,rk3128- 889 compatible = "rockchip,rk3128-pinctrl";
890 rockchip,grf = <&grf>; 890 rockchip,grf = <&grf>;
891 #address-cells = <1>; 891 #address-cells = <1>;
892 #size-cells = <1>; 892 #size-cells = <1>;
893 ranges; 893 ranges;
894 894
895 gpio0: gpio@2007c000 { 895 gpio0: gpio@2007c000 {
896 compatible = "rockchip 896 compatible = "rockchip,gpio-bank";
897 reg = <0x2007c000 0x10 897 reg = <0x2007c000 0x100>;
898 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cru PCLK_GP 899 clocks = <&cru PCLK_GPIO0>;
900 gpio-controller; 900 gpio-controller;
901 #gpio-cells = <2>; 901 #gpio-cells = <2>;
902 interrupt-controller; 902 interrupt-controller;
903 #interrupt-cells = <2> 903 #interrupt-cells = <2>;
904 }; 904 };
905 905
906 gpio1: gpio@20080000 { 906 gpio1: gpio@20080000 {
907 compatible = "rockchip 907 compatible = "rockchip,gpio-bank";
908 reg = <0x20080000 0x10 908 reg = <0x20080000 0x100>;
909 interrupts = <GIC_SPI 909 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&cru PCLK_GP 910 clocks = <&cru PCLK_GPIO1>;
911 gpio-controller; 911 gpio-controller;
912 #gpio-cells = <2>; 912 #gpio-cells = <2>;
913 interrupt-controller; 913 interrupt-controller;
914 #interrupt-cells = <2> 914 #interrupt-cells = <2>;
915 }; 915 };
916 916
917 gpio2: gpio@20084000 { 917 gpio2: gpio@20084000 {
918 compatible = "rockchip 918 compatible = "rockchip,gpio-bank";
919 reg = <0x20084000 0x10 919 reg = <0x20084000 0x100>;
920 interrupts = <GIC_SPI 920 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cru PCLK_GP 921 clocks = <&cru PCLK_GPIO2>;
922 gpio-controller; 922 gpio-controller;
923 #gpio-cells = <2>; 923 #gpio-cells = <2>;
924 interrupt-controller; 924 interrupt-controller;
925 #interrupt-cells = <2> 925 #interrupt-cells = <2>;
926 }; 926 };
927 927
928 gpio3: gpio@20088000 { 928 gpio3: gpio@20088000 {
929 compatible = "rockchip 929 compatible = "rockchip,gpio-bank";
930 reg = <0x20088000 0x10 930 reg = <0x20088000 0x100>;
931 interrupts = <GIC_SPI 931 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&cru PCLK_GP 932 clocks = <&cru PCLK_GPIO3>;
933 gpio-controller; 933 gpio-controller;
934 #gpio-cells = <2>; 934 #gpio-cells = <2>;
935 interrupt-controller; 935 interrupt-controller;
936 #interrupt-cells = <2> 936 #interrupt-cells = <2>;
937 }; 937 };
938 938
939 pcfg_pull_default: pcfg-pull-d 939 pcfg_pull_default: pcfg-pull-default {
940 bias-pull-pin-default; 940 bias-pull-pin-default;
941 }; 941 };
942 942
943 pcfg_pull_none: pcfg-pull-none 943 pcfg_pull_none: pcfg-pull-none {
944 bias-disable; 944 bias-disable;
945 }; 945 };
946 946
947 emmc { 947 emmc {
948 emmc_clk: emmc-clk { 948 emmc_clk: emmc-clk {
949 rockchip,pins 949 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
950 }; 950 };
951 951
952 emmc_cmd: emmc-cmd { 952 emmc_cmd: emmc-cmd {
953 rockchip,pins 953 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
954 }; 954 };
955 955
956 emmc_cmd1: emmc-cmd1 { 956 emmc_cmd1: emmc-cmd1 {
957 rockchip,pins 957 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
958 }; 958 };
959 959
960 emmc_pwr: emmc-pwr { 960 emmc_pwr: emmc-pwr {
961 rockchip,pins 961 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
962 }; 962 };
963 963
964 emmc_bus1: emmc-bus1 { 964 emmc_bus1: emmc-bus1 {
965 rockchip,pins 965 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
966 }; 966 };
967 967
968 emmc_bus4: emmc-bus4 { 968 emmc_bus4: emmc-bus4 {
969 rockchip,pins 969 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
970 970 <1 RK_PD1 2 &pcfg_pull_default>,
971 971 <1 RK_PD2 2 &pcfg_pull_default>,
972 972 <1 RK_PD3 2 &pcfg_pull_default>;
973 }; 973 };
974 974
975 emmc_bus8: emmc-bus8 { 975 emmc_bus8: emmc-bus8 {
976 rockchip,pins 976 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
977 977 <1 RK_PD1 2 &pcfg_pull_default>,
978 978 <1 RK_PD2 2 &pcfg_pull_default>,
979 979 <1 RK_PD3 2 &pcfg_pull_default>,
980 980 <1 RK_PD4 2 &pcfg_pull_default>,
981 981 <1 RK_PD5 2 &pcfg_pull_default>,
982 982 <1 RK_PD6 2 &pcfg_pull_default>,
983 983 <1 RK_PD7 2 &pcfg_pull_default>;
984 }; 984 };
985 }; 985 };
986 986
987 gmac { 987 gmac {
988 rgmii_pins: rgmii-pins 988 rgmii_pins: rgmii-pins {
989 rockchip,pins 989 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
990 990 <2 RK_PB1 3 &pcfg_pull_default>,
991 991 <2 RK_PB3 3 &pcfg_pull_default>,
992 992 <2 RK_PB4 3 &pcfg_pull_default>,
993 993 <2 RK_PB5 3 &pcfg_pull_default>,
994 994 <2 RK_PB6 3 &pcfg_pull_default>,
995 995 <2 RK_PC0 3 &pcfg_pull_default>,
996 996 <2 RK_PC1 3 &pcfg_pull_default>,
997 997 <2 RK_PC2 3 &pcfg_pull_default>,
998 998 <2 RK_PC3 3 &pcfg_pull_default>,
999 999 <2 RK_PD1 3 &pcfg_pull_default>,
1000 1000 <2 RK_PC4 4 &pcfg_pull_default>,
1001 1001 <2 RK_PC5 4 &pcfg_pull_default>,
1002 1002 <2 RK_PC6 4 &pcfg_pull_default>,
1003 1003 <2 RK_PC7 4 &pcfg_pull_default>;
1004 }; 1004 };
1005 1005
1006 rmii_pins: rmii-pins 1006 rmii_pins: rmii-pins {
1007 rockchip,pins 1007 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
1008 1008 <2 RK_PB4 3 &pcfg_pull_default>,
1009 1009 <2 RK_PB5 3 &pcfg_pull_default>,
1010 1010 <2 RK_PB6 3 &pcfg_pull_default>,
1011 1011 <2 RK_PB7 3 &pcfg_pull_default>,
1012 1012 <2 RK_PC0 3 &pcfg_pull_default>,
1013 1013 <2 RK_PC1 3 &pcfg_pull_default>,
1014 1014 <2 RK_PC2 3 &pcfg_pull_default>,
1015 1015 <2 RK_PC3 3 &pcfg_pull_default>,
1016 1016 <2 RK_PD1 3 &pcfg_pull_default>;
1017 }; 1017 };
1018 }; 1018 };
1019 1019
1020 hdmi { 1020 hdmi {
1021 hdmii2c_xfer: hdmii2c 1021 hdmii2c_xfer: hdmii2c-xfer {
1022 rockchip,pins 1022 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1023 1023 <0 RK_PA7 2 &pcfg_pull_none>;
1024 }; 1024 };
1025 1025
1026 hdmi_hpd: hdmi-hpd { 1026 hdmi_hpd: hdmi-hpd {
1027 rockchip,pins 1027 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1028 }; 1028 };
1029 1029
1030 hdmi_cec: hdmi-cec { 1030 hdmi_cec: hdmi-cec {
1031 rockchip,pins 1031 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1032 }; 1032 };
1033 }; 1033 };
1034 1034
1035 i2c0 { 1035 i2c0 {
1036 i2c0_xfer: i2c0-xfer 1036 i2c0_xfer: i2c0-xfer {
1037 rockchip,pins 1037 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1038 1038 <0 RK_PA1 1 &pcfg_pull_none>;
1039 }; 1039 };
1040 }; 1040 };
1041 1041
1042 i2c1 { 1042 i2c1 {
1043 i2c1_xfer: i2c1-xfer 1043 i2c1_xfer: i2c1-xfer {
1044 rockchip,pins 1044 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1045 1045 <0 RK_PA3 1 &pcfg_pull_none>;
1046 }; 1046 };
1047 }; 1047 };
1048 1048
1049 i2c2 { 1049 i2c2 {
1050 i2c2_xfer: i2c2-xfer 1050 i2c2_xfer: i2c2-xfer {
1051 rockchip,pins 1051 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
1052 1052 <2 RK_PC5 3 &pcfg_pull_none>;
1053 }; 1053 };
1054 }; 1054 };
1055 1055
1056 i2c3 { 1056 i2c3 {
1057 i2c3_xfer: i2c3-xfer 1057 i2c3_xfer: i2c3-xfer {
1058 rockchip,pins 1058 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1059 1059 <0 RK_PA7 1 &pcfg_pull_none>;
1060 }; 1060 };
1061 }; 1061 };
1062 1062
1063 i2s { 1063 i2s {
1064 i2s_bus: i2s-bus { 1064 i2s_bus: i2s-bus {
1065 rockchip,pins 1065 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1066 1066 <0 RK_PB1 1 &pcfg_pull_none>,
1067 1067 <0 RK_PB3 1 &pcfg_pull_none>,
1068 1068 <0 RK_PB4 1 &pcfg_pull_none>,
1069 1069 <0 RK_PB5 1 &pcfg_pull_none>,
1070 1070 <0 RK_PB6 1 &pcfg_pull_none>;
1071 }; 1071 };
1072 1072
1073 i2s1_bus: i2s1-bus { 1073 i2s1_bus: i2s1-bus {
1074 rockchip,pins 1074 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
1075 1075 <1 RK_PA1 1 &pcfg_pull_none>,
1076 1076 <1 RK_PA2 1 &pcfg_pull_none>,
1077 1077 <1 RK_PA3 1 &pcfg_pull_none>,
1078 1078 <1 RK_PA4 1 &pcfg_pull_none>,
1079 1079 <1 RK_PA5 1 &pcfg_pull_none>;
1080 }; 1080 };
1081 }; 1081 };
1082 1082
1083 lcdc { 1083 lcdc {
1084 lcdc_dclk: lcdc-dclk 1084 lcdc_dclk: lcdc-dclk {
1085 rockchip,pins 1085 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
1086 }; 1086 };
1087 1087
1088 lcdc_den: lcdc-den { 1088 lcdc_den: lcdc-den {
1089 rockchip,pins 1089 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
1090 }; 1090 };
1091 1091
1092 lcdc_hsync: lcdc-hsyn 1092 lcdc_hsync: lcdc-hsync {
1093 rockchip,pins 1093 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1094 }; 1094 };
1095 1095
1096 lcdc_vsync: lcdc-vsyn 1096 lcdc_vsync: lcdc-vsync {
1097 rockchip,pins 1097 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
1098 }; 1098 };
1099 1099
1100 lcdc_rgb24: lcdc-rgb2 1100 lcdc_rgb24: lcdc-rgb24 {
1101 rockchip,pins 1101 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1102 1102 <2 RK_PB5 1 &pcfg_pull_none>,
1103 1103 <2 RK_PB6 1 &pcfg_pull_none>,
1104 1104 <2 RK_PB7 1 &pcfg_pull_none>,
1105 1105 <2 RK_PC0 1 &pcfg_pull_none>,
1106 1106 <2 RK_PC1 1 &pcfg_pull_none>,
1107 1107 <2 RK_PC2 1 &pcfg_pull_none>,
1108 1108 <2 RK_PC3 1 &pcfg_pull_none>,
1109 1109 <2 RK_PC4 1 &pcfg_pull_none>,
1110 1110 <2 RK_PC5 1 &pcfg_pull_none>,
1111 1111 <2 RK_PC6 1 &pcfg_pull_none>,
1112 1112 <2 RK_PC7 1 &pcfg_pull_none>,
1113 1113 <2 RK_PD0 1 &pcfg_pull_none>,
1114 1114 <2 RK_PD1 1 &pcfg_pull_none>;
1115 }; 1115 };
1116 }; 1116 };
1117 1117
1118 nfc { 1118 nfc {
1119 flash_ale: flash-ale 1119 flash_ale: flash-ale {
1120 rockchip,pins 1120 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
1121 }; 1121 };
1122 1122
1123 flash_cle: flash-cle 1123 flash_cle: flash-cle {
1124 rockchip,pins 1124 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
1125 }; 1125 };
1126 1126
1127 flash_wrn: flash-wrn 1127 flash_wrn: flash-wrn {
1128 rockchip,pins 1128 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1129 }; 1129 };
1130 1130
1131 flash_rdn: flash-rdn 1131 flash_rdn: flash-rdn {
1132 rockchip,pins 1132 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
1133 }; 1133 };
1134 1134
1135 flash_rdy: flash-rdy 1135 flash_rdy: flash-rdy {
1136 rockchip,pins 1136 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1137 }; 1137 };
1138 1138
1139 flash_cs0: flash-cs0 1139 flash_cs0: flash-cs0 {
1140 rockchip,pins 1140 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1141 }; 1141 };
1142 1142
1143 flash_dqs: flash-dqs 1143 flash_dqs: flash-dqs {
1144 rockchip,pins 1144 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
1145 }; 1145 };
1146 1146
1147 flash_bus8: flash-bus 1147 flash_bus8: flash-bus8 {
1148 rockchip,pins 1148 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1149 1149 <1 RK_PD1 1 &pcfg_pull_none>,
1150 1150 <1 RK_PD2 1 &pcfg_pull_none>,
1151 1151 <1 RK_PD3 1 &pcfg_pull_none>,
1152 1152 <1 RK_PD4 1 &pcfg_pull_none>,
1153 1153 <1 RK_PD5 1 &pcfg_pull_none>,
1154 1154 <1 RK_PD6 1 &pcfg_pull_none>,
1155 1155 <1 RK_PD7 1 &pcfg_pull_none>;
1156 }; 1156 };
1157 }; 1157 };
1158 1158
1159 pwm0 { 1159 pwm0 {
1160 pwm0_pin: pwm0-pin { 1160 pwm0_pin: pwm0-pin {
1161 rockchip,pins 1161 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1162 }; 1162 };
1163 }; 1163 };
1164 1164
1165 pwm1 { 1165 pwm1 {
1166 pwm1_pin: pwm1-pin { 1166 pwm1_pin: pwm1-pin {
1167 rockchip,pins 1167 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1168 }; 1168 };
1169 }; 1169 };
1170 1170
1171 pwm2 { 1171 pwm2 {
1172 pwm2_pin: pwm2-pin { 1172 pwm2_pin: pwm2-pin {
1173 rockchip,pins 1173 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1174 }; 1174 };
1175 }; 1175 };
1176 1176
1177 pwm3 { 1177 pwm3 {
1178 pwm3_pin: pwm3-pin { 1178 pwm3_pin: pwm3-pin {
1179 rockchip,pins 1179 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
1180 }; 1180 };
1181 }; 1181 };
1182 1182
1183 sdio { 1183 sdio {
1184 sdio_clk: sdio-clk { 1184 sdio_clk: sdio-clk {
1185 rockchip,pins 1185 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1186 }; 1186 };
1187 1187
1188 sdio_cmd: sdio-cmd { 1188 sdio_cmd: sdio-cmd {
1189 rockchip,pins 1189 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1190 }; 1190 };
1191 1191
1192 sdio_pwren: sdio-pwre 1192 sdio_pwren: sdio-pwren {
1193 rockchip,pins 1193 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1194 }; 1194 };
1195 1195
1196 sdio_bus4: sdio-bus4 1196 sdio_bus4: sdio-bus4 {
1197 rockchip,pins 1197 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1198 1198 <1 RK_PA2 2 &pcfg_pull_default>,
1199 1199 <1 RK_PA4 2 &pcfg_pull_default>,
1200 1200 <1 RK_PA5 2 &pcfg_pull_default>;
1201 }; 1201 };
1202 }; 1202 };
1203 1203
1204 sdmmc { 1204 sdmmc {
1205 sdmmc_clk: sdmmc-clk 1205 sdmmc_clk: sdmmc-clk {
1206 rockchip,pins 1206 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1207 }; 1207 };
1208 1208
1209 sdmmc_cmd: sdmmc-cmd 1209 sdmmc_cmd: sdmmc-cmd {
1210 rockchip,pins 1210 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1211 }; 1211 };
1212 1212
1213 sdmmc_det: sdmmc-det 1213 sdmmc_det: sdmmc-det {
1214 rockchip,pins 1214 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
1215 }; 1215 };
1216 1216
1217 sdmmc_wp: sdmmc-wp { 1217 sdmmc_wp: sdmmc-wp {
1218 rockchip,pins 1218 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1219 }; 1219 };
1220 1220
1221 sdmmc_pwren: sdmmc-pw 1221 sdmmc_pwren: sdmmc-pwren {
1222 rockchip,pins 1222 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
1223 }; 1223 };
1224 1224
1225 sdmmc_bus4: sdmmc-bus 1225 sdmmc_bus4: sdmmc-bus4 {
1226 rockchip,pins 1226 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1227 1227 <1 RK_PC3 1 &pcfg_pull_default>,
1228 1228 <1 RK_PC4 1 &pcfg_pull_default>,
1229 1229 <1 RK_PC5 1 &pcfg_pull_default>;
1230 }; 1230 };
1231 }; 1231 };
1232 1232
1233 sfc { 1233 sfc {
1234 sfc_bus2: sfc-bus2 { 1234 sfc_bus2: sfc-bus2 {
1235 rockchip,pins 1235 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
1236 1236 <1 RK_PD1 3 &pcfg_pull_default>;
1237 }; 1237 };
1238 1238
1239 sfc_bus4: sfc-bus4 { 1239 sfc_bus4: sfc-bus4 {
1240 rockchip,pins 1240 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
1241 1241 <1 RK_PD1 3 &pcfg_pull_default>,
1242 1242 <1 RK_PD2 3 &pcfg_pull_default>,
1243 1243 <1 RK_PD3 3 &pcfg_pull_default>;
1244 }; 1244 };
1245 1245
1246 sfc_clk: sfc-clk { 1246 sfc_clk: sfc-clk {
1247 rockchip,pins 1247 rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
1248 }; 1248 };
1249 1249
1250 sfc_cs0: sfc-cs0 { 1250 sfc_cs0: sfc-cs0 {
1251 rockchip,pins 1251 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>;
1252 }; 1252 };
1253 1253
1254 sfc_cs1: sfc-cs1 { 1254 sfc_cs1: sfc-cs1 {
1255 rockchip,pins 1255 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>;
1256 }; 1256 };
1257 }; 1257 };
1258 1258
1259 spdif { 1259 spdif {
1260 spdif_tx: spdif-tx { 1260 spdif_tx: spdif-tx {
1261 rockchip,pins 1261 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1262 }; 1262 };
1263 }; 1263 };
1264 1264
1265 spi0 { 1265 spi0 {
1266 spi0_clk: spi0-clk { 1266 spi0_clk: spi0-clk {
1267 rockchip,pins 1267 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1268 }; 1268 };
1269 1269
1270 spi0_cs0: spi0-cs0 { 1270 spi0_cs0: spi0-cs0 {
1271 rockchip,pins 1271 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1272 }; 1272 };
1273 1273
1274 spi0_tx: spi0-tx { 1274 spi0_tx: spi0-tx {
1275 rockchip,pins 1275 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1276 }; 1276 };
1277 1277
1278 spi0_rx: spi0-rx { 1278 spi0_rx: spi0-rx {
1279 rockchip,pins 1279 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1280 }; 1280 };
1281 1281
1282 spi0_cs1: spi0-cs1 { 1282 spi0_cs1: spi0-cs1 {
1283 rockchip,pins 1283 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1284 }; 1284 };
1285 1285
1286 spi1_clk: spi1-clk { 1286 spi1_clk: spi1-clk {
1287 rockchip,pins 1287 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1288 }; 1288 };
1289 1289
1290 spi1_cs0: spi1-cs0 { 1290 spi1_cs0: spi1-cs0 {
1291 rockchip,pins 1291 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1292 }; 1292 };
1293 1293
1294 spi1_tx: spi1-tx { 1294 spi1_tx: spi1-tx {
1295 rockchip,pins 1295 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1296 }; 1296 };
1297 1297
1298 spi1_rx: spi1-rx { 1298 spi1_rx: spi1-rx {
1299 rockchip,pins 1299 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1300 }; 1300 };
1301 1301
1302 spi1_cs1: spi1-cs1 { 1302 spi1_cs1: spi1-cs1 {
1303 rockchip,pins 1303 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1304 }; 1304 };
1305 1305
1306 spi2_clk: spi2-clk { 1306 spi2_clk: spi2-clk {
1307 rockchip,pins 1307 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1308 }; 1308 };
1309 1309
1310 spi2_cs0: spi2-cs0 { 1310 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 1311 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1312 }; 1312 };
1313 1313
1314 spi2_tx: spi2-tx { 1314 spi2_tx: spi2-tx {
1315 rockchip,pins 1315 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1316 }; 1316 };
1317 1317
1318 spi2_rx: spi2-rx { 1318 spi2_rx: spi2-rx {
1319 rockchip,pins 1319 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1320 }; 1320 };
1321 }; 1321 };
1322 1322
1323 uart0 { 1323 uart0 {
1324 uart0_xfer: uart0-xfe 1324 uart0_xfer: uart0-xfer {
1325 rockchip,pins 1325 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1326 1326 <2 RK_PD3 2 &pcfg_pull_none>;
1327 }; 1327 };
1328 1328
1329 uart0_cts: uart0-cts 1329 uart0_cts: uart0-cts {
1330 rockchip,pins 1330 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1331 }; 1331 };
1332 1332
1333 uart0_rts: uart0-rts 1333 uart0_rts: uart0-rts {
1334 rockchip,pins 1334 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1335 }; 1335 };
1336 }; 1336 };
1337 1337
1338 uart1 { 1338 uart1 {
1339 uart1_xfer: uart1-xfe 1339 uart1_xfer: uart1-xfer {
1340 rockchip,pins 1340 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1341 1341 <1 RK_PB2 2 &pcfg_pull_default>;
1342 }; 1342 };
1343 1343
1344 uart1_cts: uart1-cts 1344 uart1_cts: uart1-cts {
1345 rockchip,pins 1345 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1346 }; 1346 };
1347 1347
1348 uart1_rts: uart1-rts 1348 uart1_rts: uart1-rts {
1349 rockchip,pins 1349 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1350 }; 1350 };
1351 }; 1351 };
1352 1352
1353 uart2 { 1353 uart2 {
1354 uart2_xfer: uart2-xfe 1354 uart2_xfer: uart2-xfer {
1355 rockchip,pins 1355 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1356 1356 <1 RK_PC3 2 &pcfg_pull_none>;
1357 }; 1357 };
1358 1358
1359 uart2_cts: uart2-cts 1359 uart2_cts: uart2-cts {
1360 rockchip,pins 1360 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1361 }; 1361 };
1362 1362
1363 uart2_rts: uart2-rts 1363 uart2_rts: uart2-rts {
1364 rockchip,pins 1364 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1365 }; 1365 };
1366 }; 1366 };
1367 }; 1367 };
1368 }; 1368 };
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