1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 2
3 #include <dt-bindings/gpio/gpio.h> 3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq 4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h> 6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h> 7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h> 8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h> 9 #include <dt-bindings/power/rk3228-power.h>
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 14
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 16
17 aliases { 17 aliases {
18 gpio0 = &gpio0; <<
19 gpio1 = &gpio1; <<
20 gpio2 = &gpio2; <<
21 gpio3 = &gpio3; <<
22 serial0 = &uart0; 18 serial0 = &uart0;
23 serial1 = &uart1; 19 serial1 = &uart1;
24 serial2 = &uart2; 20 serial2 = &uart2;
25 spi0 = &spi0; 21 spi0 = &spi0;
26 }; 22 };
27 23
28 cpus { 24 cpus {
29 #address-cells = <1>; 25 #address-cells = <1>;
30 #size-cells = <0>; 26 #size-cells = <0>;
31 27
32 cpu0: cpu@f00 { 28 cpu0: cpu@f00 {
33 device_type = "cpu"; 29 device_type = "cpu";
34 compatible = "arm,cort 30 compatible = "arm,cortex-a7";
35 reg = <0xf00>; 31 reg = <0xf00>;
36 resets = <&cru SRST_CO 32 resets = <&cru SRST_CORE0>;
37 operating-points-v2 = 33 operating-points-v2 = <&cpu0_opp_table>;
38 #cooling-cells = <2>; 34 #cooling-cells = <2>; /* min followed by max */
39 clock-latency = <40000 35 clock-latency = <40000>;
40 clocks = <&cru ARMCLK> 36 clocks = <&cru ARMCLK>;
41 enable-method = "psci" 37 enable-method = "psci";
42 }; 38 };
43 39
44 cpu1: cpu@f01 { 40 cpu1: cpu@f01 {
45 device_type = "cpu"; 41 device_type = "cpu";
46 compatible = "arm,cort 42 compatible = "arm,cortex-a7";
47 reg = <0xf01>; 43 reg = <0xf01>;
48 resets = <&cru SRST_CO 44 resets = <&cru SRST_CORE1>;
49 operating-points-v2 = 45 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; 46 #cooling-cells = <2>; /* min followed by max */
51 enable-method = "psci" 47 enable-method = "psci";
52 }; 48 };
53 49
54 cpu2: cpu@f02 { 50 cpu2: cpu@f02 {
55 device_type = "cpu"; 51 device_type = "cpu";
56 compatible = "arm,cort 52 compatible = "arm,cortex-a7";
57 reg = <0xf02>; 53 reg = <0xf02>;
58 resets = <&cru SRST_CO 54 resets = <&cru SRST_CORE2>;
59 operating-points-v2 = 55 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; 56 #cooling-cells = <2>; /* min followed by max */
61 enable-method = "psci" 57 enable-method = "psci";
62 }; 58 };
63 59
64 cpu3: cpu@f03 { 60 cpu3: cpu@f03 {
65 device_type = "cpu"; 61 device_type = "cpu";
66 compatible = "arm,cort 62 compatible = "arm,cortex-a7";
67 reg = <0xf03>; 63 reg = <0xf03>;
68 resets = <&cru SRST_CO 64 resets = <&cru SRST_CORE3>;
69 operating-points-v2 = 65 operating-points-v2 = <&cpu0_opp_table>;
70 #cooling-cells = <2>; 66 #cooling-cells = <2>; /* min followed by max */
71 enable-method = "psci" 67 enable-method = "psci";
72 }; 68 };
73 }; 69 };
74 70
75 cpu0_opp_table: opp-table-0 { 71 cpu0_opp_table: opp-table-0 {
76 compatible = "operating-points 72 compatible = "operating-points-v2";
77 opp-shared; 73 opp-shared;
78 74
79 opp-408000000 { 75 opp-408000000 {
80 opp-hz = /bits/ 64 <40 76 opp-hz = /bits/ 64 <408000000>;
81 opp-microvolt = <95000 77 opp-microvolt = <950000>;
82 clock-latency-ns = <40 78 clock-latency-ns = <40000>;
83 opp-suspend; 79 opp-suspend;
84 }; 80 };
85 opp-600000000 { 81 opp-600000000 {
86 opp-hz = /bits/ 64 <60 82 opp-hz = /bits/ 64 <600000000>;
87 opp-microvolt = <97500 83 opp-microvolt = <975000>;
88 }; 84 };
89 opp-816000000 { 85 opp-816000000 {
90 opp-hz = /bits/ 64 <81 86 opp-hz = /bits/ 64 <816000000>;
91 opp-microvolt = <10000 87 opp-microvolt = <1000000>;
92 }; 88 };
93 opp-1008000000 { 89 opp-1008000000 {
94 opp-hz = /bits/ 64 <10 90 opp-hz = /bits/ 64 <1008000000>;
95 opp-microvolt = <11750 91 opp-microvolt = <1175000>;
96 }; 92 };
97 opp-1200000000 { 93 opp-1200000000 {
98 opp-hz = /bits/ 64 <12 94 opp-hz = /bits/ 64 <1200000000>;
99 opp-microvolt = <12750 95 opp-microvolt = <1275000>;
100 }; 96 };
101 }; 97 };
102 98
103 arm-pmu { 99 arm-pmu {
104 compatible = "arm,cortex-a7-pm 100 compatible = "arm,cortex-a7-pmu";
105 interrupts = <GIC_SPI 76 IRQ_T 101 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 77 IRQ_T 102 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 78 IRQ_T 103 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 79 IRQ_T 104 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-affinity = <&cpu0>, 105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
110 }; 106 };
111 107
112 psci { 108 psci {
113 compatible = "arm,psci-1.0", " 109 compatible = "arm,psci-1.0", "arm,psci-0.2";
114 method = "smc"; 110 method = "smc";
115 }; 111 };
116 112
117 timer { 113 timer {
118 compatible = "arm,armv7-timer" 114 compatible = "arm,armv7-timer";
119 arm,cpu-registers-not-fw-confi 115 arm,cpu-registers-not-fw-configured;
120 interrupts = <GIC_PPI 13 (GIC_ 116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 14 (GIC_ 117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 11 (GIC_ 118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
123 <GIC_PPI 10 (GIC_ 119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
124 clock-frequency = <24000000>; 120 clock-frequency = <24000000>;
125 }; 121 };
126 122
127 xin24m: oscillator { 123 xin24m: oscillator {
128 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
129 clock-frequency = <24000000>; 125 clock-frequency = <24000000>;
130 clock-output-names = "xin24m"; 126 clock-output-names = "xin24m";
131 #clock-cells = <0>; 127 #clock-cells = <0>;
132 }; 128 };
133 129
134 display_subsystem: display-subsystem { 130 display_subsystem: display-subsystem {
135 compatible = "rockchip,display 131 compatible = "rockchip,display-subsystem";
136 ports = <&vop_out>; 132 ports = <&vop_out>;
137 }; 133 };
138 134
139 i2s1: i2s1@100b0000 { 135 i2s1: i2s1@100b0000 {
140 compatible = "rockchip,rk3228- 136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
141 reg = <0x100b0000 0x4000>; 137 reg = <0x100b0000 0x4000>;
142 interrupts = <GIC_SPI 27 IRQ_T 138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
143 clock-names = "i2s_clk", "i2s_ 139 clock-names = "i2s_clk", "i2s_hclk";
144 clocks = <&cru SCLK_I2S1>, <&c 140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
145 dmas = <&pdma 14>, <&pdma 15>; 141 dmas = <&pdma 14>, <&pdma 15>;
146 dma-names = "tx", "rx"; 142 dma-names = "tx", "rx";
147 pinctrl-names = "default"; 143 pinctrl-names = "default";
148 pinctrl-0 = <&i2s1_bus>; 144 pinctrl-0 = <&i2s1_bus>;
149 status = "disabled"; 145 status = "disabled";
150 }; 146 };
151 147
152 i2s0: i2s0@100c0000 { 148 i2s0: i2s0@100c0000 {
153 compatible = "rockchip,rk3228- 149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
154 reg = <0x100c0000 0x4000>; 150 reg = <0x100c0000 0x4000>;
155 interrupts = <GIC_SPI 26 IRQ_T 151 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
156 clock-names = "i2s_clk", "i2s_ 152 clock-names = "i2s_clk", "i2s_hclk";
157 clocks = <&cru SCLK_I2S0>, <&c 153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
158 dmas = <&pdma 11>, <&pdma 12>; 154 dmas = <&pdma 11>, <&pdma 12>;
159 dma-names = "tx", "rx"; 155 dma-names = "tx", "rx";
160 status = "disabled"; 156 status = "disabled";
161 }; 157 };
162 158
163 spdif: spdif@100d0000 { 159 spdif: spdif@100d0000 {
164 compatible = "rockchip,rk3228- 160 compatible = "rockchip,rk3228-spdif";
165 reg = <0x100d0000 0x1000>; 161 reg = <0x100d0000 0x1000>;
166 interrupts = <GIC_SPI 29 IRQ_T 162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&cru SCLK_SPDIF>, <& 163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
168 clock-names = "mclk", "hclk"; 164 clock-names = "mclk", "hclk";
169 dmas = <&pdma 10>; 165 dmas = <&pdma 10>;
170 dma-names = "tx"; 166 dma-names = "tx";
171 pinctrl-names = "default"; 167 pinctrl-names = "default";
172 pinctrl-0 = <&spdif_tx>; 168 pinctrl-0 = <&spdif_tx>;
173 status = "disabled"; 169 status = "disabled";
174 }; 170 };
175 171
176 i2s2: i2s2@100e0000 { 172 i2s2: i2s2@100e0000 {
177 compatible = "rockchip,rk3228- 173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
178 reg = <0x100e0000 0x4000>; 174 reg = <0x100e0000 0x4000>;
179 interrupts = <GIC_SPI 28 IRQ_T 175 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
180 clock-names = "i2s_clk", "i2s_ 176 clock-names = "i2s_clk", "i2s_hclk";
181 clocks = <&cru SCLK_I2S2>, <&c 177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
182 dmas = <&pdma 0>, <&pdma 1>; 178 dmas = <&pdma 0>, <&pdma 1>;
183 dma-names = "tx", "rx"; 179 dma-names = "tx", "rx";
184 status = "disabled"; 180 status = "disabled";
185 }; 181 };
186 182
187 grf: syscon@11000000 { 183 grf: syscon@11000000 {
188 compatible = "rockchip,rk3228- 184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
189 reg = <0x11000000 0x1000>; 185 reg = <0x11000000 0x1000>;
190 #address-cells = <1>; 186 #address-cells = <1>;
191 #size-cells = <1>; 187 #size-cells = <1>;
192 188
193 io_domains: io-domains { 189 io_domains: io-domains {
194 compatible = "rockchip 190 compatible = "rockchip,rk3228-io-voltage-domain";
195 status = "disabled"; 191 status = "disabled";
196 }; 192 };
197 193
198 power: power-controller { 194 power: power-controller {
199 compatible = "rockchip 195 compatible = "rockchip,rk3228-power-controller";
200 #power-domain-cells = 196 #power-domain-cells = <1>;
201 #address-cells = <1>; 197 #address-cells = <1>;
202 #size-cells = <0>; 198 #size-cells = <0>;
203 199
204 power-domain@RK3228_PD 200 power-domain@RK3228_PD_VIO {
205 reg = <RK3228_ 201 reg = <RK3228_PD_VIO>;
206 clocks = <&cru 202 clocks = <&cru ACLK_HDCP>,
207 <&cru 203 <&cru SCLK_HDCP>,
208 <&cru 204 <&cru ACLK_IEP>,
209 <&cru 205 <&cru HCLK_IEP>,
210 <&cru 206 <&cru ACLK_RGA>,
211 <&cru 207 <&cru HCLK_RGA>,
212 <&cru 208 <&cru SCLK_RGA>;
213 pm_qos = <&qos 209 pm_qos = <&qos_hdcp>,
214 <&qos 210 <&qos_iep>,
215 <&qos 211 <&qos_rga_r>,
216 <&qos 212 <&qos_rga_w>;
217 #power-domain- 213 #power-domain-cells = <0>;
218 }; 214 };
219 215
220 power-domain@RK3228_PD 216 power-domain@RK3228_PD_VOP {
221 reg = <RK3228_ 217 reg = <RK3228_PD_VOP>;
222 clocks = <&cru 218 clocks = <&cru ACLK_VOP>,
223 <&cru 219 <&cru DCLK_VOP>,
224 <&cru 220 <&cru HCLK_VOP>;
225 pm_qos = <&qos 221 pm_qos = <&qos_vop>;
226 #power-domain- 222 #power-domain-cells = <0>;
227 }; 223 };
228 224
229 power-domain@RK3228_PD 225 power-domain@RK3228_PD_VPU {
230 reg = <RK3228_ 226 reg = <RK3228_PD_VPU>;
231 clocks = <&cru 227 clocks = <&cru ACLK_VPU>,
232 <&cru 228 <&cru HCLK_VPU>;
233 pm_qos = <&qos 229 pm_qos = <&qos_vpu>;
234 #power-domain- 230 #power-domain-cells = <0>;
235 }; 231 };
236 232
237 power-domain@RK3228_PD 233 power-domain@RK3228_PD_RKVDEC {
238 reg = <RK3228_ 234 reg = <RK3228_PD_RKVDEC>;
239 clocks = <&cru 235 clocks = <&cru ACLK_RKVDEC>,
240 <&cru 236 <&cru HCLK_RKVDEC>,
241 <&cru 237 <&cru SCLK_VDEC_CABAC>,
242 <&cru 238 <&cru SCLK_VDEC_CORE>;
243 pm_qos = <&qos 239 pm_qos = <&qos_rkvdec_r>,
244 <&qos 240 <&qos_rkvdec_w>;
245 #power-domain- 241 #power-domain-cells = <0>;
246 }; 242 };
247 243
248 power-domain@RK3228_PD 244 power-domain@RK3228_PD_GPU {
249 reg = <RK3228_ 245 reg = <RK3228_PD_GPU>;
250 clocks = <&cru 246 clocks = <&cru ACLK_GPU>;
251 pm_qos = <&qos 247 pm_qos = <&qos_gpu>;
252 #power-domain- 248 #power-domain-cells = <0>;
253 }; 249 };
254 }; 250 };
255 251
256 u2phy0: usb2phy@760 { 252 u2phy0: usb2phy@760 {
257 compatible = "rockchip 253 compatible = "rockchip,rk3228-usb2phy";
258 reg = <0x0760 0x0c>; 254 reg = <0x0760 0x0c>;
259 clocks = <&cru SCLK_OT 255 clocks = <&cru SCLK_OTGPHY0>;
260 clock-names = "phyclk" 256 clock-names = "phyclk";
261 clock-output-names = " 257 clock-output-names = "usb480m_phy0";
262 #clock-cells = <0>; 258 #clock-cells = <0>;
263 status = "disabled"; 259 status = "disabled";
264 260
265 u2phy0_otg: otg-port { 261 u2phy0_otg: otg-port {
266 interrupts = < 262 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
267 < 263 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
268 < 264 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-name 265 interrupt-names = "otg-bvalid", "otg-id",
270 266 "linestate";
271 #phy-cells = < 267 #phy-cells = <0>;
272 status = "disa 268 status = "disabled";
273 }; 269 };
274 270
275 u2phy0_host: host-port 271 u2phy0_host: host-port {
276 interrupts = < 272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277 interrupt-name 273 interrupt-names = "linestate";
278 #phy-cells = < 274 #phy-cells = <0>;
279 status = "disa 275 status = "disabled";
280 }; 276 };
281 }; 277 };
282 278
283 u2phy1: usb2phy@800 { 279 u2phy1: usb2phy@800 {
284 compatible = "rockchip 280 compatible = "rockchip,rk3228-usb2phy";
285 reg = <0x0800 0x0c>; 281 reg = <0x0800 0x0c>;
286 clocks = <&cru SCLK_OT 282 clocks = <&cru SCLK_OTGPHY1>;
287 clock-names = "phyclk" 283 clock-names = "phyclk";
288 clock-output-names = " 284 clock-output-names = "usb480m_phy1";
289 #clock-cells = <0>; 285 #clock-cells = <0>;
290 status = "disabled"; 286 status = "disabled";
291 287
292 u2phy1_otg: otg-port { 288 u2phy1_otg: otg-port {
293 interrupts = < 289 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-name 290 interrupt-names = "linestate";
295 #phy-cells = < 291 #phy-cells = <0>;
296 status = "disa 292 status = "disabled";
297 }; 293 };
298 294
299 u2phy1_host: host-port 295 u2phy1_host: host-port {
300 interrupts = < 296 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
301 interrupt-name 297 interrupt-names = "linestate";
302 #phy-cells = < 298 #phy-cells = <0>;
303 status = "disa 299 status = "disabled";
304 }; 300 };
305 }; 301 };
306 }; 302 };
307 303
308 uart0: serial@11010000 { 304 uart0: serial@11010000 {
309 compatible = "snps,dw-apb-uart 305 compatible = "snps,dw-apb-uart";
310 reg = <0x11010000 0x100>; 306 reg = <0x11010000 0x100>;
311 interrupts = <GIC_SPI 55 IRQ_T 307 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
312 clock-frequency = <24000000>; 308 clock-frequency = <24000000>;
313 clocks = <&cru SCLK_UART0>, <& 309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
314 clock-names = "baudclk", "apb_ 310 clock-names = "baudclk", "apb_pclk";
315 pinctrl-names = "default"; 311 pinctrl-names = "default";
316 pinctrl-0 = <&uart0_xfer &uart 312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
317 reg-shift = <2>; 313 reg-shift = <2>;
318 reg-io-width = <4>; 314 reg-io-width = <4>;
319 status = "disabled"; 315 status = "disabled";
320 }; 316 };
321 317
322 uart1: serial@11020000 { 318 uart1: serial@11020000 {
323 compatible = "snps,dw-apb-uart 319 compatible = "snps,dw-apb-uart";
324 reg = <0x11020000 0x100>; 320 reg = <0x11020000 0x100>;
325 interrupts = <GIC_SPI 56 IRQ_T 321 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
326 clock-frequency = <24000000>; 322 clock-frequency = <24000000>;
327 clocks = <&cru SCLK_UART1>, <& 323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
328 clock-names = "baudclk", "apb_ 324 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default"; 325 pinctrl-names = "default";
330 pinctrl-0 = <&uart1_xfer>; 326 pinctrl-0 = <&uart1_xfer>;
331 reg-shift = <2>; 327 reg-shift = <2>;
332 reg-io-width = <4>; 328 reg-io-width = <4>;
333 status = "disabled"; 329 status = "disabled";
334 }; 330 };
335 331
336 uart2: serial@11030000 { 332 uart2: serial@11030000 {
337 compatible = "snps,dw-apb-uart 333 compatible = "snps,dw-apb-uart";
338 reg = <0x11030000 0x100>; 334 reg = <0x11030000 0x100>;
339 interrupts = <GIC_SPI 57 IRQ_T 335 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
340 clock-frequency = <24000000>; 336 clock-frequency = <24000000>;
341 clocks = <&cru SCLK_UART2>, <& 337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
342 clock-names = "baudclk", "apb_ 338 clock-names = "baudclk", "apb_pclk";
343 pinctrl-names = "default"; 339 pinctrl-names = "default";
344 pinctrl-0 = <&uart2_xfer>; 340 pinctrl-0 = <&uart2_xfer>;
345 reg-shift = <2>; 341 reg-shift = <2>;
346 reg-io-width = <4>; 342 reg-io-width = <4>;
347 status = "disabled"; 343 status = "disabled";
348 }; 344 };
349 345
350 efuse: efuse@11040000 { 346 efuse: efuse@11040000 {
351 compatible = "rockchip,rk3228- 347 compatible = "rockchip,rk3228-efuse";
352 reg = <0x11040000 0x20>; 348 reg = <0x11040000 0x20>;
353 clocks = <&cru PCLK_EFUSE_256> 349 clocks = <&cru PCLK_EFUSE_256>;
354 clock-names = "pclk_efuse"; 350 clock-names = "pclk_efuse";
355 #address-cells = <1>; 351 #address-cells = <1>;
356 #size-cells = <1>; 352 #size-cells = <1>;
357 353
358 /* Data cells */ 354 /* Data cells */
359 efuse_id: id@7 { 355 efuse_id: id@7 {
360 reg = <0x7 0x10>; 356 reg = <0x7 0x10>;
361 }; 357 };
362 cpu_leakage: cpu_leakage@17 { 358 cpu_leakage: cpu_leakage@17 {
363 reg = <0x17 0x1>; 359 reg = <0x17 0x1>;
364 }; 360 };
365 }; 361 };
366 362
367 i2c0: i2c@11050000 { 363 i2c0: i2c@11050000 {
368 compatible = "rockchip,rk3228- 364 compatible = "rockchip,rk3228-i2c";
369 reg = <0x11050000 0x1000>; 365 reg = <0x11050000 0x1000>;
370 interrupts = <GIC_SPI 36 IRQ_T 366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>; 367 #address-cells = <1>;
372 #size-cells = <0>; 368 #size-cells = <0>;
373 clock-names = "i2c"; 369 clock-names = "i2c";
374 clocks = <&cru PCLK_I2C0>; 370 clocks = <&cru PCLK_I2C0>;
375 pinctrl-names = "default"; 371 pinctrl-names = "default";
376 pinctrl-0 = <&i2c0_xfer>; 372 pinctrl-0 = <&i2c0_xfer>;
377 status = "disabled"; 373 status = "disabled";
378 }; 374 };
379 375
380 i2c1: i2c@11060000 { 376 i2c1: i2c@11060000 {
381 compatible = "rockchip,rk3228- 377 compatible = "rockchip,rk3228-i2c";
382 reg = <0x11060000 0x1000>; 378 reg = <0x11060000 0x1000>;
383 interrupts = <GIC_SPI 37 IRQ_T 379 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
384 #address-cells = <1>; 380 #address-cells = <1>;
385 #size-cells = <0>; 381 #size-cells = <0>;
386 clock-names = "i2c"; 382 clock-names = "i2c";
387 clocks = <&cru PCLK_I2C1>; 383 clocks = <&cru PCLK_I2C1>;
388 pinctrl-names = "default"; 384 pinctrl-names = "default";
389 pinctrl-0 = <&i2c1_xfer>; 385 pinctrl-0 = <&i2c1_xfer>;
390 status = "disabled"; 386 status = "disabled";
391 }; 387 };
392 388
393 i2c2: i2c@11070000 { 389 i2c2: i2c@11070000 {
394 compatible = "rockchip,rk3228- 390 compatible = "rockchip,rk3228-i2c";
395 reg = <0x11070000 0x1000>; 391 reg = <0x11070000 0x1000>;
396 interrupts = <GIC_SPI 38 IRQ_T 392 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>; 393 #address-cells = <1>;
398 #size-cells = <0>; 394 #size-cells = <0>;
399 clock-names = "i2c"; 395 clock-names = "i2c";
400 clocks = <&cru PCLK_I2C2>; 396 clocks = <&cru PCLK_I2C2>;
401 pinctrl-names = "default"; 397 pinctrl-names = "default";
402 pinctrl-0 = <&i2c2_xfer>; 398 pinctrl-0 = <&i2c2_xfer>;
403 status = "disabled"; 399 status = "disabled";
404 }; 400 };
405 401
406 i2c3: i2c@11080000 { 402 i2c3: i2c@11080000 {
407 compatible = "rockchip,rk3228- 403 compatible = "rockchip,rk3228-i2c";
408 reg = <0x11080000 0x1000>; 404 reg = <0x11080000 0x1000>;
409 interrupts = <GIC_SPI 39 IRQ_T 405 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
410 #address-cells = <1>; 406 #address-cells = <1>;
411 #size-cells = <0>; 407 #size-cells = <0>;
412 clock-names = "i2c"; 408 clock-names = "i2c";
413 clocks = <&cru PCLK_I2C3>; 409 clocks = <&cru PCLK_I2C3>;
414 pinctrl-names = "default"; 410 pinctrl-names = "default";
415 pinctrl-0 = <&i2c3_xfer>; 411 pinctrl-0 = <&i2c3_xfer>;
416 status = "disabled"; 412 status = "disabled";
417 }; 413 };
418 414
419 spi0: spi@11090000 { 415 spi0: spi@11090000 {
420 compatible = "rockchip,rk3228- 416 compatible = "rockchip,rk3228-spi";
421 reg = <0x11090000 0x1000>; 417 reg = <0x11090000 0x1000>;
422 interrupts = <GIC_SPI 49 IRQ_T 418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>; 419 #address-cells = <1>;
424 #size-cells = <0>; 420 #size-cells = <0>;
425 clocks = <&cru SCLK_SPI0>, <&c 421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
426 clock-names = "spiclk", "apb_p 422 clock-names = "spiclk", "apb_pclk";
427 pinctrl-names = "default"; 423 pinctrl-names = "default";
428 pinctrl-0 = <&spi0_clk &spi0_t 424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
429 status = "disabled"; 425 status = "disabled";
430 }; 426 };
431 427
432 wdt: watchdog@110a0000 { 428 wdt: watchdog@110a0000 {
433 compatible = "rockchip,rk3228- 429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
434 reg = <0x110a0000 0x100>; 430 reg = <0x110a0000 0x100>;
435 interrupts = <GIC_SPI 40 IRQ_T 431 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&cru PCLK_CPU>; 432 clocks = <&cru PCLK_CPU>;
437 status = "disabled"; 433 status = "disabled";
438 }; 434 };
439 435
440 pwm0: pwm@110b0000 { 436 pwm0: pwm@110b0000 {
441 compatible = "rockchip,rk3288- 437 compatible = "rockchip,rk3288-pwm";
442 reg = <0x110b0000 0x10>; 438 reg = <0x110b0000 0x10>;
443 #pwm-cells = <3>; 439 #pwm-cells = <3>;
444 clocks = <&cru PCLK_PWM>; 440 clocks = <&cru PCLK_PWM>;
445 pinctrl-names = "default"; 441 pinctrl-names = "default";
446 pinctrl-0 = <&pwm0_pin>; 442 pinctrl-0 = <&pwm0_pin>;
447 status = "disabled"; 443 status = "disabled";
448 }; 444 };
449 445
450 pwm1: pwm@110b0010 { 446 pwm1: pwm@110b0010 {
451 compatible = "rockchip,rk3288- 447 compatible = "rockchip,rk3288-pwm";
452 reg = <0x110b0010 0x10>; 448 reg = <0x110b0010 0x10>;
453 #pwm-cells = <3>; 449 #pwm-cells = <3>;
454 clocks = <&cru PCLK_PWM>; 450 clocks = <&cru PCLK_PWM>;
455 pinctrl-names = "default"; 451 pinctrl-names = "default";
456 pinctrl-0 = <&pwm1_pin>; 452 pinctrl-0 = <&pwm1_pin>;
457 status = "disabled"; 453 status = "disabled";
458 }; 454 };
459 455
460 pwm2: pwm@110b0020 { 456 pwm2: pwm@110b0020 {
461 compatible = "rockchip,rk3288- 457 compatible = "rockchip,rk3288-pwm";
462 reg = <0x110b0020 0x10>; 458 reg = <0x110b0020 0x10>;
463 #pwm-cells = <3>; 459 #pwm-cells = <3>;
464 clocks = <&cru PCLK_PWM>; 460 clocks = <&cru PCLK_PWM>;
465 pinctrl-names = "default"; 461 pinctrl-names = "default";
466 pinctrl-0 = <&pwm2_pin>; 462 pinctrl-0 = <&pwm2_pin>;
467 status = "disabled"; 463 status = "disabled";
468 }; 464 };
469 465
470 pwm3: pwm@110b0030 { 466 pwm3: pwm@110b0030 {
471 compatible = "rockchip,rk3288- 467 compatible = "rockchip,rk3288-pwm";
472 reg = <0x110b0030 0x10>; 468 reg = <0x110b0030 0x10>;
473 #pwm-cells = <2>; 469 #pwm-cells = <2>;
474 clocks = <&cru PCLK_PWM>; 470 clocks = <&cru PCLK_PWM>;
475 pinctrl-names = "default"; 471 pinctrl-names = "default";
476 pinctrl-0 = <&pwm3_pin>; 472 pinctrl-0 = <&pwm3_pin>;
477 status = "disabled"; 473 status = "disabled";
478 }; 474 };
479 475
480 timer: timer@110c0000 { 476 timer: timer@110c0000 {
481 compatible = "rockchip,rk3228- 477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
482 reg = <0x110c0000 0x20>; 478 reg = <0x110c0000 0x20>;
483 interrupts = <GIC_SPI 43 IRQ_T 479 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru PCLK_TIMER>, <& 480 clocks = <&cru PCLK_TIMER>, <&xin24m>;
485 clock-names = "pclk", "timer"; 481 clock-names = "pclk", "timer";
486 }; 482 };
487 483
488 cru: clock-controller@110e0000 { 484 cru: clock-controller@110e0000 {
489 compatible = "rockchip,rk3228- 485 compatible = "rockchip,rk3228-cru";
490 reg = <0x110e0000 0x1000>; 486 reg = <0x110e0000 0x1000>;
491 clocks = <&xin24m>; 487 clocks = <&xin24m>;
492 clock-names = "xin24m"; 488 clock-names = "xin24m";
493 rockchip,grf = <&grf>; 489 rockchip,grf = <&grf>;
494 #clock-cells = <1>; 490 #clock-cells = <1>;
495 #reset-cells = <1>; 491 #reset-cells = <1>;
496 assigned-clocks = 492 assigned-clocks =
497 <&cru PLL_GPLL>, <&cru 493 <&cru PLL_GPLL>, <&cru ARMCLK>,
498 <&cru PLL_CPLL>, <&cru 494 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
499 <&cru HCLK_PERI>, <&cr 495 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
500 <&cru ACLK_CPU>, <&cru 496 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
501 <&cru PCLK_CPU>; 497 <&cru PCLK_CPU>;
502 assigned-clock-rates = 498 assigned-clock-rates =
503 <594000000>, <81600000 499 <594000000>, <816000000>,
504 <500000000>, <15000000 500 <500000000>, <150000000>,
505 <150000000>, <75000000 501 <150000000>, <75000000>,
506 <150000000>, <15000000 502 <150000000>, <150000000>,
507 <75000000>; 503 <75000000>;
508 }; 504 };
509 505
510 pdma: dma-controller@110f0000 { 506 pdma: dma-controller@110f0000 {
511 compatible = "arm,pl330", "arm 507 compatible = "arm,pl330", "arm,primecell";
512 reg = <0x110f0000 0x4000>; 508 reg = <0x110f0000 0x4000>;
513 interrupts = <GIC_SPI 0 IRQ_TY 509 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 1 IRQ_TY 510 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
515 #dma-cells = <1>; 511 #dma-cells = <1>;
516 arm,pl330-periph-burst; 512 arm,pl330-periph-burst;
517 clocks = <&cru ACLK_DMAC>; 513 clocks = <&cru ACLK_DMAC>;
518 clock-names = "apb_pclk"; 514 clock-names = "apb_pclk";
519 }; 515 };
520 516
521 thermal-zones { 517 thermal-zones {
522 cpu_thermal: cpu-thermal { 518 cpu_thermal: cpu-thermal {
523 polling-delay-passive 519 polling-delay-passive = <100>; /* milliseconds */
524 polling-delay = <5000> 520 polling-delay = <5000>; /* milliseconds */
525 521
526 thermal-sensors = <&ts 522 thermal-sensors = <&tsadc 0>;
527 523
528 trips { 524 trips {
529 cpu_alert0: cp 525 cpu_alert0: cpu_alert0 {
530 temper 526 temperature = <70000>; /* millicelsius */
531 hyster 527 hysteresis = <2000>; /* millicelsius */
532 type = 528 type = "passive";
533 }; 529 };
534 cpu_alert1: cp 530 cpu_alert1: cpu_alert1 {
535 temper 531 temperature = <75000>; /* millicelsius */
536 hyster 532 hysteresis = <2000>; /* millicelsius */
537 type = 533 type = "passive";
538 }; 534 };
539 cpu_crit: cpu_ 535 cpu_crit: cpu_crit {
540 temper 536 temperature = <90000>; /* millicelsius */
541 hyster 537 hysteresis = <2000>; /* millicelsius */
542 type = 538 type = "critical";
543 }; 539 };
544 }; 540 };
545 541
546 cooling-maps { 542 cooling-maps {
547 map0 { 543 map0 {
548 trip = 544 trip = <&cpu_alert0>;
549 coolin 545 cooling-device =
550 546 <&cpu0 THERMAL_NO_LIMIT 6>,
551 547 <&cpu1 THERMAL_NO_LIMIT 6>,
552 548 <&cpu2 THERMAL_NO_LIMIT 6>,
553 549 <&cpu3 THERMAL_NO_LIMIT 6>;
554 }; 550 };
555 map1 { 551 map1 {
556 trip = 552 trip = <&cpu_alert1>;
557 coolin 553 cooling-device =
558 554 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
559 555 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
560 556 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
561 557 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
562 }; 558 };
563 }; 559 };
564 }; 560 };
565 }; 561 };
566 562
567 tsadc: tsadc@11150000 { 563 tsadc: tsadc@11150000 {
568 compatible = "rockchip,rk3228- 564 compatible = "rockchip,rk3228-tsadc";
569 reg = <0x11150000 0x100>; 565 reg = <0x11150000 0x100>;
570 interrupts = <GIC_SPI 58 IRQ_T 566 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cru SCLK_TSADC>, <& 567 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
572 clock-names = "tsadc", "apb_pc 568 clock-names = "tsadc", "apb_pclk";
573 assigned-clocks = <&cru SCLK_T 569 assigned-clocks = <&cru SCLK_TSADC>;
574 assigned-clock-rates = <32768> 570 assigned-clock-rates = <32768>;
575 resets = <&cru SRST_TSADC>; 571 resets = <&cru SRST_TSADC>;
576 reset-names = "tsadc-apb"; 572 reset-names = "tsadc-apb";
577 pinctrl-names = "init", "defau 573 pinctrl-names = "init", "default", "sleep";
578 pinctrl-0 = <&otp_pin>; 574 pinctrl-0 = <&otp_pin>;
579 pinctrl-1 = <&otp_out>; 575 pinctrl-1 = <&otp_out>;
580 pinctrl-2 = <&otp_pin>; 576 pinctrl-2 = <&otp_pin>;
581 #thermal-sensor-cells = <1>; 577 #thermal-sensor-cells = <1>;
582 rockchip,hw-tshut-temp = <9500 578 rockchip,hw-tshut-temp = <95000>;
583 status = "disabled"; 579 status = "disabled";
584 }; 580 };
585 581
586 hdmi_phy: hdmi-phy@12030000 { 582 hdmi_phy: hdmi-phy@12030000 {
587 compatible = "rockchip,rk3228- 583 compatible = "rockchip,rk3228-hdmi-phy";
588 reg = <0x12030000 0x10000>; 584 reg = <0x12030000 0x10000>;
589 clocks = <&cru PCLK_HDMI_PHY>, 585 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
590 clock-names = "sysclk", "refoc 586 clock-names = "sysclk", "refoclk", "refpclk";
591 #clock-cells = <0>; 587 #clock-cells = <0>;
592 clock-output-names = "hdmiphy_ 588 clock-output-names = "hdmiphy_phy";
593 #phy-cells = <0>; 589 #phy-cells = <0>;
594 status = "disabled"; 590 status = "disabled";
595 }; 591 };
596 592
597 gpu: gpu@20000000 { 593 gpu: gpu@20000000 {
598 compatible = "rockchip,rk3228- 594 compatible = "rockchip,rk3228-mali", "arm,mali-400";
599 reg = <0x20000000 0x10000>; 595 reg = <0x20000000 0x10000>;
600 interrupts = <GIC_SPI 6 IRQ_TY 596 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 5 IRQ_TY 597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 4 IRQ_TY 598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 5 IRQ_TY 599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 4 IRQ_TY 600 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 5 IRQ_TY 601 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-names = "gp", 602 interrupt-names = "gp",
607 "gpmmu", 603 "gpmmu",
608 "pp0", 604 "pp0",
609 "ppmmu0", 605 "ppmmu0",
610 "pp1", 606 "pp1",
611 "ppmmu1"; 607 "ppmmu1";
612 clocks = <&cru ACLK_GPU>, <&cr 608 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
613 clock-names = "bus", "core"; 609 clock-names = "bus", "core";
614 power-domains = <&power RK3228 610 power-domains = <&power RK3228_PD_GPU>;
615 resets = <&cru SRST_GPU_A>; 611 resets = <&cru SRST_GPU_A>;
616 status = "disabled"; 612 status = "disabled";
617 }; 613 };
618 614
619 vpu: video-codec@20020000 { 615 vpu: video-codec@20020000 {
620 compatible = "rockchip,rk3228- 616 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
621 reg = <0x20020000 0x800>; 617 reg = <0x20020000 0x800>;
622 interrupts = <GIC_SPI 11 IRQ_T 618 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 9 IRQ_T 619 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "vepu", "vdp 620 interrupt-names = "vepu", "vdpu";
625 clocks = <&cru ACLK_VPU>, <&cr 621 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
626 clock-names = "aclk", "hclk"; 622 clock-names = "aclk", "hclk";
627 iommus = <&vpu_mmu>; 623 iommus = <&vpu_mmu>;
628 power-domains = <&power RK3228 624 power-domains = <&power RK3228_PD_VPU>;
629 }; 625 };
630 626
631 vpu_mmu: iommu@20020800 { 627 vpu_mmu: iommu@20020800 {
632 compatible = "rockchip,iommu"; 628 compatible = "rockchip,iommu";
633 reg = <0x20020800 0x100>; 629 reg = <0x20020800 0x100>;
634 interrupts = <GIC_SPI 10 IRQ_T 630 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cru ACLK_VPU>, <&cr 631 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
636 clock-names = "aclk", "iface"; 632 clock-names = "aclk", "iface";
637 power-domains = <&power RK3228 633 power-domains = <&power RK3228_PD_VPU>;
638 #iommu-cells = <0>; 634 #iommu-cells = <0>;
639 }; 635 };
640 636
641 vdec: video-codec@20030000 { 637 vdec: video-codec@20030000 {
642 compatible = "rockchip,rk3228- 638 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
643 reg = <0x20030000 0x480>; 639 reg = <0x20030000 0x480>;
644 interrupts = <GIC_SPI 7 IRQ_TY 640 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru ACLK_RKVDEC>, < 641 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
646 <&cru SCLK_VDEC_CABAC 642 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
647 clock-names = "axi", "ahb", "c 643 clock-names = "axi", "ahb", "cabac", "core";
648 assigned-clocks = <&cru SCLK_V 644 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
649 assigned-clock-rates = <300000 645 assigned-clock-rates = <300000000>, <300000000>;
650 iommus = <&vdec_mmu>; 646 iommus = <&vdec_mmu>;
651 power-domains = <&power RK3228 647 power-domains = <&power RK3228_PD_RKVDEC>;
652 }; 648 };
653 649
654 vdec_mmu: iommu@20030480 { 650 vdec_mmu: iommu@20030480 {
655 compatible = "rockchip,iommu"; 651 compatible = "rockchip,iommu";
656 reg = <0x20030480 0x40>, <0x20 652 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
657 interrupts = <GIC_SPI 8 IRQ_TY 653 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cru ACLK_RKVDEC>, < 654 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
659 clock-names = "aclk", "iface"; 655 clock-names = "aclk", "iface";
660 power-domains = <&power RK3228 656 power-domains = <&power RK3228_PD_RKVDEC>;
661 #iommu-cells = <0>; 657 #iommu-cells = <0>;
662 }; 658 };
663 659
664 vop: vop@20050000 { 660 vop: vop@20050000 {
665 compatible = "rockchip,rk3228- 661 compatible = "rockchip,rk3228-vop";
666 reg = <0x20050000 0x1ffc>; 662 reg = <0x20050000 0x1ffc>;
667 interrupts = <GIC_SPI 32 IRQ_T 663 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&cru ACLK_VOP>, <&cr 664 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
669 clock-names = "aclk_vop", "dcl 665 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
670 resets = <&cru SRST_VOP_A>, <& 666 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
671 reset-names = "axi", "ahb", "d 667 reset-names = "axi", "ahb", "dclk";
672 iommus = <&vop_mmu>; 668 iommus = <&vop_mmu>;
673 power-domains = <&power RK3228 669 power-domains = <&power RK3228_PD_VOP>;
674 status = "disabled"; 670 status = "disabled";
675 671
676 vop_out: port { 672 vop_out: port {
677 #address-cells = <1>; 673 #address-cells = <1>;
678 #size-cells = <0>; 674 #size-cells = <0>;
679 675
680 vop_out_hdmi: endpoint 676 vop_out_hdmi: endpoint@0 {
681 reg = <0>; 677 reg = <0>;
682 remote-endpoin 678 remote-endpoint = <&hdmi_in_vop>;
683 }; 679 };
684 }; 680 };
685 }; 681 };
686 682
687 vop_mmu: iommu@20053f00 { 683 vop_mmu: iommu@20053f00 {
688 compatible = "rockchip,iommu"; 684 compatible = "rockchip,iommu";
689 reg = <0x20053f00 0x100>; 685 reg = <0x20053f00 0x100>;
690 interrupts = <GIC_SPI 32 IRQ_T 686 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cru ACLK_VOP>, <&cr 687 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
692 clock-names = "aclk", "iface"; 688 clock-names = "aclk", "iface";
693 power-domains = <&power RK3228 689 power-domains = <&power RK3228_PD_VOP>;
694 #iommu-cells = <0>; 690 #iommu-cells = <0>;
695 status = "disabled"; 691 status = "disabled";
696 }; 692 };
697 693
698 rga: rga@20060000 { 694 rga: rga@20060000 {
699 compatible = "rockchip,rk3228- 695 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
700 reg = <0x20060000 0x1000>; 696 reg = <0x20060000 0x1000>;
701 interrupts = <GIC_SPI 33 IRQ_T 697 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&cru ACLK_RGA>, <&cr 698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
703 clock-names = "aclk", "hclk", 699 clock-names = "aclk", "hclk", "sclk";
704 power-domains = <&power RK3228 700 power-domains = <&power RK3228_PD_VIO>;
705 resets = <&cru SRST_RGA>, <&cr 701 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
706 reset-names = "core", "axi", " 702 reset-names = "core", "axi", "ahb";
707 }; 703 };
708 704
709 iep_mmu: iommu@20070800 { 705 iep_mmu: iommu@20070800 {
710 compatible = "rockchip,iommu"; 706 compatible = "rockchip,iommu";
711 reg = <0x20070800 0x100>; 707 reg = <0x20070800 0x100>;
712 interrupts = <GIC_SPI 31 IRQ_T 708 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&cru ACLK_IEP>, <&cr 709 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
714 clock-names = "aclk", "iface"; 710 clock-names = "aclk", "iface";
715 power-domains = <&power RK3228 711 power-domains = <&power RK3228_PD_VIO>;
716 #iommu-cells = <0>; 712 #iommu-cells = <0>;
717 status = "disabled"; 713 status = "disabled";
718 }; 714 };
719 715
720 hdmi: hdmi@200a0000 { 716 hdmi: hdmi@200a0000 {
721 compatible = "rockchip,rk3228- 717 compatible = "rockchip,rk3228-dw-hdmi";
722 reg = <0x200a0000 0x20000>; 718 reg = <0x200a0000 0x20000>;
723 reg-io-width = <4>; 719 reg-io-width = <4>;
724 interrupts = <GIC_SPI 35 IRQ_T 720 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
725 assigned-clocks = <&cru SCLK_H 721 assigned-clocks = <&cru SCLK_HDMI_PHY>;
726 assigned-clock-parents = <&hdm 722 assigned-clock-parents = <&hdmi_phy>;
727 clocks = <&cru PCLK_HDMI_CTRL> 723 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
728 clock-names = "iahb", "isfr", 724 clock-names = "iahb", "isfr", "cec";
729 pinctrl-names = "default"; 725 pinctrl-names = "default";
730 pinctrl-0 = <&hdmii2c_xfer &hd 726 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
731 resets = <&cru SRST_HDMI_P>; 727 resets = <&cru SRST_HDMI_P>;
732 reset-names = "hdmi"; 728 reset-names = "hdmi";
733 phys = <&hdmi_phy>; 729 phys = <&hdmi_phy>;
734 phy-names = "hdmi"; 730 phy-names = "hdmi";
735 rockchip,grf = <&grf>; 731 rockchip,grf = <&grf>;
736 status = "disabled"; 732 status = "disabled";
737 733
738 ports { 734 ports {
739 #address-cells = <1>; !! 735 hdmi_in: port {
740 #size-cells = <0>; !! 736 #address-cells = <1>;
741 !! 737 #size-cells = <0>;
742 hdmi_in: port@0 { !! 738 hdmi_in_vop: endpoint@0 {
743 reg = <0>; !! 739 reg = <0>;
744 <<
745 hdmi_in_vop: e <<
746 remote 740 remote-endpoint = <&vop_out_hdmi>;
747 }; 741 };
748 }; <<
749 <<
750 hdmi_out: port@1 { <<
751 reg = <1>; <<
752 }; 742 };
753 }; 743 };
754 }; 744 };
755 745
756 sdmmc: mmc@30000000 { 746 sdmmc: mmc@30000000 {
757 compatible = "rockchip,rk3228- 747 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
758 reg = <0x30000000 0x4000>; 748 reg = <0x30000000 0x4000>;
759 interrupts = <GIC_SPI 12 IRQ_T 749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&cru HCLK_SDMMC>, <& 750 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
761 <&cru SCLK_SDMMC_DRV> 751 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
762 clock-names = "biu", "ciu", "c 752 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
763 fifo-depth = <0x100>; 753 fifo-depth = <0x100>;
764 pinctrl-names = "default"; 754 pinctrl-names = "default";
765 pinctrl-0 = <&sdmmc_clk &sdmmc 755 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
766 status = "disabled"; 756 status = "disabled";
767 }; 757 };
768 758
769 sdio: mmc@30010000 { 759 sdio: mmc@30010000 {
770 compatible = "rockchip,rk3228- 760 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
771 reg = <0x30010000 0x4000>; 761 reg = <0x30010000 0x4000>;
772 interrupts = <GIC_SPI 13 IRQ_T 762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&cru HCLK_SDIO>, <&c 763 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
774 <&cru SCLK_SDIO_DRV>, 764 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
775 clock-names = "biu", "ciu", "c 765 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
776 fifo-depth = <0x100>; 766 fifo-depth = <0x100>;
777 pinctrl-names = "default"; 767 pinctrl-names = "default";
778 pinctrl-0 = <&sdio_clk &sdio_c 768 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
779 status = "disabled"; 769 status = "disabled";
780 }; 770 };
781 771
782 emmc: mmc@30020000 { 772 emmc: mmc@30020000 {
783 compatible = "rockchip,rk3228- 773 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
784 reg = <0x30020000 0x4000>; 774 reg = <0x30020000 0x4000>;
785 interrupts = <GIC_SPI 14 IRQ_T 775 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
786 clock-frequency = <37500000>; 776 clock-frequency = <37500000>;
787 max-frequency = <37500000>; 777 max-frequency = <37500000>;
788 clocks = <&cru HCLK_EMMC>, <&c 778 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
789 <&cru SCLK_EMMC_DRV>, 779 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
790 clock-names = "biu", "ciu", "c 780 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
791 bus-width = <8>; 781 bus-width = <8>;
792 rockchip,default-sample-phase 782 rockchip,default-sample-phase = <158>;
793 fifo-depth = <0x100>; 783 fifo-depth = <0x100>;
794 pinctrl-names = "default"; 784 pinctrl-names = "default";
795 pinctrl-0 = <&emmc_clk &emmc_c 785 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
796 resets = <&cru SRST_EMMC>; 786 resets = <&cru SRST_EMMC>;
797 reset-names = "reset"; 787 reset-names = "reset";
798 status = "disabled"; 788 status = "disabled";
799 }; 789 };
800 790
801 usb_otg: usb@30040000 { 791 usb_otg: usb@30040000 {
802 compatible = "rockchip,rk3228- 792 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
803 "snps,dwc2"; 793 "snps,dwc2";
804 reg = <0x30040000 0x40000>; 794 reg = <0x30040000 0x40000>;
805 interrupts = <GIC_SPI 23 IRQ_T 795 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&cru HCLK_OTG>; 796 clocks = <&cru HCLK_OTG>;
807 clock-names = "otg"; 797 clock-names = "otg";
808 dr_mode = "otg"; 798 dr_mode = "otg";
809 g-np-tx-fifo-size = <16>; 799 g-np-tx-fifo-size = <16>;
810 g-rx-fifo-size = <280>; 800 g-rx-fifo-size = <280>;
811 g-tx-fifo-size = <256 128 128 801 g-tx-fifo-size = <256 128 128 64 32 16>;
812 phys = <&u2phy0_otg>; 802 phys = <&u2phy0_otg>;
813 phy-names = "usb2-phy"; 803 phy-names = "usb2-phy";
814 status = "disabled"; 804 status = "disabled";
815 }; 805 };
816 806
817 usb_host0_ehci: usb@30080000 { 807 usb_host0_ehci: usb@30080000 {
818 compatible = "generic-ehci"; 808 compatible = "generic-ehci";
819 reg = <0x30080000 0x20000>; 809 reg = <0x30080000 0x20000>;
820 interrupts = <GIC_SPI 16 IRQ_T 810 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cru HCLK_HOST0>, <& 811 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
822 phys = <&u2phy0_host>; 812 phys = <&u2phy0_host>;
823 phy-names = "usb"; 813 phy-names = "usb";
824 status = "disabled"; 814 status = "disabled";
825 }; 815 };
826 816
827 usb_host0_ohci: usb@300a0000 { 817 usb_host0_ohci: usb@300a0000 {
828 compatible = "generic-ohci"; 818 compatible = "generic-ohci";
829 reg = <0x300a0000 0x20000>; 819 reg = <0x300a0000 0x20000>;
830 interrupts = <GIC_SPI 17 IRQ_T 820 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cru HCLK_HOST0>, <& 821 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
832 phys = <&u2phy0_host>; 822 phys = <&u2phy0_host>;
833 phy-names = "usb"; 823 phy-names = "usb";
834 status = "disabled"; 824 status = "disabled";
835 }; 825 };
836 826
837 usb_host1_ehci: usb@300c0000 { 827 usb_host1_ehci: usb@300c0000 {
838 compatible = "generic-ehci"; 828 compatible = "generic-ehci";
839 reg = <0x300c0000 0x20000>; 829 reg = <0x300c0000 0x20000>;
840 interrupts = <GIC_SPI 19 IRQ_T 830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&cru HCLK_HOST1>, <& 831 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
842 phys = <&u2phy1_otg>; 832 phys = <&u2phy1_otg>;
843 phy-names = "usb"; 833 phy-names = "usb";
844 status = "disabled"; 834 status = "disabled";
845 }; 835 };
846 836
847 usb_host1_ohci: usb@300e0000 { 837 usb_host1_ohci: usb@300e0000 {
848 compatible = "generic-ohci"; 838 compatible = "generic-ohci";
849 reg = <0x300e0000 0x20000>; 839 reg = <0x300e0000 0x20000>;
850 interrupts = <GIC_SPI 20 IRQ_T 840 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&cru HCLK_HOST1>, <& 841 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
852 phys = <&u2phy1_otg>; 842 phys = <&u2phy1_otg>;
853 phy-names = "usb"; 843 phy-names = "usb";
854 status = "disabled"; 844 status = "disabled";
855 }; 845 };
856 846
857 usb_host2_ehci: usb@30100000 { 847 usb_host2_ehci: usb@30100000 {
858 compatible = "generic-ehci"; 848 compatible = "generic-ehci";
859 reg = <0x30100000 0x20000>; 849 reg = <0x30100000 0x20000>;
860 interrupts = <GIC_SPI 66 IRQ_T 850 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru HCLK_HOST2>, <& 851 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
862 phys = <&u2phy1_host>; 852 phys = <&u2phy1_host>;
863 phy-names = "usb"; 853 phy-names = "usb";
864 status = "disabled"; 854 status = "disabled";
865 }; 855 };
866 856
867 usb_host2_ohci: usb@30120000 { 857 usb_host2_ohci: usb@30120000 {
868 compatible = "generic-ohci"; 858 compatible = "generic-ohci";
869 reg = <0x30120000 0x20000>; 859 reg = <0x30120000 0x20000>;
870 interrupts = <GIC_SPI 67 IRQ_T 860 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru HCLK_HOST2>, <& 861 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
872 phys = <&u2phy1_host>; 862 phys = <&u2phy1_host>;
873 phy-names = "usb"; 863 phy-names = "usb";
874 status = "disabled"; 864 status = "disabled";
875 }; 865 };
876 866
877 gmac: ethernet@30200000 { 867 gmac: ethernet@30200000 {
878 compatible = "rockchip,rk3228- 868 compatible = "rockchip,rk3228-gmac";
879 reg = <0x30200000 0x10000>; 869 reg = <0x30200000 0x10000>;
880 interrupts = <GIC_SPI 24 IRQ_T 870 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
881 interrupt-names = "macirq"; 871 interrupt-names = "macirq";
882 clocks = <&cru SCLK_MAC>, <&cr 872 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
883 <&cru SCLK_MAC_TX>, <& 873 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
884 <&cru SCLK_MAC_REFOUT> 874 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
885 <&cru PCLK_GMAC>; 875 <&cru PCLK_GMAC>;
886 clock-names = "stmmaceth", "ma 876 clock-names = "stmmaceth", "mac_clk_rx",
887 "mac_clk_tx", "clk_mac 877 "mac_clk_tx", "clk_mac_ref",
888 "clk_mac_refout", "acl 878 "clk_mac_refout", "aclk_mac",
889 "pclk_mac"; 879 "pclk_mac";
890 resets = <&cru SRST_GMAC>; 880 resets = <&cru SRST_GMAC>;
891 reset-names = "stmmaceth"; 881 reset-names = "stmmaceth";
892 rockchip,grf = <&grf>; 882 rockchip,grf = <&grf>;
893 status = "disabled"; 883 status = "disabled";
894 }; 884 };
895 885
896 qos_iep: qos@31030080 { 886 qos_iep: qos@31030080 {
897 compatible = "rockchip,rk3228- 887 compatible = "rockchip,rk3228-qos", "syscon";
898 reg = <0x31030080 0x20>; 888 reg = <0x31030080 0x20>;
899 }; 889 };
900 890
901 qos_rga_w: qos@31030100 { 891 qos_rga_w: qos@31030100 {
902 compatible = "rockchip,rk3228- 892 compatible = "rockchip,rk3228-qos", "syscon";
903 reg = <0x31030100 0x20>; 893 reg = <0x31030100 0x20>;
904 }; 894 };
905 895
906 qos_hdcp: qos@31030180 { 896 qos_hdcp: qos@31030180 {
907 compatible = "rockchip,rk3228- 897 compatible = "rockchip,rk3228-qos", "syscon";
908 reg = <0x31030180 0x20>; 898 reg = <0x31030180 0x20>;
909 }; 899 };
910 900
911 qos_rga_r: qos@31030200 { 901 qos_rga_r: qos@31030200 {
912 compatible = "rockchip,rk3228- 902 compatible = "rockchip,rk3228-qos", "syscon";
913 reg = <0x31030200 0x20>; 903 reg = <0x31030200 0x20>;
914 }; 904 };
915 905
916 qos_vpu: qos@31040000 { 906 qos_vpu: qos@31040000 {
917 compatible = "rockchip,rk3228- 907 compatible = "rockchip,rk3228-qos", "syscon";
918 reg = <0x31040000 0x20>; 908 reg = <0x31040000 0x20>;
919 }; 909 };
920 910
921 qos_gpu: qos@31050000 { 911 qos_gpu: qos@31050000 {
922 compatible = "rockchip,rk3228- 912 compatible = "rockchip,rk3228-qos", "syscon";
923 reg = <0x31050000 0x20>; 913 reg = <0x31050000 0x20>;
924 }; 914 };
925 915
926 qos_vop: qos@31060000 { 916 qos_vop: qos@31060000 {
927 compatible = "rockchip,rk3228- 917 compatible = "rockchip,rk3228-qos", "syscon";
928 reg = <0x31060000 0x20>; 918 reg = <0x31060000 0x20>;
929 }; 919 };
930 920
931 qos_rkvdec_r: qos@31070000 { 921 qos_rkvdec_r: qos@31070000 {
932 compatible = "rockchip,rk3228- 922 compatible = "rockchip,rk3228-qos", "syscon";
933 reg = <0x31070000 0x20>; 923 reg = <0x31070000 0x20>;
934 }; 924 };
935 925
936 qos_rkvdec_w: qos@31070080 { 926 qos_rkvdec_w: qos@31070080 {
937 compatible = "rockchip,rk3228- 927 compatible = "rockchip,rk3228-qos", "syscon";
938 reg = <0x31070080 0x20>; 928 reg = <0x31070080 0x20>;
939 }; 929 };
940 930
941 gic: interrupt-controller@32010000 { 931 gic: interrupt-controller@32010000 {
942 compatible = "arm,gic-400"; 932 compatible = "arm,gic-400";
943 interrupt-controller; 933 interrupt-controller;
944 #interrupt-cells = <3>; 934 #interrupt-cells = <3>;
945 #address-cells = <0>; 935 #address-cells = <0>;
946 936
947 reg = <0x32011000 0x1000>, 937 reg = <0x32011000 0x1000>,
948 <0x32012000 0x2000>, 938 <0x32012000 0x2000>,
949 <0x32014000 0x2000>, 939 <0x32014000 0x2000>,
950 <0x32016000 0x2000>; 940 <0x32016000 0x2000>;
951 interrupts = <GIC_PPI 9 (GIC_C 941 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
952 }; 942 };
953 943
954 pinctrl: pinctrl { 944 pinctrl: pinctrl {
955 compatible = "rockchip,rk3228- 945 compatible = "rockchip,rk3228-pinctrl";
956 rockchip,grf = <&grf>; 946 rockchip,grf = <&grf>;
957 #address-cells = <1>; 947 #address-cells = <1>;
958 #size-cells = <1>; 948 #size-cells = <1>;
959 ranges; 949 ranges;
960 950
961 gpio0: gpio@11110000 { 951 gpio0: gpio@11110000 {
962 compatible = "rockchip 952 compatible = "rockchip,gpio-bank";
963 reg = <0x11110000 0x10 953 reg = <0x11110000 0x100>;
964 interrupts = <GIC_SPI 954 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&cru PCLK_GP 955 clocks = <&cru PCLK_GPIO0>;
966 956
967 gpio-controller; 957 gpio-controller;
968 #gpio-cells = <2>; 958 #gpio-cells = <2>;
969 959
970 interrupt-controller; 960 interrupt-controller;
971 #interrupt-cells = <2> 961 #interrupt-cells = <2>;
972 }; 962 };
973 963
974 gpio1: gpio@11120000 { 964 gpio1: gpio@11120000 {
975 compatible = "rockchip 965 compatible = "rockchip,gpio-bank";
976 reg = <0x11120000 0x10 966 reg = <0x11120000 0x100>;
977 interrupts = <GIC_SPI 967 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cru PCLK_GP 968 clocks = <&cru PCLK_GPIO1>;
979 969
980 gpio-controller; 970 gpio-controller;
981 #gpio-cells = <2>; 971 #gpio-cells = <2>;
982 972
983 interrupt-controller; 973 interrupt-controller;
984 #interrupt-cells = <2> 974 #interrupt-cells = <2>;
985 }; 975 };
986 976
987 gpio2: gpio@11130000 { 977 gpio2: gpio@11130000 {
988 compatible = "rockchip 978 compatible = "rockchip,gpio-bank";
989 reg = <0x11130000 0x10 979 reg = <0x11130000 0x100>;
990 interrupts = <GIC_SPI 980 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&cru PCLK_GP 981 clocks = <&cru PCLK_GPIO2>;
992 982
993 gpio-controller; 983 gpio-controller;
994 #gpio-cells = <2>; 984 #gpio-cells = <2>;
995 985
996 interrupt-controller; 986 interrupt-controller;
997 #interrupt-cells = <2> 987 #interrupt-cells = <2>;
998 }; 988 };
999 989
1000 gpio3: gpio@11140000 { 990 gpio3: gpio@11140000 {
1001 compatible = "rockchi 991 compatible = "rockchip,gpio-bank";
1002 reg = <0x11140000 0x1 992 reg = <0x11140000 0x100>;
1003 interrupts = <GIC_SPI 993 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&cru PCLK_G 994 clocks = <&cru PCLK_GPIO3>;
1005 995
1006 gpio-controller; 996 gpio-controller;
1007 #gpio-cells = <2>; 997 #gpio-cells = <2>;
1008 998
1009 interrupt-controller; 999 interrupt-controller;
1010 #interrupt-cells = <2 1000 #interrupt-cells = <2>;
1011 }; 1001 };
1012 1002
1013 pcfg_pull_up: pcfg-pull-up { 1003 pcfg_pull_up: pcfg-pull-up {
1014 bias-pull-up; 1004 bias-pull-up;
1015 }; 1005 };
1016 1006
1017 pcfg_pull_down: pcfg-pull-dow 1007 pcfg_pull_down: pcfg-pull-down {
1018 bias-pull-down; 1008 bias-pull-down;
1019 }; 1009 };
1020 1010
1021 pcfg_pull_none: pcfg-pull-non 1011 pcfg_pull_none: pcfg-pull-none {
1022 bias-disable; 1012 bias-disable;
1023 }; 1013 };
1024 1014
1025 pcfg_pull_none_drv_12ma: pcfg 1015 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1026 drive-strength = <12> 1016 drive-strength = <12>;
1027 }; 1017 };
1028 1018
1029 sdmmc { 1019 sdmmc {
1030 sdmmc_clk: sdmmc-clk 1020 sdmmc_clk: sdmmc-clk {
1031 rockchip,pins 1021 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
1032 }; 1022 };
1033 1023
1034 sdmmc_cmd: sdmmc-cmd 1024 sdmmc_cmd: sdmmc-cmd {
1035 rockchip,pins 1025 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
1036 }; 1026 };
1037 1027
1038 sdmmc_bus4: sdmmc-bus 1028 sdmmc_bus4: sdmmc-bus4 {
1039 rockchip,pins 1029 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1040 1030 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1041 1031 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
1042 1032 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
1043 }; 1033 };
1044 }; 1034 };
1045 1035
1046 sdio { 1036 sdio {
1047 sdio_clk: sdio-clk { 1037 sdio_clk: sdio-clk {
1048 rockchip,pins 1038 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
1049 }; 1039 };
1050 1040
1051 sdio_cmd: sdio-cmd { 1041 sdio_cmd: sdio-cmd {
1052 rockchip,pins 1042 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
1053 }; 1043 };
1054 1044
1055 sdio_bus4: sdio-bus4 1045 sdio_bus4: sdio-bus4 {
1056 rockchip,pins 1046 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
1057 1047 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
1058 1048 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
1059 1049 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
1060 }; 1050 };
1061 }; 1051 };
1062 1052
1063 emmc { 1053 emmc {
1064 emmc_clk: emmc-clk { 1054 emmc_clk: emmc-clk {
1065 rockchip,pins 1055 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
1066 }; 1056 };
1067 1057
1068 emmc_cmd: emmc-cmd { 1058 emmc_cmd: emmc-cmd {
1069 rockchip,pins 1059 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
1070 }; 1060 };
1071 1061
1072 emmc_bus8: emmc-bus8 1062 emmc_bus8: emmc-bus8 {
1073 rockchip,pins 1063 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
1074 1064 <1 RK_PD1 2 &pcfg_pull_none>,
1075 1065 <1 RK_PD2 2 &pcfg_pull_none>,
1076 1066 <1 RK_PD3 2 &pcfg_pull_none>,
1077 1067 <1 RK_PD4 2 &pcfg_pull_none>,
1078 1068 <1 RK_PD5 2 &pcfg_pull_none>,
1079 1069 <1 RK_PD6 2 &pcfg_pull_none>,
1080 1070 <1 RK_PD7 2 &pcfg_pull_none>;
1081 }; 1071 };
1082 }; 1072 };
1083 1073
1084 gmac { 1074 gmac {
1085 rgmii_pins: rgmii-pin 1075 rgmii_pins: rgmii-pins {
1086 rockchip,pins 1076 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1087 1077 <2 RK_PB4 1 &pcfg_pull_none>,
1088 1078 <2 RK_PD1 1 &pcfg_pull_none>,
1089 1079 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1090 1080 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1091 1081 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
1092 1082 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
1093 1083 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
1094 1084 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1095 1085 <2 RK_PC1 1 &pcfg_pull_none>,
1096 1086 <2 RK_PC0 1 &pcfg_pull_none>,
1097 1087 <2 RK_PC5 2 &pcfg_pull_none>,
1098 1088 <2 RK_PC4 2 &pcfg_pull_none>,
1099 1089 <2 RK_PB3 1 &pcfg_pull_none>,
1100 1090 <2 RK_PB0 1 &pcfg_pull_none>;
1101 }; 1091 };
1102 1092
1103 rmii_pins: rmii-pins 1093 rmii_pins: rmii-pins {
1104 rockchip,pins 1094 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1105 1095 <2 RK_PB4 1 &pcfg_pull_none>,
1106 1096 <2 RK_PD1 1 &pcfg_pull_none>,
1107 1097 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1108 1098 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1109 1099 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1110 1100 <2 RK_PC1 1 &pcfg_pull_none>,
1111 1101 <2 RK_PC0 1 &pcfg_pull_none>,
1112 1102 <2 RK_PB0 1 &pcfg_pull_none>,
1113 1103 <2 RK_PB7 1 &pcfg_pull_none>;
1114 }; 1104 };
1115 1105
1116 phy_pins: phy-pins { 1106 phy_pins: phy-pins {
1117 rockchip,pins 1107 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
1118 1108 <2 RK_PB0 2 &pcfg_pull_none>;
1119 }; 1109 };
1120 }; 1110 };
1121 1111
1122 hdmi { 1112 hdmi {
1123 hdmi_hpd: hdmi-hpd { 1113 hdmi_hpd: hdmi-hpd {
1124 rockchip,pins 1114 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1125 }; 1115 };
1126 1116
1127 hdmii2c_xfer: hdmii2c 1117 hdmii2c_xfer: hdmii2c-xfer {
1128 rockchip,pins 1118 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1129 1119 <0 RK_PA7 2 &pcfg_pull_none>;
1130 }; 1120 };
1131 1121
1132 hdmi_cec: hdmi-cec { 1122 hdmi_cec: hdmi-cec {
1133 rockchip,pins 1123 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1134 }; 1124 };
1135 }; 1125 };
1136 1126
1137 i2c0 { 1127 i2c0 {
1138 i2c0_xfer: i2c0-xfer 1128 i2c0_xfer: i2c0-xfer {
1139 rockchip,pins 1129 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1140 1130 <0 RK_PA1 1 &pcfg_pull_none>;
1141 }; 1131 };
1142 }; 1132 };
1143 1133
1144 i2c1 { 1134 i2c1 {
1145 i2c1_xfer: i2c1-xfer 1135 i2c1_xfer: i2c1-xfer {
1146 rockchip,pins 1136 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1147 1137 <0 RK_PA3 1 &pcfg_pull_none>;
1148 }; 1138 };
1149 }; 1139 };
1150 1140
1151 i2c2 { 1141 i2c2 {
1152 i2c2_xfer: i2c2-xfer 1142 i2c2_xfer: i2c2-xfer {
1153 rockchip,pins 1143 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1154 1144 <2 RK_PC5 1 &pcfg_pull_none>;
1155 }; 1145 };
1156 }; 1146 };
1157 1147
1158 i2c3 { 1148 i2c3 {
1159 i2c3_xfer: i2c3-xfer 1149 i2c3_xfer: i2c3-xfer {
1160 rockchip,pins 1150 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1161 1151 <0 RK_PA7 1 &pcfg_pull_none>;
1162 }; 1152 };
1163 }; 1153 };
1164 1154
1165 spi0 { 1155 spi0 {
1166 spi0_clk: spi0-clk { 1156 spi0_clk: spi0-clk {
1167 rockchip,pins 1157 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1168 }; 1158 };
1169 spi0_cs0: spi0-cs0 { 1159 spi0_cs0: spi0-cs0 {
1170 rockchip,pins 1160 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1171 }; 1161 };
1172 spi0_tx: spi0-tx { 1162 spi0_tx: spi0-tx {
1173 rockchip,pins 1163 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1174 }; 1164 };
1175 spi0_rx: spi0-rx { 1165 spi0_rx: spi0-rx {
1176 rockchip,pins 1166 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1177 }; 1167 };
1178 spi0_cs1: spi0-cs1 { 1168 spi0_cs1: spi0-cs1 {
1179 rockchip,pins 1169 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1180 }; 1170 };
1181 }; 1171 };
1182 1172
1183 spi1 { 1173 spi1 {
1184 spi1_clk: spi1-clk { 1174 spi1_clk: spi1-clk {
1185 rockchip,pins 1175 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1186 }; 1176 };
1187 spi1_cs0: spi1-cs0 { 1177 spi1_cs0: spi1-cs0 {
1188 rockchip,pins 1178 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1189 }; 1179 };
1190 spi1_rx: spi1-rx { 1180 spi1_rx: spi1-rx {
1191 rockchip,pins 1181 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1192 }; 1182 };
1193 spi1_tx: spi1-tx { 1183 spi1_tx: spi1-tx {
1194 rockchip,pins 1184 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1195 }; 1185 };
1196 spi1_cs1: spi1-cs1 { 1186 spi1_cs1: spi1-cs1 {
1197 rockchip,pins 1187 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1198 }; 1188 };
1199 }; 1189 };
1200 1190
1201 i2s1 { 1191 i2s1 {
1202 i2s1_bus: i2s1-bus { 1192 i2s1_bus: i2s1-bus {
1203 rockchip,pins 1193 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1204 1194 <0 RK_PB1 1 &pcfg_pull_none>,
1205 1195 <0 RK_PB3 1 &pcfg_pull_none>,
1206 1196 <0 RK_PB4 1 &pcfg_pull_none>,
1207 1197 <0 RK_PB5 1 &pcfg_pull_none>,
1208 1198 <0 RK_PB6 1 &pcfg_pull_none>,
1209 1199 <1 RK_PA2 2 &pcfg_pull_none>,
1210 1200 <1 RK_PA4 2 &pcfg_pull_none>,
1211 1201 <1 RK_PA5 2 &pcfg_pull_none>;
1212 }; 1202 };
1213 }; 1203 };
1214 1204
1215 pwm0 { 1205 pwm0 {
1216 pwm0_pin: pwm0-pin { 1206 pwm0_pin: pwm0-pin {
1217 rockchip,pins 1207 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1218 }; 1208 };
1219 }; 1209 };
1220 1210
1221 pwm1 { 1211 pwm1 {
1222 pwm1_pin: pwm1-pin { 1212 pwm1_pin: pwm1-pin {
1223 rockchip,pins 1213 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1224 }; 1214 };
1225 }; 1215 };
1226 1216
1227 pwm2 { 1217 pwm2 {
1228 pwm2_pin: pwm2-pin { 1218 pwm2_pin: pwm2-pin {
1229 rockchip,pins 1219 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1230 }; 1220 };
1231 }; 1221 };
1232 1222
1233 pwm3 { 1223 pwm3 {
1234 pwm3_pin: pwm3-pin { 1224 pwm3_pin: pwm3-pin {
1235 rockchip,pins 1225 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1236 }; 1226 };
1237 }; 1227 };
1238 1228
1239 spdif { 1229 spdif {
1240 spdif_tx: spdif-tx { 1230 spdif_tx: spdif-tx {
1241 rockchip,pins 1231 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1242 }; 1232 };
1243 }; 1233 };
1244 1234
1245 tsadc { 1235 tsadc {
1246 otp_pin: otp-pin { 1236 otp_pin: otp-pin {
1247 rockchip,pins 1237 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1248 }; 1238 };
1249 1239
1250 otp_out: otp-out { 1240 otp_out: otp-out {
1251 rockchip,pins 1241 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1252 }; 1242 };
1253 }; 1243 };
1254 1244
1255 uart0 { 1245 uart0 {
1256 uart0_xfer: uart0-xfe 1246 uart0_xfer: uart0-xfer {
1257 rockchip,pins 1247 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1258 1248 <2 RK_PD3 1 &pcfg_pull_none>;
1259 }; 1249 };
1260 1250
1261 uart0_cts: uart0-cts 1251 uart0_cts: uart0-cts {
1262 rockchip,pins 1252 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1263 }; 1253 };
1264 1254
1265 uart0_rts: uart0-rts 1255 uart0_rts: uart0-rts {
1266 rockchip,pins 1256 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1267 }; 1257 };
1268 }; 1258 };
1269 1259
1270 uart1 { 1260 uart1 {
1271 uart1_xfer: uart1-xfe 1261 uart1_xfer: uart1-xfer {
1272 rockchip,pins 1262 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1273 1263 <1 RK_PB2 1 &pcfg_pull_none>;
1274 }; 1264 };
1275 1265
1276 uart1_cts: uart1-cts 1266 uart1_cts: uart1-cts {
1277 rockchip,pins 1267 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1278 }; 1268 };
1279 1269
1280 uart1_rts: uart1-rts 1270 uart1_rts: uart1-rts {
1281 rockchip,pins 1271 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1282 }; 1272 };
1283 }; 1273 };
1284 1274
1285 uart2 { 1275 uart2 {
1286 uart2_xfer: uart2-xfe 1276 uart2_xfer: uart2-xfer {
1287 rockchip,pins 1277 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1288 1278 <1 RK_PC3 2 &pcfg_pull_none>;
1289 }; 1279 };
1290 1280
1291 uart21_xfer: uart21-x 1281 uart21_xfer: uart21-xfer {
1292 rockchip,pins 1282 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1293 1283 <1 RK_PB1 2 &pcfg_pull_none>;
1294 }; 1284 };
1295 1285
1296 uart2_cts: uart2-cts 1286 uart2_cts: uart2-cts {
1297 rockchip,pins 1287 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1298 }; 1288 };
1299 1289
1300 uart2_rts: uart2-rts 1290 uart2_rts: uart2-rts {
1301 rockchip,pins 1291 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1302 }; 1292 };
1303 }; 1293 };
1304 }; 1294 };
1305 }; 1295 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.