1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2014, 2015 Andy Yan <andy.yan@
4 */
5
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include "rk3288.dtsi"
9
10 / {
11 model = "PopMetal-RK3288";
12 compatible = "chipspark,popmetal-rk328
13
14 memory@0 {
15 device_type = "memory";
16 reg = <0x0 0x0 0x0 0x80000000>
17 };
18
19 ext_gmac: external-gmac-clock {
20 compatible = "fixed-clock";
21 clock-frequency = <125000000>;
22 clock-output-names = "ext_gmac
23 #clock-cells = <0>;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 autorepeat;
29
30 pinctrl-names = "default";
31 pinctrl-0 = <&pwrbtn>;
32
33 key-power {
34 gpios = <&gpio0 RK_PA5
35 linux,code = <KEY_POWE
36 label = "GPIO Key Powe
37 linux,input-type = <1>
38 wakeup-source;
39 debounce-interval = <1
40 };
41 };
42
43 ir: ir-receiver {
44 compatible = "gpio-ir-receiver
45 gpios = <&gpio0 RK_PA6 GPIO_AC
46 pinctrl-names = "default";
47 pinctrl-0 = <&ir_int>;
48 };
49
50 vcc_flash: flash-regulator {
51 compatible = "regulator-fixed"
52 regulator-name = "vcc_flash";
53 regulator-min-microvolt = <180
54 regulator-max-microvolt = <180
55 vin-supply = <&vcc_io>;
56 };
57
58 vcc_sd: sdmmc-regulator {
59 compatible = "regulator-fixed"
60 gpio = <&gpio7 RK_PB3 GPIO_ACT
61 pinctrl-names = "default";
62 pinctrl-0 = <&sdmmc_pwr>;
63 regulator-name = "vcc_sd";
64 regulator-min-microvolt = <330
65 regulator-max-microvolt = <330
66 startup-delay-us = <100000>;
67 vin-supply = <&vcc_io>;
68 };
69
70 vcc_sys: vsys-regulator {
71 compatible = "regulator-fixed"
72 regulator-name = "vcc_sys";
73 regulator-min-microvolt = <500
74 regulator-max-microvolt = <500
75 regulator-always-on;
76 regulator-boot-on;
77 };
78
79 /*
80 * A PT5128 creates both dovdd_1v8 and
81 * by the dvp_pwr pin.
82 */
83 vcc18_dvp: vcc18-dvp-regulator {
84 compatible = "regulator-fixed"
85 regulator-name = "vcc18-dvp";
86 regulator-min-microvolt = <180
87 regulator-max-microvolt = <180
88 vin-supply = <&vcc28_dvp>;
89 };
90
91 vcc28_dvp: vcc28-dvp-regulator {
92 compatible = "regulator-fixed"
93 enable-active-high;
94 gpio = <&gpio0 RK_PC1 GPIO_ACT
95 pinctrl-names = "default";
96 pinctrl-0 = <&dvp_pwr>;
97 regulator-name = "vcc28_dvp";
98 regulator-min-microvolt = <280
99 regulator-max-microvolt = <280
100 regulator-always-on;
101 vin-supply = <&vcc_io>;
102 };
103 };
104
105 &cpu0 {
106 cpu-supply = <&vdd_cpu>;
107 };
108
109 &cpu1 {
110 cpu-supply = <&vdd_cpu>;
111 };
112
113 &cpu2 {
114 cpu-supply = <&vdd_cpu>;
115 };
116
117 &cpu3 {
118 cpu-supply = <&vdd_cpu>;
119 };
120
121 &emmc {
122 bus-width = <8>;
123 cap-mmc-highspeed;
124 mmc-ddr-1_8v;
125 mmc-hs200-1_8v;
126 non-removable;
127 pinctrl-names = "default";
128 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc
129 vmmc-supply = <&vcc_io>;
130 vqmmc-supply = <&vcc_flash>;
131 status = "okay";
132 };
133
134 &sdmmc {
135 bus-width = <4>;
136 cap-mmc-highspeed;
137 cap-sd-highspeed;
138 card-detect-delay = <200>;
139 disable-wp; /* wp
140 pinctrl-names = "default";
141 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sd
142 sd-uhs-sdr12;
143 sd-uhs-sdr25;
144 sd-uhs-sdr50;
145 sd-uhs-sdr104;
146 vmmc-supply = <&vcc_sd>;
147 vqmmc-supply = <&vccio_sd>;
148 status = "okay";
149 };
150
151 &gmac {
152 phy-supply = <&vcc_lan>;
153 phy-mode = "rgmii";
154 clock_in_out = "input";
155 snps,reset-gpio = <&gpio4 RK_PB0 GPIO_
156 snps,reset-active-low;
157 snps,reset-delays-us = <0 10000 100000
158 assigned-clocks = <&cru SCLK_MAC>;
159 assigned-clock-parents = <&ext_gmac>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&rgmii_pins>;
162 tx_delay = <0x30>;
163 rx_delay = <0x10>;
164 status = "okay";
165 };
166
167 &hdmi {
168 ddc-i2c-bus = <&i2c5>;
169 status = "okay";
170 };
171
172 &i2c0 {
173 status = "okay";
174 clock-frequency = <400000>;
175
176 rk808: pmic@1b {
177 compatible = "rockchip,rk808";
178 reg = <0x1b>;
179 interrupt-parent = <&gpio0>;
180 interrupts = <RK_PA4 IRQ_TYPE_
181 pinctrl-names = "default";
182 pinctrl-0 = <&pmic_int &global
183 rockchip,system-power-controll
184 wakeup-source;
185 #clock-cells = <1>;
186 clock-output-names = "xin32k",
187
188 vcc1-supply = <&vcc_sys>;
189 vcc2-supply = <&vcc_sys>;
190 vcc3-supply = <&vcc_sys>;
191 vcc4-supply = <&vcc_sys>;
192 vcc6-supply = <&vcc_sys>;
193 vcc7-supply = <&vcc_sys>;
194 vcc8-supply = <&vcc_18>;
195 vcc9-supply = <&vcc_io>;
196 vcc10-supply = <&vcc_io>;
197 vcc11-supply = <&vcc_sys>;
198 vcc12-supply = <&vcc_io>;
199 vddio-supply = <&vcc_io>;
200
201 regulators {
202 vdd_cpu: DCDC_REG1 {
203 regulator-alwa
204 regulator-boot
205 regulator-min-
206 regulator-max-
207 regulator-name
208 regulator-stat
209 regula
210 };
211 };
212
213 vdd_gpu: DCDC_REG2 {
214 regulator-alwa
215 regulator-boot
216 regulator-min-
217 regulator-max-
218 regulator-name
219 regulator-stat
220 regula
221 regula
222 };
223 };
224
225 vcc_ddr: DCDC_REG3 {
226 regulator-alwa
227 regulator-boot
228 regulator-name
229 regulator-stat
230 regula
231 };
232 };
233
234 vcc_io: DCDC_REG4 {
235 regulator-alwa
236 regulator-boot
237 regulator-min-
238 regulator-max-
239 regulator-name
240 regulator-stat
241 regula
242 regula
243 };
244 };
245
246 vcc_lan: LDO_REG1 {
247 regulator-alwa
248 regulator-boot
249 regulator-min-
250 regulator-max-
251 regulator-name
252 regulator-stat
253 regula
254 regula
255 };
256 };
257
258 vccio_sd: LDO_REG2 {
259 regulator-alwa
260 regulator-boot
261 regulator-min-
262 regulator-max-
263 regulator-name
264 regulator-stat
265 regula
266 };
267 };
268
269 vdd_10: LDO_REG3 {
270 regulator-alwa
271 regulator-boot
272 regulator-min-
273 regulator-max-
274 regulator-name
275 regulator-stat
276 regula
277 regula
278 };
279 };
280
281 vcc18_lcd: LDO_REG4 {
282 regulator-alwa
283 regulator-boot
284 regulator-min-
285 regulator-max-
286 regulator-name
287 regulator-stat
288 regula
289 regula
290 };
291 };
292
293 ldo5: LDO_REG5 {
294 regulator-alwa
295 regulator-min-
296 regulator-max-
297 regulator-name
298 };
299
300 vdd10_lcd: LDO_REG6 {
301 regulator-alwa
302 regulator-boot
303 regulator-min-
304 regulator-max-
305 regulator-name
306 regulator-stat
307 regula
308 regula
309 };
310 };
311
312 vcc_18: LDO_REG7 {
313 regulator-alwa
314 regulator-boot
315 regulator-min-
316 regulator-max-
317 regulator-name
318 regulator-stat
319 regula
320 regula
321 };
322 };
323
324 vcca_33: LDO_REG8 {
325 regulator-alwa
326 regulator-boot
327 regulator-min-
328 regulator-max-
329 regulator-name
330 regulator-stat
331 regula
332 regula
333 };
334 };
335
336 vccio_wl: SWITCH_REG1
337 regulator-alwa
338 regulator-boot
339 regulator-name
340 regulator-stat
341 regula
342 };
343 };
344
345 vcc_lcd: SWITCH_REG2 {
346 regulator-alwa
347 regulator-boot
348 regulator-name
349 regulator-stat
350 regula
351 };
352 };
353 };
354 };
355 };
356
357 &i2c1 {
358 status = "okay";
359 clock-frequency = <400000>;
360
361 ak8963: ak8963@d {
362 compatible = "asahi-kasei,ak89
363 reg = <0x0d>;
364 interrupt-parent = <&gpio8>;
365 interrupts = <RK_PA1 IRQ_TYPE_
366 pinctrl-names = "default";
367 pinctrl-0 = <&comp_int>;
368 vdd-supply = <&vcc_io>;
369 vid-supply = <&vcc_io>;
370 };
371
372 l3g4200d: l3g4200d@69 {
373 compatible = "st,l3g4200d-gyro
374 st,drdy-int-pin = <2>;
375 reg = <0x69>;
376 vdd-supply = <&vcc_io>;
377 vddio-supply = <&vcc_io>;
378 };
379
380 mma8452: mma8452@1d {
381 compatible = "fsl,mma8452";
382 reg = <0x1d>;
383 interrupt-parent = <&gpio8>;
384 interrupts = <RK_PA0 IRQ_TYPE_
385 pinctrl-names = "default";
386 pinctrl-0 = <&gsensor_int>;
387 };
388 };
389
390 &i2c2 {
391 status = "okay";
392 };
393
394 &i2c3 {
395 status = "okay";
396 };
397
398 &i2c4 {
399 status = "okay";
400 };
401
402 &i2c5 {
403 status = "okay";
404 };
405
406 &io_domains {
407 status = "okay";
408
409 audio-supply = <&vcca_33>;
410 bb-supply = <&vcc_io>;
411 dvp-supply = <&vcc18_dvp>;
412 flash0-supply = <&vcc_flash>;
413 flash1-supply = <&vcc_lan>;
414 gpio30-supply = <&vcc_io>;
415 gpio1830-supply = <&vcc_io>;
416 lcdc-supply = <&vcc_io>;
417 sdcard-supply = <&vccio_sd>;
418 wifi-supply = <&vccio_wl>;
419 };
420
421 &pinctrl {
422 ak8963 {
423 comp_int: comp-int {
424 rockchip,pins = <8 RK_
425 };
426 };
427
428 buttons {
429 pwrbtn: pwrbtn {
430 rockchip,pins = <0 RK_
431 };
432 };
433
434 dvp {
435 dvp_pwr: dvp-pwr {
436 rockchip,pins = <0 RK_
437 };
438 };
439
440 ir {
441 ir_int: ir-int {
442 rockchip,pins = <0 RK_
443 };
444 };
445
446 mma8452 {
447 gsensor_int: gsensor-int {
448 rockchip,pins = <8 RK_
449 };
450 };
451
452 pmic {
453 pmic_int: pmic-int {
454 rockchip,pins = <0 RK_
455 };
456 };
457
458 sdmmc {
459 sdmmc_pwr: sdmmc-pwr {
460 rockchip,pins = <7 RK_
461 };
462 };
463 };
464
465 &tsadc {
466 rockchip,hw-tshut-mode = <0>;
467 rockchip,hw-tshut-polarity = <0>;
468 status = "okay";
469 };
470
471 &vopb {
472 status = "okay";
473 };
474
475 &vopb_mmu {
476 status = "okay";
477 };
478
479 &vopl {
480 status = "okay";
481 };
482
483 &vopl_mmu {
484 status = "okay";
485 };
486
487 &uart0 {
488 status = "okay";
489 };
490
491 &uart1 {
492 status = "okay";
493 };
494
495 &uart2 {
496 status = "okay";
497 };
498
499 &uart3 {
500 status = "okay";
501 };
502
503 &uart4 {
504 status = "okay";
505 };
506
507 &usbphy {
508 status = "okay";
509 };
510
511 &usb_otg {
512 status = "okay";
513 };
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