1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Google Veyron Jaq Rev 1+ board device tree 3 * Google Veyron Jaq Rev 1+ board device tree source
4 * 4 *
5 * Copyright 2015 Google, Inc 5 * Copyright 2015 Google, Inc
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "rk3288-veyron-chromebook.dtsi" 10 #include "rk3288-veyron-chromebook.dtsi"
11 #include "../cros-ec-sbs.dtsi" 11 #include "../cros-ec-sbs.dtsi"
12 12
13 / { 13 / {
14 model = "Google Jaq"; 14 model = "Google Jaq";
15 compatible = "google,veyron-jaq-rev5", 15 compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
16 "google,veyron-jaq-rev3", 16 "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
17 "google,veyron-jaq-rev1", 17 "google,veyron-jaq-rev1", "google,veyron-jaq",
18 "google,veyron", "rockchi 18 "google,veyron", "rockchip,rk3288";
19 }; 19 };
20 20
21 &backlight { 21 &backlight {
22 /* Jaq panel PWM must be >= 3%, so sta 22 /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
23 brightness-levels = <8 255>; 23 brightness-levels = <8 255>;
24 num-interpolated-steps = <247>; 24 num-interpolated-steps = <247>;
25 }; 25 };
26 26
27 &rk808 { 27 &rk808 {
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2 29 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
30 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE 30 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
31 <&gpio7 RK_PB7 GPIO_ACTIVE 31 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
32 32
33 regulators { 33 regulators {
34 mic_vcc: LDO_REG2 { 34 mic_vcc: LDO_REG2 {
35 regulator-name = "mic_ 35 regulator-name = "mic_vcc";
36 regulator-always-on; 36 regulator-always-on;
37 regulator-boot-on; 37 regulator-boot-on;
38 regulator-min-microvol 38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvol 39 regulator-max-microvolt = <1800000>;
40 regulator-state-mem { 40 regulator-state-mem {
41 regulator-off- 41 regulator-off-in-suspend;
42 }; 42 };
43 }; 43 };
44 }; 44 };
45 }; 45 };
46 46
47 &sdio0 { 47 &sdio0 {
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <0>; 49 #size-cells = <0>;
50 50
51 btmrvl: btmrvl@2 { 51 btmrvl: btmrvl@2 {
52 compatible = "marvell,sd8897-b 52 compatible = "marvell,sd8897-bt";
53 reg = <2>; 53 reg = <2>;
54 interrupt-parent = <&gpio4>; 54 interrupt-parent = <&gpio4>;
55 interrupts = <RK_PD7 IRQ_TYPE_ 55 interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
56 marvell,wakeup-pin = /bits/ 16 56 marvell,wakeup-pin = /bits/ 16 <13>;
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&bt_host_wake_l>; 58 pinctrl-0 = <&bt_host_wake_l>;
59 }; 59 };
60 }; 60 };
61 61
62 &sdmmc { 62 &sdmmc {
63 disable-wp; 63 disable-wp;
64 pinctrl-names = "default"; 64 pinctrl-names = "default";
65 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sd 65 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
66 &sdmmc_bus4>; 66 &sdmmc_bus4>;
67 }; 67 };
68 68
69 &vcc_5v { 69 &vcc_5v {
70 enable-active-high; 70 enable-active-high;
71 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH 71 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default"; 72 pinctrl-names = "default";
73 pinctrl-0 = <&drv_5v>; 73 pinctrl-0 = <&drv_5v>;
74 }; 74 };
75 75
76 &vcc50_hdmi { 76 &vcc50_hdmi {
77 enable-active-high; 77 enable-active-high;
78 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH 78 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
79 pinctrl-names = "default"; 79 pinctrl-names = "default";
80 pinctrl-0 = <&vcc50_hdmi_en>; 80 pinctrl-0 = <&vcc50_hdmi_en>;
81 }; 81 };
82 82
83 &gpio0 { 83 &gpio0 {
84 gpio-line-names = "PMIC_SLEEP_AP", 84 gpio-line-names = "PMIC_SLEEP_AP",
85 "DDRIO_PWROFF", 85 "DDRIO_PWROFF",
86 "DDRIO_RETEN", 86 "DDRIO_RETEN",
87 "TS3A227E_INT_L", 87 "TS3A227E_INT_L",
88 "PMIC_INT_L", 88 "PMIC_INT_L",
89 "PWR_KEY_L", 89 "PWR_KEY_L",
90 "AP_LID_INT_L", 90 "AP_LID_INT_L",
91 "EC_IN_RW", 91 "EC_IN_RW",
92 92
93 "AC_PRESENT_AP", 93 "AC_PRESENT_AP",
94 /* 94 /*
95 * RECOVERY_SW_L is 95 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
96 * it REC_MODE_L. 96 * it REC_MODE_L.
97 */ 97 */
98 "RECOVERY_SW_L", 98 "RECOVERY_SW_L",
99 "OTP_OUT", 99 "OTP_OUT",
100 "HOST1_PWR_EN", 100 "HOST1_PWR_EN",
101 "USBOTG_PWREN_H", 101 "USBOTG_PWREN_H",
102 "AP_WARM_RESET_H", 102 "AP_WARM_RESET_H",
103 "nFALUT2", 103 "nFALUT2",
104 "I2C0_SDA_PMIC", 104 "I2C0_SDA_PMIC",
105 105
106 "I2C0_SCL_PMIC", 106 "I2C0_SCL_PMIC",
107 "SUSPEND_L", 107 "SUSPEND_L",
108 "USB_INT"; 108 "USB_INT";
109 }; 109 };
110 110
111 &gpio2 { 111 &gpio2 {
112 gpio-line-names = "CONFIG0", 112 gpio-line-names = "CONFIG0",
113 "CONFIG1", 113 "CONFIG1",
114 "CONFIG2", 114 "CONFIG2",
115 "", 115 "",
116 "", 116 "",
117 "", 117 "",
118 "", 118 "",
119 "CONFIG3", 119 "CONFIG3",
120 120
121 "", 121 "",
122 "EMMC_RST_L", 122 "EMMC_RST_L",
123 "", 123 "",
124 "", 124 "",
125 "BL_PWR_EN", 125 "BL_PWR_EN",
126 "AVDD_1V8_DISP_EN"; 126 "AVDD_1V8_DISP_EN";
127 }; 127 };
128 128
129 &gpio3 { 129 &gpio3 {
130 gpio-line-names = "FLASH0_D0", 130 gpio-line-names = "FLASH0_D0",
131 "FLASH0_D1", 131 "FLASH0_D1",
132 "FLASH0_D2", 132 "FLASH0_D2",
133 "FLASH0_D3", 133 "FLASH0_D3",
134 "FLASH0_D4", 134 "FLASH0_D4",
135 "FLASH0_D5", 135 "FLASH0_D5",
136 "FLASH0_D6", 136 "FLASH0_D6",
137 "FLASH0_D7", 137 "FLASH0_D7",
138 138
139 "", 139 "",
140 "", 140 "",
141 "", 141 "",
142 "", 142 "",
143 "", 143 "",
144 "", 144 "",
145 "", 145 "",
146 "", 146 "",
147 147
148 "FLASH0_CS2/EMMC_CMD 148 "FLASH0_CS2/EMMC_CMD",
149 "", 149 "",
150 "FLASH0_DQS/EMMC_CLK 150 "FLASH0_DQS/EMMC_CLKO";
151 }; 151 };
152 152
153 &gpio4 { 153 &gpio4 {
154 gpio-line-names = "", 154 gpio-line-names = "",
155 "", 155 "",
156 "", 156 "",
157 "", 157 "",
158 "", 158 "",
159 "", 159 "",
160 "", 160 "",
161 "", 161 "",
162 162
163 "", 163 "",
164 "", 164 "",
165 "", 165 "",
166 "", 166 "",
167 "", 167 "",
168 "", 168 "",
169 "", 169 "",
170 "", 170 "",
171 171
172 "UART0_RXD", 172 "UART0_RXD",
173 "UART0_TXD", 173 "UART0_TXD",
174 "UART0_CTS", 174 "UART0_CTS",
175 "UART0_RTS", 175 "UART0_RTS",
176 "SDIO0_D0", 176 "SDIO0_D0",
177 "SDIO0_D1", 177 "SDIO0_D1",
178 "SDIO0_D2", 178 "SDIO0_D2",
179 "SDIO0_D3", 179 "SDIO0_D3",
180 180
181 "SDIO0_CMD", 181 "SDIO0_CMD",
182 "SDIO0_CLK", 182 "SDIO0_CLK",
183 "BT_DEV_WAKE", 183 "BT_DEV_WAKE", /* Maybe missing from mighty? */
184 "", 184 "",
185 "WIFI_ENABLE_H", 185 "WIFI_ENABLE_H",
186 "BT_ENABLE_L", 186 "BT_ENABLE_L",
187 "WIFI_HOST_WAKE", 187 "WIFI_HOST_WAKE",
188 "BT_HOST_WAKE"; 188 "BT_HOST_WAKE";
189 }; 189 };
190 190
191 &gpio5 { 191 &gpio5 {
192 gpio-line-names = "", 192 gpio-line-names = "",
193 "", 193 "",
194 "", 194 "",
195 "", 195 "",
196 "", 196 "",
197 "", 197 "",
198 "", 198 "",
199 "", 199 "",
200 200
201 "", 201 "",
202 "", 202 "",
203 "", 203 "",
204 "", 204 "",
205 "SPI0_CLK", 205 "SPI0_CLK",
206 "SPI0_CS0", 206 "SPI0_CS0",
207 "SPI0_TXD", 207 "SPI0_TXD",
208 "SPI0_RXD", 208 "SPI0_RXD",
209 209
210 "", 210 "",
211 "", 211 "",
212 "", 212 "",
213 "VCC50_HDMI_EN"; 213 "VCC50_HDMI_EN";
214 }; 214 };
215 215
216 &gpio6 { 216 &gpio6 {
217 gpio-line-names = "I2S0_SCLK", 217 gpio-line-names = "I2S0_SCLK",
218 "I2S0_LRCK_RX", 218 "I2S0_LRCK_RX",
219 "I2S0_LRCK_TX", 219 "I2S0_LRCK_TX",
220 "I2S0_SDI", 220 "I2S0_SDI",
221 "I2S0_SDO0", 221 "I2S0_SDO0",
222 "HP_DET_H", 222 "HP_DET_H",
223 "ALS_INT", 223 "ALS_INT",
224 "INT_CODEC", 224 "INT_CODEC",
225 225
226 "I2S0_CLK", 226 "I2S0_CLK",
227 "I2C2_SDA", 227 "I2C2_SDA",
228 "I2C2_SCL", 228 "I2C2_SCL",
229 "MICDET", 229 "MICDET",
230 "", 230 "",
231 "", 231 "",
232 "", 232 "",
233 "", 233 "",
234 234
235 "SDMMC_D0", 235 "SDMMC_D0",
236 "SDMMC_D1", 236 "SDMMC_D1",
237 "SDMMC_D2", 237 "SDMMC_D2",
238 "SDMMC_D3", 238 "SDMMC_D3",
239 "SDMMC_CLK", 239 "SDMMC_CLK",
240 "SDMMC_CMD"; 240 "SDMMC_CMD";
241 }; 241 };
242 242
243 &gpio7 { 243 &gpio7 {
244 gpio-line-names = "LCDC_BL", 244 gpio-line-names = "LCDC_BL",
245 "PWM_LOG", 245 "PWM_LOG",
246 "BL_EN", 246 "BL_EN",
247 "TRACKPAD_INT", 247 "TRACKPAD_INT",
248 "TPM_INT_H", 248 "TPM_INT_H",
249 "SDMMC_DET_L", 249 "SDMMC_DET_L",
250 /* 250 /*
251 * AP_FLASH_WP_L is 251 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
252 * it FW_WP_AP. 252 * it FW_WP_AP.
253 */ 253 */
254 "AP_FLASH_WP_L", 254 "AP_FLASH_WP_L",
255 "EC_INT", 255 "EC_INT",
256 256
257 "CPU_NMI", 257 "CPU_NMI",
258 "DVSOK", 258 "DVSOK",
259 "SDMMC_WP", 259 "SDMMC_WP", /* mighty only */
260 "EDP_HPD", 260 "EDP_HPD",
261 "DVS1", 261 "DVS1",
262 "nFALUT1", 262 "nFALUT1", /* nFAULT1 on jaq */
263 "LCD_EN", 263 "LCD_EN",
264 "DVS2", 264 "DVS2",
265 265
266 "VCC5V_GOOD_H", 266 "VCC5V_GOOD_H",
267 "I2C4_SDA_TP", 267 "I2C4_SDA_TP",
268 "I2C4_SCL_TP", 268 "I2C4_SCL_TP",
269 "I2C5_SDA_HDMI", 269 "I2C5_SDA_HDMI",
270 "I2C5_SCL_HDMI", 270 "I2C5_SCL_HDMI",
271 "5V_DRV", 271 "5V_DRV",
272 "UART2_RXD", 272 "UART2_RXD",
273 "UART2_TXD"; 273 "UART2_TXD";
274 }; 274 };
275 275
276 &gpio8 { 276 &gpio8 {
277 gpio-line-names = "RAM_ID0", 277 gpio-line-names = "RAM_ID0",
278 "RAM_ID1", 278 "RAM_ID1",
279 "RAM_ID2", 279 "RAM_ID2",
280 "RAM_ID3", 280 "RAM_ID3",
281 "I2C1_SDA_TPM", 281 "I2C1_SDA_TPM",
282 "I2C1_SCL_TPM", 282 "I2C1_SCL_TPM",
283 "SPI2_CLK", 283 "SPI2_CLK",
284 "SPI2_CS0", 284 "SPI2_CS0",
285 285
286 "SPI2_RXD", 286 "SPI2_RXD",
287 "SPI2_TXD"; 287 "SPI2_TXD";
288 }; 288 };
289 289
290 &pinctrl { 290 &pinctrl {
291 pinctrl-names = "default", "sleep"; 291 pinctrl-names = "default", "sleep";
292 pinctrl-0 = < 292 pinctrl-0 = <
293 /* Common for sleep and wake, 293 /* Common for sleep and wake, but no owners */
294 &ddr0_retention 294 &ddr0_retention
295 &ddrio_pwroff 295 &ddrio_pwroff
296 &global_pwroff 296 &global_pwroff
297 297
298 /* Wake only */ 298 /* Wake only */
299 &suspend_l_wake 299 &suspend_l_wake
300 &bt_dev_wake_awake 300 &bt_dev_wake_awake
301 >; 301 >;
302 pinctrl-1 = < 302 pinctrl-1 = <
303 /* Common for sleep and wake, 303 /* Common for sleep and wake, but no owners */
304 &ddr0_retention 304 &ddr0_retention
305 &ddrio_pwroff 305 &ddrio_pwroff
306 &global_pwroff 306 &global_pwroff
307 307
308 /* Sleep only */ 308 /* Sleep only */
309 &suspend_l_sleep 309 &suspend_l_sleep
310 &bt_dev_wake_sleep 310 &bt_dev_wake_sleep
311 >; 311 >;
312 312
313 buck-5v { 313 buck-5v {
314 drv_5v: drv-5v { 314 drv_5v: drv-5v {
315 rockchip,pins = <7 RK_ 315 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
316 }; 316 };
317 }; 317 };
318 318
319 hdmi { 319 hdmi {
320 vcc50_hdmi_en: vcc50-hdmi-en { 320 vcc50_hdmi_en: vcc50-hdmi-en {
321 rockchip,pins = <5 RK_ 321 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
322 }; 322 };
323 }; 323 };
324 324
325 pmic { 325 pmic {
326 dvs_1: dvs-1 { 326 dvs_1: dvs-1 {
327 rockchip,pins = <7 RK_ 327 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
328 }; 328 };
329 329
330 dvs_2: dvs-2 { 330 dvs_2: dvs-2 {
331 rockchip,pins = <7 RK_ 331 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
332 }; 332 };
333 }; 333 };
334 }; 334 };
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